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Outline
Ch-2: Differential Amplifiers
 Review on classical amplifiers
 Construction & operation of differential amplifiers
 Small signal analysis of differential amplifiers
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By: Behailu T.
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Differential mode gain
Common mode gain
Input and output impedances
Common mode rejection ratio
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Review on classical amplifiers
Single-ended data transmission
The classical amplifier schemes that were discussed in the previous
course, Applied Electronics-I, are all examples of so-called single-ended
three-terminal devices.
 This means that, basically, the amplifier has three connections to the
outside world.
 One of the terminals is used to provide input to the amplifier, a second
terminal defines the output and the third terminal serves as a reference,
as the common ground bus to which the two other terminals are
referred.

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
Due to capacitive, inductive
and/or radiative coupling with
the surrounding environment
Single ended classical amplifier
schemes are not well suited for
highly demanding applications
where noise pickup and data
transmission over long distances
compromise signal quality.
Application examples :
1. Hearing aid - microphone and loudspeaker are
Conductive coupling : Because
grounded through the same (thin) wire (high impedance)
of the finite conductivity of the
2. ECG (electro-cardiogram : heart potential
ground bus a voltage drop Vg is
measurements)
observed over the bus
3. EEG (electro-encephalogram : brain potential
measurements)
Figure 2.1. Classical single ended amplifier
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Differential data transmission
BJT differential pair: Construction
To handle high-risk or highly
demanding applications, to
enable long-distance
communication, and/or to
avoid excessive noise pickup
and ground-loop interference,
more advanced, so-called
differential amplifiers are
then called for.
 A concrete implementation
scheme, the emitter-coupled
differential pair (ECDP), is
proposed as a solution.

Figure 2.2. Differential Amplifier with isolated
ground bus
 The two transistors Q1 and Q2 have
identical characteristics
 The resistances of the circuits are equal R C
= R C1 = R C2
 The two input signals V1 and V2 are
applied at the bases of Q1 and Q2.
 The output voltage is taken between two
collectors.
 Ideally, the output voltage is zero when
the two inputs are equal.
 When V1 is greater then V2 the output
voltage with the polarity shown appears.
When V1 is less than V2, the output
voltage has the opposite polarity.
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BJT differential pair: Configuration
BJT differential pair: DC Analysis

Dual-input,
unbalanced-output
Single-input,
balanced-output
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Single-input,
unbalanced-output
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 Depending the number of input signals used and the way an output voltage is
measured, four types of configuration could be made as follows
Dual-input,
balanced-output
Figure 2.3 Emitter coupled differential pair
(ECDP)
The internal resistances of the input
signals are denoted by RS because
Rs = RS1= RS2 .
 Since both emitters biased sections
of the different amplifier are
symmetrical in all respects,
therefore, the operating point for
only one section need to be
determined.
 The same values of ICQ and VCEQ can
be used for second transistor Q2.
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Figure 2.4 DC equivalent circuit of ECDP
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BJT differential pair: DC Analysis

BJT differential pair: DC Analysis
Applying KVL to the base emitter loop of the transistor Q1
 The voltage at the emitter of Q1 is approximately
equal to -VBE if the voltage drop across Rs is
negligible.
 Knowing the value of IC the voltage at the collector
VC is given by
=
…..(1)
=
0.7 V
−
−
+
,
…..(2)
=
+
+
+
-
−
Using eqn(1) and eqn(2) , VCEQ and ICQ can be
Figure 2.4 DC equivalent circuit of ECDP
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Figure 2.4 DC equivalent circuit of ECDP
determined .
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Example-1
Example-1
The following specifications are given for the dual input,
balanced-output differential amplifier of fig.2.3. RC = 2.2kΩ,
RE = 4.7kΩ, Rs1= Rs2= 50 Ω , +VCC = 10V, -VEE = -10 V, dc=100
and VBE = 0.715V. Determine the operating points (ICQ and
VCEQ) of the two transistors.
The following specifications are given for the dual input,
balanced-output differential amplifier of fig.2.3. RC = 2.2kΩ,
RB = 4.7kΩ, Rs1= Rs2= 50 Ω , +VCC = 10V, -VEE = -10 V, dc=100
and VBE = 0.715V. Determine the operating points (ICQ and
VCEQ) of the two transistors.
Solution:
The value of ICQ can be obtained from eqn(1)
Solution: …cont.
The voltage VCEQ can be obtained from eqn(2)
s
Figure 2.3 The basic emitter coupled
differential pair (ECDP)
Figure 2.3 The basic emitter coupled
differential pair (ECDP)
The values of ICQ and VCEQ are same for both the
transistors.
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BJT differential pair: Small-signal Analysis: Gain
BJT differential pair: Small-signal Analysis: Gain
Since the two dc emitter currents are
equal, resistance
=
= .
 Assuming
= very small & =very large,
they have omitted from the model.
 The voltage across each collector
resistance is shown 180°out of phase with
respect to the input voltages v1 and v2.
 The collector C2 is assumed to be more
positive with respect to collector C1 even
though both are negative with respect to
ground


….(1)
….(2)
….(3)
….(4)
Figure 2.4 Small-signal model of ECDP
….(5)
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BJT differential pair: Small-signal Analysis: Gain

Applying KVL for both loops of the diagram
on the right, we have
Figure 2.4 Small-signal model of ECDP
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BJT differential pair: Small-signal Analysis: Gain
 From eqn(7) above, emitter currents can be
Assuming
&
are very small
compared with
and , these terms can be
negleced from eqn(4) & (5), & simplify to:
expressed by (using Cramer’s rule):
….(8)
….(6)
….(7)
….(9)
 The above eqn(6) & (7) can be re-written in
matrix form as:
=

+
….(7a)
+
Figure 2.4 Small-signal model of ECDP
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Which could be re-written as:
=
1
+
−
Figure 2.4 Small-signal model of ECDP
+
−
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−
+
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BJT differential pair: Small-signal Analysis: Gain

The differential output voltage
is given by:
=
−
= (0 −
….(10)
) − (0 −
=
(
−
)
=
(
−
)
BJT differential pair: Small-signal Analysis: Gain

Therefore, the differential output voltage
=
)
−
is:
….(12)
 Thus a differential amplifier amplifies the
difference between two input signals.
….(11)
 Defining the difference of input signals
=
 Substituting the current expression for from
eqn(8) & (9) in here and rearranging the
expression we have the output voltage as:
−
as:
….(13)
 The voltage gain of the dual input balanced
output differential amplifier can be given by
Figure 2.4 Small-signal model of ECDP
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BJT differential pair: Small-signal Analysis: Input Resistance
=
=
Figure 2.4 Small-signal model of ECDP
….(14)
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BJT differential pair: Small-signal Analysis: Input Resistance
 Differential input resistance is defined as the equivalent resistance
that would be measured at either input terminal with the other
terminal grounded.
 This means that the input resistance Ri1 seen from the input signal
source v1 is determined with the signal source v2 set at zero.
 Similarly, the input signal v1 is set at zero to determine the input
resistance Ri2 seen from the input signal source v2.
 Resistance RS1 and RS2 are ignored because they are very small
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BJT differential pair: Small-signal Analysis: Input Resistance
BJT differential pair: Small-signal Analysis: Output Resistance
 Substituting the expression of
eqn(8) we have:
 Differential output resistance is defined as the
equivalent resistance that would be measured at
output terminal with respect to ground.
 Therefore, the output resistance
measured
between collector C1 and ground is equal to that of
the collector resistance .
 Similarly
will be collector resistor .
from above
Similarly for Ri2
=
….(16)
The factor of 2 arises
because the of each
transistor is in series.
….(15)
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Example-2
b)
c)
….(17)
 The current gain of the differential amplifier is
undefined.
 Like CE amplifier the differential amplifier is a small
signal amplifier.
 It is generally used as a voltage amplifier and not as
current or power amplifier.
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Solution …example-2
The following specifications are given for the
dual input, balanced-output differential amplifier:
RC = 2.2 kΩ, RE = 4.7kΩ, Rs1 = Rs2 = 50Ω, +VCC= 10V, VEE = -10V, βac =100 and VBE = 0.715V.
a)
=
Determine the voltage gain.
Determine the input resistance
Determine the output resistance.
The basic emitter coupled differential pair
(ECDP)
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
The operating point of the two transistors from previous example, we have
0.988 mA and
=8.54V

The ac emitter resistance
a)
Therefore, substituting the known values in voltage gain eqn(14)
2.2 Ω
=
=
=
= 86.96 /
25.3Ω
b)
The input resistance seen from each input source is given by eqn(15) & (16)
c)
The output resistance seen looking back into the circuit from each of the two
output terminals is given by eqn(17).
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=
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Example-3
Solution …Example-3
For the dual input, balanced output differential amplifier of Example-2:
a)
Determine differential output voltage,
= 20 m
at 1 kHz.
if
= 50m
b)
What is the maximum peak-to-peak output voltage
b)
at 1 kHz and
without clipping?
Note that in case of dual input, balanced output difference amplifier, the
output voltage
is measured across the collector. Therefore, to
calculate the maximum peak to peak output voltage, we need to
determine the voltage drop across each collector resistor:
=
= 2.2 Ω 0.988
= 2.17 <
= 8.54
Solution:
a)
=
−
= 50
− 20

= (2)(4.34) = 8.68
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BJT differential pair: Common Mode Gain
In differential amplifier the differential
output voltage
is given by:
 A common mode signal
d( 1 −
2)

When
2 = 0,
0=
d 1

When
1 = 0,
0= −
d 2
is one that drives both inputs of a differential
amplifier equally.
 The common mode signal is interference, static and other undesirable pickups.
 If a differential amplifier is operating in an environment with lot of
electromagnetic interference, each base picks up an unwanted interference
voltage.
 If both the transistors were matched in all respects, then the balanced output
would be theoretically zero
Therefore the input voltage 1 is called
the non-inventing input because a
positive voltage 1 acting alone
produces a positive output voltage 0
 DA discriminates against common mode input signals.
 In other words, it refuses to amplify the common mode signals,
Similarly, the positive voltage 2 acting
alone produces a negative output
voltage hence 2 is called inverting
input.
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BJT differential pair: Inverting and Non-Inverting Inputs
0d =

In other words, the maximum peak to peak output voltage without clipping is
* 86.96 = 2.61
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
This means that the maximum change in voltage across each collector
resistor is ± 2.17 (ideally) or 4.34
We have determined the voltage gain of the dual input, balanced output
differential amplifier. Substituting this voltage gain (
= 86.96) and
given values of input voltages in eqn(12), we get
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BJT differential pair: Common Mode Gain
BJT differential pair: Common Mode Gain
The practical effectiveness of rejecting the common signal depends on the
degree of matching between the two CE stages forming the differential
amplifier.
 In practical differential amplifier, the output depends not only on difference
signal
but also upon the common mode signal
(average).
1
…(a)
=
−
= ( + )
2
 The output voltage, under the condition that input-2 (1) is grounded:

=
where
+
=
=
and
=
−

1
1
…(c)
=
−
2
2
 Substituting eqn(c) into eqn(b) for the input voltages results in an output
voltage of:
−0 =
and
0 −
=−
are voltage amplifications from input-1 (2) to output
=
(
+
)−
+
+
+
(
−
)
−
…(d)
= differential mode gain
= common mode gain
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Dual Input, Unbalanced Output Differential Amplifier
In this case, two input signals are given
however the output is measured at only
one of the two-collector w.r.t. ground.
 DC analysis: exactly same as that Dualinput balanced-output(DIBO)
CMRR is a measure of how well the differential amplifier rejects the
common-mode input voltage in favor of the differential-input
voltage.

…(e)

 Therefore, the differential amplifier should be designed so that
ρ is large compared with the ratio of the common mode signal
to the difference signal.
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+
where,
Common mode rejection ratio (CMRR)

=
1
=
2
=
…(b)
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By adding & subtracting the two equations of eqn(a) above,
AC analysis: The output voltage gain in
this case is given by:
Dual-input unbalanced-output ECDP
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Biasing of Differential Amplifiers
Differential amplifier with swamping resistors

In the dc analysis of differential amplifier,
we have seen that the emitter current IE
depends upon the value of
.
 To make operating point stable,
should
be constant irrespective value of
.
By using external resistors R′ in series with each emitter, the
dependence of voltage gain on variations of r′ can be reduced. It
also increases the linearity range of the differential amplifier.
=

=

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This means that should very high to
maintain
constant.
Fig. DIBO ECDP
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Biasing of Differential Amplifiers: Constant Current Bias
Biasing of Differential Amplifiers: Constant Current Bias
This can be achieved by having constant
current biasing through Q3 as shown in fig
 Applying KVL in base of Q3, we have


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Because the two halves of the differential amplifiers are symmetrical,
each has half of the current IC3
The collector current, IC3 in transistor Q3 is fixed because no signal is
injected Into either the emitter or the base of Q3
 Besides supplying constant emitter current, the constant current bias
also provides a very high source resistance since the ac equivalent of
the dc source is ideally an open circuit.
 Therefore, all the performance equations obtained for differential
amplifier using emitter bias are also valid.

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Fig. DIBO constant current biased circuit
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Biasing of Differential Amplifiers: Constant Current Bias
Biasing of Differential Amplifiers: Constant Current Bias
As seen in the IE expressions, current depends upon the VBE3. If the temperature
changes, VBE changes and current IE also changes.
 To improve the thermal stability, a diode is placed in series with the resistance R1
as


By applying KVL to the base circuit of Q3.
Thus, the current IE3 is constant and independent of the
temperature due to the added diode D. In the absence of
D the current would vary with temperature because VBE3
decreases approximately by 2mV/°C.
Assuming Ib3≅ 0
Substituting equation
(*) in equation(**)
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Example-4
Biasing of Differential Amplifiers: Constant Current Bias
Zener diode can be used in place of the diodes and resistance as shown in the
figure 3. Zeners are available over the wide range of voltages and can have the
matching temperature coefficient
 The voltage at base of transistor Q3 is

2.3
Value of R2 is selected so that I2 >> 1.2IZ(min) here IZ(min) is minimum current needed
to cause the zener diode to conduct in reverse region, which is to block the rated
voltage VZ.
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Fig 2.3 DIBO ECDP
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Example-5
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What is the input impedance of the following circuit when i) Vin = 1mV ii) Vin = -1mV?
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Example-8
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References
Design a Zener constant current bias circuit as shown in fig. below according to
the following specifications. Emitter current -IE = 5 mA, Zener diode with Vz = 4.7V
and Iz = 53mA, βac = βdc = 100, VBE = 0.715V, supply voltage -VEE = -9V.

Solution:

Chapter 9 of S&S: Microelectronic Circuits
Chapter 11 of Donald A. Neamen, Microelectronics: Circuit Analysis and Design
Applying KVL,
Practically we use RE = 820 kΩ
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