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Ver.
2.6
Eff_Date
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ECN No.
E120201933134
Author
M. H. Yang
(PDS)
Change Description
Please refer to Appendix A.13 Revision
History for the update from V2.5 to V2.6.
2.5_R
10-31-18
E120201842189
M. H. Yang
(PDS)
Correct attached seal ring gds file names.
No any rule and gds content change.
2.5
09-19-18
E120201838097
M. H. Yang
(PDS)
Please refer to Appendix A.12 Revision
History for the update from V2.4 to V2.5.
2.4
07-29-16
E120201631098
M. S. Hsieh
(PDS)
Please refer to Appendix A.11 Revision
History for the update from V2.3 to V2.4.
Approvals :
Title
Please refer to EDW workflow to see detail approval
records
TSMC 45/40 NM CMOS LOGIC AND
MS_RF DESIGN RULE
(CLN45LP/LPG, CLN40LP/LPG/LP+,
CLN40G)
Document No. : T-N45-CL-DR-001
Contents
Attach.
Total
: 600
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: 600
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Ver.
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Eff_Date
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ECN No.
E120201531138
Author
Y. L. Chen
(PDS)
Change Description
Please refer to Appendix A.10 Revision
History for the update from V2.2 to V2.3.
2.2
12-01-14
E120201436190
Y. L. Chen
(PDS)
Please refer to Appendix A.9 Revision
History for the update from V2.1 to V2.2
2.1
06-28-13
E120201316032
Y. L. Chen
(PDS)
1.Please refer to Appendix A.8 Revision
History for the update from V2.0 to V2.1.
2.Change title
2.0
07-31-12
E120201231088
C. M. Kao
(PDS)
Please refer to Appendix A.7 Revision
History for the update from V1.3_1 to V2.0.
1.3_1
12-15-10
E070201048072
C. M. Kao
(PDS)
Please refer to Appendix A.6 Revision
History for the update from V1.3 to V1.3_1.
1.3
09-03-10
E070201036011
M. C. Lee
(PDS)
Please refer to Appendix A.5 Revision
History for the update from V1.2 to V1.3.
1.2
09-30-09
E070200935010
Y. M. Chen
Please refer to Appendix A.4 Revision
History for the update from V1.1 to V1.2.
1.1
06-30-08
E120200826098
C. H. Lu
Please refer to Appendix A.3 Revision
History for the update from V1.0 to V1.1.
1.0
01-31-08
E120200802093
C. H. Lu
Please refer to Appendix A.2 Revision
History for the update from V0.2 to V1.0.
0.2
10-18-07
E120200742028
C. H. Lu
Please refer to Appendix A.1 Revision
History for the update from V0.1 to V0.2.
0.1
04-04-07
E120200713104
C. T. Tsai
Provide the official N45GS design rule
manual
0.04
01-05-07
E120200704034
C. T. Tsai
Original
Title
TSMC 45/40 NM CMOS LOGIC AND
MS_RF DESIGN RULE
(CLN45LP/LPG, CLN40LP/LPG/LP+,
CLN40G)
Document No. : T-N45-CL-DR-001
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: 2.6
TSMC 45/40 NM CMOS LOGIC AND MS_RF DESIGN RULE
(CLN45LP/LPG, CLN40LP/LPG/LP+, CLN40G)
Table of Contents
1 INTRODUCTION ................................................................................................................................................................. 8
1.1
1.2
OVERVIEW .................................................................................................................................................................. 8
REFERENCE DOCUMENT ............................................................................................................................................. 9
2 TECHNOLOGY OVERVIEW ............................................................................................................................................. 12
2.1
SEMICONDUCTOR PROCESS ...................................................................................................................................... 12
2.1.1
Front-End Features ......................................................................................................................................... 12
2.1.2
Back-End Features.......................................................................................................................................... 14
2.2
DEVICES................................................................................................................................................................... 15
2.3
POWER SUPPLY AND OPERATION TEMPERATURE RANGES.......................................................................................... 16
2.4
CROSS–SECTION ...................................................................................................................................................... 17
2.5
METALLIZATION OPTIONS .......................................................................................................................................... 23
3 GENERAL LAYOUT INFORMATION ............................................................................................................................... 27
3.1
MASK INFORMATION, KEY PROCESS SEQUENCE, AND CAD LAYERS............................................................................ 27
3.2
METAL/VIA CAD LAYER INFORMATION FOR METALLIZATION OPTIONS ......................................................................... 51
3.3
DUMMY PATTERN FILL CAD LAYERS ......................................................................................................................... 53
3.4
SPECIAL RECOGNITION CAD LAYER SUMMARY .......................................................................................................... 54
3.5
DEVICE TRUTH TABLES ............................................................................................................................................. 58
3.5.1
N45/N40 Low Power (LP): 1.1V Core Design ................................................................................................. 59
3.5.2
N40 Low Power Plus (N40LP+): 1.1V Core and 2.5V I/O Design .................................................................. 61
3.5.3
N45LPG/N40LPG: 1.1V/0.9V Core Design ..................................................................................................... 62
3.5.4
N40G (N45GS) General Purpose Superb: 0.9V Core Design ........................................................................ 64
3.5.5
MOM ................................................................................................................................................................ 65
3.5.6
Inductor ........................................................................................................................................................... 67
3.6
MASK REQUIREMENT FOR DEVICE OPTIONS (HIGH/STD/LOW VT/ULTRA LOW VT PLUS).............................................. 69
3.7
DESIGN GEOMETRY RESTRICTIONS ........................................................................................................................... 70
3.7.1
Design Grid Rules ........................................................................................................................................... 70
3.7.2
OPC Recommendations and Guidelines ........................................................................................................ 71
3.8
DESIGN HIERARCHY GUIDELINES ............................................................................................................................... 73
3.9
CHIP IMPLEMENTATION AND TAPE OUT CHECKLIST ..................................................................................................... 74
4 LAYOUT RULES AND RECOMMENDATIONS ............................................................................................................... 75
4.1
LAYOUT RULE CONVENTIONS .................................................................................................................................... 75
4.2
DERIVED GEOMETRIES USED IN PHYSICAL DESIGN RULES.......................................................................................... 76
4.2.1
Derived Geometries ........................................................................................................................................ 76
4.2.2
Special Definition............................................................................................................................................. 77
4.3
DEFINITION OF LAYOUT GEOMETRICAL TERMINOLOGY ................................................................................................ 78
4.4
MINIMUM PITCHES .................................................................................................................................................... 86
4.5
LAYOUT RULES AND GUIDELINES ............................................................................................................................... 87
4.5.1
Gate Oxide and Diffusion (OD) Layout Rules (Mask ID: 120) ........................................................................ 87
4.5.2
Deep N-Well (DNW) Layout Rules (Mask ID: 119) [Optional] ........................................................................ 91
4.5.3
N-Well (NW) Layout Rules .............................................................................................................................. 94
4.5.4
N-Well Resistor Within OD (NWROD) Layout Rules ...................................................................................... 95
4.5.5
N-Well Resistor Under STI (NWRSTI) Layout Rules ...................................................................................... 97
4.5.6
Native Device (NT_N) Layout Rules ............................................................................................................... 98
4.5.7
Thick Oxide (OD2) Layout Rules (Mask ID: 152) .......................................................................................... 100
4.5.8
Dual Core Oxide (DCO) Layout Rules (Mask ID: 153) ................................................................................. 102
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.9
1.2V Core Oxide (OD_12) Layout Rules (Mask ID: 12A).............................................................................. 104
4.5.10 OD25_33 Layout Rules ................................................................................................................................. 106
4.5.11 OD25_18 Layout Rules ................................................................................................................................. 107
4.5.12 OD18_15 Layout Rules ................................................................................................................................. 108
4.5.13 Poly (PO) Layout Rules (Mask ID: 130) ........................................................................................................ 109
4.5.14 High Vt NMOS (VTH_N) Layout Rules (Mask ID: 11H) ................................................................................ 116
4.5.15 High Vt PMOS (VTH_P) Layout Rules (Mask ID: 11G) ................................................................................ 117
4.5.16 Low Vt NMOS (VTL_N) Layout Rules (Mask ID: 118) .................................................................................. 118
4.5.17 Low Vt PMOS (VTL_P) Layout Rules (Mask ID: 117) .................................................................................. 119
4.5.18 Ultra Low Vt Plus Devices Layout Rules ....................................................................................................... 120
4.5.19 P+ Source/Drain Ion Implantation (PP) Layout Rules (Mask ID: 197) .......................................................... 124
4.5.20 N+ Source/Drain Ion Implantation (NP) Rules (Mask ID: 198) ..................................................................... 126
4.5.21 Layout Rules for LDD Mask Logical Operations ........................................................................................... 128
4.5.22 Resist Protection Oxide (RPO) Layout Rules (Mask ID: 155) ...................................................................... 130
4.5.23 OD and Poly Resistor Layout Rules.............................................................................................................. 131
4.5.24 HVMOS_25 Layout Rules ............................................................................................................................. 133
4.5.25 HVMOS_18 Layout Rules ............................................................................................................................. 139
4.5.26 HVMOS Guard-Ring Rules and Guidelines for HVMOS_25 and HVMOS_18 ............................................. 145
4.5.27 MOS Varactor Layout Rules (VAR)............................................................................................................... 146
4.5.28 Contact (CO) Layout Rules (Mask ID: 156) .................................................................................................. 149
4.5.29 Metal-1 (M1) Layout Rules (Mask ID: 360) ................................................................................................... 152
4.5.30 VIAx Layout Rules (Mask ID: 378, 379, 373, 374, 375, 376, 377) ................................................................ 159
4.5.31 Mx Layout Rules (Mask ID: 380, 381, 384, 385, 386, 387, 388) .................................................................. 165
4.5.32 LOWMEDN Layout Rules ............................................................................................................................. 172
4.5.33 VIAy Layout Rules (Mask ID: 379, 373, 374, 375, 376, 377, 372, 37A) ....................................................... 174
4.5.34 My Layout Rules (Mask ID: Second Inter-layer Metal (385, 386, 387, 388) and Top Metal (381, 384, 385,
386, 387, 388, 389, 38A)) ............................................................................................................................................ 179
4.5.35 Top VIAz Layout Rules (Mask ID: 379, 373, 374, 375, 376, 377, 372, 37A) ................................................ 182
4.5.36 Top Mz Layout Rules (Mask ID: 381, 384, 385, 386, 387, 388, 389, 38A) ................................................... 186
4.5.37 Top VIAr Layout Rules (Mask ID: 375, 376, 377, 372, 37A) ......................................................................... 188
4.5.38 Top Mr Layout Rules (Mask ID: 386, 387, 388, 389, 38A) ........................................................................... 191
4.5.39 RV Layout Rules (Mask ID: 306)................................................................................................................... 193
4.5.40 Al Redistributional Layer (AP RDL) Layout Rules (Mask ID: 309) ................................................................ 194
4.5.41 Via Layout Recommendations ...................................................................................................................... 196
4.5.42 MOM Layout Rules........................................................................................................................................ 197
4.5.43 Top VIAu Layout Rules (Mask ID: 373, 374, 375, 376, 377, 372, 37A) ........................................................ 203
4.5.44 Mu (Ultra Thick Metal) Layout Rules ............................................................................................................. 204
4.5.45 Inductor Layout Rules ................................................................................................................................... 206
4.5.46 Introduction of Inductor and Transmission Line ............................................................................................ 215
4.5.47 SRAM Rules .................................................................................................................................................. 219
4.5.48 NPreDOSRM (50;21) Layout Rules .............................................................................................................. 225
4.5.49 SRAM Periphery (Word Line Driver) Rules ................................................................................................... 227
4.5.50 SRAM CO2 (100;0) Layout Rule for Embedded DRAM (eDRAM) Process ................................................. 228
4.5.51 ROM Rules .................................................................................................................................................... 229
4.5.52 Antenna Effect Prevention (A) Layout Rules ................................................................................................ 230
4.5.53 Product Labels and Logo Rules .................................................................................................................... 235
4.5.54 Seal Ring Overview ....................................................................................................................................... 236
4.5.55 Resistor Warning Rules ................................................................................................................................ 276
4.5.56 DRM and DRC Completeness ...................................................................................................................... 277
5 LAYOUT GUIDELINES FOR THE DEVICE GEOMETRY EFFECT ............................................................................... 278
5.1
LAYOUT RULES FOR THE WPE (W ELL PROXIMITY EFFECT)....................................................................................... 278
5.2
LAYOUT GUIDELINES FOR LOD (LENGTH OF THE OD REGION) EFFECT ...................................................................... 282
5.2.1
What is LOD? ................................................................................................................................................ 282
5.2.2
How to have a precise LOD Simulation ........................................................................................................ 282
5.3
LAYOUT GUIDELINES FOR OSE (OD SPACE EFFECT) ............................................................................................... 283
5.3.1
What is OSE? ................................................................................................................................................ 283
5.3.2
Id change on device due to OSE .................................................................................................................. 283
5.3.3
How to reduce the differences between pre-simulation and post-simulation ............................................... 284
5.4
LAYOUT GUIDELINES FOR PSE (POLY SPACE EFFECT) ............................................................................................. 287
5.4.1
What is PSE? ................................................................................................................................................ 287
5.4.2
Id change on device due to PSE ................................................................................................................... 287
5.4.3
How to reduce the differences between pre-simulation and post-simulation on N40G circuit? ................... 287
5.5
LAYOUT GUIDELINES FOR D-CESL EFFECT .............................................................................................................. 288
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
What is d-CESL effect? ................................................................................................................................. 288
Id change on the N40G device due to d-CESL ............................................................................................. 288
How to reduce the differences between pre-simulation and post-simulation on N40G circuit? ................... 289
6 N40LP/LPG DESIGN INFORMATION ............................................................................................................................ 291
6.1
NON-SHRINKABLE LAYOUT RULES ........................................................................................................................... 291
6.1.1
Purpose: ........................................................................................................................................................ 291
6.1.2
Non-shrinkable Rules .................................................................................................................................... 291
6.1.3
Stress Migration and Wide Metal Spacing Rules Adjustment (Rule Relaxing) ............................................. 292
6.1.4
Pad Rule for Wire Bond ................................................................................................................................ 294
6.1.5
Flip Chip Bump Rules ................................................................................................................................... 294
6.2
DESIGN FLOW FOR TAPE-OUT ................................................................................................................................ 295
6.2.1
How to design for CLN40LP/LPG shrink technology .................................................................................... 295
6.2.2
How to prepare a new design of CLN40LP/LPG .......................................................................................... 295
6.2.3
CLN45LP/LPG Design Migration to CLN40LP/LPG Technology .................................................................. 296
6.2.4
Layout check and post simulation ................................................................................................................. 297
7 LAYOUT RULES AND RECOMMENDATIONS FOR ANALOG CIRCUITS .................................................................. 301
7.1
USER GUIDES ......................................................................................................................................................... 301
7.2
LAYOUT RULES, RECOMMENDATIONS AND GUIDELINES FOR THE ANALOG DESIGNS ................................................... 302
7.2.1
General Guidelines........................................................................................................................................ 302
7.2.2
MOS Recommendations ............................................................................................................................... 303
7.2.3
Bipolar Transistor (BJT) Rules and Recommendations ................................................................................ 304
7.2.4
Resistor Rules ............................................................................................................................................... 305
7.2.5
Capacitor Guidelines ..................................................................................................................................... 306
7.3
LAYOUT RULES AND GUIDELINES FOR DEVICE PLACEMENT ....................................................................................... 307
7.3.1
General Rules and Guidelines ...................................................................................................................... 307
7.3.2
Matching Rules and Guidelines .................................................................................................................... 308
7.3.3
Electrical Performance Rules and Guidelines ............................................................................................... 315
7.3.4
Noise ............................................................................................................................................................. 320
7.4
BURN-IN GUIDELINES FOR ANALOG CIRCUITS ........................................................................................................... 323
8 DUMMY PATTERN RULE AND FILLING GUIDELINE .................................................................................................. 325
8.1
DUMMY OD (DOD/SR_DOD) RULES AND GUIDELINES ............................................................................................ 325
8.1.1
DOD Layout Rules ........................................................................................................................................ 326
8.1.2
SR_DOD Layout Rules ................................................................................................................................. 328
8.2
DUMMY POLY (DPO/SR_DPO) RULES AND GUIDELINES ......................................................................................... 330
8.2.1
DPO Layout Rules......................................................................................................................................... 331
8.2.2
SR_DPO Layout Rules ................................................................................................................................. 332
8.3
DUMMY TCD RULE AND FILLING GUIDELINE ............................................................................................................. 334
8.3.1
Dummy TCD Rules ....................................................................................................................................... 334
8.3.2
Dummy TCD layout Summary ...................................................................................................................... 338
8.4
DUMMY TCD DESIGN INFORMATION ........................................................................................................................ 339
8.4.1
Overview ....................................................................................................................................................... 339
8.4.2
Design Consideration of Dummy TCD Insertion ........................................................................................... 339
8.4.3
Dummy TCD Macro Placement .................................................................................................................... 340
8.4.4
P&R Dummy TCD Rule Check ..................................................................................................................... 341
8.4.5
Dummy TCD Macros Insertion Flow ............................................................................................................. 341
8.4.6
TCD Library Kits ............................................................................................................................................ 342
8.5
IN CHIP OVERLAY (ICOVL) RULE AND FILLING GUIDELINE........................................................................................ 343
8.5.1
In Chip Overlay (ICOVL) Rules ..................................................................................................................... 343
8.5.2
ICOVL layout Summary ................................................................................................................................ 349
8.5.3
N40 In-Chip OVL Marker Design Insertion Methodology .............................................................................. 350
8.6
DUMMY METAL (DM) RULES ................................................................................................................................... 353
8.7
DUMMY VIA (DVIAX) RULES ................................................................................................................................... 357
8.8
DUMMY PATTERN FILL USAGE SUMMARY ................................................................................................................. 359
8.8.1
Dummy Pattern Filling Requirements ........................................................................................................... 359
8.8.2
Recommended Flow for Dummy Pattern Filling ........................................................................................... 360
8.8.3
Blockage Layer (ODBLK/POBLK/DMxEXCL/ DVIAxEXCL) Requirements and Recommendations ........... 361
8.8.4
Dummy Pattern Filling Guidelines ................................................................................................................. 362
8.8.5
Mask Revision Guidelines ............................................................................................................................. 363
8.8.6
Dummy Pattern Re-fill Evaluation Flow Chart ............................................................................................... 364
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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9 DESIGN FOR MANUFACTURING (DFM) ...................................................................................................................... 368
9.1
LAYOUT GUIDELINES FOR YIELD ENHANCEMENT....................................................................................................... 368
9.1.1
Layout Tips for Minimizing Critical Areas ...................................................................................................... 368
9.1.2
Guidelines for Optimal Electrical Model and Silicon Correlation ................................................................... 371
9.1.3
Electrical Wiring............................................................................................................................................. 378
9.1.4
Guidelines for Mask Making Efficiency ......................................................................................................... 378
9.2
DFM RECOMMENDATIONS AND GUIDELINES SUMMARY............................................................................................. 379
9.2.1
Action-Required Rules .................................................................................................................................. 379
9.2.2
Recommendations ........................................................................................................................................ 380
9.2.3
Guidelines ..................................................................................................................................................... 385
9.2.4
Grouping Table of Recommendations .......................................................................................................... 386
9.3
GDA DIE SIZE OPTIMIZATION KIT ............................................................................................................................ 389
9.3.1
What is MFU?................................................................................................................................................ 390
9.3.2
Design Guidelines for Higher MFU ............................................................................................................... 390
9.3.3
Recommended GDA criteria MFU > 80% ..................................................................................................... 390
9.3.4
MFU Reference Table for N45 ...................................................................................................................... 391
9.3.5
MFU Reference Table for N40 ...................................................................................................................... 392
10 LAYOUT GUIDELINES FOR LATCH-UP AND I/O ESD .............................................................................................. 393
10.1 LAYOUT RULES AND GUIDELINES FOR LATCH-UP PREVENTION .................................................................................. 394
10.1.1 Latch-up Introduction .................................................................................................................................... 394
10.1.2 Layout Rules and Guidelines for Latch-up Prevention.................................................................................. 397
10.1.3 Test Specification and Requirements ........................................................................................................... 416
10.2 I/O ESD PROTECTION CIRCUIT DESIGN, LAYOUT RULES AND GUIDELINES ................................................................ 417
10.2.1 ESD introduction ........................................................................................................................................... 417
10.2.2 TSMC IO ESD layout style introduction ........................................................................................................ 420
10.2.3 ESD Implant (ESDIMP) Layout Rules (MASK ID: 111) ................................................................................ 422
10.2.4 SR_ESD device Layout Rules (N40G only) .................................................................................................. 423
10.2.5 ESD Dummy Layers Summary ..................................................................................................................... 424
10.2.6 ESD circuits Definition ................................................................................................................................... 425
10.2.7 Requirements for ESD Implant Masks .......................................................................................................... 426
10.2.8 DRC methodology for ESD guidelines .......................................................................................................... 426
10.2.9 ESD Guidelines ............................................................................................................................................. 431
10.3 ESD BACK-END RELIABILITY GUIDELINES ................................................................................................................ 456
10.3.1 Test Methodology .......................................................................................................................................... 456
10.3.2 Failure Mechanism ........................................................................................................................................ 457
10.3.3 Maximum ESD Current Density for Resistor ................................................................................................. 457
10.3.4 Maximum ESD Current Density for Via and Metal ........................................................................................ 458
10.3.5 Minimum ESD Current for ESD Device......................................................................................................... 459
10.4 TIPS FOR THE ESD/LATCHUP DESIGN ...................................................................................................................... 460
10.4.1 Tips for General Latchup Design .................................................................................................................. 460
10.4.2 Tips for General ESD Design ........................................................................................................................ 460
10.4.3 Tips for Power-Ground ESD Protection ........................................................................................................ 462
10.4.4 Tips for MOS gate directly connected to power/ground/IO PAD .................................................................. 463
10.5 ESD TESTING METHODOLOGY ................................................................................................................................. 466
10.5.1 Stress condition and Measurement condition ............................................................................................... 466
10.5.2 Failure criteria................................................................................................................................................ 466
11 CLN45LP/LPG RELIABILITY RULES .......................................................................................................................... 467
11.1 TERMINOLOGY ........................................................................................................................................................ 467
11.2 FRONT-END PROCESS RELIABILITY RULES AND MODELS .......................................................................................... 467
11.2.1 I/O Over Drive Voltage .................................................................................................................................. 467
11.2.2 Gate Oxide Integrity ...................................................................................................................................... 467
11.2.3 Hot Carrier Injection Effect ............................................................................................................................ 470
11.2.4 Negative Bias Temperature Instability (NBTI) ............................................................................................... 473
11.2.5 N45 Poly Current Density .............................................................................................................................. 475
11.2.6 N45 Poly EM Joule heating ........................................................................................................................... 475
11.2.7 N45 OD Current Density ............................................................................................................................... 476
11.3 BACK-END PROCESS RELIABILITY RULES................................................................................................................. 477
11.3.1 Stress Migration (SM) ................................................................................................................................... 477
11.3.2 Low-k Dielectric Integrity ............................................................................................................................... 477
11.3.3 Cu Metal Current Density (EM) Specifications .............................................................................................. 478
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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AP RDL Current Density (EM) Specifications ............................................................................................... 484
Cu Metal AC Operation ................................................................................................................................. 485
AP RDL AC Operation .................................................................................................................................. 494
12 CLN40LP/LPG/45GS(=40G) RELIABILITY RULES .................................................................................................... 495
12.1 TERMINOLOGY ........................................................................................................................................................ 495
12.2 FRONT-END PROCESS RELIABILITY RULES AND MODELS .......................................................................................... 495
12.2.1 I/O Over Drive Voltage .................................................................................................................................. 495
12.2.2 Gate Oxide Integrity ...................................................................................................................................... 495
12.2.3 Hot Carrier Injection Effect ............................................................................................................................ 499
12.2.4 Negative Bias Temperature Instability (NBTI) ............................................................................................... 502
12.2.5 N40 Poly Current Density .............................................................................................................................. 504
12.2.6 N40 Poly EM Joule heating ........................................................................................................................... 504
12.2.7 N40 OD Current Density ............................................................................................................................... 505
12.3 BACK-END PROCESS RELIABILITY RULES................................................................................................................. 506
12.3.1 Stress Migration (SM) ................................................................................................................................... 506
12.3.2 Low-k Dielectric Integrity ............................................................................................................................... 506
12.3.3 Cu Metal Current Density (EM) Specifications .............................................................................................. 508
12.3.4 AP RDL Current Density (EM) Specifications ............................................................................................... 514
12.3.5 Cu Metal AC Operation ................................................................................................................................. 515
12.3.6 AP RDL AC Operation .................................................................................................................................. 526
13 APPENDIX A REVISION HISTORY .............................................................................................................................. 527
A.1 FROM VERSION 0.1 TO 0.2........................................................................................................................................... 527
A.2 FROM VERSION 0.2 TO 1.0........................................................................................................................................... 537
A.3 FROM VERSION 1.0 TO 1.1........................................................................................................................................... 539
A.4 FROM VERSION 1.1 TO 1.2........................................................................................................................................... 544
A.5 FROM VERSION 1.2 TO 1.3........................................................................................................................................... 563
A.6 FROM VERSION 1.3 TO 1.3_1....................................................................................................................................... 565
A.7 FROM VERSION 1.3_1 TO 2.0....................................................................................................................................... 567
A.8 FROM VERSION 2.0 TO 2.1........................................................................................................................................... 592
A.9 FROM VERSION 2.1 TO 2.2........................................................................................................................................... 595
A.10 FROM VERSION 2.2 TO 2.3......................................................................................................................................... 597
A.11 FROM VERSION 2.3 TO 2.4......................................................................................................................................... 599
A.12 FROM VERSION 2.4 TO 2.5......................................................................................................................................... 599
A.13 FROM VERSION 2.5 TO 2.6......................................................................................................................................... 600
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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1 Introduction
This chapter has been divided into the following topics:
1.1
Overview
1.2
Reference document
1.1
Overview
This document provides all the rules and reference information for the design and layout of integration circuits
using the TSMC 45 nm CMOS LOGIC 1P10M (single poly, 10 metal layers), salicide, Cu technology. These
rules and information about other specifications apply to TSMC semiconductor process: CLN45LP, CLN40LP,
CLN40LP+, CLN45LPG, N40LPG, N40G (= N45GS), and N45/N40 MSRF.





CLN45LP is a low-power product for applications with an 1.1V core design and with an 1.8V or a 2.5V
capable I/O’s.
CLN40LP is a low-power product which is 90% linear shrinkage from CLN45LP layout dimension for
applications with an 1.1V core design, and with an 1.8V or a 2.5V capable I/O’s.
CLN40LP+ (40nm low power plus) is a low-power product for applications with an 1.1V core design and
with a 2.5V capable I/O’s by adding ultra low Vt plus devices into TSMC 40nm CMOS logic low power
(CLN40LP) process.
CLN45LPG is a low-power and low standby power product for applications with both 1.1V (LP) and 0.9V
(G) core designs and with an 1.8V capable I/O’s.
CLN40LPG is a low-power and low standby power product which is 90% linear shrinkage from CLN45
layout dimension for applications with both 1.1V (LP) and 0.9V (G) core designs and with a 3.3V capable
I/O’s. If you want to shrink CLN45LPG to CLN40LPG, you must redesign 3.3V I/O since 1.8V I/O cannot
be shrunk in LPG process.

N40G (= N45GS) is a general-purpose product which is 90% linear shrinkage from 45nm layout
dimension for applications with a 0.9V core design and with 1.8V, 2.5V capable I/O’s.

N45/N40 MSRF process can adopt the regular logic processes (CLN45LP/ CLN40LP/ CLN45LPG/
CLN40LPG/ CLN40G (=CLN45GS)), or adopt an ultra thick metal (Mu: 34KÅ or 35KÅ ) as the most top
metal layer (Mu layer only can be used as the most top metal layer).
In this document, figures and tables are usually numbered with 3 digits. The first two digits indicate section
number and the last one is sequence number. For example, Table 1.2.1 is the first table in the section 1.2 of
Chapter 1.
Warning: All tape-outs MUST be DRC clean.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Reference Document
Table 1.2.1
Reference Documents
Content
GDS layer usage
DRC deck
Wire bond and EU Flip Chip
DRM
Wire bond and EU Flip Chip
DRC deck
DENMOS DRM
LF Flip Chip DRM
LF Flip Chip DRC
Dummy pattern generation
utility
DFM guideline
DFM utility
SPICE
Confidential – Do Not Copy
Reference Document
 T-N45-CL-LE-001
TSMC 45/40 NM GENERAL PURPOSE GDS LAYER USAGE DESCRIPTION FILE
 T-N45-CL-DR-001-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45 NM CMOS LOGIC AND 40NM CMOS LOGIC DRC COMMAND FILE (CLN45LP/LPG, CLN40LP/LPG,
CLN40G)
 T-N45-CL-DR-003
TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND INTERCONNECTION DESIGN RULE
 T-N45-CL-DR-003-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND INTERCONNECTION DRC COMMAND FILE
 T-N40-CM-DR-004
TSMC 40 NM RF HIGH VOLTAGE NMOS (DEMOS) DESIGN RULE
 T-N45-CL-DR-017
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD UP SUBSTRATE (FCBGA, FLIP CHIP BALL
GRID ARRAY) AND INTERCONNECTION DESIGN RULE
 T-N45-CL-DR-022
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH LAMINATE SUBSTRATE (FCCSP, FLIP CHIP CHIP
SCALE PACKAGE) AND INTERCONNECTION DESIGN RULE
 T-N45-CL-DR-017-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD UP SUBSTRATE (FCBGA, FLIP CHIP BALL
GRID ARRAY) AND INTERCONNECTION DRC COMMAND FILE
 T-N45-CL-DR-022-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH LAMINATE SUBSTRATE (FCCSP, FLIP CHIP CHIP
SCALE PACKAGE) AND INTERCONNECTION DRC COMMAND FILE
 T-N45-CL-DR-001-X2 (X is the code of EDA tool. Please refer to TSMC-Online for the details)
TSMC 45NM CMOS LOGIC DUMMY OD/PO GENERATION UTILITY
 T-N45-CL-DR-001-X3 (X is the code of EDA tool. Please refer to TSMC-Online for the details)
TSMC 45NM CMOS LOGIC DUMMY METAL GENERATION UTILITY
 T-N40-CL-RP-020
TSMC 40 NM CMOS LOGIC GENERAL PURPOSE DFM ROLLOUT PACKAGE REPORT
 T-N40-CL-RP-016
TSMC N45/N40 LAYOUT GUIDELINES FOR LAYOUT ENVIRONMENT AND CO PLACEMENT
 T-N45-CL-DR-001-X4 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45NM DFM REDUNDANT VIA UTILITY
 T-N45-CL-SP-001
TSMC 45NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE Cu_ELK 1.1V/1.8V SPICE MODELS
(CLN45LP)
 T-N45-CL-SP-012
TSMC 45 NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1V/2.5V SPICE MODELS
(CLN45LP)
 T-N45-CL-SP-051
TSMC 45 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+AL_RDL SALICIDE CU_ELK 2.5V SPICE
MODELS 45LP
 T-N40-CL-SP-040
TSMC 40 NM CMOS LOGIC GENERAL PURPOSE SALICIDE 1P10M_7X2Z+UT-ALRDL CU_ELK HD BEOL SPICE
MODEL 40G
 T-N45-CE-SP-001
TSMC 45 NM CMOS EMBEDDED DRAM GENERAL PURPOSE SUPERB 1P8M_5X2R_UT-ALRDL SALICIDE
CU_LOWK 0.9V&1.4V SPICE MODELS 40G (CLN45GS EDRAM)
 T-N40-CL-SP-038
TSMC 40 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+AL_RDL SALICIDE CU_ELK 1.8V SPICE
MODELS 40LP
 T-N40-CL-SP-034
TSMC 40 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+ AL_RDL SALICIDE CU_ELK 2.5V SPICE
MODEL 40LP
 T-N40-CL-SP-041
TSMC 40 NM CMOS LOGIC LOW POWER SALICIDE 1P10M_7X2Z+UT-ALRDL CU_ELK HD BEOL SPICE
MODEL 40LP
 T-N40-CL-SP-031-P1
TSMC 40 NM CMOS LOGIC LP-BASED TRIPLE GATE OXIDE WITH DUAL CORE 1P10M+AL_RDL SALICIDE
ELK CU 0.9/1.1/3.3V SPICE MODEL 40LPG (PRE-RELEASE)
 T-N40-CE-SP-001
TSMC 40 NM CMOS EMBEDDED DRAM LOW POWER 1P8MT2 (2XTM : M7-M8) SALICIDE CU_LOWK
1.1V&1.5V SPICE MODELS (CLN40LP EDRAM)
 T-N40-CL-SP-051
TSMC 40 NM CMOS LOGIC LOW POWER PLUS 1P10M SALICIDE CU_ELK 1.1/2.5V SPICE MODEL 40LE
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Device formation examples
and LVS properties
LVS
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Reference Document
 T-N40-CL-SP-038
TSMC 40 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+AL_RDL SALICIDE CU_ELK 1.8V SPICE
MODELS 40LP
 T-N40-CL-SP-034
TSMC 40 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+ AL_RDL SALICIDE CU_ELK 2.5V SPICE
MODEL 40LP
 T-N40-CL-SP-032
TSMC 40NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1V/1.8V SPICE MODELS 40LP
 T-N40-CL-SP-004
TSMC 40NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1V/2.5V SPICE MODELS 40LP
 T-N45-CL-SP-012
TSMC 45NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE Cu_ELK 1.1V/2.5V SPICE MODELS
(CLN45LP)
 T-N45-CL-SP-010
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL_RDL SALICIDE CU_ELK 0.9V/1.2V/1.8V
SPICE MODELS 40G
 T-N45-CL-SP-011
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL_RDL SALICIDE CU_ELK 0.9/1.2V/2.5V
SPICE MODEL 40G
 T-N45-CL-SP-053
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL RDL SALICIDE CU_ELK 0.9/1.8V
SPICE MODELS 40G
 T-N45-CM-SP-004
TSMC 45 NM CMOS MIXED SIGNAL RF LOW POWER 1P9M+AL_RDL SALICIDE CU_ELK 1.1&1.8V SPICE
MODEL 45LP
 T-N40-CM-SP-004
TSMC 40 NM CMOS MIXED SIGNAL RF GENERAL PURPOSE 1P10M+AL_RDL SALICIDE CU_ELK 0.9/1.8V
SPICE MODEL 40G (45GS, TGO)
 T-N40-CM-SP-007
TSMC 40 NM CMOS MIXED SIGNAL RF GENERAL PURPOSE 1P10M+AL_RDL SALICIDE CU_ELK 0.9/1.8V
SPICE MODEL 40G (45GS, DGO)
 T-N40-CM-SP-003
TSMC 40 NM CMOS MIXED SIGNAL RF GENERAL PURPOSE 1P10M+AL_RDL SALICIDE CU_ELK 0.9/2.5V
SPICE MODEL 40G (45GS)
 T-N40-CM-SP-002
TSMC 40 NM CMOS MIXED SIGNAL RF LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1&1.8V SPICE
MODEL 40LP
 T-N40-CM-SP-001
TSMC 40 NM CMOS MIXED SIGNAL RF LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1&2.5V SPICE
MODEL 40LP
 T-N45-CM-SP-003
TSMC 45 NM CMOS MIXED SIGNAL RF LOW POWER 1P9M+AL_RDL SALICIDE CU_ELK 1.1&2.5V SPICE
MODEL 45LP
 T-N45-CL-LS-001
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE 1P10M SALICIDE DEVICE FORMATION EXAMPLES AND LVS
PROPERTIES
 T-N45-CL-LS-002
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9&2.5V DEVICE
FORMATION EXAMPLES AND LVS PROPERTIES
 T-N40-CL-LS-001
TSMC 40 NM CMOS LOW POWER DEVICE FORMATION EXAMPLES AND LVS PROPERTIES
(CLN40LP/CLN40LPG/CRN40LP)
 T-N45-CL-LS-001-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE DEVICE FORMATION EXAMPLES AND LVS PROPERTIES
LVS COMMAND FILE
 T-N45-CL-LS-002-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9&2.5V DEVICE
FORMATION EXAMPLES AND LVS PROPERTIES
 T-N40-CL-LS-001-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 40 NM CMOS LOW POWER LVS COMMAND FILE (CLN40LP/CLN40LPG/CRN40LP)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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PDK
SRAM
Qualification report
Test Line Layout
Automotive
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: T-N45-CL-DR-001
: 2.6
Reference Document
 T-N45-CL-SP-010-K1
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL_RDL SALICIDE CU_ELK 0.9V/1.8V PDK
CLN45GS=CLN40G (INCLUDES: CLN45GS 0.9V/2.5V)
 T-N45-CM-SP-003-K1
TSMC 45 NM CMOS MIXED SIGNAL RF LOW POWER 1P9M+AL_RDL SALICIDE CU_ELK 1.1&2.5V PDK
(CRN45LP) (INCLUDES: CRN45LP 1.1V/2.5V; CRN45LP 1.1V/1.8V)
 T-N40-CM-SP-001-K1
TSMC 40 NM CMOS MIXED SIGNAL RF LOW POWER 1P9M+AL_RDL SALICIDE CU_ELK 1.1&2.5V PDK
(INCLUDES: CRN40LP 1.1V/1.8V)
 T-N40-CL-SP-051-K1
TSMC 40 NM CMOS MIXED SIGNAL RF LOW POWER PLUS 1P10M+AL_RDL SALICIDE CU_ELK 1.1&2.5V PDK
(1.1V/1.8V)
 T-N45-CL-CL-010
TSMC 45 NM CMOS LOGIC LOW POWER 1P10M SALICIDE CU_LOWK 1.1/1.8V 6T/8T SRAM CELL LAYOUT &
MODEL
 T-N45-CL-CL-014
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9V 6T/8T SRAM CELL
LAYOUT & MODEL (45GS (=40G), G SRAM)
 T-N45-CL-CL-015
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9V (0.8V) 6T/8T SRAM
CELL LAYOUT & MODEL (45GS (=40G), GL SRAM)
 T-N40-CL-CL-001
TSMC 40 NM CMOS LOGIC LOW POWER 1P10M SALICIDE CU_ELK 6T/8T SRAM CELL LAYOUT & SPICE
MODEL (6T SINGLE PORT SRAM AND 8T DUAL PORT SRAM)
 T-000-CL-RP-002
TSMC EMBEDDED SRAM REDUNDANCY IMPLEMENTATION RULE AND ECC GUIDELINE
 T-N45-CL-QR-001
TSMC 45 NM CMOS LOGIC LOW POWER 1P7M SALICIDE CU_LOWK 1.1/1.8V QUALIFICATION REPORTFAB12
 T-N45-CL-QR-005
TSMC 45 NM CMOS LOGIC LOW POWER 1P7M SALICIDE CU_LOWK 1.1/2.5V QUALIFICATION REPORTFAB12
 T-N45-CL-QR-006
TSMC 45 NM CMOS LOGIC LOW POWER 1P9M SALICIDE CU_ELK 1.1/1.8V CUP WIRE BOND PBGA
PACKAGE QUALIFICATION REPORT – 12 INCH FAB
 T-N45-CL-QR-010
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU ELK 0.9V/2.5V
QUALIFICATION REPORT-FAB12 (45GS (=40G))
 T-N45-CL-QR-011
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU ELK 0.9/1.8V QUALIFICATION
REPORT-FAB12 (45GS (=40G))
 T-N40-CL-QR-004
TSMC 40 NM CMOS LOGIC LOW POWER 1P10M SALICIDE CU_ELK 1.1/2.5V QUALIFICATION REPORT-FAB12
(40LP)
 T-N40-CL-QR-005
TSMC 45 NM / 40 NM CMOS LOGIC 1P9M CU_ELK CUP WIRE BOND PBGA PACKAGE QUALIFICATION
REPORT-12 INCH FAB
 T-N40-CL-QR-027
TSMC 40 NM CMOS LOGIC LOW POWER HVMOS 1P10M SALICIDE CU_LOW K 1.1&2.5V AND HVMOS
(D5G2.5) PROCESS QUALIFICATION REPORT- FAB12
 T-N40-CL-QR-031
TSMC 40 NM CMOS LOGIC LOW POWER HVMOS 1P10M SALICIDE CU_LOW K 1.1&1.8V AND HVMOS
(D5G1.8) PROCESS QUALIFICATION REPORT- FAB12
 T-N40-CL-QR-043
TSMC 40 NM CMOS LOGIC LOW POWER HVMOS 1P10M SALICIDE CU_LOW K 1.1&2.5V and HVMOS
(D5G2.5) PROCESS QUALIFICATION REPORT-FAB14
 T-N40-CL-QR-049
TSMC 40 NM CMOS LOGIC LOW POWER 1P10M SALICIDE CU_LOWK 1.1/2.5V QUALIFICATION REPORTFAB14 (HVMOS, D5G2.5)- FAB14
 E-MSS-02-02-024
TSMC TEST LINE LAYOUT USER GUIDELINE
 Q-QSM-05-03-221
TSMC AUTOMOTIVE SERVICE FOR WAFER MANUFACTURING
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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2 Technology Overview
This chapter provides information about the following:
2.1
Semiconductor process (including front-end and back-end features)
2.2
Devices
2.3
Power supply and operation temperature ranges
2.4
Cross-section
2.5
Metallization options
2.1
Semiconductor Process
The process consists of the front-end features and the back-end features.
2.1.1

Front-End Features
Shallow trench isolation (STI)
Used for active isolation to reduce active pitch (OD pitch)

Retrograde twin well CMOS technology on <110> P- substrate (epitaxy wafer) (subtrate resistivity
of 8-12 Ω-cm) for N40G, and on <100> P- substrate (epitaxy wafer) (subtrate resistivity of 8-12 Ωcm) for N45LP/N40LP.

Retrograde twin well CMOS technology
For a low well sheet resistance and enhancement of latch-up behavior (compared to conventionally
diffused wells). Also provides for a good control of short parasitic field transistors.

Triple well, Deep N-Well (optional)
For isolating P-Well from the substrate

Dual gate oxide process
Dual gate oxide LP (1.1V/2.5V or 1.1V/1.8V), GS (0.9V/2.5V,or 0.9V/1.8V)

Triple gate oxide process
Dual core gate oxide and IO gate oxide N45LPG (0.9V/1.1V/1.8V(I/O)) and N40LPG(0.9V/1.1V/3.3V(I/O))

N+/P+ poly gate
Allows symmetrical design of NMOS and PMOS devices

Multiple Vt devices for low leakage or high performance requirements
These devices may be mixed on the same die.

Native devices with dual gate oxide
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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SRAM cells offering (The cells described here are before shrinkage)
Technology
Cell Size
N45LP/N45LPG-LP
N40LP/N40LP+/N40LPG-LP
HD = 0.299um^2
(Vcc_nom = 1.1V)
HC = 0.374um^2
(Vcc_nom = 1.1V)
HD = 0.299um^2
(Vcc_nom = 1.1V)
HC (HP) = 0.374um^2
(Vcc_nom = 1.0V - 1.1V)
HDDP (HP) = 0.589um^2*
(Vcc_nom = 1.1V)
DP = 0.589um^2
(Vcc_nom = 1.1V)
HCDP (HP) = 0.741um^2
(Vcc_nom = 1.1V)
-DP = 0.589um^2
(Vcc_nom = 1.1V)
HCDP = 0.741um^2
(Vcc_nom = 1.1V)
*HDDP(HP) 0.589um^2 will replace DP 0.589um^2 and share the same implant mask 11N/11P with HC(HP) and
HCDP(HP). Original DP will be kept supporting but not official offering any more. Please refer to SRAM cell doc TN40-CL-CL-001 for HDDP(HP) GDS and more information.
Technology
Process Option
Cell Size
N40G(=N45GS)
G
GL
HD = 0.299um^2
(Vcc_nom = 0.9V - 1.0V)
HC = 0.374um^2
(Vcc_nom = 0.9V - 1.0V)
DP = 0.589um^2
(Vcc_nom = 0.9V - 1.0V)
HCDP = 0.741um^2
(Vcc_nom = 0.9V - 1.0V)
HD = 0.299um^2 (=G)*
(Vcc_nom = 0.9V - 1.0V)
HC = 0.374um^2
(Vcc_nom = 0.8V - 1.0V)
DP = 0.589um^2 (=G)**
(Vcc_nom = 0.9V - 1.0V)
HCDP = 0.741um^2
(Vcc_nom = 0.8V - 1.0V)
**D299 and D589 in N40GL process belong to N40G.

Self-aligned Ni-silicided drain, source, and gate
Silicide is necessary to short N+ and P+ gates; furthermore, it drastically reduces gate and S/D serial
resistance. Self-aligned silicide on source/drain structures allows butting straps with only one minimally
sized contact.

Unsilicided poly and OD resistors
Silicide protection (requires one additional mask, RPO) is used to prevent silicide formation over the active
and poly area.

Varactor
MOS varactor provides 0.9V/1.1V/1.2V/1.8V/2.5V NMOS-in-NW capacitor structure and 0.9V/1.8V/2.5V
PMOS-in-PW capacitor structure.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
Back-End Features

Tungsten contact connecting poly or OD to first metal level

Three to ten Cu metal levels, plus last metal level in Al pad.

Two kinds of inter-layer metal:
 Mx: First Inter-layer Metal, W/S=0.07μm/0.07μm.
 My: Second Inter-layer Metal, W/S=0.14μm/0.14μm.

Four kinds of top-layer metal:
 Mz (TM): top metal pitch is 0.8μm (W/S=0.4μm/0.4μm).
 My (2XTM): top metal pitch is two times of Mx pitch (W/S=0.14μm/0.14μm).
 Mr: top metal pitch is 1.0μm (W/S=0.5μm/0.5μm)
 Mu: top metal pitch is 3.0μm (W/S=2μm/1μm)

AlCu pad layer can be used as a redistribution layer (AP RDL) option.

One or two thick last (top) Cu metal layers at a relaxed pitch for power, clock, busses, and major
interconnect signal distribution

Tight pitch levels for routing on thin Cu for the other metal levels below the thick level

Chemical mechanical polishing (CMP) for enhanced planarization (STI, contact, metals, vias,
passivation)

Dual damascene copper interconnection, for metal-2 to the last (top) metal

ELK inter-metal dielectric for thin metal

Metal oxide metal (MOM) capacitor
 Use metal lines to design metal capacitor. The device does not require any additional mask.

High-Q copper inductor for RF process:
 Have Mz, Mu process for inductor metal.

Wire bond or flip chip terminals
 T-N45-CL-DR-003: TSMC WIRE BOND, EUTECTUC FLIP CHIP, AND INTERCONNECTION DESIGN
RULE
 For Lead-Free Flip Chip, please refer to section 1.2, Reference Document.

Electrical fuse
The IP of electrical fuse is provided. Please contact your account manager to get the related information.
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Devices
The technology provides multiple Vt devices, and optional thin and thick gate oxide native devices.
Table 2.2.1
Available Vt in each technology
Core
Technology
N45LP/N40LP
N40LP+
N45LPG
High Vt


N/A
STD Vt



Low Vt



Ultra Low Vt Plus
N/A

N/A
Native


N/A
Varactor*
MOM
Inductor









N40LPG

(N40 LPG-LP only)


(N40 LPG-G only)
N/A

(N40 LPG-LP only)



N40G (0.9V)



N/A




* Please refer to section 4.5.26, MOS Varactor Layout Rules (VAR), in details.
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2.3
Power Supply and Operation Temperature
Ranges
Table 2.3.1
Power Supplies
N45LP/N40LP
Normal
*Max
power
power
supply
supply
Core (thin
oxide)
I/O (thick
oxide)
2.5V
overdrive
to 3.3V
2.5V
underdrive
to 1.8V
1.8V
underdrive
to 1.5V
N40LP+
Normal
*Max
power
power
supply
supply
Technology
N45LPG/N40LPG
Normal
*Max
power
power
supply
supply
5.5V**
1.1V(LP),
0.9V(G)
1.8V
(N45LPG)
N/A
3.3V
(N40LPG)
N/A
1.26(LP),
1.05V(G)
1.98V
(N45LPG)
N/A
3.63V
(N40LPG)
N/A
3.3V
3.63V
N/A
1.98V
1.8V
1.98V
1.65V
(N40LP)
NA
NA
1.1V
1.26V
1.1V
1.26V
1.8V
1.98V
N/A
N/A
2.5V
2.75V
2.5V
2.75V
N/A
N/A
N/A
N/A
5V**
5.5V**
5V**
3.3V
3.63V
1.8V
1.5V
(N40LP)
N40G
Normal
power
supply
*Max
power
supply
0.9V,
1.1V,
1.2V(OD_12) 1.32V(OD_12)
1.8V
1.98V
2.5V
2.75V
N/A
N/A
N/A
N/A
N/A
3.3V
3.63V
N/A
N/A
1.8V
1.98V
N/A
N/A
1.5V
1.65V
** Only drain side can be applied to 5V. The other terminals can only be applied to 2.5V (HVMOS_25 for
N45LP/N40LP/N40LP+) or 1.8V (HVMOS_18 for only N40LP).
The operation temperature range is -40C to 125C (junction temperature).
* Maximum power supply voltage means variation upper limit of product operation voltage.
o p e r a ti o n
M a x i m u m p o w e r s u p p ly v o lta g e
v o lta g e
N o m ina l p o w e r
s u p p ly v o lta g e
o p e r a ti o n ti m e
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Cross–section
Cross section (1P10M as inter Mx, top Mz(TM))
P a s s iv a tio n - 2
A P
P a s s iv a tio n - 1
M 1 0 (C u )
M 10
U S G
M 1 0 W /S = 0 .4 /0 .4
V 9 W /S = 0 .3 6 /0 .3 4
V 9
M 9 (C u )
M 9
U S G
M 9 W /S = 0 .4 /0 .4
V 8 W /S = 0 .3 6 /0 .3 4
V 8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
~
~
E LK
M 3 W /S = 0 .0 7 /0 .0 7
M 3
M 3 (C u )
V 2 W /S = 0 .0 7 /0 .0 7
M 2 W /S = 0 .0 7 /0 .0 7
M 2 (C u )
E LK
V 2
M 2
E LK
V 1 W /S = 0 .0 7 /0 .0 7
P O
M 1 W /S = 0 .0 7 /0 .0 7
M 1 (C u )
W /S = 0 .0 4 /0 .1 0 (o n S T I)
0 .0 4 /0 .1 4 (o n O D )
C O
P o ly
V 1
E LK
M 1
W /S = 0 .0 6 /0 .0 8
W - P lu g
P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e
S TI
Figure 2.4.1 Cross-section for 1P10M_7x2z
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Cross section (1P10M as inter Mx, top My(2XTM))
P a s s iv a tio n - 2
AP
P a s s iv a tio n - 1
M 1 0 (C u )
M 10
USG
M 1 0 W /S = 0 .1 4 /0 .1 4
V 9 W /S = 0 .1 4 /0 .1 4
V9
M 9 (C u )
M 9
USG
M 9 W /S = 0 .1 4 /0 .1 4
V 8 W /S = 0 .1 4 /0 .1 4
V8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
~
~
ELK
M 3 W /S = 0 .0 7 /0 .0 7
M 3
M 3 (C u )
ELK
V2
V 2 W /S = 0 .0 7 /0 .0 7
M 2 W /S = 0 .0 7 /0 .0 7
M 2 (C u )
M 2
ELK
V 1 W /S = 0 .0 7 /0 .0 7
M 1 W /S = 0 .0 7 /0 .0 7
M 1 (C u )
P O W /S = 0 .0 4 /0 .1 0 (o n S T I)
0 .0 4 /0 .1 4 (o n O D )
M 1
C O W /S = 0 .0 6 /0 .0 8
P o ly
V1
ELK
W - P lu g
P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e
STI
Figure 2.4.2 Cross-section for 1P10M_7x2y
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Cross section (1P10M as inter Mx/My, top Mz(TM))
P a s s iv a tio n - 2
AP
P a s s iv a tio n - 1
M 1 0 (C u )
M 10
M 1 0 W /S = 0 .4 /0 .4
V9
V 9 W /S = 0 .3 6 /0 .3 4
USG
M 9 (C u )
M9
M 9 W /S = 0 .4 /0 .4
V 8 W /S = 0 .3 6 /0 .3 4
V8
M 8 (C u )
M8
M 8 W /S = 0 .1 4 /0 .1 4
V 7 W /S = 0 .1 4 /0 .1 4
V7
M 7 (C u )
M7
M 7 W /S = 0 .1 4 /0 .1 4
V 6 W /S = 0 .1 4 /0 .1 4
V6
LK
M6
ELK
M6
M 6 W /S = 0 .0 7 /0 .0 7
~
~
-------------------------------------
LK
-------------------------------------
M 2 (C u )
M 2 W /S = 0 .0 7 /0 .0 7
USG
M2
ELK
V 1 W /S = 0 .0 7 /0 .0 7
M 1 W /S = 0 .0 7 /0 .0 7
M 1 (C u )
P O W /S = 0 .0 4 /0 .1 0 (o n S T I)
0 .0 4 /0 .1 4 (o n O D )
P o ly
V1
M1
C O W /S = 0 .0 6 /0 .0 8
ELK
W - P lu g
P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e
STI
Figure 2.4.3 Cross-section for 1P10M_5x2y2z
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Cross section (1P10M as inter Mx, top Mr)
P a s s iv a tio n - 2
A P
P a s s iv a tio n - 1
M 1 0 (C u )
M 10
U S G
M 1 0 W /S = 0 .5 /0 .5
V 9 W /S = 0 .4 6 /0 .4 4
V 9
M 9 (C u )
M 9
U S G
M 9 W /S = 0 .5 /0 .5
V 8 W /S = 0 .4 6 /0 .4 4
V 8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
~
~
E LK
M 3 W /S = 0 .0 7 /0 .0 7
M 3
M 3 (C u )
M 2 W /S = 0 .0 7 /0 .0 7
M 2 (C u )
E LK
V 2
V 2 W /S = 0 .0 7 /0 .0 7
M 2
E LK
V 1 W /S = 0 .0 7 /0 .0 7
M 1 W /S = 0 .0 7 /0 .0 7
P O
M 1 (C u )
W /S = 0 .0 4 /0 .1 0 (o n S T I)
0 .0 4 /0 .1 4 (o n O D )
P o ly
C O
V 1
E LK
M 1
W /S = 0 .0 6 /0 .0 8
W - P lu g
P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e
S TI
Figure 2.4.4 Cross-section for 1P10M_7x2r
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Cross section (1P10M as inter Mx, top Mz/Mu (TM))
P a s s iv a tio n - 2
A P
P a s s iv a tio n
M 1 0 (C u )
1
M 10
U S G
M 1 0 W /S = 2 .0 /1 .0
V 9 W /S = 0 .3 6 /0 .3 4
V 9
M 9 (C u )
M 9
U S G
M 9 W /S = 0 .4 /0 .4
V 8 W /S = 0 .3 6 /0 .3 4
V 8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
~
~
E LK
M 3
M 3 W /S = 0 .0 7 /0 .0 7
M 3
(C u )
E LK
V 2
V 2 W /S = 0 .0 7 /0 .0 7
M 2
M 2 W /S = 0 .0 7 /0 .0 7
M 2
(C u )
E LK
V 1 W /S = 0 .0 7 /0 .0 7
M 1
M 1 W /S = 0 .0 7 /0 .0 7
P O
W /S = 0 .0 4 /0 .1 0 (o n S T I)
0 .0 4 /0 .1 4 (o n O D )
O D W /S =
V 1
(C u ) C O
P o ly
E LK
M 1
W /S =
0 .0 6 /0 .0 8
W P lu g
P o ly
0 .0 6 /0 .0 8
S a lic id e
S TI
Figure 2.4.5 Cross-section for 1P10M_7x1z1u
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Cross section (1P10M as inter Mx, top My(2XTM)/Mu(TM))
P a s s iv a tio n - 2
AP
P a s s iv a tio n
M 1 0 (C u )
1
M 10
USG
M 1 0 W /S = 2 .0 /1 .0
V 9 W /S = 0 .3 6 /0 .3 4
V9
M 9 (C u )
M 9
USG
M 9 W /S = 0 .1 4 /0 .1 4
V 8 W /S = 0 .1 4 /0 .1 4
V8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
~
~
ELK
M 3
M 3 W /S = 0 .0 7 /0 .0 7
M 3
(C u )
ELK
V2
V 2 W /S = 0 .0 7 /0 .0 7
M 2
M 2 W /S = 0 .0 7 /0 .0 7
M 2
(C u )
ELK
V 1 W /S = 0 .0 7 /0 .0 7
M 1
M 1 W /S = 0 .0 7 /0 .0 7
P O W /S = 0 .0 4 /0 .1 0 (o n S T I)
0 .0 4 /0 .1 4 (o n O D )
O D W /S =
V1
P o ly
(C u ) C O W /S =
0 .0 6 /0 .0 8
ELK
M 1
W P lu g
P o ly
0 .0 6 /0 .0 8
S a lic id e
Figure 2.4.6
STI
Cross-section for 1P10M_7x1y1u
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Metallization Options
1. The general 45 nm logic process is offered with a single poly and ten metal layers (1P10M). In addition to
1P10M, please refer to the following tables for the other metallization options.
2. CAD layer datatype of Mu metal is “60” (that of dummy Mu layer is “61”), and CAD layer datatype of its
associated VIA (VIAu, the VIA under Mu) is “40” (the same as that of VIAz due to the same via size).
3. Follow VIAz rule for VIAu design.
4. For eddy current reduction to achieve better inductor RF performance, a special metal (and OD/PO) dummy
block layer called "INDDMY" (CAD layer:144) is offered to allow very low metal density within an inductor.
When "INDDMY" layer is used to construct inductors, one must follow the additional process-related design
rules listed in INDDMY inductor section.
5. For the INDDMY layer identified low metal density inductor region, the inter-via (both Vx and Vy) and top via
Vy (2XTM) are all not allowed. Please refer to the section 4.5.45 for the rules in details.
Table 2.5.1
N40G/N45LP/N40LP/N45LPG/N40LPG Naming for Different Metal
W/S (μm)
Metal type
Code
N45LP/
N45LPG
N40G/
N40LP/
N40LPG
M1
First Inter-layer
Metal
Second Inter-layer
Metal
*Top Metal (2XTM)
Top Metal (TM)
*Top Metal (TM)
M1
0.07/0.07
0.07/0.07
M1 (360) only
Mx
0.07/0.07
0.07/0.07
M2~M8 (380, 381, 384, 385, 386, 387, 388), max : seven layers
My
0.14/0.14
0.14/0.14
M5~M8 (385, 386, 387, 388), max : two layers
My
Mz
Mr
0.14/0.14
0.4/0.4
0.5/0.5
0.14/0.14
0.4/0.4
0.5/0.5
Ultra Thick Metal
Mu
2.0/1.0
2.0/1.0
M3~M10 (381, 384, 385, 386, 387, 388, 389, 38A), max : two layers
M3~M10 (381, 384, 385, 386, 387, 388, 389, 38A), max : two layers
M6~M10 (386, 387, 388, 389, 38A), max: two layers
M4~M10 (384, 385, 386, 387, 388, 389, 38A), max: one layer only
(the most top metal)
Mask layers
*: not for N45LP/N45LPG
Table 2.5.2
N40G/N45LP/N40LP/N45LPG/N40LPG Naming for Different Via Types
W/S(μm)
Via type
First Inter-layer
Via
Second Interlayer Via
*Top Via (2XTM)
Top Via (TM)
*Top Via
Via under Ultra
Thick Metal
Code
N45LP/
N45LPG
N40G/
N40LP/
N40LPG
Mask layers
Vx
0.07/0.07
0.07/0.07
VIA1~VIA7 (378, 379, 373, 374, 375, 376, 377), max : seven layers
Vy
0.14/0.14
0.14/0.14
VIA4~VIA7 (374, 375, 376, 377), max : two layers
Vy
Vz
Vr
Vu
(Datatype:40)
0.14/0.14
0.36/0.34
0.46/0.44
0.14/0.14
0.36/0.34
0.46/0.44
0.36/0.34
0.36/0.34
VIA2~VIA9 (379, 373, 374, 375, 376, 377, 372, 37A), max : two layers
VIA2~VIA9 (379, 373, 374, 375, 376, 377, 372, 37A), max : two layers
VIA5~VIA9 (375, 376, 377, 372, 37A), max: two layers
VIA3~VIA9 (373, 374, 375, 376, 377, 372, 37A),
max : one layer only
*: not for N45LP/N45LPG
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Table 2.5.3 Metallization Options for Mz (My/Vy are used as second inter-layer Metal/Via, where the
dielectric film material for inter-layer My/Vy is “LK”.)
Metal/
Via
Total Number of Metal Layers
3
4
5
6
7
8
9
10
M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1
VIA1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1
M2 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1
VIA2 Vz1 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2
M3 Mz1 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2
VIA3
Vz1 Vx3 Vz1 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3
M4
Mz1 Mx3 Mz1 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3
VIA4
Vz1 Vz2 Vx4 Vz1 Vy1 Vx4 Vx4 Vy1 Vx4 Vy1 Vx4 Vx4 Vx4 Vx4 Vx4 Vy1 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4
M5
Mz1 Mz2 Mx4 Mz1 My1 Mx4 Mx4 My1 Mx4 My1 Mx4 Mx4 Mx4 Mx4 Mx4 My1 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4
VIA5
Vz1 Vz2 Vz1 Vx5 Vy1 Vy2 Vz1 Vz1 Vx5 Vx5 Vy1 Vx5 Vy1 Vy2 Vx5 Vx5 Vx5 Vx5 Vx5 Vy1 Vx5 Vx5 Vx5
M6
Mz1 Mz2 Mz1 Mx5 My1 My2 Mz1 Mz1 Mx5 Mx5 My1 Mx5 My1 My2 Mx5 Mx5 Mx5 Mx5 Mx5 My1 Mx5 Mx5 Mx5
VIA6
Vz1 Vz1 Vz1 Vz2 Vz2 Vx6 Vy1 Vy2 Vz1 Vz1 Vz1 Vx6 Vx6 Vy1 Vx6 Vy1 Vy2 Vx6 Vx6 Vy1
M7
Mz1 Mz1 Mz1 Mz2 Mz2 Mx6 My1 My2 Mz1 Mz1 Mz1 Mx6 Mx6 My1 Mx6 My1 My2 Mx6 Mx6 My1
VIA7
Vz1 Vz1 Vz1 Vz2 Vz2 Vz2 Vx7 Vy1 Vy2 Vz1 Vz1 Vz1 Vx7 Vy1 Vy2
M8
Mz1 Mz1 Mz1 Mz2 Mz2 Mz2 Mx7 My1 My2 Mz1 Mz1 Mz1 Mx7 My1 My2
VIA8
Vz1 Vz1 Vz1 Vz2 Vz2 Vz2 Vz1 Vz1 Vz1
M9
Mz1 Mz1 Mz1 Mz2 Mz2 Mz2 Mz1 Mz1 Mz1
VIA9
Vz2 Vz2 Vz2
M10
Mz2 Mz2 Mz2
Table 2.5.4 Metallization Options for My (My/Vy are used as 2X top Metal/Via, where the dielectric film
material for top My/Vy is “USG”.)
Total Number of Metal Layers
Metal /
Via
3
4
5
6
7
8
9
10
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
VIA1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
M2
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
VIA2 VyTV1
Vx2
Vx2
Vx2
Vx2
Vx2
Vx2
Vx2
Vx2
Vx2
Vx2
Vx2
M3
MyTM1
Mx2
Mx2
Mx2
Mx2
Mx2
Mx2
Mx2
Mx2
Mx2
Mx2
Mx2
VIA3
VyTV1
Vx3
VyTV1
Vx3
Vx3
Vx3
Vx3
Vx3
Vx3
Vx3
Vx3
M4
MyTM1
Mx3
MyTM1
Mx3
Mx3
Mx3
Mx3
Mx3
Mx3
Mx3
Mx3
VIA4
VyTV1 VyTV2
Vx4
VyTV1
Vx4
Vx4
Vx4
Vx4
Vx4
Vx4
M5
MyTM1 MyTM2
Mx4
MyTM1
Mx4
Mx4
Mx4
Mx4
Mx4
Mx4
VIA5
VyTV1 VyTV2
Vx5
VyTV1
Vx5
Vx5
Vx5
Vx5
M6
MyTM1 MyTM2
Mx5
MyTM1
Mx5
Mx5
Mx5
Mx5
VIA6
VyTV1 VyTV2
Vx6
VyTV1
Vx6
Vx6
M7
MyTM1 MyTM2
Mx6
MyTM1
Mx6
Mx6
VIA7
VyTV1 VyTV2 VyTV1
Vx7
M8
MyTM1 MyTM2 MyTM1
Mx7
VIA8
VyTV2 VyTV1
M9
MyTM2 MyTM1
VIA9
VyTV2
M10
MyTM2
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Table 2.5.5 Metallization Options for Mr
Total Number of Metal Layers
Metal
/Via
7
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
M1
Vx1
Mx1
Vx2
Mx2
Vx3
Mx3
Vx4
Mx4
Vx5
Mx5
Vr1
Mr1
Table 2.5.6
8
M1
Vx1
Mx1
Vx2
Mx2
Vx3
Mx3
Vx4
Mx4
Vr1
Mr1
Vr2
Mr2
M1
Vx1
Mx1
Vx2
Mx2
Vx3
Mx3
Vx4
Mx4
Vx5
Mx5
Vx6
Mx6
Vr1
Mr1
9
M1
Vx1
Mx1
Vx2
Mx2
Vx3
Mx3
Vx4
Mx4
Vx5
Mx5
Vr1
Mr1
Vr2
Mr2
M1
Vx1
Mx1
Vx2
Mx2
Vx3
Mx3
Vx4
Mx4
Vx5
Mx5
Vx6
Mx6
Vx7
Mx7
Vr1
Mr1
M1
Vx1
Mx1
Vx2
Mx2
Vx3
Mx3
Vx4
Mx4
Vx5
Mx5
Vx6
Mx6
Vr1
Mr1
Vr2
Mr2
10
M1
Vx1
Mx1
Vx2
Mx2
Vx3
Mx3
Vx4
Mx4
Vx5
Mx5
Vx6
Mx6
Vx7
Mx7
Vr1
Mr1
Vr2
Mr2
Metallization Options for Mu (Mu with second inter-layer metal/via (My/Vy) are used,
where the dielectric film material for inter-layer My/Vy is “LK”.)
Total Number of Metal Layers
Metal/
Via
4
M1
M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1
5
6
7
8
9
10
VIA1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1
M2
Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1
VIA2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2
M3
Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2
VIA3 Vu1 Vx3 Vz1 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3
M4 Mu1 Mx3 Mz1 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3
VIA4
Vu1 Vu1 Vx4 Vz1 Vy1 Vx4 Vx4 Vx4 Vy1 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4
M5
Mu1 Mu1 Mx4 Mz1 My1 Mx4 Mx4 Mx4 My1 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4
VIA5
Vu1 Vu1 Vu1 Vx5 Vy1 Vz1 Vz1 Vx5 Vx5 Vx5 Vy1 Vx5 Vx5 Vx5 Vx5 Vx5 Vx5
M6
Mu1 Mu1 Mu1 Mx5 My1 Mz1 Mz1 Mx5 Mx5 Mx5 My1 Mx5 Mx5 Mx5 Mx5 Mx5 Mx5
VIA6
Vu1 Vu1 Vu1 Vu1 Vx6 Vy1 Vz1 Vz1 Vx6 Vx6 Vx6 Vy1 Vx6 Vx6
M7
Mu1 Mu1 Mu1 Mu1 Mx6 My1 Mz1 Mz1 Mx6 Mx6 Mx6 My1 Mx6 Mx6
VIA7
Vu1 Vu1 Vu1 Vu1 Vx7 Vy1 Vz1 Vz1 Vx7 Vy1
M8
Mu1 Mu1 Mu1 Mu1 Mx7 My1 Mz1 Mz1 Mx7 My1
VIA8
Vu1 Vu1 Vu1 Vu1 Vz1 Vz1
M9
Mu1 Mu1 Mu1 Mu1 Mz1 Mz1
VIA9
Vu1 Vu1
M10
Mu1 Mu1
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Table 2.5.7 Metallization Options (Mu with top metal/via (My/Vy, 2XTM) are used, where the dielectric
film material for top My/Vy is “USG”.)
Metal/
Via
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
Total Number of Metal Layers
5
6
7
8
9
10
M1
M1
M1
M1
M1
M1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Mx1
Mx1
Mx1
Mx1
Mx1
Mx1
Vx2
Vx2
Vx2
Vx2
Vx2
Vx2
Mx2
Mx2
Mx2
Mx2
Mx2
Mx2
VyTV1
Vx3
Vx3
Vx3
Vx3
Vx3
MyTM1
Mx3
Mx3
Mx3
Mx3
Mx3
Vu1
VyTV1
Vx4
Vx4
Vx4
Vx4
Mu1 MyTM1
Mx4
Mx4
Mx4
Mx4
Vu1
VyTV1
Vx5
Vx5
Vx5
Mu1 MyTM1
Mx5
Mx5
Mx5
Vu1
VyTV1
Vx6
Vx6
Mu1 MyTM1
Mx6
Mx6
Vu1
VyTV1
Vx7
Mu1 MyTM1
Mx7
Vu1
VyTV1
Mu1 MyTM1
Vu1
Mu1
Table 2.5.8
Reference documents about top metal scheme requirement for wire bond and flip chip
(EU and LF bumps) applications
Assmebly Type
Wire bond (WB)
Eutectic (EU) Bump Flip
Chip
Lead Free (LF) Bump Flip
Chip with build up (FCBGA)
substrate
Lead Free (LF) Bump Flip
Chip
with
laminate
(FCCSP) substrate
Document No.
T-N45-CL-DR-003
T-N45-CL-DR-003
T-N45-CL-DR-017
T-N45-CL-DR-022
Document Title
TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND
INTERCONNECTION DESIGN RULE
TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND
INTERCONNECTION DESIGN RULE
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD
UP SUBSTRATE (FCBGA, FLIP CHIP BALL GRID ARRAY) AND
INTERCONNECTION DESIGN RULE
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH
LAMINATE SUBSTRATE (FCCSP, FLIP CHIP CHIP SCALE
PACKAGE) AND INTERCONNECTION DESIGN RULE
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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3 General Layout Information
This chapter provides the following general layout information:
3.1
Mask information, key process sequence, and CAD layers
3.2
Metal/via CAD layer information for metallization options
3.3
Dummy pattern fill CAD Layers
3.4
Special recognition CAD layer summary
3.5
Device truth tables
3.6
Mask requirements for device options (High/Std/Low Vt)
3.7
Design geometry restrictions
3.8
Design hierarchy guidelines
3.9
Chip Implementation and Tape Out Checklist
3.1
Mask Information, Key Process Sequence,
and CAD Layers
All tables list masks and corresponding masking steps.
1. TSMC uses NW and OD2 (OD_18, OD_25) to generate NW1V, NW2V, PW1V, and PW2V masks by
logical operations. Designers can draw NW only.
2. TSMC uses NP, PP, and other layers to generate N1V, N2V, P1V, and P2V masks by logical operations.
Designers do not need to draw these masks.
3. An Al pad is a reverse tone of CB with bias. However, in a flip-chip product, Al pad is a drawn layer.
The Mask Name column lists names that are reserved for standard mask steps. These names should not
be used for another purpose in tape out files without prior authorization from TSMC.
The CAD Layer column lists CAD layer numbers. To obtain all related CAD layer usage information,
please refer to TSMC Document, T-N45-CL-LE-001
4. In the tables of section 3.1, “ * “ means an optional mask. “ # “ means a non-design level mask which is no
need to draw (or design) this layer. This non-design level mask is generated by logical operation from other
drawn layers.
Warning:
1.
Please contact TSMC for actually re-tapeout mask set if FEOL OD/Poly/CO GDS are
changed except all-FEOL-layer-change RTO.
2.
12E and 12F are composed of NW, OD, PO, NP, PP, CO, OD2, SRM, RH, VAR,
BJTDMY, and POFUSE. Whenever 12E and 12F tape out, up-to-date CAD layers
mentioned above must be enclosed in one database to generate correct pattern. If ≥
one of the above CAD layers is revised, both 12E and 12F must be re-taped out.
3.
Must include VIA layer with metal layer while tape out, since metal OPC requires to
refer to VIA layer.
Warning:
A CAD layer number must be less than, or equal to, 255. If the number is greater than 255, the
mask making will fail.
Table 3.1.1
Mask Name and ID, Key Process Sequence, and CAD Layer for CLN45LP/CLN40LP
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Key Process
Sequence
Digitized Area
Reference Layer in Logical Operation
Mask Name Mask ID
CAD Layer
(Dark or Clear)
and OPC
* = Optional
Mask
1
OD
120
D
Derived
2*
3#
DNW
PW1V
119
191
C
D
1
Derived
4#
PW2V
193
C
Derived
5#
NW1V
192
C
Derived
6
OD2
152
D
7#
NPO
196
C
16
18
Derived
8
PO
130
D
Derived
9#
N2V
116
C
Derived
10#
P2V
115
C
Derived
11*
VTH_N
11H
C
Derived
12*
VTL_N
118
D
Derived
13#
N1V
114
C
Derived
14*
ULVT_N
11E
C
Derived
15*
VTC_N2
11N
C
Derived
16*
17*
VTC_N
VTH_P
112
11G
C
C
Derived
Derived
18*
VTL_P
117
C
Derived
19*
VTL_P2
11C
C
Derived
20#
P1V
113
C
Derived
21*
ULVT_P
11F
C
Derived
22*
VTC_P2
11P
C
Derived
23*
VTC_P
199
C
Derived
24
PP
197
C
Derived
25
NP
198
C
Derived
26*
ESD
111
C
189;0
27*
RPO2
124
C
Derived
28
RPO
155
D
Derived
Description
OD, DOD, SR_DOD, DUMMYOD1~12,
DUMMYOD16, DPSRM, SRM_10TTP,
Device, ACTIVE, STRAP and
SRM_8TTP, SRM_HC, SRM_HD,
interconnection regions
SRM_LV, SRM_HCDP, SRM, NW,
NDIFF, PDIFF, PRSRM
Deep N-Well.
NW, NT_N, OD2, SRM;0, HVD_P
Core device P-Well.
OD2, NW, NT_N, HVD_N, NDIFF,
1.8V or 2.5V (only for N40LP) P-Well.
PDIFF, OD, PO
OD2, NW, NT_N, SRM;0, HVD_N,
Core and I/O device N-Well.
HVD_P, NDIFF, PDIFF, OD, PO
1.8V: OD_18
1.8V or 2.5V (only for N40LP) thick
2.5V: OD_25
oxide for DGO process.
NP, SRM;21, SRM;0, POFUSE
Pre-doped N+ poly.
PO, OD, OD2, NP, PP, SRM;0, SRM;1,
SRM;2, SRM_HC, PRSRM,
Poly-Si.
DUMMYPO5, DPO, SR_DPO. NDIFF,
PDIFF, POFUSE
NP, NW, OD2, RH, VAR, POFUSE,
1.8V or 2.5V (only for N40LP) NLDD
BJTDMY, HVD_N, HVD_P, NDIFF,
implantation.
PDIFF, NT_N, OD, PO, PP.
PP, NW, OD2, RH, VAR, NT_N,
1.8V or 2.5V (only for N40LP) PLDD
POFUSE, BJTDMY, HVD_N, HVD_P,
implantation.
NDIFF, PDIFF, OD, PO, NP.
VTH_N, SRM;0
High Vt NMOS implantation.
OD2, NW, VTL_N, SRM;0, BJTDMY,
Low Vt NMOS implantation for LP
VTH_N, NT_N, SRM;1, RH, VAR,
only.
POFUSE, SRM;2, ULVT_N, PP
NP, NW, OD2, RH, VAR, SRM;0,
POFUSE, SRM;1, VTH_N, BJTDMY,
Core device NLDD implantation.
SRM;2, ULVT_N, PP
Ultra-low Vt plus NMOS implantation
ULVT_N, SRM;0
(only for N40LP)
SRM;0, NW, SRM;1, SRM_8TTP,
SRAM HP cell NMOS Vt IMP2 only for
SRM_LV, PRSRM, PP
N40LP.
PP, SRM;1, ULVT_N , VTH_N
SRAM cell NMOS Vt.
VTH_P, SRM;0
High Vt PMOS implantation.
Low Vt PMOS implantation for LP
OD2, NW, VTL_P, SRM;0, SRM;2, RH,
only.
VAR, POFUSE, VTH_P, BJTDMY,
N40LP: Mask 117 is a must if
HVD_P, PO, NP, SRM;1, ULVT_P ,
HVPMOS_18 is used.
OD2, NW, VTL_P, SRM;0, SRM;2, RH, N45LP: 11C is a must if
VAR, POFUSE, VTH_P, BJTDMY, PP,
(a) No PMOS LVT (117) and
NP
(b) NCI SRAM cell is used
PP, NW, OD2, RH, VAR, SRM;0,
SRM;2, BJTDMY, VTH_P, NP, SRM;1, Core device PLDD implantation.
ULVT_P, POFUSE
Ultra-low Vt plus PMOS implantation
ULVT_P, SRM;0
(only for N40LP)
NW, SRM;0, SRM;2, NP, VTH_P,
SRAM HP cell PMOS Vt IMP2 only for
ULVT_P
N40LP.
NP, SRM;2, ULVT_P , VTH_P
SRAM cell PMOS Vt.
PP, SRM;0, DOD, DPO, HVD_P,
P+ implantation.
NDIFF, PDIFF, OD, PO
NP, SRM;0, POFUSE, DOD, DPO,
DUMMYOD9, HVD_N, NDIFF, PDIFF,
N+ implantation.
OD, PO, PP, PRSRM, SRM_8TTP,
SRM_HC, SRM_HD, SRM_LV
ESD3, ESDIMP, NW, NP, NDIFF,
ESD implantation.
PDIFF, OD, PO, RPO
It can be skipped for N40LP 2.5V I/O
OD2, BJTDMY, POFUSE, RH
w/o RPO2 mask
PO, RPO, HVD_N, HVD_P, OD, CO,
Silicide protection.
NDIFF, PDIFF
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Key Process
Sequence
Digitized Area
Reference Layer in Logical Operation
Mask Name Mask ID
CAD Layer
(Dark or Clear)
and OPC
* = Optional
Mask
29
CO
156
C
Derived
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
360
378
380
379
381
373
384
374
385
375
386
376
387
377
388
372
389
37A
38A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
31
51
32
52
33
53
34
54
35
55
36
56
37
57
38
58
39
59
40
CO;0, CO;11, OD, SRM;0,
SRAMDMY;4, SRAMDMY;1, PRSRM,
SRM_UHD, DUMMYOD1,
DUMMYOD3, DUMMYOD10,
DUMMYOD11, DUMMYOD12,
SRM_HD, NW, SRM_HCDP, PO,
SRM_HC, PP, DUMMYPO1, SDPRM,
DPSRM, SRM_10TTP, SRM_8TTP,
SRM_LV
M1, DM1, DM1_O, VIA1
DVIA1
M2, DM2, DM2_O, VIA1, VIA2
DVIA2
M3, DM3, DM3_O, VIA2, VIA3
DVIA3
M4, DM4, DM4_O, VIA3, VIA4
DVIA4
M5, DM5, DM5_O, VIA4, VIA5
DVIA5
M6, DM6, DM6_O, VIA5, VIA6
DVIA6
M7, DM7, DM7_O, VIA6, VIA7
DVIA7
M8, DM8, DM8_O, VIA7, VIA8
M9, DM9, VIA8, VIA9
M10, DM10, VIA9
Description
Contact window from M1 to OD or PO.
1st metal for interconnection.
Via1 hole between M2 and M1.
2nd metal for interconnection.
Via2 hole between M3 and M2.
3rd metal for interconnection.
Via3 hole between M4 and M3.
4th metal for interconnection.
Via4 hole between M5 and M4.
5th metal for interconnection.
Via5 hole between M6 and M5.
6th metal for interconnection.
Via6 hole between M7 and M6.
7th metal for interconnection.
Via7 hole between M8 and M7.
8th metal for interconnection.
Via8 hole between M9 and M8.
9th metal for interconnection.
Via9 hole between M10 and M9.
10th metal for interconnection
FBEOL option1 (Wire bond without AP RDL)
49
50
CB
AP
107
307
C
D
51
CB2
308
C
52*
PM
009
D
76
Derived
86;20
(CB2_WB)
Derived
5;0
CB, CB2_WB
Passivation-1 open for bond pad.
Al pad.
-
Passivation-2 open for bond pad.
CB2_WB
-
Polyimide opening
-
Passivation-1 open for bump pad.
Al pad.
-
Passivation-2 open for bump pad.
-
Polyimide opening
Under bump metallurgy for flip chip.
Derived
74
86;20
(CB2_WB)
Derived
5;0
CB, RV
-
Passivation-1 open for bond pad, AP RDL via.
Al pad, AP RDL.
-
Passivation-2 open.
CB2_WB
-
Polyimide opening
Derived
74
86;0
(CB2_FC)
5;0
170;0
CBD, RV
-
Passivation-1 open for bump pad, AP RDL via.
Al pad, AP RDL.
-
Passivation-2 open.
-
Polyimide opening
Under bump metallurgy for flip chip.
FBEOL option2 (Flip chip without AP RDL)
48
49
CB
AP
107
307
C
D
50
CB2
308
C
51
52
PM
UBM
009
020
D
D
169
74
86;0
(CB2_FC)
5;0
170;0
FBEOL option3 (Wire bond with AP RDL)
48
49
CB-VD
AP-MD
306
309
C
D
50
CB2
308
C
51*
PM
009
D
FBEOL option4 (Flip chip with AP RDL)
48
49
CB-VD
AP-MD
306
309
C
D
50
CB2
308
C
51
52
PM
UBM
009
020
D
D
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Table 3.1.2
Key Process
Sequence
* = Optional
Mask
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Mask Name and ID, Key Process Sequence, and CAD Layer for CLN40LP+ (1.1V Core and
2.5V I/O Design)
Mask
Name
Mask ID
Digitized Area
(Dark or
Clear)
CAD
Layer
1
OD
120
D
Derived
2*
3#
DNW
PW1V
119
191
C
D
1
Derived
4#
PW2V
193
C
Derived
5#
NW1V
192
C
Derived
6
OD2
152
D
Derived
7
DCO_LPP
153
C
90;1
8#
NPO
196
C
Derived
9
PO
130
D
Derived
10#
N2V
116
C
Derived
11#
P2V
115
C
Derived
12*
VTH_N
11H
C
Derived
13
VTL_N
118
D
Derived
14#
N1V
114
C
Derived
15
ULVT_N
11E
C
Derived
16*
VTC_N2
11N
C
Derived
17*
18*
VTC_N
VTH_P
112
11G
C
C
Derived
Derived
19*
VTL_P
117
C
Derived
20#
P1V
113
C
Derived
21
ULVT_P
11F
C
Derived
22*
VTC_P2
11P
C
Derived
23*
24
VTC_P
PP
199
197
C
C
Derived
Derived
25
NP
198
C
Derived
26*
27*
28
ESD
RPO2
RPO
111
124
155
C
C
D
189;0
Derived
Dirived
Reference Layer in Logical Operation and
OPC
Description
OD,
DOD,
SR_DOD,
DUMMYOD1~12,
DUMMYOD16,
DPSRM,
SRM_10TTP,
Device, ACTIVE, STRAP and
SRM_HCDP, SRM;0, NW,
SRM_8TTP,
interconnection regions
SRM_HC, SRM_HD, SRM_LV, NDIFF, PDIFF,
PRSRM
Deep N-Well.
NW, NT_N, OD2, SRM;0, HVD_P
Core device P-Well.
OD2, NW, NT_N, OD, PO, HVD_N, NDIFF,
2.5V P-Well.
PDIFF
OD2, NW, NT_N, SRM;0, HVD_N, HVD_P, OD,
Core and I/O device N-Well.
PO, NDIFF, PDIFF
2.5V thick oxide for DGO
OD_25, DCO_LPP
process.
N40LP+ dual core oxide for ultra
low Vt plus devices’ speed boost
NP, SRM;21, SRM;0, POFUSE
Pre-doped N+ poly.
PO, OD, OD2, NP, PP, SRM;0, SRM;1, SRM;2,
SRM_HC,
PRSRM,
DUMMYPO5,
DPO,
Poly-Si.
SR_DPO, DCO_LPP, NDIFF, PDIFF, POFUSE,
ULVT_N, ULVT_P
NP, NW, OD2, RH, VAR, POFUSE, BJTDMY,
HVD_N, HVD_P, OD, PO, NDIFF, PDIFF, NT_N, 2.5V NLDD implantation.
PP
PP, NW, OD2, RH, VAR, NT_N, POFUSE,
BJTDMY, HVD_N, HVD_P, OD, PO, NDIFF, 2.5V PLDD implantation.
PDIFF, NP
VTH_N, SRM;0
High Vt NMOS implantation.
OD2, NW, VTL_N, SRM;0, BJTDMY, VTH_N,
NT_N, SRM;1, SRM;2, RH, VAR, POFUSE, Low Vt NMOS implantation.
DCO_LPP, PP, ULVT_N
NP, NW, OD2, RH, VAR, SRM;0, POFUSE,
SRM;1, VTH_N, BJTDMY, DCO_LPP, PP, Core device NLDD implantation.
SRM;2, ULVT_N
Ultra-low
Vt
plus
NMOS
ULVT_N, SRM;0, DCO_LPP
implantation for N40LP+ only
SRM;0, NW, SRM;1, SRM_8TTP, SRM_LV, SRAM HP cell NMOS Vt IMP2
PRSRM, DCO_LPP, PP
only for N40LP+.
SRM;1, DCO_LPP, PP, ULVT_N, VTH_N
SRAM cell NMOS Vt.
VTH_P, SRM;0
High Vt PMOS implantation.
OD2, NW, VTL_P, SRM;0, SRM;2, RH, VAR,
POFUSE, VTH_P, BJTDMY, DCO_LPP, NP, Low Vt PMOS implantation.
SRM;1, ULVT_P
PP, NW, OD2, RH, VAR, SRM;0, SRM;2,
BJTDMY, VTH_P, NP, DCO_LPP, POFUSE, Core device PLDD implantation.
SRM;1, ULVT_P
Ultra-low
Vt
plus
PMOS
ULVT_P, SRM;0, DCO_LPP
implantation for N40LP+ only
NW, SRM;0, SRM;2, NP, VTH_P, DCO_LPP, SRAM HP cell PMOS Vt IMP2
ULVT_P
only for N40LP+.
SRM;2, DCO_LPP, NP, ULVT_P, VTH_P
SRAM cell PMOS Vt.
PP, SRM;0, HVD_P, PO
P+ implantation.
NP, SRM;0, POFUSE, DUMMYOD9, HVD_N,
N+ implantation.
PO, PP, PRSRM, SRM_HC, SRM_HD
ESD implantation.
OD2, BJTDMY, POFUSE, RH
It is must for 2.5V [N40LP+]
HVD_N, HVD_P, PO, RPO
Silicide protection.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
30 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Key Process
Sequence
* = Optional
Mask
Confidential – Do Not Copy
Mask
Name
Mask ID
Digitized Area
(Dark or
Clear)
29
CO
156
C
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
360
378
380
379
381
373
384
374
385
375
386
376
387
377
388
372
389
37A
38A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
CAD
Layer
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Reference Layer in Logical Operation and
OPC
Description
CO;0, CO;11, OD, SRM;0,
SRAMDMY;4,
SRAMDMY;1,
PRSRM,
SRM_UHD,
DUMMYOD1~4, DUMMYOD10, DUMMYOD11,
Contact window from M1 to OD
Derived DUMMYOD12, SRM_HD, NW, SRM_HCDP, PO,
or PO.
SRM_HC, PP, DUMMYPO1, DUMMYPO5,
SDPRM,
DPSRM,
NP,
NDIFF, PDIFF,
SRM_10TTP, SRM_8TTP, SRM_LV
31
M1, DM1, DM1_O, VIA1
1st metal for interconnection.
51
DVIA1
Via1 hole between M2 and M1.
32
M2, DM2, DM2_O, VIA1, VIA2
2nd metal for interconnection.
52
DVIA2
Via2 hole between M3 and M2.
33
M3, DM3, DM3_O, VIA2, VIA3
3rd metal for interconnection.
53
DVIA3
Via3 hole between M4 and M3.
34
M4, DM4, DM4_O, VIA3, VIA4
4th metal for interconnection.
54
DVIA4
Via4 hole between M5 and M4.
35
M5, DM5, DM5_O, VIA4, VIA5
5th metal for interconnection.
55
DVIA5
Via5 hole between M6 and M5.
36
M6, DM6, DM6_O, VIA5, VIA6
6th metal for interconnection.
56
DVIA6
Via6 hole between M7 and M6.
37
M7, DM7, DM7_O, VIA6, VIA7
7th metal for interconnection.
57
DVIA7
Via7 hole between M8 and M7.
38
M8, DM8, DM8_O, VIA7, VIA8
8th metal for interconnection.
58
Via8 hole between M9 and M8.
39
M9, DM9, VIA8, VIA9
9th metal for interconnection.
59
Via9 hole between M10 and M9.
40
M10, DM10, VIA9
10th metal for interconnection
FBEOL option1 (Wire bond without AP RDL)
49
50
CB
AP
107
307
C
D
51
CB2
308
C
52*
PM
009
D
76
Derived
86;20
(CB2_WB)
CB, CB2_WB
Passivation-1 open for bond pad.
Al pad.
-
Passivation-2 open for bond pad.
Derived
5;0
CB2_WB
-
Polyimide opening
-
Passivation-1 open for bump pad.
Al pad.
-
Passivation-2 open for bump pad.
-
Polyimide opening
Under bump metallurgy for flip chip.
Derived
74
86;20
(CB2_WB)
CB, RV
-
Passivation-1 open for bond pad, AP RDL via.
Al pad, AP RDL.
-
Passivation-2 open.
Derived
5;0
CB2_WB
-
Polyimide opening
Derived
74
86;0
(CB2_FC)
5;0
170;0
CBD, RV
-
Passivation-1 open for bump pad, AP RDL via.
Al pad, AP RDL.
-
Passivation-2 open.
-
Polyimide opening
Under bump metallurgy for flip chip.
FBEOL option2 (Flip chip without AP RDL)
49
50
CB
AP
107
307
C
D
51
CB2
308
C
52
53
PM
UBM
009
020
D
D
169
74
86;0
(CB2_FC)
5;0
170;0
FBEOL option3 (Wire bond with AP RDL)
49
50
CB-VD
AP-MD
306
309
C
D
51
CB2
308
C
52*
PM
009
D
FBEOL option4 (Flip chip with AP RDL)
49
50
CB-VD
AP-MD
306
309
C
D
51
CB2
308
C
52
53
PM
UBM
009
020
D
D
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
31 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Table 3.1.3
Key Process
Sequence
* = Optional
Mask
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Mask Name and ID, Key Process Sequence, and CAD Layer for CLN45LPG/N40LPG
Mask
Name
Mask
ID
Digitized Area
Reference Layer in Logical Operation
CAD Layer
(Dark or Clear)
and OPC
1
OD
120
D
Derived
2*
3#
4#
5#
6#
DNW
PW1V
PW2V
NW1V
NW2V
119
191
193
192
194
C
D
C
C
C
1
Derived
Derived
Derived
Derived
OD, DOD, SR_DOD, DUMMYOD1~12,
DUMMYOD16, DPSRM, SRM_10TTP,
SRM_8TTP, SRM_HC, SRM_HD,
SRM_LV, SRM_HCDP, SRM;0, NW,
NDIFF, PDIFF, PRSRM
NW, NT_N, OD2, SRM;0,DCO
OD2, NW, NT_N, DCO
OD2, NW, NT_N, SRM;0,DCO
OD2, NW, NT_N, DCO
7
OD2
152
D
Derived
OD2, DCO
8
9#
DCO
NPO
153
196
C
C
90
Derived
10
PO
130
D
Derived
11#
N2V
116
C
Derived
12#
P2V
115
C
Derived
13*
VTL_N
118
D
Derived
14#
N1V_G
106
C
Derived
15
VTC_N2
11N
C
Derived
16
VTC_P2
11P
C
Derived
17*#
VTC_N_
GP
104
C
Derived
18#
N1V
114
C
Derived
19#
VTC_N
112
C
Derived
20*
VTL_P
117
C
Derived
21#
P1V_G
105
C
Derived
22*#
VTC_P_
GP
103
C
Derived
23*
VTL_P2
11C
C
Derived
24#
P1V
113
C
Derived
25#
26
VTC_P
PP
199
197
C
C
Derived
Derived
27
NP
198
C
Derived
28
ESD
111
C
189;0
Description
Device, ACTIVE, STRAP and
interconnection regions
Deep N-Well.
Core device P-Well.
1.8V or 3.3V P-Well.
Core device/1.8V N-Well.
3.3V N-Well.(N40LPG only)
1.8V or 3.3V thick oxide for DGO
process.
GP oxide
Pre-doped N+ poly.
NP, SRM;21, SRM;0, POFUSE
PO, OD, OD2, NP, PP, SRM;0, SRM;1,
SRM;2, SRM_HC, PRSRM,
Poly-Si.
DUMMYPO5, DPO, DCO, SR_DPO,
NDIFF, PDIFF, POFUSE.
NP, NW, OD2, RH, VAR, POFUSE,
BJTDMY, NDIFF, PDIFF, NT_N, OD,
1.8V or 3.3V NLDD implantation.
PO, PP.
PP, NW, OD2, RH, VAR, NT_N,
POFUSE, BJTDMY, NDIFF, PDIFF, OD, 1.8V or 3.3V PLDD implantation.
PO, NP.
1.45LPG: Low Vt NMOS
OD2, NW, VTL_N, SRM;0, BJTDMY,
implantation for both LP and GP.
VTH_N, NT_N, SRM;1, RH, VAR,DCO,
2.40LPG: Delta dose implantation for
POFUSE, NP
LPHVt NMOS and G LVt NMOS.
NP, NW, OD2, RH, VAR, SRM;0,
POFUSE, SRM;1, SRM;2, VTH_N,
GP Core device NLDD implantation.
BJTDMY,DCO
SRM;0, NW, SRM;1, SRM_8TTP,
SRAM HP cell NMOS Vt IMP2 only
SRM_LV, PRSRM , DCO, PP
for N40LPG-LP.
SRAM HP cell PMOS Vt IMP2 only
NW, SRM;0, SRM;2, NP, VTH_P, DCO
for N40LPG-LP
GP SRAM cell NMOS Vt
SRM;1, DCO, PP, VTH_N
It is a must if GP SRAM cell is used.
(N40LPG only)
NP, NW, OD2, RH, VAR, SRM;0,
POFUSE, SRM;1, SRM;2, VTH_N,
LP Core device NLDD implantation.
BJTDMY, DCO, PP
SRM;1, DCO, VTH_N, PP
LP SRAM cell NMOS Vt.
1.45LPG: Low Vt PMOS
OD2, NW, VTL_P, SRM;0, SRM;1,
implantation for both LP and GP.
SRM;2, RH, VAR, POFUSE, VTH_P,
2.40LPG: Delta dose implantation for
BJTDMY, DCO, NP
LPHVt PMOS and G LVt PMOS.
NP, NW, OD2, RH, VAR, SRM;0,
POFUSE, SRM;1, SRM;2, VTH_N,
GP Core device PLDD implantation.
BJTDMY, DCO, PP
GP SRAM cell PMOS Vt
SRM;2, DCO, VTH_P, NP
It is a must if GP SRAM cell is used.
(N40LPG only)
(1) N45LPG: 11C is a must if
OD2, NW, VTL_P, SRM;0, SRM;2, RH,
(a) No PMOS LVT (117) and
VAR, POFUSE, VTH_P, BJTDMY
(b) NCI SRAM cell is used
(c) Only for LP of LPG
PP, NW, OD2, RH, VAR, SRM;0,
SRM;1, SRM;2, BJTDMY, VTH_P, DCO, LP Core device PLDD implantation.
POFUSE
SRM;2, DCO, VTH_P, NP
LP SRAM cell PMOS Vt.
PP, SRM;0
P+ implantation.
NP, SRM;0, POFUSE, DUMMYOD9,
N+ implantation.
PP, PRSRM, SRM_HC, SRM_HD
ESD implantation.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
32 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Key Process
Sequence
* = Optional
Mask
Confidential – Do Not Copy
Mask
Name
Mask
ID
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Digitized Area
Reference Layer in Logical Operation
CAD Layer
(Dark or Clear)
and OPC
29*
RPO2
124
C
Derived
30
RPO
155
D
Derived
31
CO
156
C
Derived
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
360
378
380
379
381
373
384
374
385
375
386
376
387
377
388
372
389
37A
38A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
31
51
32
52
33
53
34
54
35
55
36
56
37
57
38
58
39
59
40
OD2, BJTDMY, POFUSE, RH, DCO,
SRM;0
PO
CO;0, CO;11, OD, SRM;0,
SRAMDMY;4, SRAMDMY;1, PRSRM,
SRM_UHD, DUMMYOD1~4,
DUMMYOD10~12, DUMMYPO1,
DUMMYPO5, SRM_HD, NW,
SRM_HCDP, DPSRM, NDIFF, PDIFF,
NP, PO, PP, SRM_10TTP, SRM_8TTP,
SRM_LV, SRM_HC
M1, DM1, DM1_O, VIA1
DVIA1
M2, DM2, DM2_O, VIA1, VIA2
DVIA2
M3, DM3, DM3_O, VIA2, VIA3
DVIA3
M4, DM4, DM4_O, VIA3, VIA4
DVIA4
M5, DM5, DM5_O, VIA4, VIA5
DVIA5
M6, DM6, DM6_O, VIA5, VIA6
DVIA6
M7, DM7, DM7_O, VIA6, VIA7
DVIA7
M8, DM8, DM8_O, VIA7, VIA8
M9, DM9, VIA8, VIA9
M10, DM10, VIA9
Description
It is a must for 3.3V(N40LPG only)
Silicide protection.
Contact window from M1 to OD or
PO.
1st metal for interconnection.
Via1 hole between M2 and M1.
2nd metal for interconnection.
Via2 hole between M3 and M2.
3rd metal for interconnection.
Via3 hole between M4 and M3.
4th metal for interconnection.
Via4 hole between M5 and M4.
5th metal for interconnection.
Via5 hole between M6 and M5.
6th metal for interconnection.
Via6 hole between M7 and M6.
7th metal for interconnection.
Via7 hole between M8 and M7.
8th metal for interconnection.
Via8 hole between M9 and M8.
9th metal for interconnection.
Via9 hole between M10 and M9.
10th metal for interconnection
FBEOL option1 (Wire bond without AP RDL)
51
52
CB
AP
107
307
C
D
53
CB2
308
C
54*
PM
009
D
76
Derived
86;20
(CB2_WB)
Derived
5;0
CB, CB2_WB
Passivation-1 open for bond pad.
Al pad.
-
Passivation-2 open for bond pad.
CB2_WB
-
Polyimide opening
-
Passivation-1 open for bump pad.
Al pad.
-
Passivation-2 open for bump pad.
-
Polyimide opening
Under bump metallurgy for flip chip.
Derived
74
86;20
(CB2_WB)
Derived
5;0
CB, RV
-
Passivation-1 open for bond pad, AP RDL via.
Al pad, AP RDL.
-
Passivation-2 open.
CB2_WB
-
Polyimide opening
Derived
74
86;0
(CB2_FC)
5;0
170;0
CBD, RV
-
Passivation-1 open for bump pad, AP RDL via.
Al pad, AP RDL.
-
Passivation-2 open.
-
Polyimide opening
Under bump metallurgy for flip chip.
FBEOL option2 (Flip chip without AP RDL)
51
52
CB
AP
107
307
C
D
53
CB2
308
C
54
55
PM
UBM
009
020
D
D
169
74
86;0
(CB2_FC)
5;0
170;0
FBEOL option3 (Wire bond with AP RDL)
51
52
CB-VD
AP-MD
306
309
C
D
53
CB2
308
C
54*
PM
009
D
FBEOL option4 (Flip chip with AP RDL)
51
52
CB-VD
AP-MD
306
309
C
D
53
CB2
308
C
54
55
PM
UBM
009
020
D
D
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
33 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Table 3.1.4 Mask Name and ID, Key Process Sequence, and CAD Layer for CLN40G
Key Process
Sequence
* = Optional
Mask
Mask
Name
Mask
ID
Digitized
Area (Dark
or Clear)
CAD
Layer
Reference Layer in Logical
Operation and OPC
1
OD
120
D
Derived
2*
3#
4#
DNW
PW1V
PW2V
119
191
193
C
D
C
1
Derived
Derived
OD, DOD, SR_DOD,
DUMMYOD1~12, DUMMYOD16,
DPSRM, SRM_10TTP,
SRM_HCDP, SRM;0, NW, OD2,
PO, PP, CO, NDIFF, PDIFF,
PRSRM, SRM_8TTP, SRM_HC,
SRM_HD, SRM_LV,
NW, NT_N, OD2, SRM;0
OD2, NW, NT_N
5*
VTH_N
11H
C
Derived
VTH_N, SRM;0, SRM;1
6#
7#
8*
9*
NW1V
NW2V
VTH_P
OD_12
192
194
11G
12A
C
C
C
C
OD2, NW, NT_N, SRM;0
NW, OD2, NT_N
VTH_P, SRM;0
-
10
OD2
152
D
11#
NPO
196
C
Derived
Derived
Derived
14;1
16
18
Derived
12
PO
130
D
Derived
13#
N2V
116
C
Derived
14#
P2V
115
C
Derived
15
ODRZ
123
C
Derived
16*
VTL_N
118
D
Derived
17#
N1V
114
C
Derived
18*
VTC_N
112
C
50;1
19*
VTL_P
117
C
Derived
20#
P1V
113
C
Derived
21*
VTC_P
199
C
50;2
22*
VTL_P2
11C
C
Derived
23
24*
25
26
NSSD
ESD
PP
NP
13A
111
197
198
C
C
C
C
Derived
189;0
Derived
Derived
27
SSMT
124
C
Derived
28
RPO
155
D
Derived
29
NILD
12E
C
Derived
30
PILD
12F
C
Derived
OD2, OD_12
Description
Device, ACTIVE, STRAP and
interconnection regions
Deep N-Well.
Core device P-Well.
1.8V or 2.5V P-Well.
High Vt NMOS implantation.
N40G: 11H is a must if SRAM is
used.
Core device N-Well.
1.8V or 2.5V N-Well.
High Vt PMOS implantation.
1.2V device oxide
1.8V or 2.5V thick oxide for DGO
process.
Pre-doped N+ poly.
NP, SRM;0, SRM;21, POFUSE
PO, OD, OD2, OD_12, NP, PP,
SRM;0, DPO, SR_DPO, NDIFF,
PDIFF, POFUSE, DPSRM,
Poly-Si.
SRM_HCDP, PRSRM,
DUMMYPO5, SRAMDMY;1
NP, NW, OD2, RH, VAR, POFUSE,
1.8V or 2.5V NLDD implantation.
NT_N, BJTDMY,
PP, NW, OD2, RH, VAR, NT_N,
1.8V or 2.5V PLDD implantation.
POFUSE, BJTDMY
PP, NP, NW, OD2, RH, VAR, AP,
DOD, SRM;0, SR_ESD, OD, PO,
DPO, SR_DPO, BJTDMY, NDIFF,
PDIFF,
OD2, NW, VTL_N, SRM;0, NT_N,
SRM;1, RH, VAR, POFUSE,
Low Vt NMOS implantation
SRM;2, , BJTDMY
NP, NW, OD2, RH, VAR, SRM;0,
POFUSE, SRM;1, SRM;2 , VTH_N, Core device NLDD implantation.
BJTDMY
SRAM cell NMOS Vt.
OD2, NW, VTL_P, SRM;0, SRM;1,
SRM;2, RH, VAR, POFUSE, NT_N, Low Vt PMOS implantation
PP, BJTDMY
PP, NW, OD2, RH, VAR, SRM;0,
SRM;2, BJTDMY, VTH_P, SRM;1, Core device PLDD implantation.
NT_N, POFUSE
SRAM cell PMOS Vt.
11C is a must if N40GL 0.8V and N40G
SRM;2, SRM_HC, SRM_HCDP
0.9V SRAM cell are both used
PO, DPO, SR_DPO
ESD implantation.
PP, SRM;0
P+ implantation.
NP, SRM;0, POFUSE
N+ implantation.
NW, OD2, PP, SRN;0, BJTDMY,
RH, VAR, POFUSE, SRM;0,
SRM;1, SRM;2
PO
Silicide protection.
NW, OD, OD2 (OD_18, OD_25,
OD_33), PO, NP, PP, CO, SRM;0,
RH, VAR, POFUSE, BJTDMY,
NDIFF, PDIFF, DOD
NW, OD, OD2 (OD_18, OD_25,
OD_33), PO, NP, PP, CO, SRM;0,
RH, VAR, POFUSE, BJTDMY,
NDIFF, PDIFF, DOD
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
34 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Key Process
Sequence
* = Optional
Mask
Confidential – Do Not Copy
Mask
Name
Mask
ID
Digitized
Area (Dark
or Clear)
CAD
Layer
31
CO
156
C
Derived
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
360
378
380
379
381
373
384
374
385
375
386
376
387
377
388
372
389
37A
38A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
31
51
32
52
33
53
34
54
35
55
36
56
37
57
38
58
39
59
40
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Reference Layer in Logical
Operation and OPC
CO;0, CO;11, OD, SRM;0,
SRAMDMY;1, SRAMDMY;5, NP,
NW, PO, PP, DUMMYOD1~4,
DUMMYOD11, DUMMYOD12,
NDIFF, PDIFF, DPSRM, SRM_HC,
PRSRM, DUMMYPO1,
DUMMYPO5, SRM_10TTP,
SRM_8TTP, SRM_LV, SRM_HD,
SRM_HCDP
M1, DM1, DM1_O, VIA1
DVIA1
M2, DM2, DM2_O, VIA1, VIA2
DVIA2
M3, DM3, DM3_O, VIA2, VIA3
DVIA3
M4, DM4, DM4_O, VIA3, VIA4
DVIA4
M5, DM5, DM5_O, VIA4, VIA5
DVIA5
M6, DM6, DM6_O, VIA5, VIA6
DVIA6
M7, DM7, DM7_O, VIA6, VIA7
DVIA7
M8, DM8, DM8_O, VIA7, VIA8
M9, DM9, VIA8, VIA9
M10, DM10, VIA9
Description
Contact window from M1 to OD or PO.
1st metal for interconnection.
Via1 hole between M2 and M1.
2nd metal for interconnection.
Via2 hole between M3 and M2.
3rd metal for interconnection.
Via3 hole between M4 and M3.
4th metal for interconnection.
Via4 hole between M5 and M4.
5th metal for interconnection.
Via5 hole between M6 and M5.
6th metal for interconnection.
Via6 hole between M7 and M6.
7th metal for interconnection.
Via7 hole between M8 and M7.
8th metal for interconnection.
Via8 hole between M9 and M8.
9th metal for interconnection.
Via9 hole between M10 and M9.
10th metal for interconnection
FBEOL option1 (Wire bond without AP RDL)
51
52
CB
AP
107
307
C
D
53
CB2
308
C
54*
PM
009
D
76
Derived
86;20
(CB2_WB)
Derived
5;0
CB, CB2_WB
Passivation-1 open for bond pad.
Al pad.
-
Passivation-2 open for bond pad.
CB2_WB
-
Polyimide opening
169
74
86;0
(CB2_FC)
5;0
170;0
-
Passivation-1 open for bump pad.
Al pad.
-
Passivation-2 open for bump pad.
-
Polyimide opening
Under bump metallurgy for flip chip.
FBEOL option2 (Flip chip without AP RDL)
51
52
CB
AP
107
307
C
D
53
CB2
308
C
54
55
PM
UBM
009
020
D
D
FBEOL option3 (Wire bond with AP RDL)
51
CB-VD
306
C
Derived
CB, RV
52
AP-MD
309
D
-
53
CB2
308
C
-
Passivation-2 open.
54*
PM
009
D
74
86;20
(CB2_WB)
Derived
5;0
Passivation-1 open for bond pad, AP
RDL via.
Al pad, AP RDL.
CB2_WB
-
Polyimide opening
FBEOL option4 (Flip chip with AP RDL)
51
CB-VD
306
C
Derived
CBD, RV
52
AP-MD
309
D
-
53
CB2
308
C
-
Passivation-2 open.
54
55
PM
UBM
009
020
D
D
74
86;0
(CB2_FC)
5;0
170;0
Passivation-1 open for bump pad, AP
RDL via.
Al pad, AP RDL.
-
Polyimide opening
Under bump metallurgy for flip chip.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
35 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Table 3.1.5
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
N45LP/N40LP/N40LP+/N45LPG/N40LPG Mask Name/ID/Grade/Type, OPC, and PSM
Information
Mask Name
Mask ID
Mask Grade
Mask Type
OPC
PSM
Group
OD
DNW
PW1V
VTC_N
VTC_P
PW2V
VTH_N
NW1V
NW2V
VTH_P
OD2
DCO/DCO_LPP
NPO
PO
VTC_N2
VTC_P2
N2V
P2V
VTL_N
ULVT_N
N1V_G
VTC_N_GP
VTC_P_GP
N1V
VTL_P
ULVT_P
VTL_P2
P1V_G
P1V
NP
PP
ESD
RPO2
RPO
CO
M1
VIA1
M2
120
119
191
112
199
193
11H
192
194
11G
152
153
196
130
11N
11P
116
115
118
11E
106
104
103
114
117
11F
11C
105
113
198
197
111
124
155
156
360
378
380
L
E
H
H
H
H
H
H
H
H
H
H
H
M
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
F
L
L
K
K
K
I (N45)
J (N40)
F
K
I
F
K
I (N45)
J (N40)
F
K
I
F
F
K
I (N45)
J (N40)
F
K
I
F
F
ASF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
ASF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
ASF
ASF
ASF
ASF
ASF
DSF (N45)
ASF (N40)
DSF
ASF
DSF
DSF
ASF
DSF (N45)
ASF (N40)
DSF
ASF
DSF
DSF
DSF
ASF
DSF (N45)
ASF (N40)
DSF
ASF
DSF
DSF
DSF
A
B
B
A
A
B
A
B
B
A
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
B
A
A
A
A
A
C
B
B
B
B
B
B
B
B
B
B
B
B
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
VIAx
A
C
VIAy
B
A
A
B
A
B
C
B
B
C
VIAz
Mx
My
Mz
VIAx
A
C
VIAy
B
A
A
B
B
A
B
C
B
B
B
C
VIAz
Mx
My
Mz
Mu
VIAx
A
C
VIAy
B
A
A
B
B
B
C
B
B
B
VIAz
Mx
My
Mz
Mu
VIA2
379
M3
381
VIA3
373
M4
384
VIA4
374
M5
385
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
36 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Mask Name
VIA5
Document No.
Version
Confidential – Do Not Copy
Mask ID
375
M6
386
VIA6
376
M7
387
VIA7
377
M8
388
VIA8
372
M9
389
VIA9
37A
M10
38A
CB
CB-VD
AP
AP-MD
CB2
107
306
307
309
308
: T-N45-CL-DR-001
: 2.6
Mask Grade
Mask Type
OPC
PSM
Group
K
I (N45)
J (N40)
F
K
I
F
F
K
I (N45)
J (N40)
F
F
F
K
I
F
F
F
K
I (N45)
J (N40)
F
F
K
I
F
F
F
I (N45)
J (N40)
F
F
I
F
F
F
F
I (N45)
J (N40)
F
F
I
F
F
F
A
D
A
D
A
ASF
DSF (N45)
ASF (N40)
DSF
ASF
DSF
DSF
DSF
ASF
DSF (N45)
ASF (N40)
DSF
DSF
DSF
ASF
DSF
DSF
DSF
DSF
ASF
DSF (N45)
ASF (N40)
DSF
DSF
ASF
DSF
DSF
DSF
DSF
DSF (N45)
ASF (N40)
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF (N45)
ASF (N40)
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
A
C
VIAx
A
C
VIAy
B
A
A
B
B
A
B
C
B
B
B
C
VIAz
Mx
My
Mz
Mu
VIAx
A
C
VIAy
B
B
B
A
A
B
B
B
A
B
B
B
C
B
B
B
B
C
VIAz
VIAu
VIAr
Mx
My
Mz
Mr
Mu
VIAx
A
C
VIAy
B
B
A
A
B
B
B
B
B
C
B
B
B
B
VIAz
VIAr
Mx
My
Mz
Mr
Mu
A
C
VIAy
B
B
A
B
B
B
B
B
B
B
B
B
B
B
VIAz
VIAr
My
Mz
Mr
Mr
Mu
A
C
VIAy
B
B
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
VIAz
VIAr
My
Mz
Mr
Mu
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
37 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Table 3.1.6
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
N40G Mask Name/ID/Grade/Type, OPC, and PSM Information
Mask Name
OD
DNW
PW1V
VTC_N
VTC_P
PW2V
VTH_N
NW1V
NW2V
VTH_P
OD2
OD_12
NILD
PILD
ODRZ
NSSD
SSMT
NPO
PO
N2V
P2V
VTL_N
N1V
VTL_P
VTL_P2
P1V
NP
PP
ESD
RPO
CO
M1
VIA1
M2
Mask ID
120
119
191
112
199
193
11H
192
194
11G
152
12A
12E
12F
123
13A
124
196
130
116
115
118
114
117
11C
113
198
197
111
155
156
360
378
380
VIA2
379
M3
381
VIA3
373
M4
384
VIA4
374
M5
385
VIA5
375
M6
386
VIA6
376
Mask Grade
L
E
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
M
H
H
H
H
H
H
H
H
H
H
F
L
L
K
K
K
J
F
K
I
F
K
J
F
K
I
F
K
J
F
K
I
F
K
J
F
K
I
F
K
J
F
F
F
Mask Type
ASF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
ASF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
ASF
ASF
ASF
ASF
ASF
ASF
DSF
ASF
DSF
DSF
ASF
ASF
DSF
ASF
DSF
DSF
ASF
ASF
DSF
ASF
DSF
DSF
ASF
ASF
DSF
ASF
DSF
DSF
ASF
ASF
DSF
DSF
DSF
OPC
A
B
B
A
A
B
A
B
B
A
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
A
A
A
A
A
A
B
A
A
B
A
A
B
A
A
B
A
A
B
A
A
B
A
A
B
A
A
B
A
A
B
B
B
PSM
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
B
C
B
B
C
C
B
C
B
B
C
C
B
C
B
B
C
C
B
C
B
B
C
C
B
B
B
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Group
VIAx
VIAy
VIAz
Mx
My
Mz
VIAx
VIAy
VIAz
Mx
My
Mz
VIAx
VIAy
VIAz
Mx
My
Mz
VIAx
VIAy
VIAz
Mx
My
Mz
VIAx
VIAy
VIAz
VIAu
VIAr
38 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Confidential – Do Not Copy
Mask Name
Mask ID
M7
387
VIA7
377
M8
388
VIA8
372
M9
389
VIA9
37A
M10
38A
CB
CB-VD
AP
AP-MD
CB2
107
306
307
309
308
Category
Mask type:
OPC:
PSM:
Mask Grade
K
I
F
F
K
J
F
F
K
I
F
F
J
F
F
I
F
F
J
F
F
I
F
F
A
D
A
D
A
Abbreviation
Description
DSF
ASF
B
A
B
C
DUV scanner
193nm scanner
Non-OPC (Binary)
OPC
Non-PSM (Binary)
PSM
Mask Type
ASF
DSF
DSF
DSF
ASF
ASF
DSF
DSF
ASF
DSF
DSF
DSF
ASF
DSF
DSF
DSF
DSF
DSF
ASF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
DSF
Document No.
Version
OPC
A
A
B
B
A
A
B
B
A
A
B
B
B
B
B
A
B
B
B
B
B
A
B
B
B
B
B
B
B
: T-N45-CL-DR-001
: 2.6
PSM
C
B
B
B
C
C
B
B
C
B
B
B
C
B
B
B
B
B
C
B
B
B
B
B
B
B
B
B
B
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Group
Mx
My
Mz
Mr
VIAx
VIAy
VIAz
VIAr
Mx
My
Mz
Mr
VIAy
VIAz
VIAr
My
Mz
Mr
VIAy
VIAz
VIAr
My
Mz
Mr
39 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Table 3.1.7
Mask
120
119
191
193
192
194
152
12A
196
130
116
115
11H
118
114
112
11G
117
113
199
13A
197
198
111
124
123
12E
12F
155
156
Mask
120
119
191
193
192
194
152
12A
196
130
116
115
11H
118
114
112
11G
117
113
199
13A
197
198
111
124
123
12E
12F
155
156
: T-N45-CL-DR-001
: 2.6
N40G 1.8V Mask to CAD layer mapping table
CAD
Mask
120
119
191
193
192
194
152
12A
196
130
116
115
11H
118
114
112
11G
117
113
199
13A
197
198
111
124
123
12E
12F
155
156
Document No.
Version
Confidential – Do Not Copy
OD
DNW
PW1V
PW2V
NW1V
NW2V
OD2
OD_12
NPO
PO
N2V
P2V
VTH_N
VTL_N
N1V
VTC_N
VTH_P
VTL_P
P1V
VTC_P
NSSD
PP
NPO
ESD
SSMT
ODRZ
NILD
PILD
RPO
CO
CAD
OD
DNW
PW1V
PW2V
NW1V
NW2V
OD2
OD_12
NPO
PO
N2V
P2V
VTH_N
VTL_N
N1V
VTC_N
VTH_P
VTL_P
P1V
VTC_P
NSSD
PP
NPO
ESD
SSMT
ODRZ
NILD
PILD
RPO
CO
CAD
OD
DNW
PW1V
PW2V
NW1V
NW2V
OD2
OD_12
NPO
PO
N2V
P2V
VTH_N
VTL_N
N1V
VTC_N
VTH_P
VTL_P
P1V
VTC_P
NSSD
PP
NPO
ESD
SSMT
ODRZ
NILD
PILD
RPO
CO
DNW
1;0
NW
3;0
V
OD
6;0
V
DOD
6;1
V
NT_N
11;0
VTL_N
12;0
VTL_P
13;0
OD_12
14;1
OD_18
16;0
V
PO
17;0
V
DPO
17;1
SR_DPO
17;7
PP
25;0
V
V
V
V
V
NP
26;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RPO
29;0
V
CO
30;0
V
V
V
V
V
CO;11
30;11
V
V
V
SRM;0
50;0
V
V
SRM;1
50;1
SRM;2
50;2
SRM;21
50;21
VTH_N
67;0
VTH_P
68;0
V
V
V
V
V
DPSRM
80;0
V
PRSRM
80;11
V
V
V
V
VAR
143;0
V
POFUSE
156;0
V
V
V
V
V
SRM_HC
80;13
V
V
SRM_HD
80;14
V
V
SRAMDMY
186
V
ESDIMP
189;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SRM_LV
80;15
V
V
SRM_HCDP
80;16
V
V
SRM_8TTP
80;17
V
V
SRM_10TTP
80;18
V
DUMMYOD
82
V
V
DUMMYPO
83
BJTDMY
110;0
RH
117;0
SR_ESD
121;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
V
40 of 600
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SECURITY B – TSMC RESTRICTED SECRET
tsmc
Table 3.1.8
Mask
120
119
191
193
192
194
152
12A
196
130
116
115
11H
118
114
112
11G
117
113
199
13A
197
198
111
124
123
12E
12F
155
156
Mask
120
119
191
193
192
194
152
12A
196
130
116
115
11H
118
114
112
11G
117
113
199
13A
197
198
111
124
123
12E
12F
155
156
: T-N45-CL-DR-001
: 2.6
N40G 2.5V Mask to CAD layer mapping table
CAD
Mask
120
119
191
193
192
194
152
12A
196
130
116
115
11H
118
114
112
11G
117
113
199
13A
197
198
111
124
123
12E
12F
155
156
Document No.
Version
Confidential – Do Not Copy
OD
DNW
PW1V
PW2V
NW1V
NW2V
OD2
OD_12
NPO
PO
N2V
P2V
VTH_N
VTL_N
N1V
VTC_N
VTH_P
VTL_P
P1V
VTC_P
NSSD
PP
NPO
ESD
SSMT
ODRZ
NILD
PILD
RPO
CO
CAD
OD
DNW
PW1V
PW2V
NW1V
NW2V
OD2
OD_12
NPO
PO
N2V
P2V
VTH_N
VTL_N
N1V
VTC_N
VTH_P
VTL_P
P1V
VTC_P
NSSD
PP
NPO
ESD
SSMT
ODRZ
NILD
PILD
RPO
CO
CAD
OD
DNW
PW1V
PW2V
NW1V
NW2V
OD2
OD_12
NPO
PO
N2V
P2V
VTH_N
VTL_N
N1V
VTC_N
VTH_P
VTL_P
P1V
VTC_P
NSSD
PP
NPO
ESD
SSMT
ODRZ
NILD
PILD
RPO
CO
DNW
1;0
NW
3;0
V
OD
6;0
V
DOD
6;1
V
NT_N
11;0
VTL_N
12;0
VTL_P
13;0
OD_12
14;1
OD_25
18;0
V
PO
17;0
V
DPO
17;1
SR_DPO
17;7
PP
25;0
V
V
V
V
V
NP
26;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RPO
29;0
V
CO
30;0
V
V
V
V
V
CO;11
30;11
V
V
V
V
V
V
V
SRM;0
50;0
V
SRM;1
50;1
SRM;2
50;2
SRM;21
50;21
VTH_N
67;0
VTH_P
68;0
V
V
V
V
V
DPSRM
80;0
V
PRSRM
80;11
V
V
V
V
VAR
143;0
V
POFUSE
156;0
V
V
V
V
V
SRM_HC
80;13
V
V
SRM_HD
80;14
V
V
SRAMDMY
186
V
ESDIMP
189;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SRM_LV
80;15
V
V
SRM_HCDP
80;16
V
V
SRM_8TTP
80;17
V
V
SRM_10TTP
80;18
V
DUMMYOD
82
V
V
DUMMYPO
83
BJTDMY
110;0
RH
117;0
SR_ESD
121;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
V
41 of 600
V
V
V
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Table 3.1.9
DNW
1;0
: T-N45-CL-DR-001
: 2.6
N40LP 1.8V Mask to CAD layer mapping table
NW
OD
DOD
NT_N
Mask
3;0
6;0
6;1
11;0
120
OD
V
V
V
119 DNW
V
191 PW1V
V
V
193 PW2V
V
V
192 NW1V
V
V
152
OD2
196
NPO
130
PO
V
116
N2V
V
V
115
P2V
V
V
V
11H VTH_N
118 VTL_N
V
114
N1V
V
11N VTC_N2
V
112 VTC_N
11G VTH_P
117 VTL_P
V
113
P1V
V
11P VTC_P2
V
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
V
156
CO
V
V
SRM;1
SRM;2
SRM;21
VTH_N
VTH_P
CAD
Mask
50;1
50;2
50;21
67;0
68;0
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
V
130
PO
V
V
116
N2V
115
P2V
11H VTH_N
V
118 VTL_N
V
V
V
114
N1V
V
V
V
11N VTC_N2
V
112 VTC_N
V
V
11G VTH_P
V
117 VTL_P
V
V
V
113
P1V
V
V
V
11P VTC_P2
V
V
199 VTC_P
V
V
197
PP
198
NP
111
ESD
155
RPO
156
CO
CAD DUMMYOD4 DUMMYOD5 DUMMYOD6 DUMMYOD7 DUMMYOD8
Mask
82;4
82;5
82;6
82;7
82;8
120
OD
V
V
V
V
V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
130
PO
116
N2V
115
P2V
11H VTH_N
118 VTL_N
114
N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
156
CO
HVD_N
HVD_P
CAD
Mask
91;1
91;2
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
130
PO
116
N2V
V
115
P2V
11H VTH_N
118 VTL_N
114
N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
V
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
V
V
156
CO
CAD
Document No.
Version
Confidential – Do Not Copy
VTL_N
12;0
VTL_P
13;0
OD_18
16;0
PO
17;0
DPO
17;1
SR_DPO
17;7
PP
25;0
NP
26;0
RPO
29;0
CO
30;0
CO;11
30;11
V
V
SRM;0
50;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SRM_10TTP DUMMYOD DUMMYOD1 DUMMYOD2 DUMMYOD3
DPSRM
PRSRM
SRM_HC
SRM_HD
SRM_LV
SRM_HCDP
SRM_8TTP
80;0
V
80;11
V
80;13
V
80;14
V
80;15
V
80;16
V
80;17
V
80;18
V
82
82;1
V
V
V
82;2
V
82;3
V
V
V
V
V
V
V
DUMMYOD11 DUMMYOD12
82;11
82;12
V
V
V
V
V
V
DUMMYOD16 DUMMYPO1 DUMMYPO5
82;16
V
83;1
83;5
V
V
V
V
V
V
V
V
BJTDMY
RH
VAR
POFUSE
SRAMDMY;1
SRAMDMY;4
ESDIMP
110;0
117;0
143;0
156;0
186;1
186;4
189;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
42 of 600
SECURITY B – TSMC RESTRICTED SECRET
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Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
Table 3.1.10 N45LP 1.8V Mask to CAD layer mapping table
DNW
NW
OD
DOD
NT_N
CAD
Mask
1;0
3;0
6;0
6;1
11;0
120
OD
V
V
V
119 DNW
V
191 PW1V
V
V
193 PW2V
V
V
192 NW1V
V
V
152
OD2
196
NPO
130
PO
V
116
N2V
V
V
115
P2V
V
V
V
11H VTH_N
118 VTL_N
V
114
N1V
V
11N VTC_N2
V
112 VTC_N
11G VTH_P
117 VTL_P
V
113
P1V
V
11P VTC_P2
V
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
V
156
CO
V
V
SRM;1
SRM;2
SRM;21
VTH_N
VTH_P
CAD
Mask
50;1
50;2
50;21
67;0
68;0
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
V
130
PO
V
V
116
N2V
115
P2V
11H VTH_N
V
118 VTL_N
V
V
V
114
N1V
V
V
V
11N VTC_N2
V
112 VTC_N
V
V
11G VTH_P
V
117 VTL_P
V
V
V
113
P1V
V
V
V
11P VTC_P2
V
V
199 VTC_P
V
V
197
PP
198
NP
111
ESD
155
RPO
156
CO
CAD DUMMYOD4 DUMMYOD5 DUMMYOD6 DUMMYOD7 DUMMYOD8
Mask
82;4
82;5
82;6
82;7
82;8
120
OD
V
V
V
V
V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
130
PO
116
N2V
115
P2V
11H VTH_N
118 VTL_N
114
N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
156
CO
VTL_N
12;0
VTL_P
13;0
OD_18
16;0
PO
17;0
DPO
17;1
SR_DPO
17;7
PP
25;0
NP
26;0
RPO
29;0
CO
30;0
CO;11
30;11
V
V
SRM;0
50;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SRM_10TTP DUMMYOD DUMMYOD1 DUMMYOD2 DUMMYOD3
DPSRM
PRSRM
SRM_HC
SRM_HD
SRM_LV
SRM_HCDP
SRM_8TTP
80;0
V
80;11
V
80;13
V
80;14
V
80;15
V
80;16
V
80;17
V
80;18
V
82
82;1
V
V
V
82;2
V
82;3
V
V
V
V
V
V
V
DUMMYOD11 DUMMYOD12
82;11
82;12
V
V
V
V
V
V
DUMMYOD16 DUMMYPO1 DUMMYPO5
82;16
V
83;1
83;5
V
V
V
V
V
V
V
V
BJTDMY
RH
VAR
POFUSE
SRAMDMY;1
SRAMDMY;4
ESDIMP
110;0
117;0
143;0
156;0
186;1
186;4
189;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
43 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
Table 3.1.11 N40LP 2.5V Mask to CAD layer mapping table
DNW
NW
OD
DOD
NT_N
CAD
Mask
1;0
3;0
6;0
6;1
11;0
120
OD
V
V
V
119 DNW
V
191 PW1V
V
V
193 PW2V
V
V
192 NW1V
V
V
152
OD2
196
NPO
130
PO
V
116
N2V
V
V
V
115
P2V
V
V
V
11H VTH_N
118 VTL_N
V
114
N1V
V
11N VTC_N2
V
112 VTC_N
11G VTH_P
117 VTL_P
V
113
P1V
V
11P VTC_P2
V
199 VTC_P
197
PP
198
NP
111
ESD
124 SSMT
155
RPO
V
156
CO
V
V
SRM;1
SRM;2
SRM;21
VTH_N
VTH_P
CAD
Mask
50;1
50;2
50;21
67;0
68;0
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
V
130
PO
V
V
116
N2V
115
P2V
11H VTH_N
V
118 VTL_N
V
V
V
114
N1V
V
V
V
11N VTC_N2
V
112 VTC_N
V
V
11G VTH_P
V
117 VTL_P
V
V
V
113
P1V
V
V
V
11P VTC_P2
V
V
199 VTC_P
V
V
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
CAD DUMMYOD4 DUMMYOD5 DUMMYOD6 DUMMYOD7 DUMMYOD8
82;4
82;5
82;6
82;7
82;8
Mask
120
OD
V
V
V
V
V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
130
PO
116
N2V
115
P2V
11H VTH_N
118 VTL_N
114
N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
HVD_N
HVD_P
CAD
Mask
91;1
91;2
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
130
PO
116
N2V
V
V
115
P2V
11H VTH_N
118 VTL_N
114
N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
V
V
156
CO
VTL_N
12;0
VTL_P
13;0
OD_25
18;0
PO
17;0
DPO
17;1
SR_DPO
17;7
PP
25;0
NP
26;0
RPO
29;0
CO
30;0
CO;11
30;11
V
V
SRM;0
50;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DPSRM
PRSRM
SRM_HC
SRM_HD
V
V
SRM_LV
SRM_HCDP
SRM_8TTP
SRM_10TTP DUMMYOD DUMMYOD1 DUMMYOD2 DUMMYOD3
V
80;0
V
80;11
V
80;13
V
80;14
V
80;15
V
80;16
V
80;17
V
80;18
V
82
82;1
V
V
V
82;2
V
82;3
V
V
V
V
V
V
V
DUMMYOD11 DUMMYOD12
82;11
82;12
V
V
V
V
V
V
DUMMYOD16 DUMMYPO1 DUMMYPO5
82;16
V
83;1
83;5
V
V
V
V
V
V
V
V
BJTDMY
RH
VAR
POFUSE
SRAMDMY;1
SRAMDMY;4
ESDIMP
110;0
117;0
143;0
156;0
186;1
186;4
189;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
V
V
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Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
Table 3.1.12 N45LP 2.5V Mask to CAD layer mapping table
DNW
NW
OD
DOD
NT_N
CAD
Mask
1;0
3;0
6;0
6;1
11;0
120
OD
V
V
V
119 DNW
V
191 PW1V
V
V
193 PW2V
V
V
192 NW1V
V
V
152
OD2
196
NPO
130
PO
V
116
N2V
V
V
V
115
P2V
V
V
V
11H VTH_N
118 VTL_N
V
114
N1V
V
11N VTC_N2
V
112 VTC_N
11G VTH_P
117 VTL_P
V
113
P1V
V
11P VTC_P2
V
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
V
156
CO
V
V
SRM;1
SRM;2
SRM;21
VTH_N
VTH_P
CAD
Mask
50;1
50;2
50;21
67;0
68;0
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
V
130
PO
V
V
116
N2V
115
P2V
11H VTH_N
V
118 VTL_N
V
V
V
114
N1V
V
V
V
11N VTC_N2
V
112 VTC_N
V
V
11G VTH_P
V
117 VTL_P
V
V
V
113
P1V
V
V
V
11P VTC_P2
V
V
199 VTC_P
V
V
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
CAD DUMMYOD4 DUMMYOD5 DUMMYOD6 DUMMYOD7 DUMMYOD8
82;4
82;5
82;6
82;7
82;8
Mask
120
OD
V
V
V
V
V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
130
PO
116
N2V
115
P2V
11H VTH_N
118 VTL_N
114
N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
HVD_N
HVD_P
CAD
Mask
91;1
91;2
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
196
NPO
130
PO
116
N2V
115
P2V
11H VTH_N
118 VTL_N
114
N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
V
V
156
CO
VTL_N
12;0
VTL_P
13;0
OD_25
18;0
PO
17;0
DPO
17;1
SR_DPO
17;7
PP
25;0
NP
26;0
RPO
29;0
CO
30;0
CO;11
30;11
V
V
SRM;0
50;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DPSRM
PRSRM
SRM_HC
SRM_HD
V
V
SRM_LV
SRM_HCDP
SRM_8TTP
SRM_10TTP DUMMYOD DUMMYOD1 DUMMYOD2 DUMMYOD3
V
80;0
V
80;11
V
80;13
V
80;14
V
80;15
V
80;16
V
80;17
V
80;18
V
82
82;1
V
V
V
82;2
V
82;3
V
V
V
V
V
V
V
DUMMYOD11 DUMMYOD12
82;11
82;12
V
V
V
V
V
V
DUMMYOD16 DUMMYPO1 DUMMYPO5
82;16
V
83;1
83;5
V
V
V
V
V
V
V
V
BJTDMY
RH
VAR
POFUSE
SRAMDMY;1
SRAMDMY;4
ESDIMP
110;0
117;0
143;0
156;0
186;1
186;4
189;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
V
V
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Table 3.1.13 N40LP Plus (N40LP+) 2.5V Mask to CAD layer mapping table
DNW
NW
OD
DOD
NT_N
VTL_N
VTL_P
OD_25
PO
DPO
SR_DPO
PP
NP
RPO
CO
CO;11
SRM;0
SRM;1
CAD
Mask
1;0
3;0
6;0
6;1
11;0
12;0
13;0
18;0
17;0
17;1
17;7
25;0
26;0
29;0
30;0
30;11
50;0
50;1
120
OD
V
V
V
V
119
DNW
V
191
PW1V
V
V
V
V
193
PW2V
V
V
V
192
NW1V
V
V
V
152
OD2
V
153 DCO_LPP
196
NPO
V
V
130
PO
V
V
V
V
V
V
V
V
V
116
N2V
V
V
V
V
V
V
V
115
P2V
V
V
V
V
V
V
V
11H VTH_N
V
118 VTL_N
V
V
V
V
V
V
11E ULVT_N
V
114
N1V
V
V
V
V
V
V
11N VTC_N2
V
V
V
V
112 VTC_N
V
V
11G VTH_P
V
117 VTL_P
V
V
V
V
V
V
11F ULVT_P
V
113
P1V
V
V
V
V
V
11P VTC_P2
V
V
V
199 VTC_P
V
197
PP
V
V
198
NP
V
V
111
ESD
124
RPO2
V
155
RPO
V
V
156
CO
V
V
V
V
V
V
V
SRM;2
SRM;21
VTH_N
VTH_P
DPSRM
PRSRM
SRM_HC
SRM_HD SRM_LV SRM_HCDP SRM_8TTP SRM_10TTP DUMMYOD DUMMYOD1 DUMMYOD2 DUMMYOD3 DUMMYOD4 DUMMYOD5
CAD
Mask
50;2
50;21
67;0
68;0
80;0
80;11
80;13
80;14
80;15
80;16
80;17
80;18
82
82;1
82;2
82;3
82;4
82;5
120
OD
V
V
V
V
V
V
V
V
V
V
V
V
V
119
DNW
191
PW1V
193
PW2V
192
NW1V
152
OD2
153 DCO_LPP
196
NPO
V
130
PO
V
V
116
N2V
115
P2V
11H VTH_N
V
118 VTL_N
V
V
V
V
V
11E ULVT_N
114
N1V
V
V
V
V
V
11N VTC_N2
V
V
V
112 VTC_N
V
11G VTH_P
V
117 VTL_P
V
V
11F ULVT_P
113
P1V
V
V
11P VTC_P2
V
V
199 VTC_P
V
V
197
PP
198
NP
111
ESD
124
RPO2
155
RPO
156
CO
V
V
V
V
V
V
V
V
V
V
RH
VAR
ULVT_N
ULVT_P
POFUSE SRAMDMY;1 SRAMDMY;4 ESDIMP
CAD DUMMYOD6 DUMMYOD7 DUMMYOD8 DUMMYOD11 DUMMYOD12 DUMMYOD16 DUMMYPO1 DUMMYPO5 DCO_LPP BJTDMY
Mask
82;6
82;7
82;8
82;11
82;12
82;16
83;1
83;5
90;1
110;0
117;0
143;0
151;1
152;1
156;0
186;1
186;4
189;0
120
OD
V
V
V
V
119
DNW
191
PW1V
193
PW2V
192
NW1V
152
OD2
V
153 DCO_LPP
V
196
NPO
V
130
PO
V
V
V
116
N2V
V
V
V
V
115
P2V
V
V
V
V
11H VTH_N
118 VTL_N
V
V
V
V
V
V
11E ULVT_N
V
114
N1V
V
V
V
V
V
11N VTC_N2
V
112 VTC_N
V
11G VTH_P
117 VTL_P
V
V
V
V
V
11F ULVT_P
V
V
113
P1V
V
V
V
V
V
11P VTC_P2
V
199 VTC_P
V
197
PP
198
NP
V
111
ESD
V
124
RPO2
V
V
V
155
RPO
156
CO
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
46 of 600
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Document No.
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: T-N45-CL-DR-001
: 2.6
Table 3.1.14 N45LPG 1.8V Mask to CAD layer mapping table
CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11C VTL_P2
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
156
CO
DNW
1;0
CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11C VTL_P2
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
156
CO
CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11C VTL_P2
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
156
CO
NW
3;0
V
OD
6;0
V
DOD
6;1
V
NT_N
11;0
VTL_N
12;0
VTL_P
13;0
OD_12
14;1
OD_18
16;0
PO
17;0
DPO
17;1
SR_DPO
17;7
PP
25;0
NP
26;0
V
V
V
V
V
V
V
V
V
RPO
29;0
CO
30;0
CO;11
30;11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SRM;0
SRM;1
SRM;2
SRM_RP
SRM;21
VTH_N
VTH_P
DPSRM
PRSRM
SRM_UHD
SRM_HC
SRM_HD
SRM_LV
50;0
V
50;1
50;2
50;5
50;21
67;0
68;0
80;0
V
80;11
V
80;12
80;13
V
80;14
V
80;15
V
V
V
V
V
V
V
V
V
V
V
V
SRM_HCD
SRM_10TT
SRM_8TTP
DUMMYOD
P
P
80;16
80;17
80;18
82
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD
DUMMYPO DUMMYPO
DUMMYPO
1
2
3
4
5
6
7
8
11
12
16
1
5
82;1
82;2
82;3
82;4
82;5
82;6
82;7
82;8
82;11
82;12
82;16
83
83;1
83;5
V
V
V
V
V
V
V
V
V
DCO
BJTDMY
RH
90;0
110;0
117;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11C VTL_P2
199 VTC_P
197
PP
198
NP
111
ESD
155
RPO
156
CO
Confidential – Do Not Copy
SR_ESD
VAR
POFUSE
SRAMDMY
121;0
143;0
156;0
186
SRAMDMY SRAMDMY
;1
;4
186;1
186;4
Document No.
Version
: T-N45-CL-DR-001
: 2.6
ESDIMP
189;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: T-N45-CL-DR-001
: 2.6
Table 3.1.15 N40LPG 3.3V Mask to CAD layer mapping table
CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
11N VTC_N2
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
DNW
1;0
CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
11N VTC_N2
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
11N VTC_N2
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
NW
3;0
V
OD
6;0
V
DOD
6;1
V
NT_N
11;0
VTL_N
12;0
VTL_P
13;0
OD_12
14;1
OD_33
15;0
PO
17;0
DPO
17;1
SR_DPO
17;7
PP
25;0
V
V
V
V
V
V
V
V
NP
26;0
RPO
29;0
CO
30;0
CO;11
30;11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SRM;0
SRM;1
SRM;2
SRM_RP
SRM;21
VTH_N
VTH_P
DPSRM
PRSRM
SRM_UHD
SRM_HC
SRM_HD
SRM_LV
50;0
V
50;1
50;2
50;5
50;21
67;0
68;0
80;0
V
80;11
V
80;12
80;13
V
80;14
V
80;15
V
V
V
V
V
V
V
V
V
V
V
SRM_HCD
SRM_10TT
SRM_8TTP
DUMMYOD
P
P
80;16
80;17
80;18
82
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD
DUMMYPO DUMMYPO
DUMMYPO
1
2
3
4
5
6
7
8
11
12
16
1
5
82;1
82;2
82;3
82;4
82;5
82;6
82;7
82;8
82;11
82;12
82;16
83
83;1
83;5
V
V
V
V
V
V
V
V
V
V
V
DCO
BJTDMY
RH
90;0
110;0
117;0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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CAD
Mask
120
OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152
OD2
153 DCO
196
NPO
130
PO
116
N2V
115
P2V
118 VTL_N
106 N1V_G
VTC_N_
104
GP
114
N1V
11N VTC_N2
112 VTC_N
117 VTL_P
105 P1V_G
VTC_P_
103
GP
113
P1V
11P VTC_P2
199 VTC_P
197
PP
198
NP
111
ESD
124 RPO2
155
RPO
156
CO
Confidential – Do Not Copy
SR_ESD
VAR
POFUSE
SRAMDMY
121;0
143;0
156;0
186
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SRAMDMY SRAMDMY
;1
;4
186;1
186;4
Document No.
Version
: T-N45-CL-DR-001
: 2.6
ESDIMP
189;0
V
V
V
V
V
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
Metal/Via CAD Layer Information for
Metallization Options
Due to the complexity of metallization schemes, Table 3.2.1 is the summary of TSMC metal/via CAD
layer number, name, and datatype.
The labels “x”, “y’, “z”, “r”, “u” denote different metal schemes and minimum pitches. “x” using datatype “0”
is first inter-layer metal (Mx) with minimum pitch 0.14μm. “y” using datatype “20” is second inter-layer
metal (My) or 2x top layer metal (My) with minimum pitch 0.28μm. “z” using datatype “40” is top layer metal
(Mz) with minimum pitch 0.8μm. “r” using datatype “80” is top layer metal (Mr) with minimum pitch 1.0 m.
The via datatype is the same as the metal right upon the via.

For any metal combination, a marker (1+A+B+C) M_AxByCz or (1+A+D)M_AxDr can be used to
represent the metal combination of Mx, My, Mz and Mr.
The marker is interpreted as one layer of M1, A layers of Mx, B layers of My, C layers of Mz and D layers
of Mr. The total metal layer number is 1+A+B+C or 1+A+D. For example, a 7 metal layer process with one
M1 layer, three Mx layers, one My layer and two Mz layers, can be denoted as 7M_3x1y2z.
Table 3.2.1
Metal/Via CAD Layer Number, Name, and Datatype
Layer Name
CAD
Layer #
x
y
Datatype
z
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
31
51
32
52
33
53
34
54
35
55
36
56
37
57
38
58
39
59
40
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
r
u
-
-
80
80
80
80
80
80
80
80
40
60
40
60
40
60
40
60
40
60
40
60
40
60
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
The following is the CAD layer/datatype example of a 7 metal layer process with one M1 layer, three Mx layers,
one My layers and two Mz layers, which can be denoted as 7M_3x1y2z. The CAD layer designators are
specified according to the format of GDS layer #; datatype.
CAD layer datatype of Mu metal is “60” (that of dummy Mu layer is “61”), and CAD layer datatype of its
associated VIA (VIAu, the VIA under Mu) is “40” (the same as that of VIAz due to the same via size).
Follow VIAz rule for VIAu design.
Table 3.2.2
CAD Layer/Datatype Example for 7M_3x1y2z
Process
Sequence
CAD
Layer #/Datatype
Metal-1
Via-1
Metal-2
Via-2
Metal-3
Via-3
Metal-4
Via-4
Metal-5
Via-5
Metal-6
Via-6
Metal-7
31; 0
51; 0
32; 0
52; 0
33; 0
53; 0
34; 0
54; 20
35; 20
55; 40
36; 40
56; 40
37; 40
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: 2.6
Dummy Pattern Fill CAD Layers
The layers in Table 3.3.1 are for planarization (dummy fill) geometry, referring to Table 3.2.1.
Table 3.3.1
Dummy Pattern CAD Layer Number, Name, and Datatype
Layer Name
CAD
Layer #
X
DOD
DPO
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DM9
DM10
DVIA1
DVIA2
DVIA3
DVIA4
DVIA5
DVIA6
DVIA7
6
17
31
32
33
34
35
36
37
38
39
40
51
52
53
54
55
56
57
1
1,7
1,7
1,7
1,7
1,7
1,7
1,7
1,7
1,7
1
1
1
1
1
1
1
y
Dummy Datatype
z
r
u
21
21
21
21
21
21
21
21
-
41
41
41
41
41
41
41
41
-
81
81
81
81
-
61
61
61
61
61
61
61
-
Table notes:
Metal datatypes 1 (DMx) and 41 (DMz) are the dummy metals without receiving OPC. Datatypes 7 (DMx_O), which will
be generated from TSMC metal dummy utility, will receive OPC same as main metal pattern. Please refer to the
Dummy Metal Rules chapter.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Version
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: 2.6
Special Recognition CAD Layer Summary
Table 3.4.1 lists special layers used in CLN45 design rules and in DRC/LVS command files. These layers are
used for CAD device recognition, and DRC waivers. Some CAD layer designators include a GDS datatype
according to the GDS layer;datatype format.
The column "Tape out required layer" indicates that this layer must be noted on the mask tapeout form to
provide information for mask making.
Table 3.4.1
Special Layer Summary
Special Layer Name
TSMC Default
CAD Layer
Description
Tape out
required
layer
Associated With
DRC
NWROD and NWRSTI
rules

NT_N rules

OD25_33 rules

OD25_18 rules

OD18_15 rules
OD and PO resistor
rules

RES.R.1

MOS/Junc. Varactor
rules
Analog layout rule
VAR rules





Poly layout rule

OD and Poly Resistor
Layout Rules
SR_DOD layout rule
Poly layout rule
HVNMOS rules
HVPMOS rules
Logo rules
Metal1 rules
Metal1 rules
Metal1 rules
Metal1 rules
Metal1 rules
Metal1 rules
Metalx rules
Metalx rules
Metalx rules
Metalx rules
Metalx rules
Metalx rules

LOWMEDN rules

General
NW resistor dummy layer for DRC and LVS.
NWDMY
114
Ncap_NTN
11;20
OD25_33
18;3
OD25_18
18;4
OD18_15
16;4
The NW region covered by both NWDMY and RPO layers is
the "NW within OD resistor.” The NW region covered by only
NWDMY is the "NW under STI resistor."
DRC needs NCap_NTN to waive the NMOS capacitors with
same potential.
DRC also flags NCap_NTN and OD outside of the NCap_NTN
in the same NT_N.
DRC dummy layer for 2.5V thick oxide (second gate oxide)
overdrive to 3.3V
DRC dummy layer for 2.5V thick oxide (second gate oxide)
underdrive to 1.8V
DRC dummy layer for 1.8V thick oxide underdrive to 1.5V
RH
117;0
For OD, PO resistors
RHDMY1
117;4
Dummy layer to exclude unsilicided OD/PO resistor with square
number (length/width) less than one for non-precision usage
VAR
143
This layer is for MOS and Junc. type varactors.
BJTDMY
RFDMY
110;0
161;0
RODMY
49;0
Cover BJT device
For RF device DRC/LVS.
LVS dummy layer for SRAM process to exclude OD area and
DRC dummy layer for PO.R.7 exclusion, TSMC internally used
layer. Please review with TSMC whenever used.
RPDMY
115
SR_DOD
SR_DPO
HVD_N
HVD_P
LOGO
M1_LV
M1_MV
M1_HV
M1_HV
M1_HV
M1_5V
Mn_LV
Mn_MV
Mn_HV
Mn_HV
Mn_HV
Mn_5V
IP
LOWMEDN
6;7
17;7
91;1
91;2
158
31;200~31;214
31;215~31;217
31;218
31;219
31;220
31;221
3n;200~3n;214
3n;215~3n;217
3n;218
3n;219
3n;220
3n;221
63;63
255;15
Poly/OD resistors dummy layer for LVS and DRC
SR_DOD (6;7) only can be used for dummy patterns.
SR_DPO (17;7) only can be used for dummy patterns.
Define N-HVMOS drain side where sustains high voltage
Define P-HVMOS drain side where sustains high voltage
LOGO and product labels layer for DRC
For the nets of voltage 0~1.4V
For the nets of voltage 1.5~1.7V
For the nets of voltage 1.8V
For the nets of voltage 2.5V
For the nets of voltage 3.3V
For the nets of voltage 5V
For the nets of voltage 0~1.4V
For the nets of voltage 1.5~1.7V
For the nets of voltage 1.8V
For the nets of voltage 2.5V
For the nets of voltage 3.3V
For the nets of voltage 5V
IP tagging layer
For low metal density region
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.


















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Special Layer Name
Confidential – Do Not Copy
TSMC Default
CAD Layer
Document No.
Version
Description
: T-N45-CL-DR-001
: 2.6
Associated With
DRC
Tape out
required
layer
DCO_LPP, ULVT_N,
and ULVT_P rules
DCO_LPP rules
DCO_LPP and
ULVT_N rules
DCO_LPP and
ULVT_P rules


Inductor rules
INDDMY_MD rules
INDDMY_HD rules
Inductor rules




MOM rules
MOM rules
MOM rules
MOM rules
MOM rules
MOM rules
MOM rules
MOM rules
MOM rules
MOM rules
MOM rules
OD.W.1® , OD.L.2,
NT_N.R.3,
SR_DPO.R.4,
SR_DPO.R.6,
RES.W.1, RES.R.5,











DOD rules
DPO rules
DMx rules
DVIAx rules
DTCD Rules
DTCD Rules
DTCD Rules
ICOVL rules
OD.L.2, PO.DN.3,
RES.R.4, RES.R.5








SRAM rules


SRAM rules
SRAM rules
SRAM rules






SRAM rules


SRAM rules


SRAM rules


SRAM rules


N40LP+
90;1
Dual core OX for ultra low Vt plus devices’ speed boost.
DCODMY_SC
90;2
DRC dummy layer for TSMC N40LP+ standard cell recognition
ULVT_N
151;1
Ultra low Vt N+ implant for N40LP+ Logic
ULVT_P
152;1
Ultra low Vt P+ implant for N40LP+ Logic
DCO_LPP





RF
INDDMY
INDDMY_MD
INDDMY_HD
TLDMY
144;0
144;42
144;43
116;30
MOMDMY_1
MOMDMY_2
MOMDMY_3
MOMDMY_4
MOMDMY_5
MOMDMY_6
MOMDMY_7
MOMDMY_8
MOMDMY_9
MOMDMY_10
MOMDMY_AP
155;1
155;2
155;3
155;4
155;5
155;6
155;7
155;8
155;9
155;10
155;20
Dummy layer for inductor.
Dummy layer for medium metal density inductor
Dummy layer for high metal density (logic) inductor
Dummy layer for transmission line
MOM
Dummy layer for M1 MOM region
Dummy layer for M2 MOM region
Dummy layer for M3 MOM region
Dummy layer for M4 MOM region
Dummy layer for M5 MOM region
Dummy layer for M6 MOM region
Dummy layer for M7 MOM region
Dummy layer for M8 MOM region
Dummy layer for M9 MOM region
Dummy layer for M10 MOM region
Dummy layer for AP MOM region
MOMDMY
155;21
Dummy layer for RTMOM
ODBLK
POBLK
DMxEXCL
DVIAxEXCL
TCDDMY
TCDDMY_H
TCDDMY_V
ICOVL
150;20
150;21
150;x
150;5x
165;1
165;4
165;5
165;3
Dummy
Dummy OD exclusion marker layer
Dummy PO exclusion marker layer
Dummy Mx exclusion marker layer and redundant VIA
Dummy VIAx exclusion marker layer
Dummy TCD layer
Dummy layer for Horizonal dummy TCD pattern
Dummy layer for Vertical dummy TCD pattern
Dummy layer for ICOVL monitor pattern
RFIP_DMY
161;1
RFIP Dummy layer for tsmc PDK cell
SRM;0
50;0
SRM;1
SRM;2
NPreDOSRM
50;1
50;2
50;21
SRAMDMY;0
186;0
SRAMDMY;1
186;1
SRAMDMY;4
186;4
SRAMDMY;5
186;5
SRAM
Covers the SRAM cell array. The edge of the SRM layer should
be aligned to the boundary of the SRAM cell array, which may
include storage, strapping, and dummy edge cells.
Define SRAM NMOS cell imp
Define SRAM PMOS cell imp
SRAM drawing layer for N+ Predoping area
SRAM DRC Violation waiver layer and OPC. Detail waived rule
list, please refer to the section of SRAM Rules. Before using
SRAMDMY, please make sure that TSMC has revised the
SRAM library to avoid real violations that are automatically
waived by the SRAMDMY marker layer.
To identify PG transistor for LVS and PG transistor sizing
SRAM periphery DRC layer can only be used in the word-line
driver of TSMC SRAM for LP process. This layer is only to
waive CO.S.3 and G.1. And the SRAM and word-line driver
must be reviewed by TSMC’s R&D and PE even if customer
uses TSMC cell.
SRAMDMY;4 (186;4) overlap of SRAMDMY;0 (186;0) is not
allowed.
SRAM periphery DRC layer can only be used in the word-line
driver of TSMC SRAM for N40G process. This layer is only to
waive CO.S.3 and G.1. And the SRAM and word-line driver
must be reviewed by TSMC’s R&D and PE even if customer
uses TSMC cell.
SRAMDMY;5 (186;5) overlap of SRAMDMY;0 (186;0) is not
allowed.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.






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Special Layer Name
TSMC Default
CAD Layer
DPSRM
SRAM_HS
80;0
50;7
PRSRM
80;11
SRM_UHD
SRM_HC
SRM_HD
SRM_LV
80;12
80;13
80;14
80;15
SRM_HCDP
80;16
SRM_8TTP
80;17
SRM_10TTP
80;18
DUMMYOD1
~
DUMMYOD16
DUMMYPO1
~
DUMMYPO7
82;1
~
82;16
83;1
~
83;7
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Associated With
DRC
To identify TSMC standard offer DP SRAM for transistor sizing
Identify HS cell
SRAM bit-cell process logic operation; only in bit-cell not
including strap and edge and dummy cell
To identify UHD SRAM (cover bit-cell, strapping and edge cell)
To identify HC SRAM (cover bit-cell, strapping and edge cell)
To identify HD SRAM (cover bit-cell, strapping and edge cell)
To identify LV SRAM (cover bit-cell, strapping and edge cell)
To identify HCDP SRAM (cover bit-cell, strapping and edge
cell)
To identify 8T TP SRAM (cover bit-cell, strapping and edge
cell)
To identify 10T TP SRAM (cover bit-cell, strapping and edge
cell)
SRAM rules
SRAM rules


Tape out
required
layer


SRAM rules


SRAM rules
SRAM rules
SRAM rules
SRAM rules








SRAM rules


SRAM rules


SRAM rules


For SRAM data preparation
SRAM rules


For SRAM data preparation
SRAM rules


SRAM rules


IP tagging layer


CO2 rule
PO.R.7, PO.R.9,
SRAM.R.15,
SRAM.R.21


ROM rule

Latch-Up rule

Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule
Latch-Up rule














ESD guidelines

ESD guidelines
and
ESDIMP rule


SR_ESD rules


HIA_DIO guideline

PO rule

CO;11
30;11
IP
63;63
CO2
100;0
CO;11 (30;11) is a must for CO mask tape-out in SRAM.
The CO_11 is square CO in bit cell except butted CO.
1. If CO;11 exists, it must cover CO;0
2. CO;11 must be 0.06μm x 0.06μm
3. CO;11 must be exactly the same as CO;0.
4. CO;11 must be fully covered by SRM (50;0) and
SRAMDMY;0 (186;0)
IP tagging layer
eDRAM
Stacked contact for eDRAM process
RAM1TDMY
160;0
Recognize 1TRAM region

ROM
ROM
50;6
LUPWDMY
255;1
VDDDMY
VSSDMY
RES200
LUPWDMY_2
M1(pin)
M2(pin)
M3(pin)
M4(pin)
M5(pin)
M6(pin)
M7(pin)
M8(pin)
M9(pin)
M10(pin)
255;4
255;5
255;9
255;18
131;0
132;0
133;0
134;0
135;0
136;0
137;0
138;0
139;0
140;0
SDI
122
ESDIMP
189;0
SR_ESD
121;0
HIA_DUMMY
168;0
POFUSE
156;0
This layer is required for ROM rule checks in ROM devices.
Latch-Up
LUPWDMY is a drawn layer to waive latch up rules for verified
circuit.
Dummy Layer for Power(Vdd) PAD
Dummy Layer for Power(Vss) PAD
Recognize resistor over 200ohm
Area Array IO LUP rules check
Metal1 pin for text layer
Metal2 pin for text layer
Metal3 pin for text layer
Metal4 pin for text layer
Metal5 pin for text layer
Metal6 pin for text layer
Metal7 pin for text layer
Metal8 pin for text layer
Metal9 pin for text layer
Metal10 pin for text layer
ESD
It is required to cover all ESD MOS OD regions that are
connected to the pads.
This drawn layer is required for ESD implant.
SR (special rule) exclusion marker layer for N40G ESD device
only
Dummy layer for high current diode
Fuse
Poly fuse implant layer, cover all poly fuse regions.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

(for N40G )
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Special Layer Name
Confidential – Do Not Copy
TSMC Default
CAD Layer
Document No.
Version
Description
: T-N45-CL-DR-001
: 2.6
Associated With
DRC
DFM redundant VIA
utility
DFM redundant VIA
utility
DFM redundant VIA
utility
DFM Action-Required
DFM Recommended
Rules and
Recommendations for
Analog Designs

DFM Action-Required

DFM Recommended

Tape out
required
layer
DFM
DFMEXCL
153;20
Blockage layer for all DFM redundant VIA utility
COEXCL
153;0
Blockage layer for CO redundant VIA utility
RRuleRequire
RRuleRecommend
153;x,
x=1-9,
182;1
182;2
RRuleAnalog
182;3
excludeRRuleRequire
182;11
excludeRRuleRecom
mended
182;12
excludeRRuleAnalog
182;13
SENDMY
255;8
DMxEXCL
WBDMY
SEALRING
SEALRING_DB
SEALRING_ALL
150;x
157;0
162;0
162;1
162;2
LMARK
109;0
CSRDMY
CSRBIB1DMY
CSRBIB2DMY
CDUDMY
166;0
166;1
166;2
165;0
VIAxEXCL
Blockage layer for redundant VIA utility
DRC dummy layer for DFM Action-Required recommendation
DRC dummy layer for DFM Recommended recommendation
DRC dummy layer for DFM Recommended Dimension for
Analog Designs
dummy layer for excluding DFM action-required
recommnedation check
dummy layer for excluding DFM recommendaed
recommendation check
Rules and
dummy layer for excluding Rules and Recommendations check
Recommendations for
for Analog Designs
Analog Designs
DRC recognition layer for sensitive circuit
DFM Recommended
Package and interconnect
Dummy Mx exclusion within oxide slot of MT region
DMx rules
Design rule waiver within CUP pad region
CUP rules
Sealring region
Sealring rules
Scribe line dummy bar region
Sealring rules
Sealring region, SLDB, CSR, and assembly isolation
Sealring rules
It is required for sealring structure and DFM VIA enhancer. It’s
Metal rules
also a DRC recognition layer of L-mark for DRC purpose.
Chip corner stress relief pattern dummy layer
Sealring rules
Sealring region
Sealring rules
Sealring region
Sealring rules
DRC dummy layer to recognize CDU pattern
Sealring rules
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

















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Device Truth Tables
This section contains the device truth tables for:



CLN45/CLN40 CMOS Logic Low Power (LP) technology
CLN40 CMOS Logic Low Power Plus (LP+) technology
CLN45/CLN40 CMOS Logic LP-based Triple Gate Oxide (LPG) technology

CLN45 CMOS Logic General Purpose Superb (N40G) technology

CLN45/CLN40 MOM

CMN45/CMN40 Inductor
The following provides a legend for the following device truth table.
Table 3.5.1.1 Device Truth Table for N45LP/N40LP
Table 3.5.1.2 Device Truth Table for N40LP 5V HVMOS_18
Table 3.5.2 Device Truth Table for N40LP Plus (N40LP+): 1.1V Core and 2.5V I/O DesignTable 3.5.3 Device
Truth Table for N45LPG
Table 3.5.4 Device Truth Table for N40LPG
Table 3.5.5 Device Truth Table for N40G (=N45GS)
Table 3.5.6 Device Truth Table for MOM
Table 3.5.7 Device Truth Table for Inductor
0 Does not cover the structures
1 Covers or matches the structures
* Don’t care
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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N45/N40 Low Power (LP): 1.1V Core Design
Table 3.5.1.1 Device Truth Table for N45LP/N40LP
OD
NW
NT_N
OD_25
OD_18
POLY
VTH_N
VTH_P
VTL_N
VTL_P
N+
P+
RPO
RH
RHDMY1
NWDMY
VAR
BJTDMY
DIODMY
RPDMY
HVD_N
HVD_P
Device
*
*
*
*
*
*
*
*
*
*
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
*
*
1
1
1
1
0
1
0
1
0
0
0
0
1
1
*
*
0
0
*
*
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0#a
0#a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
SPICE Name
NMOS (1.1V)
nch
PMOS (1.1V)
pch
High Vt NMOS (1.1V)
nch_hvt
High Vt PMOS (1.1V)
pch_hvt
Low Vt NMOS (1.1V)
nch_lvt
Low Vt PMOS (1.1V)
pch_lvt
I/O NMOS (1.8V)
nch_18
I/O PMOS (1.8V)
pch_18
I/O NMOS (2.5V)
nch_25
I/O PMOS (2.5V)
pch_25
Native NMOS (1.1V)
nch_na
Native I/O NMOS
nch_na18
(1.8V)
Native I/O NMOS
nch_na25
(2.5V)
HV NMOS (5V)
nch_hv25_snw
HV PMOS (5V)
pch_hv25_spw
N+/PW Junction Diode
ndio
P+/NW Junction Diode
pdio
N+/PW Junction Diode
ndio_hvt
w/ High Vt
N-Well Psub Diode
nwdio
P-Well Contact
N-Well Contact
Silicided N+ PO
rnpoly
Resistor
Silicided P+ PO
rppoly
Resistor
Silicided N+ OD
rnod
Resistor
Silicided P+ OD
rpod
Resistor
Unsilicided N+ PO
rnpolywo
Resistor
Unsilicided P+ PO
rppolywo
Resistor
Unsilicided N+ OD
rnodwo
Resistor
Unsilicided P+ OD
rpodwo
Resistor
NW Resistor (under
rnwsti
STI)
NW Resistor (under
rnwod
OD)
Vertical PNP
pnp2 (2x2μm 2)
(P+/NW/Psub)
pnp5 (5x5μm 2)
(constant emitter size) pnp10 (10x10μm 2)
Vertical NPN
npn2 (2x2μm 2)
(N+/PW/DNW)
npn5 (5x5μm 2)
(constant emitter size) npn10 (10x10μm 2)
1.1V Varactor
nmoscap
1.8V Varactor
nmoscap_18
2.5V Varactor
nmoscap_25
Special Layer
DNW
Design Levels
*
1
0
0
*
*
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
*
*
1
1
1
1
0
1
0
0
0
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
*
0
*
0
*
*
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
*
0
*
0
*
*
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
*
1
0
0
*
*
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
*
1
1
0
*
*
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
*
0
*
0
*
*
1
0
0
0
0
1
0
1
1
*
0
0
0
0
1
0
0
*
0
*
0
*
*
1
0
0
0
0
0
1
1
1
*
0
0
0
0
1
0
0
*
1
0
0
*
*
0
0
0
0
0
1
0
1
1
*
0
0
0
0
1
0
0
*
1
1
0
*
*
0
0
0
0
0
0
1
1
1
*
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
*
*
*
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
#a: Both HVNMOS_25 and HVPMOS_25 require RPO layer, but customers don't have to draw RPO (29;0) CAD layer for HVNMOS_25
or HVPMOS_25. TSMC will use logic operation to generate the RPO pattern for HVNMOS_25 and HVPMOS_25 during mask
masking, so customers must tape out RPO (155) mask when using HVNMOS_25 or HVPMOS_25.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Table 3.5.1.2 Device Truth Table for N40LP 5V HVMOS_18
OD_25
OD_18
POLY
VTH_N
VTH_P
VTL_N
VTL_P
N+
P+
RPO
RH
NWDMY
VAR
BJTDMY
DIODMY
RPDMY
HVD_N
HVD_P
nch_hv18_snw
pch_hv18_spw
NT_N
HV NMOS (5V)
HV PMOS (5V)
NW
SPICE Name
OD
Device
Special Layer
DNW
Design Levels
0
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0#b
1
0
0
1
0#a
0#a
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
#a: Both HVNMOS_18 and HVPMOS_18 require RPO layer, but customers don't have to draw RPO (29;0) CAD layer for HVNMOS_18
or HVPMOS_18. TSMC will use logic operation to generate the RPO pattern for HVNMOS_18 and HVPMOS_18 during mask
masking, so customers must tape out RPO (155) mask when using HVNMOS_18 or HVPMOS_18.
#b: HVPMOS_18 requires VTL_P layer, but customers don't have to draw VTL_P (13;0) CAD layer for HVPMOS_18. TSMC will use
logic operation to generate the VTL_P pattern for HVPMOS_18 during mask masking, so customers must tape out VTL_P (117)
mask when using HVPMOS_18.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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N40 Low Power Plus (N40LP+): 1.1V Core and
2.5V I/O Design
Table 3.5.2 Device Truth Table for N40LP Plus (N40LP+): 1.1V Core and 2.5V I/O Design
Device
SPICE Name
OD
DCO_LPP
NW
NT_N
OD_25
POLY
VTH_N
VTH_P
VTL_N
VTL_P
ULVT_N
ULVT_P
N+
P+
RPO
RH
NWDMY
VAR
BJTDMY
DIODMY
RPDMY
HVD_N
HVD_P
Special Layer
DNW
Design Levels
NMOS (1.1V)
PMOS (1.1V)
High Vt NMOS (1.1V)
High Vt PMOS (1.1V)
Low Vt NMOS (1.1V)
Low Vt PMOS (1.1V)
Ultra Low Vt Plus
NMOS (1.1V)
Ultra Low Vt Plus
PMOS (1.1V)
I/O NMOS (2.5V)
I/O PMOS (2.5V)
Native NMOS (1.1V)
Native I/O NMOS
(2.5V)
HV NMOS (5V)
HV PMOS (5V)
N+/PW Junction Diode
P+/NW Junction Diode
Ultra Low Vt Plus
N+/PW Junction Diode
Ultra Low Vt Plus
P+/NW Junction Diode
N-Well Psub Diode
P-Well Contact
N-Well Contact
Silicided N+ PO
Resistor
Silicided P+ PO
Resistor
Silicided N+ OD
Resistor
Silicided P+ OD
Resistor
Unsilicided N+ PO
Resistor
Unsilicided P+ PO
Resistor
Unsilicided N+ OD
Resistor
Unsilicided P+ OD
Resistor
NW Resistor (under
STI)
NW Resistor (under
OD)
nch
pch
nch_hvt
pch_hvt
nch_lvt
pch_lvt
*
*
*
*
*
*
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
nch_lppulvt
*
1
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
pch_lppulvt
*
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
nch_25
pch_25
nch_na
*
*
0
1
1
1
0
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
nch_na25
0
1
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
nch_hv25_snw
pch_hv25_spw
ndio
pdio
0
1
*
*
1
1
1
1
0
0
*
*
0
1
0
1
0
0
0
0
1
1
*
*
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0 0#a 0
1 0#a 0
0 0
0
1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
ndio_lppulvt
*
1
1
0
0
*
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
pdio_lppulvt
*
1
1
1
0
*
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
nwdio
0
*
*
1
1
1
0
0
0
1
0
1
0
0
0
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
rnpoly
*
0
0
*
0
*
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
rppoly
*
0
0
*
0
*
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
rnod
*
1
0
0
0
*
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
rpod
*
1
0
1
0
*
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
rnpolywo
*
0
0
*
0
*
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
rppolywo
*
0
0
*
0
*
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
rnodwo
*
1
0
0
0
*
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
rpodwo
*
1
0
1
0
*
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
rnwsti
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
rnwod
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
*
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
*
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
*
*
1
1
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Vertical PNP
(P+/NW/Psub)
(constant emitter size)
Vertical NPN
(N+/PW/DNW)
(constant emitter size)
1.1V Varactor
2.5V Varactor
pnp2 (2x2μm2)
pnp5 (5x5μm2)
pnp10
(10x10μm2)
npn2 (2x2μm2)
npn5 (5x5μm2)
npn10
(10x10μm2)
nmoscap
nmoscap_25
#a: Both HVNMOS_25 and HVPMOS_25 require RPO layer, but customers don't have to draw RPO (29;0) CAD layer for HVNMOS_25
or HVPMOS_25. TSMC will use logic operation to generate the RPO pattern for HVNMOS_25 and HVPMOS_25 during mask
masking, so customers must tape out RPO (155) mask when using HVNMOS_25 or HVPMOS_25.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
N45LPG/N40LPG: 1.1V/0.9V Core Design
Table 3.5.3.1 Device Truth Table for N45LPG
POLY
VTL_N
VTL_P
N+
P+
RPO
RH
NWDMY
VAR
BJTDMY
DIODMY
RPDMY
0.9V Varactor
1.1V Varactor
1.8V Varactor
DCO
Vertical NPN (N+/PW/DNW)
(constant emitter size)
OD_18
Vertical PNP (P+/NW/Psub)
(constant emitter size)
NT_N
N-Well Contact
Silicided N+ PO Resistor
Silicided P+ PO Resistor
Silicided N+ OD Resistor
Silicided P+ OD Resistor
Unsilicided N+ PO Resistor
Unsilicided P+ PO Resistor
Unsilicided N+ OD Resistor
Unsilicided P+ OD Resistor
NW Resistor (under STI)
NW Resistor (under OD)
NW
NMOS (1.1V)
PMOS (1.1V)
Low Vt NMOS (1.1V)
Low Vt PMOS (1.1V)
NMOS (0.9V)
PMOS (0.9V)
Low Vt NMOS (0.9V)
Low Vt PMOS (0.9V)
I/O NMOS (1.8V)
I/O PMOS (1.8V)
N+/PW Junction Diode (1.1V)
P+/NW Junction Diode (1.1V)
N+/PW Junction Diode (0.9V)
P+/NW Junction Diode (0.9V)
N-Well Psub Diode
P-Well Contact
OD
Device
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
*
*
*
*
*
*
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
0
0
1
0
0
1
1
0
0
1
1
1
1
1
*
*
0
1
*
*
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
*
0
0
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
*
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
SPICE Name
nch
pch
nch_lvt
pch_lvt
nch_lpg
pch_lpg
nch_lpglvt
pch_lpglvt
nch_18
pch_18
ndio
pdio
ndio_lpg
pdio_lpg
nwdio
rnpoly
rppoly
rnod
rpod
rnpolywo
rppolywo
rnodwo
rpodwo
rnwsti
rnwod
pnp2 (2x2μm2)
pnp5 (5x5μm2)
pnp10 (10x10μm2)
npn2 (2x2μm2)
npn5 (5x5μm2)
npn10 (10x10μm2)
nmoscap_lpg
nmoscap
nmoscap_18
Special Layer
DNW
Design Levels
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
Table 3.5.3.2 Device Truth Table for N40LPG
Special Layer
VTH_N
VTH_P
N+
P+
RPO
RH
NWDMY
VAR
BJTDMY
DIODMY
RPDMY
0.9V Varactor
1.1V Varactor
3.3V Varactor
VTL_P
Vertical NPN (N+/PW/DNW)
(constant emitter size)
VTL_N
Vertical PNP (P+/NW/Psub)
(constant emitter size)
rnpoly
rppoly
rnod
rpod
rnpolywo
rppolywo
rnodwo
rpodwo
rnwsti
rnwod
pnp2 (2x2μm2)
pnp5 (5x5μm2)
pnp10 (10x10μm2)
npn2 (2x2μm2)
npn5 (5x5μm2)
npn10 (10x10μm2)
nmoscap
nmoscap
nmoscap_33
POLY
N-Well Contact
Silicided N+ PO Resistor
Silicided P+ PO Resistor
Silicided N+ OD Resistor
Silicided P+ OD Resistor
Unsilicided N+ PO Resistor
Unsilicided P+ PO Resistor
Unsilicided N+ OD Resistor
Unsilicided P+ OD Resistor
NW Resistor (under STI)
NW Resistor (under OD)
DCO
P-Well Contact
OD_33
nch
pch
nch_hvt
pch_hvt
nch_lpg
pch_lpg
nch_lpglvt
pch_lpglvt
nch_33
pch_33
nch_na
nch_na33
ndio
pdio
ndio_lpg
pdio_lpg
nwdio
NT_N
NMOS (1.1V)
PMOS (1.1V)
High Vt NMOS (1.1V)
High Vt PMOS (1.1V)
NMOS (0.9V)
PMOS (0.9V)
Low Vt NMOS (0.9V)
Low Vt PMOS (0.9V)
I/O NMOS (3.3V)
I/O PMOS (3.3V)
Native NMOS (1.1V)
Native I/O NMOS (3.3V)
N+/PW Junction Diode (1.1V)
P+/NW Junction Diode (1.1V)
N+/PW Junction Diode (0.9V)
P+/NW Junction Diode (0.9V)
N-Well Psub Diode
NW
SPICE Name
OD
Device
DNW
Design Levels
*
*
*
*
*
*
*
*
*
*
0
0
*
*
*
*
0
*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
*
*
*
*
*
*
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
0
0
1
0
0
1
1
0
0
1
1
1
1
1
*
*
0
1
*
*
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
*
0
0
0
0
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
*
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
63 of 600
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3.5.4
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
N40G (N45GS) General Purpose Superb: 0.9V
Core Design
Table 3.5.4 Device Truth Table for N40G (N45GS)
OD
NW
NT_N
OD_25
OD_18
OD_12
POLY
VTH_N
VTH_P
VTL_N
VTL_P
N+
P+
RPO
RH
NWDMY
VAR
BJTDMY
DIODMY
RPDMY
SR_ESD
SDI
Special Layer
DNW
Design Levels
rnpoly
rppoly
rnod
rpod
*
*
*
*
*
*
*
*
0
*
*
*
*
0
0
0
0
*
*
0
*
*
*
*
*
*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
0
0
0
0
1
1
0
1
*
*
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
*
*
*
*
*
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
*
*
*
*
*
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rnpolywo
*
0
*
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
rppolywo
*
0
*
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
rnodwo
*
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
rpodwo
*
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
rnwsti
rnwod
pnp2 (2x2 μm2)
pnp5 (5x5 μm2)
pnp10 (10x10 μm2)
npn2 (2x2 μm2)
npn5 (5x5 μm2)
npn10 (10x10 μm2)
nmoscap
pmoscap
nmoscap_12
nmoscap_18
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
*
*
*
*
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
pmoscap_18
*
1
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
nmoscap_25
*
1
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
pmoscap_25
*
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
Device
SPICE Name
NMOS (0.9V)
NMOS (1.2V)
PMOS (0.9V)
PMOS (1.2V)
High Vt NMOS (0.9V)
High Vt PMOS (0.9V)
Low Vt NMOS (0.9V)
Low Vt PMOS (0.9V)
ESD NMOS (0.9V)
I/O NMOS (1.8V)
I/O PMOS (1.8V)
I/O NMOS (2.5V)
I/O PMOS (2.5V)
Native NMOS (0.9V)
Native NMOS (1.2V)
Native I/O NMOS (1.8V)
Native I/O NMOS (2.5V)
N+/PW Junction Diode
P+/NW Junction Diode
N-Well Psub Diode
P-Well Contact
N-Well Contact
Silicided N+ PO Resistor
Silicided P+ PO Resistor
Silicided N+ OD Resistor
Silicided P+ OD Resistor
Unsilicided N+ PO
Resistor
Unsilicided P+ PO
Resistor
Unsilicided N+ OD
Resistor
Unsilicided P+ OD
Resistor
NW Resistor (under STI)
NW Resistor (under OD)
Vertical PNP
(P+/NW/Psub)
(constant emitter size)
Vertical NPN
(N+/PW/DNW)
(constant emitter size)
0.9V NMOS Varactor
0.9V PMOS Varactor
1.2V NMOS Varactor
1.8V NMOS Varactor
1.8V PMOS Varactor for
PMOS
2.5V NMOS Varactor
(including 2.5V overdrive
3.3V)
2.5V PMOS Varactor
(including 2.5V overdrive
3.3V)
nch
nch_12
pch
pch_12
nch_hvt
pch_hvt
nch_lvt
pch_lvt
nch_hia
nch_18
pch_18
nch_25
pch_25
nch_na
nch_na12
nch_na18
nch_na25
NDIO
PDIO
nwdio
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
64 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
3.5.5
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
MOM
Table 3.5.5 Device Truth Table for MOM
M5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
RV
AP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VIA5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VIA4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M3
1
1
1
1
1
1
1
1
1
1
1
1
*
1
1
1
1
1
1
1
1
1
1
1
1
*
VIA3
0
1
1
1
0
1
1
1
0
1
1
1
*
0
1
1
1
0
1
1
1
0
1
1
1
*
M2
1
0
1
1
1
0
1
1
1
0
1
1
*
1
0
1
1
1
0
1
1
1
0
1
1
*
VIA2
1
1
0
0
1
1
0
0
1
1
0
0
*
1
1
0
0
1
1
0
0
1
1
0
0
*
M1
1
0
0
0
1
0
0
0
1
0
0
0
*
1
0
0
0
1
0
0
0
1
0
0
0
*
VIA1
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
CO
1
1
1
1
1
1
1
1
1
1
1
1
*
1
1
1
1
1
1
1
1
1
1
1
1
*
P+
1
1
1
1
1
1
1
1
1
1
1
1
*
1
1
1
1
1
1
1
1
1
1
1
1
*
RPO
1
1
1
1
1
1
1
1
1
1
1
1
*
1
1
1
1
1
1
1
1
1
1
1
1
*
N+
1
1
1
1
1
1
1
1
1
1
1
1
*
1
1
1
1
1
1
1
1
1
1
1
1
*
POLY
OD_33
0
1
1
1
0
1
1
1
0
1
1
1
*
0
1
1
1
0
1
1
1
0
1
1
1
*
SR_DPO
OD_25
0
0
0
1
0
0
0
1
0
0
0
1
*
0
0
0
1
0
0
0
1
0
0
0
1
*
OD_18
1
0
1
0
1
0
1
0
1
0
1
0
*
1
0
1
0
1
0
1
0
1
0
1
0
*
OD
1
1
0
0
1
1
0
0
1
1
0
0
*
1
1
0
0
1
1
0
0
1
1
0
0
*
DOD
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
PW
N40
crtmom
crtmom_wo, NW
crtmom_wo, PW
crtmom_wo, NTN
crtmom_rf
crtmom_wo_rf, NW
crtmom_wo_rf, PW
crtmom_wo_rf, NTN
crtmom_mx
crtmom_wo_mx, NW
crtmom_wo_mx, PW
crtmom_wo_mx, NTN
crtmom_2t
cfmom
cfmom_wo, NW
cfmom_wo, PW
cfmom_wo, NTN
cfmom_rf
cfmom_wo_rf, NW
cfmom_wo_rf, PW
cfmom_wo_rf, NTN
cfmom_mx
cfmom_wo_mx, NW
cfmom_wo_mx, PW
cfmom_wo_mx, NTN
cfmom_2t
NT_N
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
Device
NW
Node
DNW
Design Levels
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
*
MOMDMY_1(155;1)
MOMDMY_2(155;2)
MOMDMY_3(155;3)
MOMDMY_4(155;4)
MOMDMY_5(155;5)
MOMDMY_6(155;6)
MOMDMY_7(155;7)
MOMDMY_8(155;8)
MOMDMY(155;21)
MOMDMY(155;22)
MOMDMY(155;23)
MOMDMY(155;24)
MOMDMY(155;25)
MOMDMY(155;27)
MOMDMY(155;31)
MOMDMY(155;32)
MOMDMY(155;33)
ODBLK(150;20)
POBLK(150;21)
DM1EXCL(150;1)
DM2EXCL(150;2)
DM3EXCL(150;3)
DM4EXCL(150;4)
DM5EXCL(150;5)
DM6EXCL(150;6)
DM7EXCL(150;7)
DM8EXCL(150;8)
DM9EXCL(150;9)
DM10EXCL(150;10)
crtmom
crtmom_wo, NW
crtmom_wo, PW
crtmom_wo, NTN
crtmom_rf
crtmom_wo_rf, NW
crtmom_wo_rf, PW
crtmom_wo_rf, NTN
crtmom_mx
crtmom_wo_mx, NW
crtmom_wo_mx, PW
crtmom_wo_mx, NTN
crtmom_2t
cfmom
cfmom_wo, NW
cfmom_wo, PW
cfmom_wo, NTN
cfmom_rf
cfmom_wo_rf, NW
cfmom_wo_rf, PW
cfmom_wo_rf, NTN
cfmom_mx
cfmom_wo_mx, NW
cfmom_wo_mx, PW
cfmom_wo_mx, NTN
cfmom_2t
MOMDMY(155;100)
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N45/N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
N40
Device
MOMDMY(155;0)
Node
RFDMY(161;0)
Special Layers
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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Note:
1. MOMDMY(155;0) dummy layer RTMOM device
2. MOMDMY(155;100) dummy layer FMOM device
3. MOMDMY(155;21) dummy layer to waive violations in MOM region
4. MOMDMY(155;22) denotes MX MOM recogition.
5. MOMDMY(155;23) to recognize pin plus 1, minus 1 for MX MOM.
6. MOMDMY(155;24) to recognize pin plus 2, minus 2 for MX MOM.
7. MOMDMY(155;25) to recognize for cross-coupled mom pin.
8. MOMDMY(155;27) to recognize for 2T BB MOM
9. MOMDMY(155;31) dummy layer for MOM devices wi NW shield
10. MOMDMY(155;32) dummy layer for MOM devices wi PW shield
11. MOMDMY(155;33) dummy layer for MOM devices wi NTN shield
12. RFDMY(161;0) dummy layer for RF devices.
13. DOD is an option pattern layer to meet the requirement of the OD density under MOM.
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Inductor
Table 3.5.6 Device Truth Table for inductor
DNW
NW
NT_N
OD
POLY
N+
P+
RPO
CO
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
RV
AP
Design Levels
N45/N40 spiral_std_mz_a
N45/N40 spiral_sym_mz_a
N45/N40 spiral_sym_ct_mz_a_x
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
*
*
*
*
*
*
1
1
1
1
1
1
N45/N40 spiral_std_mza_a
N45/N40 spiral_sym_mza_a
N45/N40 spiral_sym_ct_mza_a_x
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
*
*
*
*
*
*
1
1
1
1
1
1
N45/N40 spiral_sym_mz_ax
N45/N40 spiral_sym_ct_mz_ax_a
N45/N40 spiral_std_m2za_za
N45/N40 spiral_sym_m2za_z
N45/N40 spiral_sym_ct_m2za_z_a
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
*
*
1
1
1
*
*
1
1
1
1
1
1
1
1
1
1
1
1
1
N45/N40 spiral_std_mu_x
N45/N40 spiral_sym_mu_x
N45/N40 spiral_sym_ct_mu_x_a
N45/N40 spiral_std_mu_z
N45/N40 spiral_sym_mu_z
N45/N40 spiral_sym_ct_mu_z_x
spiral_sym_ct_mu_z_a
N40
spiral_std_mu_a
N40
spiral_sym_mu_a
N40
spiral_sym_ct_mu_a_a
N40
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
*
*
*
1
1
1
1
*
*
*
*
*
*
1
1
1
1
*
*
*
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
1
spiral_sym_ct_mu_a_x
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
*
*
0
0
Node
N40
Device
RFIP_DMY (161;1)
INDDMY(144;0)
INDDMY(144;30)
INDDMY(DMYDIS, 144;31)
INDDMY(144;32)
INDDMY(144;33)
INDDMY(144;34)
INDDMY(144;35)
INDDMY(144;36)
INDDMY(144;37)
INDDMY(144;38)
INDDMY(144;39)
Special Layer
N45/N40 spiral_std_mz_a
N45/N40 spiral_sym_mz_a
N45/N40 spiral_sym_ct_mz_a_x
N45/N40 spiral_std_mza_a
N45/N40 spiral_sym_mza_a
N45/N40 spiral_sym_ct_mza_a_x
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
N45/N40 spiral_sym_mz_ax
N45/N40 spiral_sym_ct_mz_ax_a
N45/N40 spiral_std_m2za_za
N45/N40 spiral_sym_m2za_z
N45/N40 spiral_sym_ct_m2za_z_a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
N45/N40 spiral_std_mu_x
N45/N40 spiral_sym_mu_x
N45/N40 spiral_sym_ct_mu_x_a
N45/N40 spiral_std_mu_z
N45/N40 spiral_sym_mu_z
N45/N40 spiral_sym_ct_mu_z_x
spiral_sym_ct_mu_z_a
N40
spiral_std_mu_a
N40
spiral_sym_mu_a
N40
spiral_sym_ct_mu_a_a
N40
spiral_sym_ct_mu_a_x
N40
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
1
1
1
0
1
1
1
Node
Device
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Note:
1. The inductor with most metal layers scheme (1P10M for two top metal layers scheme and 1P9M for one top metal layer
scheme) is illustrated in the truth table
2. RFIP_DMY (161;1, drawing1) identifies the tsmc msrf specific (tsmc msrf process design kit) device structure.
3. INDDMY(144;0, drawing) identifies the Metal/OD/PO dummy blocked low pattern density inductor.
4. INDDMY(144;30, rad) identifies the inductor inner radius.
5. INDDMY(144;31, dummy1) identifies the distance from spiral outer edge to [guard-ring outer edge + 2.5um]
6. INDDMY(144;32, dummy2) identifies the inductor turn numbers.
7. INDDMY(144;33, dummy3) identifies the inductor coil width at Port2.
8. INDDMY(144;34, dummy4) identifies the inductor center-tap port region.
9. INDDMY(144;35, dummy5) identifies the inductor coil width.
10. INDDMY(144;36, dummy6) identifies the inductor coil spacing.
11. INDDMY(144;37, dummy7) identifies the inductor type by text label.
12. INDDMY(144;38, dummy8) identifies the stacked Mx layer number(s) of inductor center-tap .
13. INDDMY(144;39) identifies the ratio of inductor center-tap width over coil width
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Mask Requirement for Device options
(High/STD/Low VT/Ultra Low VT Plus)
Table 3.6.1 Mask Requirement for N45LP/N40LP
Mask Requirements
Device
STD Vt + I/O (DGO)
STD Vt + Low Vt + I/O
STD Vt + High Vt + I/O
STD Vt + Low Vt + High Vt + I/O
Well
LDD
3 masks
PW1V/2V, NW1V
3 masks
PW1V/2V, NW1V
3 masks
PW1V/2V, NW1V
3 masks
PW1V/2V, NW1V
4 masks
N1V/2V, P1V/2V
6 masks
N1V/2V, P1V/2V, VTL_N/P
6 masks
N1V/2V, P1V/2V, VTH_N/P
8 masks
N1V/2V, P1V/2V, VTL_N/P, VTH_N/P
Table 3.6.2 Mask Requirement for N40LP Plus (N40LP+): 1.1V Core and 2.5V I/O Design
Mask Requirements
Device
Well
LDD
STD Vt + Low Vt + Ultra Low Vt Plus‡
+ I/O
3 masks
PW1V/2V, NW1V
STD Vt + High Vt + Ultra Low Vt Plus‡
+ I/O
3 masks
PW1V/2V, NW1V
STD Vt + Low Vt + High Vt + Ultra
Low Vt Plus‡ + I/O
3 masks
PW1V/2V, NW1V
8 masks
N1V/2V, P1V/2V, VTL_N/P,
ULVT_N/P
8 masks
N1V/2V, P1V/2V, VTH_N/P,
ULVT_N/P
10 masks
N1V/2V, P1V/2V, VTL_N/P,
VTH_N/P, ULVT_N/P
‡: DCO_LPP mask (Mask code: 153) is also required for Ultra Low Vt Plus devices at N40LP+.
Table 3.6.3 Mask Requirement for N45LPG/N40LPG
Mask Requirements
Device
Well
LDD
STD Vt + I/O (DGO)
4 masks
PW1V/2V, NW1V/2V
STD Vt + Low Vt + I/O
4 masks
PW1V/2V, NW1V/2V
6 masks
N1V/N1V_G/N2V, P1V/P1V_G/P2V
8 masks
N1V/N1V_G/N2V, P1V/P1V_G/P2V,
VTL_N/P
Table 3.6.4 Mask Requirement for N40G (N45GS)
Mask Requirements
Device
STD Vt + I/O (DGO)
STD Vt + Low Vt + I/O
STD Vt + High Vt + I/O
STD Vt + Low Vt + High Vt + I/O
Well
LDD
4 masks
PW1V/2V, NW1V/2V
4 masks
PW1V/2V, NW1V/2V
6 masks
PW1V/2V, NW1V/2V,VTH_N/P
6 masks
PW1V/2V, NW1V/2V, VTH_N/P
4 masks
N1V/2V, P1V/2V
6 masks
N1V/2V, P1V/2V, VTL_N/P
4 masks
N1V/2V, P1V/2V
6 masks
N1V/2V, P1V/2V, VTL_N/P
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Design Geometry Restrictions
3.7.1
Design Grid Rules
: T-N45-CL-DR-001
: 2.6
Table 3.7.1
Rule No.
G.1
G.2
G.3
G.4
G.6gU
Description
The design grid must be an integer multiple of 0.005μm except PO and CO layers inside the layer 186;5 for
GS/GL and 186;4 for LP/LPG
0.005μm deviation is allowed for 45-degree polygon dimensions.
For circuits of 110% size-up part (40LP) can allow 1nm design grid. This is uncheckable. Please refer to the
chapter “N40LP Design Information”.
(Except UBM, CBD[in UBM], CB2_FC[in UBM], PM[in UBM], AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of
WLCSP process], PM1/Cu_PPI[in WLCSP process], PM2[in UBM for WLCSP process] region)
Shapes with acute angles between line segments are not allowed. (Except UBM, CBD[in UBM], CB2_FC[in UBM],
PM[in UBM], AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of WLCSP process], PM1/Cu_PPI[in WLCSP process],
PM2[in UBM for WLCSP process] region)
Only shapes that are orthogonal or on a 45-degree angle are allowed.
(Except UBM, CBD[in UBM], CB2_FC[in UBM], PM[in UBM], AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of
WLCSP process], PM1/Cu_PPI[in WLCSP process], PM2[in UBM for WLCSP process] region)
For the OPC layers, any edge of length < 1.0 x minimum width cannot have another adjacent edge of length < 1.0
x minimum width. (Figure 3.7.1)
The OPC layers: OD (including SR_DOD), PO (including SR_DPO), VTL_N, VTL_P, VTH_N, VTH_P, ULVT_N,
ULVT_P, DCO_LPP, NP, PP, CO, M1, VIAx, Mx, VIAy, My
For OD, PO, VTL_N, VTL_P, VTH_N, VTH_P, ULVT_N, ULVT_P, DCO_LPP, NP, PP, M1, Mx, My, all vertices
and intersections of 45-degree polygon must be on an integer multiple of 0.005 μm except PO inside the layer
186;5 for GS/GL and 186;4 for LP/LPG.
< 1 .0 X m in w id th
< 1 .0 X m in w id th
Label
Op.
0.005
< 1 .0 X m in w id th
or
> 1 .0 X m in w id th
< 1 .0 X m in w id th
< 1 .0 X m in w id th
< 1 .0 X m in w id th
or
< 1 .0 X m in w id th
> 1 .0 X m in w id th
> 1 .0 X m in w id th
< 1 .0 X m in w id th
< 1 .0 X m in w id th
or
Figure 3.7.1 Illustration for G.4.
Figure 3.7.2 Illustration for G.6gU.
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whole or in part without prior written permission of TSMC.
Rule
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OPC Recommendations and Guidelines
The following OPC recommendations are very important tips to reduce OPC and mask-making cycle time (or
physical verification) and ensure the best silicon performance:

Make certain that the design is DRC clean (free of all DRC violations).

Do not use circles, oval shapes, or logos of arbitrary geometry (Figure 3.7.3). Use rectangular or 45degree polygons to write words, logos, and other marks that are not part of the circuit.

Verify that all line-ends are rectangular.

Limit cell names to 127 or fewer characters.

Use a well-organized, hierarchical layout structure.
Avoid redundant or excessive overlaps of polygons from two, or more than two, different cells or
cell placements. For example, avoid forming a straight line from numerous cell placements, with each
one contributing a little piece. Refer to the “Design Hierarchy Guidelines” section in this chapter.

Worse performance in the simulation of contour for the layout with small jog/zigzag (Figure 3.7.4).
Rule No.
OPC.R.2gU
Description
Label
Op.
Rule
Avoid small jogs (Figure 3.7.4).
It is recommended to use greater than, or equal to, half of the
minimum width of each layer for each segment of a jog.
Figure 3.7.3 Logo Geometry Example
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whole or in part without prior written permission of TSMC.
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O rig in a l la y o u t
 0.16
S im u la tio n
o f c o n to u r
Figure 3.7.4 Simulation contour for the layout with and without small jog/zigzag. The simulation is Mx
line and not well treated due to small jog/zigzag, and cause smaller VIAx overlap.
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Design Hierarchy Guidelines
The style of the cell hierarchy in a design can significantly affect the following:

OPC and mask-making cycle time

Run time and memory usage of physical verification.
The following items are the recommended practices:

Re-use design blocks as much as possible.
Do not create two different cells for the same device.

Whenever possible, avoid using L, U, or ring shapes.
For inevitable ring structures such as seal rings and power rings, use cells for holding each ring segment
instead of drawing the whole ring at once. The same method applies to the L and U shapes.

Put everything as low in the cell hierarchy as possible. Here are some examples:
 Put all shapes required for defining a device or circuit into the same cell. An inverter cell, for example,
should include NW, OD, PO, NP, and PP, as well as CO and M1 (for pins).
 Avoid drawing a large shape to cover a whole circuit.
 Place texts at the lowermost cell where devices can be formed.
 For layout patches/revisions/ECOs, avoid changing device properties or metal connections at upper
cells in the design hierarchy.
 Draw within the cell the shapes required in TSMC’s logic operations.
Please consider all independent layers used in each rule logic operations and derived layer logic
operations. For example, LDN.EX.2 applies to NP and OD2; therefore, NP should reside in the same
cell as OD2.

Make certain each cell is DRC clean in a bottom-up construction of the cell hierarchy.
For example, when placing a contact in a cell, place M1 in that cell as well, with the required amount of M1.

Keep dummy fill geometry in a separate hierarchy from the main patterns and reduce the count of
flattened dummy fill geometry as much as possible.
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Chip Implementation and Tape Out Checklist
The following checklist is required to be completed prior to the tape out:

IP are correctly utilized in the design
 Pay attentions to the special orientation/direction (eg. SRAM), guard ring or space keep-out
requirements of placement.
 Pay attentions to routing constrains in resistance matching, power net spacing, layers available for over
block routing, layers allowed dummy fill, and power connection/width.
 To avoid using non-silicon proven library and IP, please pay attentions to the available library/IP
validation status from TSMC Online (Design Portal  Library/IP).
 It is highly recommended that do not modify or remove the IP tags (CAD 63;63) in the design.

The design passes signal/power/IR/ESD integrity analysis
 Simulations of all CKTs in setup time, hold time, and noise analysis under design operating corners or
sign-off corners.
 Analyses in leakage with considering statistical factor, total power consumption, power network
robustness, static/dynamic IR, IO SSO meet design specifics over all operating corners.
 Ensure all contacts/vias and metal lines meet EM lifetime requirement.
 ESD/latch-up layout and design requirements have been met.

The design passes DRC
 Use the most update DRC command file version corresponding to the design rule document.
 Need to choose the DRC options carefully and correctly.
 Need to cover all the DRC, including latch-up, ESD, anntena, assembly check.
 It is recommended running full chip DRC if there is any layout change in cell level.
 Any DRC violation needs to be reviewed by TSMC, to make sure no production concern.

The design passes LVS/ERC checks
 Use the most update LVS/ERC command file version corresponding to the SPICE document.

DFM services and requirements are recommended
 Utilize TSMC DFM redundant VIA utility to insert redundant vias and enlarge via enclosure.
 Utilize TSMC dummy OD/PO/metal generation utilities to insert dummy patterns to meet pattern density
requirements.
 RC extraction by DFM-LPE to have accurate SPICE simulations in IP design.
 The section 3.8 Design Hierarchy Guidelines have been considered.

Tape out information
 Make sure to have every “tape out required CAD layer” filled correctly in the TSMC i-tapeout system.
Additionally, to correctly fill DRC-only CAD layers of the design is welcome.
 It is highly recommended that the GDSII file taped out to TSMC contains IP tags information (CAD
63;63).
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whole or in part without prior written permission of TSMC.
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4 Layout Rules and Recommendations
This chapter provides information about the following:
4.1 Layout Rule Conventions
4.2 Derived Geometries Used in Physical Design Rules
4.3 Definition of Layout Geometrical Terminology
4.4 Minimum Pitches
4.5 Layout Rules and Guidelines
4.1
Layout Rule Conventions
Layout rules follow these conventions:

Unless otherwise specified, all rules are of minimum dimension.

The basic unit of measure is μm; the basic unit of area is μm2.
o Process, product, and reliability yields are expected to be improved when designs are relaxed from
minimum dimensions. Minimum dimensions showed only to be used to shrink the chip size or to improve
the circuit performance.
o Design rules requiring exact dimensions (“=” in the rule tables) are not to be relaxed.

Guideline is grouped by a separate table.

DFM recommendations and guidelines are designated by a registered symbol ® or “g” after the rule
number.

A registered symbol “U“ is marked after the rule number as the rule is not checked by DRC.

Rules denoted by “#” depend on the capability of each individual probing/ assembly house. These rules are
checked by DRC, and may be waived by customers with agreement from their subcontractors.

Rules denoted by “t” applied for tsmc bumping only. These rules are checked by DRC, and may be waived
by customers with agreement from a third-party bumping house.

Bracket usage in the rules should be noted carefully:
 Parentheses ( ) are used for explanation.
 Square brackets [ ] are used for certain conditions.
 Curved brackets { } are used to indicate that an operation is performed.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Derived Geometries Used in Physical Design
Rules
4.2.1
Derived Geometries
Term
ACTIVE
ALLOD
Butted_STRAP
FIELD
FIELD PO
GATE
N+ ACTIVE
N+OD
NW STRAP
NW1V
NW2V
NWROD
NWRSTI
OD2
P+ ACTIVE
P+OD
PW STRAP
RW STRAP
STRAP
RW
PW
BTC
Definition
N+ ACTIVE OR P+ ACTIVE
OD OR DOD OR SR_DOD
STRAP TOUCH ACTIVE
NOT OD
PO NOT OD
PO AND OD
(NP AND OD) NOT NW
NP AND OD
(NP AND OD) AND NW
1. NW NOT OD2 (Note 1)
2. NW OUTSIDE OD2 (Notes 1~2)
1. NW AND OD2 (Note 1)
2. NW NOT OUTSIDE OD2 (Notes 1~2)
(NW INTERACT NWDMY) INTERACT RPO
(NW INTERACT NWDMY) NOT INTERACT RPO
OD_18, OD_25, OD_33
(PP AND OD) AND NW
PP AND OD
(PP AND OD) NOT NW
((PP AND OD) NOT NW) INSIDE DNW
NW STRAP OR PW STRAP
(Chip NOT NW) INSIDE DNW
Chip NOT NW
(CO NOT CO;11) AND SRM;0
Table note:
1. For DRC recognition purpose, NW covered by OD2 is necessary for NW applied by voltage greater than core voltage.
It is very important to manually take care of NW to NW space ≥ 1um if NW cannot be covered by OD2 and at least
one NW is applied by voltage greater than core voltage.
2. If the switch, NW_SUGGESTED, turns ON (default), DRC will not only run NW.S.3 and NW.S.4 but also additionally
check “SUGGESTED.NW.S.3_NW.S.4” by recognizing NW1V by {NW OUTSIDE OD2} and NW2V by {NW NOT
OUTSIDE OD2}. If it turns OFF, DRC only checks NW.S.3 and NW.S.4.
NW NOT OD2
NW
OD2
N W O U T S ID E O D 2
OD2
NW
NW
NW
NW
NW
NW
NW AND OD2
N W N O T O U T S ID E O D 2
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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NW
PW
MOS
NMOS
PMOS
DOD
SR_DOD
DPO
SR_DPO
BTC
DMx
DMx_O
Prime Chip
Assembly isolation
CUP
: T-N45-CL-DR-001
: 2.6
Special Definition
Term
ENDCAP
CB
CBD
RV
CB2_FC
CB2_WB
AP
AP RDL
PM
UBM
Document No.
Version
Definition
N-WELL
P-WELL
Transistor structure consisting of a source, a drain, and a gate.
N type MOS
P type MOS
Dummy OD
Dummy OD (smaller dimension)
Dummy PO
Dummy PO (smaller dimension)
Butted Contact
Dummy Metal
OPC dummy metal. The rules of DMx_O are the same as real metal, Mx.
“Prime Chip” doesn’t include seal ring and assembly isolation.
If seal-ring is added by TSMC, the “Prime Chip” means: GDS EXTENT
If seal-ring is added by you, the “Prime Chip” means:
EXTENT of {INNER EDGE OF SEALRING_ALL (162;2)}
The 6um inner region of SEALRING_ALL (162;2) which surrounds {Prime Chip NOT triangle
empty areas}
The PO extension of a transistor gate in the width direction onto the field.
Passivation opening for wire bond design
Passivation opening for flip chip design
Redistribution VIA for connecting AP-MD with Mtop
Passivation 2 opening for flip chip
Passivation 2 opening for wire bond
Al pad metal layer after CB or CBD in Cu process
Al pad redistribution layer
Polyimide opening
Under bump metallurgy
Wire bond pad design for Circuit Under Pad.CUP has 2 solid metal layer at Mtop/Mtop-1 and
coverd by WBDMY
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Definition of Layout Geometrical Terminology
Width: Distance of interior-facing edge for single layer. (W)
W
Space: Distance of exterior-facing edge for one or two layer (S)
S
S
S
S
Overlap: Distance of interior-facing edge for two layers (O)
Enclosure: Distance of inside edge to outside edge (Fully inside) (EN)
Extension: Distance of inside edge to outside edge (EX)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Prime Chip:
GDS w/I seal ring :
GDS w/o seal ring:
Prime chip:
EXTENT of {INNER EDGE of
SEALRING_ALL (162;2)}
Prime chip:
Gds extent edge
Triangle
empty area
Seal ring (162;2)
Interact with:
A INTERACT B:
B
A
A
A
A IN T E R A C T B
A
A
A
A
A
A
A
A NOT INTERACT B:
B
A
A
A
A
A
A
A N O T IN T E R A C T B
A
A
INSIDE:
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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A INSIDE B:
B
A
A
A
A
A
A IN S ID E B
A
A
A
A NOT INSIDE B:
B
A
A
A
A
A
A N O T IN S ID E B
A
A
A
A
A
A OUTSIDE B:
B
A
A
A
A
A O U T S ID E B
A
A
A
A
A
A NOT OUTSIDE B:
B
A
A
A
A
A N O T O U T S ID E B
A
A
A
A
A
AREA (A):
ENCLOSED Area (A):
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whole or in part without prior written permission of TSMC.
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3-Neighboring:
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Projection:
Individual projection (L1, L2)
Union projection (L1 + L2)
W2
W1
L2
L1
If W1 > certain w idth and W2 > certain
w idth, L = L1+ L2
If W1 > certain w idth and W2 < certain
w idth, L = L1
Parallel run length:
Length and width
Length: the longer edge
L
L
W
W
Width: the shorter edge
Size up a
Size down b
b
a
a
original
a
a
original
b
b
b
Butted
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A ABUT B:
B
A
A
A
A
A
A ABUT B
A
A
A
A AND B:
B
A
A
A
A
A
A
A AND B
A
A
A
A OR B:
B
A
A
A
B
A
A OR B
A
A
A
A
A
A
A
A
Guard ring
R in g - t y p e O D a n d M 1 w it h C O
a s m a n y a s p o s s ib le
S e a l r in g
C h ip /IP le v e l
C h ip
P r o te c tio n r in g
I P ( w it h o u t I n d u c t o r )
CO bar
Y
V IA b a r
Y
C O h o le
Y
O p t io n
V IA h o le
N
N
S tr u c tu r e
O D /C O /
(O D /C O /M e ta l/V ia )
Y ( c o n t in u o u s )
IP
N
N
Y ( c o n t in u o u s o r b r e a c h )
N
Y
Y
O D /C O /M 1 /
a ll M e t a ls / a ll V I A s
M 1 / a ll V I A x / a ll M x
P le a s e r e fe r to s e c ti o n 4 .5 .5 4
P le a s e r e fe r to s e c ti o n 4 .5 .3 5 L O W M E D N la y o u t r u le s .
s e a l rin g o ve rvie w .
G u a r d r in g
I P ( w it h I n d u c t o r )
V I A 1 a b o v e is o p t io n a l.
P le a s e r e fe r to s e c ti o n s fo r
a n a lo g c i r c u i t/ D F M / L a tc h - u p .
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One track
O n e tr a c k = M x w id th + M x s p a c e
VTH_N
VTH_N
O n e tra c k
O n e tra c k
O n e tra c k
VTH_N
VTH_N
A llo w e d
A llo w e d
N o t a llo w e d
CUT
A CUT B:
B
A
A
A
A
A
A CUT B
A
A
B CUT A:
B
B
B
A
B
B CUT A
B CUT A
A
A
A NOT CUT B:
B
A
A
A
A
A
A
A NOT CUT B
A
A
A
A
A
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Channel width
PO
OD
Channel length
PO
OD
Vertex/Corner: Polygon whose edge form an angle
Vertex
Hole width
Enclosed space
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Minimum Pitches
Definition of Layout Geometrical Terminology
Layer
OD interconnect pitch
OD interconnect width
OD transistor pitch
PO interconnect pitch (on STI)
PO interconnect width
PO transistor pitch (on OD)
PO transistor pitch (on OD with CO)
Minimum length of a transistor
Minimum width of a transistor
N+/P+ spacing
M1 pitch
Mx pitch
My pitch
Mz Pitch
Mr pitch
Mu pitch
CO Pitch
CO Pitch in different net
CO  3 neighboring Pitch
VIAx Pitch
VIAx Pitch in different net
VIAx  3 neighboring Pitch
VIAy Pitch
VIAy  3 neighboring Pitch
VIAz Pitch
VIAz  3 neighboring Pitch
VIAr pitch
VIAr  3 neighboring pitch
CLN45
(Unit: μm)
0.14 (W/S=0.06/0.08)
0.06
0.20 (W/S=0.12/0.08)
0.14 (W/S=0.04/0.10)
0.04
0.18 (W/S=0.04/0.14)
0.18
0.04
0.12
0.16
0.14 (W/S=0.07/0.07)
0.14 (W/S=0.07/0.07)
0.28 (W/S=0.14/0.14)
0.80 (W/S=0.40/0.40)
1.0 (W/S=0.5/0.5)
3.0 (W/S=2.0/1.0)
0.14 (W/S=0.06/0.08)
0.17 (W/S=0.06/0.11)
0.16 (W/S=0.06/0.10)
0.14 (W/S=0.07/0.07)
0.165 (W/S=0.07/0.095)
0.16 (W/S=0.07/0.09)
0.28 (W/S=0.14/0.14)
0.30 (W/S=0.14/0.16)
0.70 (W/S=0.36/0.34)
0.90 (W/S=0.36/0.54)
0.90 (W/S=0.46/0.44)
1.12 (W/S=0.46/0.66)
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4.5
Layout Rules and Guidelines
4.5.1
Gate Oxide and Diffusion (OD) Layout Rules
(Mask ID: 120)
Rule No.
OD.W.1
OD.W.1®
OD.W.2
OD.W.2.1GS
OD.W.2.2GS
OD.W.3
OD.W.4
OD.S.1
OD.S.1®
OD.S.2
OD.S.3
OD.S.3.1
OD.S.4
OD.S.5
OD.A.1
OD.A.2
OD.A.3
OD.A.4
OD.A.5.GS
OD.L.1
OD.L.2
OD.DN.0
OD.DN.1
OD.DN.1.1
OD.DN.2
OD.DN.2.1
OD.DN.2.2
OD.DN.3
OD.DN.3.1
OD.DN.3.2
Description
Label
Width
A
Recommended minimum interconnect OD width (except MOMDMY (155;21) region and TCDDMY)
A
Channel width of core device
B
Maximum channel width of core NMOS device for GS and LPG G device
B
(This check doesn’t include the regions covered by layers NT_N, SR_ESD, LOGO, TCDDMY and VAR)
Maximum channel width of core PMOS device for GS
B
(This check doesn’t include the regions covered by layers NT_N, LOGO, TCDDMY and VAR)
Channel width of MOS [for I/O device]
C
Width of 45-degree bent OD. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid
D
(refer to the rule, G.6, in section 3.7))
Space
E
Recommended minimum OD space to reduce the short possibility caused by particle
E
Space (inside OD2)
F
Space to OD [width > 0.12 μm] if the parallel run length  0.14 µm (P)
G
Space to OD [width > 0.12 μm] if the parallel run length  0.14 µm (P1) in PO gate direction
G1
Space to 45-degree bent OD
H
Space between two segments of a U-shape or an O-shape OD (notch only)
I
Area (This check doesn't include the patterns filling 0.06 μm x 0.26 μm rectangular tiles)
K
Area [with all of edge lengths < 0.21 μm]
K’
Enclosed area
L
Enclosed area [with all of inner edge lengths < 0.21 μm]
L’
Maximum ACTIVE area sum of core PMOS device in the same checking area of OD. (Not including the
gate area) (For GS)
DRC methodology:
Maximum area sum of ((Core P+ ACTIVE INTERACT PO) NOT (PO OR SR_DPO)) in the same
checking area of OD.
The checking area is defined by sizing 0.22um in S/D direction, and 0.08um in endcap direction from
gate.
Maximum length of {ACTIVE (source) [width < 0.12 μm] interacts with butted_STRAP} if no CO in M
M
region.
Maximum OD length [OD width < 0.12 µm] between two contacts as well as between one contact and
N
the OD line-end. (except {RFDMY AND RFIP_DMY} and {MOMDMY(155;21) SIZING 1.2um})
1. OD.DN.2/OD.DN.2.1/OD.DN.2.2 and OD.DN.3/OD.DN.3.1/OD.DN.3.2 are checked over any window
150 μm x 150 μm, stepping 75 μm .
2. (outside OD2) means the overlapped width between the checking window and OD2 layer is smaller
than 37.5 μm.
3. For OD.DN.2/OD.DN.2.1/OD.DN.2.2/OD.DN.3/OD.DN.3.1/OD.DN.3.2, the following regions can be
excluded:
- NWDMY/LOGO/INDDMY/INDDMY_MD
- Chip corner stress relief and seal-ring
4. OD.DN.2/OD.DN.2.1/OD.DN.2.2 are applied when the width of (checking window NOT the item 3) is
 37.5 μm.
5. OD.DN.3/OD.DN.3.1/OD.DN.3.2 must be followed for every defined ODBLK region. This rule is only
applied when the width of ((checking window AND ODBLK) NOT item 3) is  37.5 μm.
Minimum {OD OR DOD OR SR_DOD} density across full chip
Maximum {OD OR DOD OR SR_DOD} density across full chip
Minimum {OD OR DOD OR SR_DOD} local density (window 150μm x 150 μm, stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density [OUTSIDE OD2] (window 150 μm x 150 μm,
stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density (window 150 μm x 150 μm, stepping 75 μm)
Minimum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm,
stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK [OUTSIDE OD2] (window 150 μm x
150 μm, stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm, stepping
75 μm)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.



Rule
0.06
0.08
0.12

10

1.5

0.32

0.17











0.08
0.10
0.15
0.10
0.11
0.17
0.15
0.035
0.055
0.04
0.077

300

0.4

60



25%
75%
20%

80%

90%

20%

80%

90%
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Rule No.
OD.DN.4®
OD.DN.5®
OD.DN.6®
OD.DN.7®
OD.DN.8®
OD.DN.9®
OD.R.1
DOD.R.1*
DOD.R.4®
OD.L.2gU
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Description
Label
It is not recommended the gate interact with the region of {(OD local density < 10%) SIZING 20um}.
The definition of the gate is as follows:
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(OD local density > 70%) SIZING 20um}.
The definition of the gate is as follows:
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(OD local density < 20%) SIZING 100um}.
The definition of the gate is as follows:
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 50umx50um, stepping 25um)
It is not recommended the gate interact with the region of {(OD local density > 70%) SIZING 100um}.
The definition of the gate is as follows:
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 50umx50um, stepping 25um)
It is not recommended the unsalicided poly resistor interact with the region of {(OD local density < 20%)
SIZING 100um}.
The definition of the unsalicided poly resistor is as follows:
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY*)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 200umx200um, stepping 100um)
It is not recommended the unsalicided poly resistor interact with the region of {(OD local density > 60%)
SIZING 100um}.
The definition of the unsalicided poly resistor is as follows:
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY*)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 200umx200um, stepping 100um)
OD must be fully covered by {NP OR PP} except for {(DOD OR SR_DOD) OR NWDMY}
DOD is a must. DOD CAD layer (TSMC default, 6;1) must be different from OD’s. Please refer to
section 8.1.
It is important to use TSMC DOD/DPO utility to insert the SR_DOD and SR_DPO properly surrounding
your IP and circuit, and then do post-simulation carefully before chip implementation.
Op.
Rule

10%

70%

20%

70%

20%

60%
DRC will flag the empty rectangle area larger than 1.8x1.8um2 inside
{(GATE SIZE 2.8) NOT (((OD OR DOD) OR SR_DOD) SIZE 0.12) NOT ((PO SIZE 0.05) OR ((DPO OR
SR_DPO) SIZE 0.03)) NOT ((NW SIZE 0.08) NOT (NW SIZE -0.08))} (Except TCDDMY and
SEALRING_ALL (162;2))
It is strongly suggested to limit the max interconnect length (M) to be as short as possible to avoid high
Rs variation.

1.8x1.8um2
* CAD layer SENDMY (255;8) is used to check OD.DN.4® ~ OD.DN.9® for sensitive circuits. If your IP is sensitive to
the Isat variation due to low/high OD density, you can cover the SENDMY to perform this check.
Table Notes:

In order to meet the extremely tight requirement in terms of process control for STI etch, polish, OSE as
well as channel length definition (inter-level dielectric (ILD) planarization), you must fill the DOD globally
and uniformly even if the originally drawn OD already satisfies the required OD density rule
(OD.DN.1~OD.DN.3.2). Inder to cover the OSE (refer to the section of Layout Guidelines for OSE (OD
Space Effect)), it is important to follow the layout guideline (refer to the section of How to reduce the
differences between pre-simulation and post-simulation) and use TSMC DOD/DPO utility to reduce the
gap between SPICE and silicon. It is recommended to manually add DOD uniformly inside regions
covered by the ODBLK layer, to gain better process window and electrical performance.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
OD
O D .S .3 / O D .S .3 .1
O D .W .1
A
E
W < = 0 .1 2
A
OD
O D .W .3
G1
P1
OD2
OD
C
P
W > 0 .1 2
PO
F
W > 0 .1 2
G
OD
O D .S .5
E
I
OD
O D .W .4 / O D .S .4 / O D .L .3
B
A
I
PO
E
O
D
H
OD
H
E
OD
O D .L .1
O D .A .1 / O D .A .3
OD
BUTTED
OD
M
OD
PO
OD
< 0 .1 2
PO
K /K ’
> 0 .1 2
OD
M
OD
L /L '
BUTTED
< 0 .1 2
OD
L /L '
OD
N o n e e d to
BUTTED
fo llo w
BUTTED
< 0 .1 2
O D .L .1
M
< 0 .1 2
OD
< 0 .1 2
> 0 .1 2
> 0 .1 2 P O
W < 0 .1 2 u m
PO
OD
OD
O D .L .2
N <= 60 um
N 
60 um
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
DOD.R.4® and SR_DOD.R.4gU
DOD/DPO
Analog Device or IP
SR_DOD/SR_DPO
: T-N45-CL-DR-001
: 2.6
Analog Device or IP
surrounded with
dummy devices
Not recommend (Si to simulation gap:)
Recommend
Recommend
(>10%)
(>10%)
(>10%)
1. Without dummy devices & DOD/DPO
2. Only surrounded by dummy devices, but no DOD/DPO
protect
3. Only surrounded by DOD/DPO, but no SR_DOD/SR_DPO
(<5%)
IP surrounded
with DOD/DPO
by updated utility
(<5%)
IP surrounded
with dummy devices
first, then insert
DOD/DPO
U
U
DOD.R.4®
D O D . R . 2 ® and
& S RSR_DOD.R.4g
_ D O D .R .4
0 .1
0 .8 8
0 .0 4 /0 .1
0 .0 4 /0 .1
0 .2
S R _ D O D (6 ;7 )
S R _ D P O (1 7 ;7 )
0 .2
P O LY (1 7 ;0 )
0 .1
O D (6 ;0 )
0 .1 2
0 .0 5
0 .1
0 .8 8
0 .5
0 .0 4 /0 .1
4um
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Deep N-Well (DNW) Layout Rules (Mask ID: 119)
[Optional]
Rule No.
Description
Label
Op.
Rule
DNW.W.1
Width
A

3
DNW.S.1
B

3.5
C

2.5
DNW.S.3
Space
Space to NW with different potential
DRC only checks when NW does not exist in same DNW.
Space to {N+ ACTIVE outside DNW}
D

1.65
DNW.S.4
RW space to {RW OR PW} with different potential
E

0.8
DNW.S.5
{RW OR PW} space to {RW INTERACT OD2} with different potential
F

1.0
DNW.EN.1®
Recommended enclosure by NW for better noise isolation
G

1.0
DNW.EN.3
Enclosure of N+ ACTIVE
K

0.48
DNW.O.1
Overlap of NW
H

0.4
DNW.R.3U
Keep {NW INTERACT DNW} and PW in reverse bias
DNW.R.4U
{NW INTERACT DNW} must be at the same potential
N+ ACTIVE cut DNW is not allowed
Recommended not using floating RW unless necessary to avoid unstable
device performance.
Maximum cumulative area ratio of DNW to {(NMOS/P-VAR core gates)
OUTSIDE DNW} [connects to {P+ ACTIVE INSIDE {NW INTERACT DNW}}]
This rule is checked by the ANTENNA DRC command file.
Maximum cumulative area ratio of DNW [area ≥ 1E+06 µm2] to {(NMOS/PVAR core gates) OUTSIDE DNW} [connects to {P+ ACTIVE INSIDE {NW
INTERACT DNW}}, and does not connect to STRAP]
≤
5.0E+05
≤
5.0E+05
≦
500000
DNW.S.2
DNW.R.5
DNW.R.6gU
DNW.R.7
DNW.R.7.1
DNW.R.7.2
This rule is checked by the cumulative connections (from M1 to AP
respectively) and the DRC command files in ANTENNA_DRC directory.
Maximum cumulative area ratio of DNW [area 1E+06 um2] to
{core_NMOS/P-VAR INSIDE DNW [area ≤1E03um2]}
If ≧ 4 um2 {N+ OD AND PW} added in discharging path with lower metal
layers (M1 or M2) which outside DNW, it is allowed maximum cumulative area
ratio of DNW [area 1E+06 um2] to {core_NMOS/P-VAR INSIDE DNW [area
≤1E03um2]} up to 4.1E+06.
Definition of core_NMOS/P-VAR:
1. NMOS and P-VAR gates do not inside OD2, and
2.Connect to {P+ ACTIVE INSIDE (NW INTERACT DNW) [area ≥1E+06
um2]}, and
3.Do not connect to STRAP
This rule is checked by the cumulative connections (from M1 to AP
respectively) and the DRC command files in ANTENNA_DRC directory.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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D
DN
NW
W
NW
G
NW
H
H
DNW
RW
X
PW
RW
X'
E
K
(F )
N + A C T IV E
E
(F )
DNW
N + A C T IV E
D
C
B
R W (P W in s id e D N W )
N
+
A C T IV E
NW
NW
DNW
DNW
A
C r o s s S e c t io n ( X - X ') f o r N W , R W , a n d D N W
X
X'
NW
RW
NW
RW
NW
PW
DW N
For better noise isolation, it is recommended to follow the DNW.EN.1® rule
G
NW
H
DNW
RW
X
RW
RW
X'
E
(F )
D
C
B
N
R W (P -w e ll in D N W )
+
OD
NW
NW
DNW
DNW
A
C r o s s S e c t io n ( X - X ') f o r N W , R W , a n d D N W
X
X'
NW
RW
NW
RW
NW
RW
NW
DW N
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.3
Rule No.
NW.W.1
NW.S.1
NW.S.2
NW.S.3
NW.S.4
NW.S.5
NW.S.6
NW.S.6.1
NW.S.7
NW.EN.1
NW.EN.2
NW.EN.2.1
NW.EN.3
NW.A.1
NW.A.2
NW.R.1g
NW.R.2U
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
N-Well (NW) Layout Rules
Description
Width, except SRAMDMY
Space
Space of two NW1V with different potentials (*)
NW1V space to NW2V with different potentials (*)
Space of two NW2V with different potentials (*)
Space to PW STRAP
Space to N+ ACTIVE (except NW resistor)
Space to N+ ACTIVE [at least one edge at each corner] (except NW resistor)
Space to {N+ ACTIVE INTERACT OD2}
Enclosure of NW STRAP (except NW resistor)
Enclosure of P+ ACTIVE
Enclosure of P+ ACTIVE [at least one edge at each corner]
Enclosure of {P+ ACTIVE INTERACT OD2}
Area
Enclosed area
Recommend not using unintentional floating well to avoid unstable device performance. DRC flags
{NW OUTSIDE {N+OD INTERACT CO}}.
OD2 must overlap NW [applied by voltage greater than core voltage]
Label
A
C
D
E
F
G
H
H1
I
K
L
L1
M
O
P
Op.















Rule
0.34
0.34
0.8
1
1
0.08
0.08
0.16
0.22
0.08
0.08
0.16
0.22
0.64
0.64
Table notes:*: DRC implementation is on different nets.
1. For DRC recognition purpose, NW overlapped by OD2 is necessary for NW applied by voltage greater than core
voltage. It is very important to manually take care of NW to NW space ≥ 1um if NW cannot be operlapped by OD2
and at least one NW is applied by voltage greater than core voltage.
2. If the switch, NW_SUGGESTED, turns ON (default), DRC will not only run NW.S.3 and NW.S.4 but also additionally
check “SUGGESTED.NW.S.3_NW.S.4” by recognizing NW1V by {NW OUTSIDE OD2} and NW2V by {NW NOT
OUTSIDE OD2}. If it turns OFF, DRC only checks NW.S.3 and NW.S.4.
N
W
NW
C
A
A
P
D /E /F
P
O
N W
N W
N W
N W
P W
N W
N W
L 1 (o r L )
H 1 (o r H )
P + O D
N + O D
L (o r L 1 )
N + O D
K
H
a t le a s t o n e e d g e a t e a c h c o r n e r
(o r H 1 )
G
P + O D
O D 2
P
+
O D
N W
M
I
N + O D
P W
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.4
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
N-Well Resistor Within OD (NWROD) Layout
Rules
Rule No.
Description
Label
Op.
Rule
A

1.8
NWROD.W.1
Width
NWROD.S.1
Space to NWROD or to NW
B

1.0
NWROD.S.2
Space to RPO
Recommended RPO space to CO in NW resistor within OD for SPICE
simulation accuracy
Enclosure by OD
C

0.3
G
=
0.3
D

1.0
E

0.3
F
=
0.4
NWROD.S.3®
NWROD.EN.1
NWROD.EN.2
NWROD.O.1
NWROD.O.2
NWROD.R.3g
NWROD.R.4
NWROD.R.5
NWROD.R.6
NWROD.R.7
NWROD.R.8g
Enclosure of CO
RPO overlap of NP. Use exact value (0.4 μm) on sides touching
NWDMY.
{OD AND NWDMY} overlap of {NP, PP, VTH_N, VTH_P, VTL_N, or
VTL_P} (all implant layers except NW) is not allowed.
Recommended to use rectangle shape resistor for the SPICE simulation
accuracy. DRC can flag {NWDMY AND NW} is not a rectangle.
Only one NW inside NWROD is allowed in one OD.
Only two NPs in NWROD are allowed in one OD.
Only two RPO holes(Sailcide) in NWROD are allowed in the same OD
For U-shape or S-shape NWROD, both OD and NW must be U-shape or
S-shape and the OD edge must be parallel to the NW edge. DRC can
only flag the pattern without OD space when two edges of NW [NW
space or notch ≤ 5 um] have a parallel run length > 0 um.
Recommend: NWDMY intersecting NWROD forms two or more NWs.
Table Notes:

The mean value and deviation of an N-Well resistor depends on the layout and dimension.

Dummy layer NWDMY is needed for DRC and LVS.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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NWROD
RPO
OD
D
N W R O D .W .1
E
F
F
E
B
NW
R P O .E X .1
NW
0 .2 2
D
A
G
G
C
NW
R P O H o le
R P O H o le
NP
N W e ll R e s is to r
NP
NW DMY
N W R O D .R .4
N W R O D .R .5
N W R O D .R .7
OD
NP
NW
NP
NP
NW
NW
OD
NW DMY
NW
OD
NW DMY
NW DMY
N W R O D .R .7
N W R O D .R .7
N W R O D .R .6
OD
NW
RPO
OD
NW
NW
NW
OD
NW DMY
NW DMY
NW DMY
T h e la y o u t is u n c h e c k a b le
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.5
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
N-Well Resistor Under STI (NWRSTI) Layout
Rules
Rule No.
Description
Label
Op.
Rule
A

1.8
NWRSTI.W.1
Width
NWRSTI.S.1
Space to NWRSTI or to NW
B

1.0
NWRSTI.EN.1
NP enclosure of OD
C

0.4
NWRSTI.EN.2
OD enclosure of CO
Recommended OD enclosure of CO in NW resistor under STI for SPICE
simulation accuracy
Enclosure of CO
D

0.3
D
=
0.3
E

0.3
OD extension on NWRSTI
{NP INTERACT NWDMY} overlap of {PP, VTH_P, or VTL_P} (all p-type
implant layers) is not allowed
Recommended to use rectangle shape resistor for the SPICE simulation
accuracy.
DRC can flag {NWDMY AND NW} is not a rectangle.
Recommend: NWDMY intersecting NWRSTI forms two or more NWs.
F

0.3
NWRSTI.EN.2®
NWRSTI.EN.3
NWRSTI.EX.1
NWRSTI.O.1
NWRSTI.R.3g
NWRSTI.R.4g
NWRSTI
N W R S T I.W .1
B
N W
N W
A
N W e ll R e s is to r
O D
O D
E
C
D
E
F
NW
NP
NP
NW DM Y
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Native Device (NT_N) Layout Rules
NT_N, Native NMOS Blocked Implant Definition
This layer is used to block NW and PW implant. If you use native NMOS devices in a circuit design, please use this drawn
layer with NW to generate PW. Native NMOS is only allowed being designed in the standard device region. It cannot be
applied to pure high/low Vt designs.
Rule No.
Description
Label
Op.
Rule
NT_N.W.1
Width
A

0.34
NT_N.W.2
Channel length of 0.9V/1.1V/1.2V native device for N45LP/N45LPG/N40G
B

0.30
NT_N.W.2.1
Channel length of 1.1V native device only for N40LP/N40LPG
B

0.20
C

1.20
D

0.8
E

0.5
NT_N.W.5
Channel length of 2.5V/3.3V native device (for 2.5V overdrive to 3.3V,
please refer to section OD25_33 Layout Rules)
Channel length of 1.8V native device (for 2.5V underdrive to 1.8V, please
refer to section OD25_18 Layout Rules)
Channel width
NT_N.S.1
Space
F

0.34
NT_N.S.2
Space to [Active outside NT_N]
G

0.38
NT_N.S.3
NT_N.EN.1
NT_N.EX.1
Space to NW
Enclosure range of N+OD.
PO extension on {OD inside NT_N} (PO endcap)
H
I
J

=

1
0.26
0.35
NT_N.A.1
Area
K

0.64
NT_N.A.2
NT_N.R.1
Enclosed area
L

0.64
NT_N.W.3
NT_N.W.4
NT_N.R.2
NT_N.R.3
Overlap of {NW OR DNW} is not allowed
P+ ACTIVE region is not allowed in NT_N but PW STRAP is allowed.
DRC only can check P+ Gate is not allowed in NT_N.
Only one OD region is allowed in NT_N

Except NMOS capacitor with the same potential, pickup and
MOMDMY (155;21) region.

You have to draw a NCap_NTN layer to cover the NMOS
capacitors. The NCap_NTN enclosure of OD have to be  0um. All
the source and drain must be connected together.

DRC also flags NCap_NTN and OD, which is outside of the
NCap_NTN in the same NT_N.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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NT_N
L
L
K
OD
N o m in a l
C, D
A
D e v ic e O D
G
F
PO LY
OD
I
E
H
J
PW
NW
N T _ N .R .3
NT_N
NT_N
Ncap_NTN
OD
OD
P r o h ib it e d
Ncap_NTN
Ncap_NTN
OD
OD
A llo w e d
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Thick Oxide (OD2) Layout Rules (Mask ID: 152)

Define thick oxide area of 1.8V or 2.5V or 3.3V I/O transistors.

The OD_33 layer (CAD layer: 15) is used for 3.3V gate oxide area only for N40LPG.

The OD_25 layer (CAD layer: 18) is used for 2.5V gate oxide area.

The OD_18 layer (CAD layer: 16) is used for 1.8V gate oxide area.

OD2 refers to any thick oxide device, for example, OD2 = OD_18, OD_25, or OD_33.
Rule No.
OD2.W.1
OD2.W.2
Description
Width
Width of {OD2 OR {NW OR NT_N}}
Width of {OD2 NOT {NW OR NT_N}}, except {{OD2 NOT {NW OR NT_N}}
OD2.W.3
[width < 0.34um] NOT INTERACT OD} and LOGO regions
OD2.S.1
Space
Space to {ACTIVE OR GATE}
OD2.S.2
({ACTIVE OR GATE} cut OD2 is not allowed)
OD2.S.3
Space to 0.9V/1.2V GATE in S/D direction.
OD2.S.4
Space to NW. Space = 0 μm is allowed.
OD2.S.5
Space of {NW NOT OD2}
OD2.S.6
Space of {NW AND OD2}
OD2.S.7
Space of {OD2 NOT {NW OR NT_N}}
Space of {OD2 OR {NW OR NT_N}}, except {{OD2 OR {NW OR NT_N}} [space
OD2.S.8
< 0.34um] NOT INTERACT OD} and LOGO regions
OD2.EN.1
Enclosure of 1.8V/2.5V/3.3V Gate in S/D direction.
OD2.EX.1
NW extension on OD2. Extension = 0 μm is allowed.
OD2.EX.2
Extension on NW. Extension = 0 μm is allowed.
OD2.EX.3
Extension on {ACTIVE OR GATE}
OD2.O.1
Overlap of NW. Overlap = 0 μm is allowed.
OD2.R.1
OD_18, OD_25, and OD_33 cannot be used on the same die.
Only OD_25 (CAD layer: 18) is allowed for N40LP+.
Neither OD_33 (CAD layer: 15) nor OD_18 (CAD layer: 16) is allowed for
OD2.R.2.LPP
N40LP+.
DRC will flag {(CHIP INTERACT DCO_LPP) INTERACT (OD_18 OR OD_33 )}
Label
A
O
Op.


Rule
0.34
0.34
W

0.34
B

0.34
C

0.2
G
E
P
Q
R





0.25
0.34
0.34
0.34
0.34
S

0.34
D
H
I
J
K





0.25
0.34
0.34
0.2
0.34
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OD2
O D 2
O D 2
J
O D 2
O D 2
I
K
A
B
K
H
C
N W
O D
N W
A C T IV E
J
O D 2
E
O D 2
O D 2
O
N W
N W
PO
PO
X
O D 2
O D 2
R
O D
P
N o t a llo w e d ( O D 2 .S .2 )
Q
N W
N W
O D 2
D
G
O D
M
PO
PO
L
O D 2
B u tte d S tra p
O D 2
O D 2
A llo w e d ( O D 2 .S .2 )
W
{O D 2 O R {N W
{N W
O R N T_N }
S
{O D 2 O R {N W
O R N T _ N }}
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
O R N T _ N }}
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Dual Core Oxide (DCO) Layout Rules (Mask ID:
153)
DCO (CAD layer: 90;0) is a layer to cover G core device in N45/40LPG process.
Rule No.
Description
Label
Op.
Rule
DCO.W.1
Width
A

0.34
DCO.W.2
Width of {DCO OR NW}, except SRAMDMY
O

0.34
DCO.S.1
Space
B

0.34
DCO.S.2
Space to ACTIVE
C

0.05
DCO.S.3
Space to LP (core 1.1V) Gate in S/D direction.
D

0.16
DCO.S.4
Space to LP (core 1.1V) Gate in end-cap direction.
D1

0.09
DCO.S.5
Space to NW. Space = 0 is allowed.
E

0.34
DCO.S.6
Space to OD2. Space = 0 is allowed.
F

0.34
DCO.S.8
Space of {DCO NOT NW}
P

0.34
DCO.S.9
Space of {DCO AND NW}
Q

0.34
DCO.S.10
Space of {NW NOT DCO}
R

0.34
DCO.EN.1
Enclosure of G (core 0.9V) Gate in S/D direction.
G

0.16
DCO.EN.2
Enclosure of G (core 0.9V) Gate in end-cap direction.
G1

0.09
DCO.EX.1
NW extension on DCO. Extension = 0 is allowed.
H

0.34
DCO.EX.2
Extension on NW. Extension = 0 is allowed.
I

DCO.EX.3
Extension on ACTIVE [Cut is not allowed if without Gate]
J

0.34
0.05
DCO.A.1
Area
M

0.7
DCO.A.2
Enclosed area
N

DCO.O.1
DCO.R.2
DCO.R.3
Overlap of NW. Overlap = 0 is allowed.
Overlap of OD2 is not allowed
DCO cut RH is not allowed
K

0.7
0.34
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DCO
M
DCO
J
DCO
B
C
DCO
DCO
K
A
I
N
OD
OD
NW
DCO
DCO
DCO
D C O .R 2
G1
OD2
D
G
PO
PO
DCO
K
H
G1
NW
D1
F
OD2
RH
DCO
DCO
DCO
E
NW
D C O .R 3
DCO
DCO
P
G
R
PO
PO
D
NW
DCO
O
OD
NW
DCO
Q
NW
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1.2V Core Oxide (OD_12) Layout Rules (Mask ID:
12A)
OD_12 (CAD layer: 14;1) is a layer to cover 1.2V core device in N40G process.
Rule No.
Description
Label
Op.
Rule
OD_12.W.1
OD_12.W.3
OD_12.S.1
OD_12.S.2
OD_12.S.3
OD_12.S.4
OD_12.S.6
OD_12.EN.1
OD_12.EN.2
OD_12.EX.3
OD_12.A.1
OD_12.A.2
Width
Channel length
Space
Space to {ACTIVE OR GATE}
Space to core 0.9V Gate in S/D direction.
Space to core 0.9V Gate in end-cap direction.
Space to OD2. Space = 0 μm is allowed.
Enclosure of core 1.2V Gate in S/D direction.
Enclosure of core 1.2V Gate in end-cap direction.
Extension on ACTIVE [Cut is not allowed if without Gate]
Area
Enclosed area
Overlap of VTH_N, VTH_P, VTL_N, VTL_P, RPO, RH, NWDMY, BJTDMY,
OD2 is not allowed
OD_12 cut {ACTIVE OR GATE} is not allowed
(Except OD shared by core and OD_12 is at same potential, DRC can not
exclude this exception.)
Point-touch, one/two track (0.14μm) space and overlap is allow
A












0.34
0.07
0.34
0.05
0.16
0.09
0.18
0.16
0.09
0.05
0.64
0.64
OD_12.R.2
OD_12.R.3
OD_12.R.4
B
C
D
D1
F
G
G1
J
M
N
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OD_12
M
O D _12
J
O D _12
B
C
O D _12
A
N
OD
OD
O D _12
O D _12
O D _ 1 2 .R .2
G1
OD2
D
G
PO
PO
O D _12
G1
D1
F
OD2
O D _ 1 2 .R .2
RH
O D _12
O D _12
O D _ 1 2 .R .3
X
PO
PO
O D _12
OD
N o t a llo w e d
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OD25_33 Layout Rules
OD25_33 (CAD layer: 18;3) is used for 2.5V overdrive to 3.3V for N45/N40LP and N40G. This is not a mask
layer.
Rule No.
Description
Label
Op.
Rule
A

0.5
A

0.55
B

0.4
B

0.44

1.2
Channel length of 2.5V NMOS overdrive to 3.3V (NMOS Gate AND
OD25_33) for N45LP/N40LP.
OD25_33.W.1.LP
It is not shrinkable as the channel length is ≤ 0.545 for N40LP. You have to
draw ≥ 0.55.
Channel length of 2.5V NMOS overdrive to 3.3V (NMOS Gate AND
OD25_33.W.1.GS
OD25_33) for N40G.
Channel length of 2.5V PMOS overdrive to 3.3V (PMOS Gate AND
OD25_33) for N45LP/N40LP.
OD25_33.W.2.LP
It is not shrinkable as the channel length is ≤ 0.435 for N40LP. You have to
draw ≥ 0.44.
Channel length of 2.5V PMOS overdrive to 3.3V (PMOS Gate AND
OD25_33.W.2.GS
OD25_33) for N40G.
Channel length of 2.5V native NMOS overdrive to 3.3V. ((Gate AND NT_N)
OD25_33.W.3
AND OD25_33)
(Gate AND OD25_33) can’t overlap OD_18 or OD_33 or OD25_18. (Gate
AND OD25_33) must be covered by OD_25. GATE cut OD25_33 is not
OD25_33.R.1
allowed.
OD25_33
O D_25
N M O S G a te
O D 25_33
P M O S G a te
PO
PO
O D
A
O D
B
O D 2 5 _ 3 3 .R .1
O D 25_33
PO
O D 25_33
PO
O D
G a te
PO
O D
G a te
O D
G a te
O D 25_33
O D _18 or O D _33 or O D 25_18
O D_25
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OD25_18 Layout Rules
OD25_18 (CAD layer: 18;4) is only used for 2.5V underdrive to 1.8V for N45/N40LP and N40G. This is not a
mask layer.
Rule No.
OD25_18.W.1
Description
Label
Op.
Rule
A

0.25
A

0.27

1.2
Channel length of 2.5V MOS underdrive to 1.8V (Gate AND OD25_18)
OD25_18.W.1.GS Channel length of 2.5V PMOS underdrive to 1.8V (Gate AND OD25_18)
Channel length of 2.5V native NMOS underdrive to 1.8V ((Gate AND
OD25_18.W.2
NT_N) AND OD25_18)
(Gate AND OD25_18) can’t overlap OD_18 or OD_33 or OD25_33. (Gate
OD25_18.R.1
AND OD25_18) must be covered by OD_25. GATE cut OD25_18 is not
allowed.
OD25_18
O D_25
N M O S G a te
O D 25_18
P M O S G a te
PO
PO
OD
A
OD
A
O D 2 5 _ 1 8 .R .1
O D 25_18
PO
O D 25_18
PO
OD
G a te
PO
OD
G a te
OD
G a te
O D 25_18
O D _18 or O D _33 or O D 25_33
O D_25
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OD18_15 Layout Rules
OD18_15 (CAD layer: 16;4) is only used for 1.8V underdrive to 1.5V in N40G (=45GS) and N40LP process.
This is not a mask layer.
Rule No.
Description
Channel length of 1.8V MOS underdrive to 1.5V (Gate AND OD18_15) for
GS
Channel length of 1.8V MOS underdrive to 1.5V (Gate AND OD18_15) for
OD18_15.W.1.LP
N40LP
(Gate AND OD18_15) can’t overlap OD_25 or OD_33 or OD25_18, or
OD18_15.R.1
OD25_33. (Gate AND OD18_15) must be covered by OD_18. OD18_15
can’t cut GATE.
OD18_15.R.2
1.8V and 1.5V cannot share the same NW.
OD18_15.W.1.GS
Label
Op.
Rule
A

0.105
A

0.125
OD18_15
O D_18
N M O S G a te
O D 18_15
P M O S G a te
PO
PO
OD
OD
A
A
O D 1 8 _ 1 5 .R .1
O D 18_15
PO
O D 18_15
PO
OD
G a te
PO
OD
G a te
OD
G a te
O D 18_15
O D _25 or O D _33or O D 25_18 or D 25_33
O D_18
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Poly (PO) Layout Rules (Mask ID: 130)
CAD layer SENDMY (255;8) is used to check PO.DN.4® ~ PO.DN.9® for sensitive circuits. If your IP is sensitive to the
Isat variation due to low/high PO density, you can cover the SENDMY to perform this check.
Rule No.
PO.W.1
PO.W.1® U
PO.W.2
PO.W.3.LP
PO.W.4
PO.W.6.GS
PO.W.7
PO.W.8
PO.S.1
PO.S.1®
PO.S.2.LP
PO.S.2.LP®
PO.S.2.GS
PO.S.2.1LP
PO.S.2.1GS
PO.S.2.1.1GS
PO.S.3
PO.S.4
PO.S.4.1
PO.S.4.1®
PO.S.5.LP®
PO.S.5.GS®
PO.S.6
PO.S.6.LP®
PO.S.6.GS®
PO.S.6.1
PO.S.7
PO.S.9
PO.S.10
PO.S.15
PO.S.16
Description
Width
Recommended minimum interconnect PO width
Channel length of 2.5V MOS (for 2.5V overdrive to 3.3V, please refer to section OD25_33 Layout
Rules)
Channel length of 3.3V MOS only for N40LP and N40LPG.
Channel length of 1.8 V MOS (For 2.5V underdrive to 1.8V, please refer to section OD25_18 Layout
Rules. For 1.8V underdrive to 1.5V, please refer to section OD18_15 Layout Rules.)
Channel length of core device for GS
(This check doesn’t include CDUDMY region and the regions covered by layers of NT_N, SDI, and
VAR.)
Width of 45-degree FIELD PO (except PO fuse element, POFUSE, 156;0). (Please make sure the
vertex of 45-degree pattern is on 5nm grid (refer to the rule, G.6U, in section 3.7))
Maximum Channel length of NMOS [for LPG G device]
Space
Recommended minimum interconnect PO space to reduce the short possibility caused by particle
The poly gate space range to neighboring {PO OR SR_DPO} [for channel length < 0.06μm]. This
allows a violation with a length ratio < 30% on one side and one segment.
The length ratio = violation length / device width.
The 0.12 ~ 0.125 are not shrinkable. This rule is for poly gate CDU control
(Except SRAMDMY;0 (186;0) region)
Recommended GATE space in the same OD to avoid Isat degradation for LP/LPG
The poly gate space range to neighboring {PO OR SR_DPO} [for channel length < 0.08 μm], and
allow a violation with a length ratio < 30% on one side and one segment.
The length ratio = violation length / device width.
This rule is for poly gate CDU control.
(This check doesn’t include the regions covered by layer SRAMDMY;5)
(Except SRAMDMY;0 (186;0) region)
Gate space [either one channel length  0.06μm] for LP/LPG
Gate space [either one channel length  0.08 μm] for GS
Maximum gate [channel length  0.08 μm] space to neighboring {PO OR SR_DPO} in core device
regions for GS
(This check doesn’t include the regions covered by layer SR_ESD and LOGO.)
{GATE inside OD2} space in the same OD
FIELD PO space to OD
(except CSRDMY (166;0) region)
Gate space [L-shape OD and L-shape PO enclosed area < 0.0121 μm2 ]
Recommended gate space [L-shape OD and L-shape PO enclosed area < 0.0196 μm2] for PO/OD
rounding effect
Recommended space to L-shape OD when PO and OD are in the same MOS (avoid corner
rounding effect) for LP/LPG
Recommended space to L-shape OD when PO and OD are in the same MOS (avoid corner
rounding effect) for GS
L-shape PO space to OD when PO and OD are in the same MOS [L-shape PO length (R1)  0.06
μm]
Recommended L-shape PO space to OD when PO and OD are in the same MOS (avoid corner
rounding effect) for LP/LPG
Recommended L-shape PO space to OD when PO and OD are in the same MOS (avoid corner
rounding effect) for GS
L-shape PO space to OD when PO and OD are in the same MOS [L-shape PO length > 0.06 μm
(R1) and L-shape PO length  0.1 μm (R1)]
Space if at least one {PO OR SR_DPO} width > 0.12 μm, and the {PO OR SR_DPO} parallel run
length > 0.14 μm (individual projection).
Space [in same RPO]
Space at {PO OR SR_DPO} line-end (W < 0.07 μm (Q1)) in a dense-line-end configuration: If {PO
OR SR_DPO} has parallel run length with opposite {PO OR SR_DPO} (measured with T1 = 0.035
μm extension) along two adjacent edges of {PO OR SR_DPO} [any one edge < Q1 distance from
the corner of the two edges], then one of the spaces (S1 or S2) needs to be at least this value
(This check doesn't include small jog with edge length < 0.04 μm (R))
Large PO to gate [channel length  0.08 μm] space. The large PO is defined as PO area  630 μm2
and interacts with regions of density > 70% in window 30 μm x 30 μm, stepping 15 μm. DPO will be
excluded from density check.
Space to 45-degree bent {PO OR SR_DPO}
Label
A
A
Op.


Rule
0.04
0.06
B

0.27
C

0.42
D

0.15
A
=
0.04 / 0.045 / 0.05
/ 0.06 / 0.07 /
0.08~10
E

0.17
A
F
F
≤


10
0.10
0.12
G
=
0.12 ~ 0.22 or
0.32
G

0.14
G
=
0.14 / 0.16 / 0.2
G1
G1


0.14
0.14
G1

0.32
H

0.22
I

0.03
I1

0.11
I1’

0.14
J

0.1
J

0.06
I2

0.04
K

0.1
K

0.07
I2’

0.05
L

0.16
N

0.18
S1/S2

0.11

1.0

0.17
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whole or in part without prior written permission of TSMC.
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Rule No.
PO.S.17®
PO.S.18.GS®
PO.EX.1
PO.EX.1®
PO.EX.2
PO.EX.2®
PO.EX.2.1GS
PO.EX.3
PO.L.1
PO.A.1
PO.A.2
PO.A.3
PO.A.4
PO.DN.1
PO.DN.1.1
PO.DN.2
PO.DN.3
PO.DN.4®
PO.DN.5®
PO.DN.6®
PO.DN.7®
PO.DN.8®
PO.DN.9®
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Label
Recommended Gate edge [channel length = 0.04um, channel width ≤ 0.2um] space to {(PO OR
SR_DPO) OR DPO } [width ≥ 0.12um] [projection in S/D direction], and Gate edge parallel run length
S0
(individual projection) in the same gate ≥ 0.1um, for poly gate CDU control
Recommend to add 2nd poly away from 1st poly [for channel length < 0.08μm] (DRC only check 1st
U
poly space to gate ≤ 0.2um and width < 0.08um)
Extension on OD (end-cap)
O
Recommended extension on OD (end-cap) to avoid line-end shortening.
O
OD extension on PO
P
Recommended OD extension on PO (full and symmetrical contact placement are recommended at
both source and drain side) to avoid Isat degradation, especially for channel width > 1.5 μm.
P
When you use poly space = 0.16 μm (PO.S.2), please use = 0.13 μm for this recommendation.
Maximum OD extension on the edge gate [channel length  0.08 μm] in core device regions. (For the
P1
edge gate, it is OK to follow either PO.S.2.1.1GS or PO.EX.2.1GS)
This check doesn’t include the regions covered by layer SR_ESD.
Extension on OD (end-cap) when the PO to L-shape OD (in the same MOS) space < 0.1 μm.
Q
(This check doesn’t include ACTIVE jog  0.02 μm.)
Maximum PO length between two contacts, as well as the length from any point inside PO gate to
the nearest CO when the PO width is < 0.08 μm. (This check doesn’t include ESD protection
R
devices.)
Area (This check doesn’t include the pattern filling 0.04 μm x 0.3 μm rectangular tile)
S
Area [with all of edge length < 0.21 μm]
S
Enclosed area
T
Enclosed area [with all of inner edge length < 0.21 μm]
T
Minimum {(PO OR DPO) OR SR_DPO} density across full chip
Maximum {(PO OR DPO) OR SR_DPO} density across full chip
{OD OR DOD OR SR_DOD OR PO OR DPO OR SR_DPO} local density
1. PO.DN.2 is checked by window 20 μm x 20 μm, stepping 10 μm.
2. For PO.DN.2 rules, the following regions can be excluded:
(1) ODBLK/POBLK/NWDMY/LOGO/INDDMY/INDDMY_MD as default
(2) Chip corner stress relief area if seal-ring and stress relief pattern added by TSMC.
3. Even in areas covered by {ODBLK OR POBLK}, this pattern density that follows the PO.DN.2
rules is recommended.
4. The rule is applied when the width of (checking window NOT item 2) is  5 μm.
PO density within POBLK. (except {RFDMY AND RFIP_DMY}, MOMDMY(155;21), and TCDDMY)
It is not recommended the gate interact with the region of {(PO local density < 5%) SIZING 20um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um
2. {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(PO local density > 35%) SIZING 20um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um
2. {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(PO local density < 15%) SIZING 100um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um
2. {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 50umx50um, stepping 25um)
It is not recommended the gate interact with the region of {(PO local density > 35%) SIZING 100um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um
2. {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 50umx50um, stepping 25um)
It is not recommended the unsalicided poly resistor interact with the region of {(PO local density <
15%) SIZING 100um}.
The definition of unsalicided poly resistor is as follows:
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY*)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 200umx200um, stepping 100um)
It is not recommended the unsalicided poly resistor interact with the region of {(PO local density >
40%) SIZING 100um}.
The definition of unsalicided poly resistor is as follows:
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY*)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 200umx200um, stepping 100um)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.
Rule

0.16
=
0.14~0.2



0.09
0.11
0.09

0.13

0.32

0.11

18






0.022
0.055
0.04
0.077
14%
40%

0.1%

14%

5%

35%

15%

35%

15%

40%
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Rule No.
PO.R.1
PO.R.2U
PO.R.4
PO.R.6
PO.R.7
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
GATE must be a rectangle orthogonal to grid. (Both bent GATE and gate with jog are not allowed).
(Except CSRDMY region)
PO line-end must be rectangular. Other shapes are not allowed.
PO intersecting OD must form two or more diffusions. (Except CSRDMY region)
H-gate that fulfills the following conditions at the same time is not allowed. [inner space < 0.43 μm
(U), channel length < 0.10 μm (V), interconnect PO width < 0.25 μm (W), and interconnect PO length
> 0.065 μm(X)]
Poly gates of all SRAM cells (50;0 OR 186;0) must be uni-directional in a chip.
(This check doesn’t include the regions covered by layer 49 (RODMY) and RAM1TDMY (160;0))
Chips on MPW or shuttles may be rotated due to this rule
Floating gate is prohibited if the effective source/drain are not connected together.
Label
Op.
Rule
Floating gate in the DRC is as follows:
(1) Gate without Poly CO.
(2) Gate with Poly CO but not connected to MOS OD, STRAP or PAD.
(3) It is not a floating gate if the Gate is connected to OD by butted CO in SRAM bit cell.
PO.R.8
The effective source/drain in DRC is as follows:
(1)Source/drain is connected to different {MOSOD NOT PO}, STRAP, Gate, or PAD.
This rule is only checked on the whole chip, not on the IP level.
Poly gates of Pass gate (PG) of all eDRAM cells (RAM1TDMY, 160;0) must be uni-directional in a
chip.
DPO is a must. DPO CAD layer (TSMC default, 17;1) must be a different layer from the PO CAD
layer. Please refer to section 8.2.
Recommend to limit the max interconnect PO length (R) as short as possible to avoid high Rs
variation.
PO.R.9
DPO.R.1
PO.L.1gU
* CAD layer SENDMY (255;8) is used to check PO.DN.4® ~ PO.DN.9® for sensitive circuits. If your IP is sensitive to
the Isat variation due to low/high PO density, you can cover the SENDMY to perform this check.
Table note:


In order to meet the tight requirement in terms of the complex photo, poly critical dimension (CCD) control
etching process, as well as the PSE layout effect (refer to the section of Layout Guidelines for PSE (Poly
Space Effect), it is important to adopt TSMC DOD//DPO utility to reduce the CD variation, and also
reduce the gap between SPICE model and silicon data.
Please use POs with the same or similar channel length neighboring with a critical device. For example,
prevent any PO with a larger channel length, eg.  70nm, from neighboring with a critical device’s gate
with the channel length as 40nm.
40nm
40nm
>= 70nm
PO
OD
x
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
PO
A /B /C /D
F
I
I
G ,G 1 ,
P O .S .5 R / P O .S .6 R
H
PO
Q
J
O
I2 '
N + /P
+
OD
I
P
O
K
F
P O .S .7
F
F
0 .1 4
A
L
> 0 .1 2
T h e fie ld P O to O D s p a c e
C O o n th e P O a x is
I2 '
(0 .0 6 < R 1 = < 0 .1 )
> = 0 .1 2
R1
R1
I (R 1 > 0 .1 )
N + /P +
N + /P +
OD
OD
R1
I2 (R 1 < = 0 .0 6 )
P O .S .9
P o ly e n d c a p
< 0 .1
(0 .0 2 < R 2 = < 0 .0 8 )
O
O
R2
O
RPO
N
O
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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P O .S .1 0
P O . S . 4PO.S.4.1 ®
PO.S.4.1/
S1
S1
PO
S1
S1
S1
I1 /I1 '
OD
: T-N45-CL-DR-001
: 2.6
<
S2
S2
T1
Q1
S2
S2
R e g io n 1 o r 2 c a n n o t h a v e o th e r p o ly
T1
p a tte r n s a t th e s a m e tim e . O n e o f th e m
w ith o th e r p o ly p a tte r n s is a llo w e d .
S1
F
T1
F
R e g io n 2
R e g io n 1
<Q 1
W <Q 1
T1
T1
T1
S2
<Q 1
S1
S2
W <Q 1
P O .R .6
PO.W.6.GS
P O .W .6 / P O .S .1 6 / P O .L .2
F A
W
V
U
U
E
M
X
PO
M
F
PO
P O .R .2
P O .A .1 / P O .A .3
PO
PO
PO
P O .R .4
OD
OD
T
S
T
PO
PO
P O .L .1
W < 0 .0 8 u m
R <= 18um
W < 0 .0 8 u m
O D
R <= 18 um
R <= 18um
O D
O D
R <= 18 um
R <= 18 um
R <= 18 um
R > 18 um
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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P O .R .8
: T-N45-CL-DR-001
: 2.6
N o n - f lo a t in g G a t e
F lo a t in g G a t e
F lo a t in g G a t e
F lo a t in g G a t e
PO
PO
PO
M e ta l
M e ta l
A llo w e d
F lo a t in g G a t e
OD
PO
M e ta l
A llo w e d
A llo w e d
F lo a t in g G a t e
A llo w e d
A llo w e d
A llo w e d
PO
OD
OD
M e ta l
F lo a t in g G a t e
PO
PO
F lo a t in g G a t e
OD
OD
OD
F lo a t in g G a t e
OD
B u tte d _
S T R A P.
M e ta l
M e ta l
M e ta l
M e ta l
M e ta l
P r o h ib it e d
M e ta l
P r o h ib it e d
P r o h ib it e d
S o u r c e / d r a in is c o n n e c t e d t o d iff e r e n t { M O S O D N O T P O } , S T R A P, G a t e , o r P A D .
P O .S .2
L1
C a s e A : P a s s d u e to o n e s e g m e n t w ith (L 1 /L ) < 3 0 % .
C a s e B : T r u e v io la tio n d u e to tw o s e g m e n t s (O n ly o n e s e g m e n t is a llo w e d ).
C a s e C : T r u e v io la tio n d u e to th r e e s e g m e n ts (O n ly o n e s e g m e n t is a llo w e d ).
C a s e D : O n e s e g m e n t (L 1 = L 2 + L 3 ). If (L 1 /L ) = 3 0 % , tr u e v io la tio n ; if (L 1 /L ) < 3 0 % , p a s s .
O K , if L 1 /L ( o r L 2 / L a , L 3 / L b ) < 3 0 %
L1
L3
L3
L3
L4
Lb
La
L2
0 .1 4 /0 .1 6 /0 .2
L2
L
L2
L1
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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P O .S .1 7 ®
v io la te
: T-N45-CL-DR-001
: 2.6
pass
P a r a lle l
r u n le n g th
< 0 .1 u m
W 1 > = 0 .1 2 u m
W 0 ( w id th o f p o ly g a te ) < = 0 . 1 2 0 ~ 0 .2 u m .
L 0 = 0 .0 4 u m .
If S 0 = < 0 .1 6 u m , v io la te .
P a r a lle l r u n le n g th
> = 0 .1 u m
P O .S .1 8 .G S ®
2
nd
1
P o ly
U
st
P o ly
G a te
L g < 0 .0 8 u m
< = 0 .2
< = 0 .2
1
st
P o ly
2
nd
P o ly
U
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
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: T-N45-CL-DR-001
: 2.6
High Vt NMOS (VTH_N) Layout Rules (Mask ID:
11H)
It is not allowed in 1.8V, 2.5V, and 3.3V devices.
Rule No.
Label
Op.
Rule
VTH_N.W.1
Width
Description
A

0.18
VTH_N.S.1
Space
B

0.18
VTH_N.S.2
Space to gate in PO endcap direction
C

0.08
VTH_N.S.2.1
Space to gate in S/D direction
D

0.14
VTH_N.S.3
Space to unsilicided PO/OD resistor
E

0.18
VTH_N.EN.1
Enclosure of gate in S/D direction
F

0.14
VTH_N.EN.2
Enclosure of gate in PO endcap direction
G

0.08
VTH_N.A.1
Area
H

0.19
VTH_N.A.2
Enclosed area
I

0.19
VTH_N.R.1
VTH_N.R.2
VTH_N.R.3
VTH_N.L.1
Overlap of P+ ACTIVE, VAR, VTL_N, NT_N, or OD2 is not allowed.
Point touch of corners is allowed.
One-track overlap / space are allowed.
45-degree edge length
=
0.14
0.5

VTH_N
H
A
O D
P O
N +
I
O D
B
P O
P O
C
P W
I
G
P O
O D
D
F
F
D
E
P O
o r O D r e s is to r
p o in t to u c h
O n e - tr a c k o v e r la p
V TH _N
is a llo w e d
is a llo w e d
0 .1 4 u m
V TH _N
X
V TH _N
V TH _N
0 .1 4 u m
O n e -tra c k s p a c e
is a llo w e d
N o t a llo w e d if s p a c e < 0 .1 8 u m
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: T-N45-CL-DR-001
: 2.6
High Vt PMOS (VTH_P) Layout Rules (Mask ID:
11G)
It is not allowed in 1.8V, 2.5V, and 3.3V devices.
Label
Op.
Rule
VTH_P.W.1
Rule No.
Width
Description
A

0.18
VTH_P.S.1
Space
B

0.18
VTH_P.S.2
Space to gate in PO endcap direction
C

0.08
VTH_P.S.2.1
Space to gate in S/D direction
D

0.14
VTH_P.S.3
Space to unsilicided PO/OD resistor
E

0.18
VTH_P.EN.1
Enclosure of gate in S/D direction
F

0.14
VTH_P.EN.2
Enclosure of gate in PO endcap direction
G

0.08
VTH_P.A.1
Area
H

0.19
VTH_P.A.2
Enclosed area
I

0.19
VTH_P.R.1
VTH_P.R.2
VTH_P.R.3
VTH_P.L.1
Overlap of N+ ACTIVE, VAR, VTL_P, NT_N, or OD2 is not allowed.
Point touch of corners is allowed.
One-track overlap / space are allowed.
45-degree edge length
=
0.14
0.5

VTH_P
H
A
O D
P O
P +
I
O D
B
P O
P O
C
N W
P O
G
I
O D
D
F
F
D
E
P O
or O D
r e s is to r
p o in t to u c h
O n e - tr a c k o v e r la p
V TH _P
is a llo w e d
is a llo w e d
0 .1 4 u m
V TH _P
X
V TH _P
V TH _P
0 .1 4 u m
O n e -tra c k s p a c e
is a llo w e d
N o t a llo w e d if s p a c e < 0 .1 8 u m
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: T-N45-CL-DR-001
: 2.6
Low Vt NMOS (VTL_N) Layout Rules (Mask ID:
118)
It is not allowed in 1.8V, 2.5V, and 3.3V devices.
Rule No.
Description
Label
Op.
Rule
VTL_N.W.1
Width
A

0.18
VTL_N.S.1
Space
B

0.18
VTL_N.S.2
Space to gate in PO endcap direction
C

0.08
VTL_N.S.2.1
Space to gate in S/D direction
D

0.14
VTL_N.S.3
Space to unsilicided PO/OD resistor
E

0.18
VTL_N.EN.1
Enclosure of gate in S/D direction
F

0.14
VTL_N.EN.2
Enclosure of gate in PO endcap direction
G

0.08
VTL_N.A.1
Area
H

0.19
VTL_N.A.2
Enclosed area
I

0.19
VTL_N.R.1
VTL_N.R.2
VTL_N.R.3
VTL_N.L.1
Overlap of P+ ACTIVE, VAR, VTH_N, NT_N, or OD2 is not allowed.
Point touch of corners is allowed.
One-track overlap / space are allowed.
45-degree edge length
=
0.14
0.5

VTL_N
H
A
O D
P O
N +
I
O D
B
P O
P O
C
P W
P O
G
I
O D
D
F
F
D
E
P O
or O D
r e s is to r
p o in t to u c h
O n e - tr a c k o v e r la p
V TL_N
is a llo w e d
is a llo w e d
0 .1 4 u m
V TL_N
X
V TL_N
V TL_N
0 .1 4 u m
O n e -tra c k s p a c e
is a llo w e d
N o t a llo w e d if s p a c e < 0 .1 8 u m
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: T-N45-CL-DR-001
: 2.6
Low Vt PMOS (VTL_P) Layout Rules (Mask ID:
117)
It is not allowed in 1.8V, 2.5V, and 3.3V devices.
Rule No.
Label
Op.
Rule
VTL_P.W.1
Width
Description
A

0.18
VTL_P.S.1
Space
B

0.18
VTL_P.S.2
Space to gate in PO endcap direction

0.08
VTL_P.S.2.1
Space to gate in S/D direction
C
D

0.14
VTL_P.S.3
Space to unsilicided PO/OD resistor
E

0.18
VTL_P.EN.1
Enclosure of gate in S/D direction

0.14
VTL_P.EN.2
Enclosure of gate in PO endcap direction
F
G

0.08
VTL_P.A.1
Area
H

0.19
VTL_P.A.2
VTL_P.R.1
VTL_P.R.2
VTL_P.R.3
VTL_P.L.1
Enclosed area
I

0.19
=
0.14
0.5
Overlap of N+ ACTIVE, VAR, VTH_P, NT_N, or OD2 is not allowed.
Point touch of corners is allowed.
One-track overlap / space are allowed.
45-degree edge length

VTL_P
H
A
O D
P O
P +
I
O D
B
P O
P O
C
N W
I
P O
G
O D
D
F
F
D
E
P O
or O D
r e s is to r
p o in t to u c h
O n e - tr a c k o v e r la p
V TL_P
is a llo w e d
is a llo w e d
0 .1 4 u m
V TL_P
X
V TL_P
V TL_P
0 .1 4 u m
O n e -tra c k s p a c e
is a llo w e d
N o t a llo w e d if s p a c e < 0 .1 8 u m
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Ultra Low Vt Plus Devices Layout Rules
Ultra low Vt plus devices layout rules, including DCO_LPP, ULVT_N, and ULVT_P layers, are only available for
N40LP+, and not allowed for other technologies.
4.5.18.1
DCO_LPPLUS (DCO_LPP) Layout Rules (Mask ID:
153)

DCO_LPP (CAD layer: 90;1) is used for ultra low Vt plus devices’ speed boost.

DCO_LPP is only used for core devices (1.1V). It is not allowed in I/O devices (2.5V).
Rule No.
Description
Label
Op.
Rule
A

0.34
DCO_LPP.W.1
Width
DCO_LPP.S.1
Space
B

0.34
DCO_LPP.S.2
C

0.04
D

0.16
D1

0.09
DCO_LPP.S.6
Space to ACTIVE
Space to {Gate NOT INTERACT (OD2 OR DCO_LPP)} in S/D
direction.
Space to {Gate NOT INTERACT (OD2 OR DCO_LPP)} in end-cap
direction.
Space to OD2. Space = 0 is allowed.
F

0.34
DCO_LPP.EN.1
Enclosure of 1.1V Gate in S/D direction.
G

0.16
DCO_LPP.EN.2
Enclosure of 1.1V Gate in end-cap direction.
Extension on ACTIVE [Cut is not allowed if without Gate]
Cut ACTIVE of TSMC N40LP+ standard cell (90;2, DCODMY_SC) is
allowed.
Area, except DCO_LPP.A.1.1
Area [width ≥ 0.42um] for only TSMC N40LP+ standard cell (90;2,
DCODMY_SC)
Enclosed area, except DCO_LPP.A.2.1
Enclosed area [hole width (N1) ≥ 0.42um] for TSMC N40LP+
standard cell (90;2, DCODMY_SC)
Overlap of VAR, VTL_N, VTL_P, VTH_N, VTH_P, NT_N, TCDDMY,
SRM, ROM, or OD2 is not allowed.
{DCO_LPP CUT RH} is not allowed
{Gate AND DCO_LPP} must be covered by {ULVT_N OR ULVT_P}
Point touch of corners is allowed for only TSMC N40LP+ standard cell
(90;2, DCODMY_SC)
One-track overlap / space are allowed for only TSMC N40LP+
standard cell (90;2, DCODMY_SC)
If DCODMY_SC exists, DCODMY_SC must be identical to
DCO_LPP. DCODMY_SC can not exist without DCO_LPP.
DCO_LPP can exist without DCODMY_SC.
G1

0.09
J

0.04
M

0.7
M

0.5292
N

0.7
N

0.5292
=
0.14, 0.19,
0.28
DCO_LPP.S.3
DCO_LPP.S.4
DCO_LPP.EX.3
DCO_LPP.A.1
DCO_LPP.A.1.1
DCO_LPP.A.2
DCO_LPP.A.2.1
DCO_LPP.R.1
DCO_LPP.R.2
DCO_LPP.R.3
DCO_LPP.R.4
DCO_LPP.R.5
DCO_LPP.R.6
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whole or in part without prior written permission of TSMC.
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DCO_LPP
M
D C O _LPP
J
D C O _LPP
B
C
D C O _LPP
A
OD
OD
N
N1
DCO _LPP
D C O _ L P P .R .1
G1
OD2
D
DCO _LPP
PO
PO
DCO _LPP
G
G1
D1
F
OD2
D C O _ L P P .R .2
RH
D C O _LPP
DCO _LPP
DCO _LPP
PO
G
PO
D
OD
point touch
is allowed
DCO_LPP (90;1)
DCODMY_SC (90;2)
DCO_LPP (90;1)
DCODMY_SC (90;2)
X
One-track overlap
is allowed
0.14, 0.19, or 0.28um
DCO_LPP (90;1)
DCODMY_SC (90;2)
DCO_LPP (90;1)
DCODMY_SC (90;2)
0.14, 0.19, or 0.28um
One-track space
is allowed
Not allowed if space < 0.34um
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Ultra Low Vt Plus NMOS (ULVT_N) Layout Rules
(Mask ID: 11E)

ULVT_N (CAD layer: 151;1), 1.1V ultra low Vt plus NMOS Implant Definition

ULVT_N is only used for core devices (1.1V). It is not allowed in I/O devices (2.5V).
Rule No.
ULVT_N.W.1
ULVT_N.S.1
ULVT_N.S.2
ULVT_N.S.2.1
ULVT_N.S.3
ULVT_N.EN.1
ULVT_N.EN.2
ULVT_N.A.1
ULVT_N.A.2
ULVT_N.R.1
ULVT_N.R.2
ULVT_N.R.3
ULVT_N.R.4
ULVT_N.L.1
Description
Width
Space
Space to gate in PO endcap direction
Space to gate in S/D direction
Space to unsilicided PO/OD resistor
Enclosure of gate in S/D direction
Enclosure of gate in PO endcap direction
Area
Enclosed area
Overlap of P+ACTIVE, VAR, VTL_N, VTH_N, NT_N, TCDDMY, {OD AND NWDMY}, SRM, ROM,
BJTDMY, RH, POFUSE, or OD2 is not allowed.
Point touch of corners is allowed.
One-track overlap / space are allowed.
{Gate AND ULVT_N} must be covered by DCO_LPP.
45-degree edge length
Label
A
B
C
D
E
F
G
H
I
Op.









Rule
0.18
0.18
0.08
0.14
0.18
0.14
0.08
0.19
0.19
=
0.14

0.5
ULVT_N
H
A
O D
P O
N +
I
O D
B
P O
P O
C
P W
P O
G
I
O D
F
D
F
D
E
P O
o r O D
r e s is to r
p o in t to u c h
is
O n e -tra c k
U L V T _ N
a llo w e d
is
0 .1 4 u m
U L V T _ N
X
U L V T _ N
o v e r la p
0 .1 4 u m
O n e -tra c k
is
N o t a llo w e d
if s p a c e
<
U L V T _ N
a llo w e d
s p a c e
a llo w e d
0 .1 8 u m
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whole or in part without prior written permission of TSMC.
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Ultra Low Vt Plus PMOS (ULVT_P) Layout Rules
(Mask ID: 11F)

ULVT_P (CAD layer: 152;1), 1.1V ultra low Vt plus PMOS Implant Definition

ULVT_P is only used for core devices (1.1V). It is not allowed in I/O devices (2.5V).
Rule No.
ULVT_P.W.1
ULVT_P.S.1
ULVT_P.S.2
ULVT_P.S.2.1
ULVT_P.S.3
ULVT_P.EN.1
ULVT_P.EN.2
ULVT_P.A.1
ULVT_P.A.2
ULVT_P.R.1
ULVT_P.R.2
ULVT_P.R.3
ULVT_P.R.4
ULVT_P.L.1
Description
Width
Space
Space to gate in PO endcap direction
Space to gate in S/D direction
Space to unsilicided PO/OD resistor
Enclosure of gate in S/D direction
Enclosure of gate in PO endcap direction
Area
Enclosed area
Overlap of N+ACTIVE, VAR, VTL_P, VTH_P, NT_N, TCDDMY, {OD AND NWDMY}, {NP
INTERACT NWDMY}, SRM, ROM, BJTDMY, RH, POFUSE, or OD2 is not allowed.
Point touch of corners is allowed.
One-track overlap / space are allowed.
{Gate AND ULVT_P} must be covered by DCO_LPP.
45-degree edge length
Label
A
B
C
D
E
F
G
H
I
Op.









Rule
0.18
0.18
0.08
0.14
0.18
0.14
0.08
0.19
0.19
=
0.14

0.5
ULVT_P
H
A
O D
P O
P +
I
O D
B
P O
P O
C
N W
I
P O
G
O D
D
F
F
D
E
P O
o r O D
r e s is to r
p o in t to u c h
is
O n e -tra c k
U L V T _ P
a llo w e d
is
0 .1 4 u m
U L V T _ P
X
N o t a llo w e d
if s p a c e
U L V T _ P
<
o v e r la p
U L V T _ P
a llo w e d
0 .1 4 u m
O n e -tra c k
is
s p a c e
a llo w e d
0 .1 8 u m
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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P+ Source/Drain Ion Implantation (PP) Layout
Rules (Mask ID: 197)
Rule No.
Description
Label
Op.
Rule
A

0.18
PP.W.1
Width
PP.S.1
Space
B

0.18
PP.S.2
PP.S.3
PP.S.4
Space to N+ ACTIVE (non-butted)
Space to {N+ ACTIVE OR NW STRAP} (butted)
Space to NW STRAP (non-butted)
C
D
E

=

0.08
0.00
0.02
PP.S.5
F

0.23
G

0.23
PP.S.7
{PP edge on OD} space to NMOS GATE
Butted PW STRAP space to PO in the same OD [the butted N+ ACTIVE
extending 0 < J1 < 0.13 μm]
Space to N-type unsilicided OD/PO resistor
H

0.14
PP.EN.1
{NP OR PP} enclosure of PO (except DPO)
I

0.11
PP.EX.1
Extension on P+ ACTIVE
J

0.08
PP.EX.2
Extension on PW STRAP (except SEALRING_ALL (162;2))
K

0.02
PP.EX.3
Extension on P-type unsilicided OD/PO resistor
L

0.14
PP.EX.4
{PP edge on OD} extension on PMOS GATE
M

0.23
PP.O.1
Overlap of OD
N

0.10
PP.A.1
Area
O

0.11
PP.A.2
Enclosed area
P

0.11
PP.A.3
Area of butted PW STRAP
Q

0.021
PP.R.1
PP.R.2
PP.R.3
PP.R.4
PP.L.1
PP must fully cover {PMOS GATE SIZING 0.08 μm}
Overlap of NP is not allowed.
OD must be fully covered by {NP OR PP} (except DOD and SR_DOD).
PO must be fully covered by {NP OR PP} (except DPO and SR_DPO).
45-degree edge length
R

0.08

0.5
PP.S.6
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whole or in part without prior written permission of TSMC.
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PP
PP
R
PO
O
J
P
P
PP
PP
PP
N
A
P
+
P
OD
+
OD
PP
K
B
P+ OD
K
PW
P+
OD
I
E
D
N
I
I
I
M
+
PO
N+
OD
I
PO
PO
OD
NW
PW
N ty p e
K
P lo y
r e s is to r
Q
P
+
OD
J1
G
PP
PO
D
L
H
C
F
K
N
+
OD
P+
OD
K
P ty p e P lo y
r e s is to r
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whole or in part without prior written permission of TSMC.
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N+ Source/Drain Ion Implantation (NP) Rules
(Mask ID: 198)
Label
Op.
Rule
NP.W.1
Rule No.
Width
A

0.18
NP.S.1
Space
B

0.18
NP.S.2
NP.S.3
NP.S.4
Space to P+ ACTIVE (non-butted)
Space to {P+ ACTIVE OR PW STRAP} (butted)
Space to PW STRAP (non-butted)
C
D
E

=

0.08
0.00
0.02
NP.S.5
F

0.23
G

0.23
NP.S.7
{NP edge on OD} space to PMOS GATE
Butted NW STRAP space to PO in the same OD [the butted P+ ACTIVE
extending 0 < J1 < 0.13 μm]
Space to P-type unsilicided OD/PO resistor
H

0.14
NP.EN.1
{NP OR PP} enclosure of PO (except DPO)
I

0.11
NP.EX.1
Extension on N+ ACTIVE (except NWROD)
J

0.08
NP.EX.2
Extension on NW STRAP (except NWROD)
K

0.02
NP.EX.3
Extension on N-type unsilicided OD/PO resistor
L

0.14
NP.EX.4
{NP edge on OD} extension on NMOS GATE
M

0.23
NP.O.1
Overlap of OD
N

0.10
NP.A.1
Area
O

0.11
NP.A.2
Enclosed area
P

0.11
NP.A.3
Area of butted NW STRAP
Q

0.021
NP.R.1
NP.R.2
NP.R.3
NP.R.4
NP.L.1
NP must fully cover {NMOS GATE SIZING 0.08 μm}
Overlap of PP is not allowed.
OD must be fully covered by {NP OR PP} (except DOD and SR_DOD).
PO must be fully covered by {NP OR PP} (except DPO and SR_DPO).
45-degree edge length
R

0.08

0.5
NP.S.6
Description
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NP
NP
R
PO
J
P
P
O
NP
N
A
NP
N+ OD
NP
NP
N+ OD
K
B
N+ OD
K
NW
N+ OD
I
E
D
I
I
I
M
P+
P+ OD
I
PO
PO
PO
OD
PW
NW
P ty p e P lo y
r e s is to r
K
Q
N+ OD
J1
G
NP
PO
D
K
L
H
C
F
P+ OD
N+ OD
K
N ty p e P lo y
r e s is to r
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Layout Rules for LDD Mask Logical Operations
N1V/N2V/P1V/P2V and VTC_N/VTC_P/VTL_N/VTL_P
As a default, TSMC generates some masking layers from drawn layers by logic operations. These include
N1V/N2V/P1V/P2V and VTC_N/VTC_P/VTL_N/VTL_P masks. The following rules (Fig. 1 - Fig. 6) are defined
to avoid small patterns during mask making.
Warning:
If the rules are not followed, the mask making cycle
time will be seriously impacted.
The following are special requirements.
d  0.18 μm
X/Y (the extension/space between two edges
of two layers in an X/Y)
Rule No.
LDN.EX.1
LDN.EX.2
LDN.EX.3
LDN.EX.4
LDN.O.1
LDP.EX.1
LDP.EX.2
LDP.EX.3
LDP.O.1
LDP.O.2
VT.S.1
VT.EX.2
The minimum extension/clearance between two
corners of two layers
If either dimension X or Y < 0.18 μm (including 0, 2
edges aligned), the other dimension must be  0.18
μm.
Description
NP extension on NW
NP extension on OD2
NP extension on {RH OR BJTDMY}
NP extension on VAR
NP overlap of OD2
PP extension on OD2
PP extension on {RH OR BJTDMY}
PP extension on VAR
PP overlap of NW
PP overlap of OD2
VTL_N space to {OD2 OR NW}
NW extension on {OD2 OR VTL_P}
Label
Op.
Rule
Fig. 1
Fig. 2
Fig. 1
Fig. 1
Fig. 3
Fig. 2
Fig. 1
Fig. 1
Fig. 3
Fig. 3
Fig. 5
Fig. 6












0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
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LDD Mask
(F ig . 1 )
(F ig . 2 )
N P /P P
Y
NP/ PP
Y
d
d
X
X
OD2
N W /R H /V A R
(F ig . 3 )
NP/ PP
Y
d
X
N W /O D 2
(F ig . 5 )
VTL_N
(F ig . 6 )
Y
d
X
(O D 2 O R N W )
NW
Y
d
X
(O D 2 O R V T L _ P )
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Resist Protection Oxide (RPO) Layout Rules
(Mask ID: 155)
Rule No.
Description
Label
Op.
Rule
A

0.40
RPO.W.1
Width
RPO.S.1
Space
B

0.40
RPO.S.2
Space to OD
C

0.22
RPO.S.3
Space to CO (overlap of CO is not allowed.)
D

0.22
RPO.S.4
Space to GATE (overlap of GATE is not allowed except ESD circuit.)
E

0.38
RPO.S.5
Space to PO
Extension on unsilicided OD/PO
(This check doesn’t include the regions covered by the layer SDI)
Extension on unsilicided OD/PO [RPO width > 10 μm]
(This check doesn’t include the regions covered by the layer SDI)
F

0.30
G

0.22
G1

0.30
G1

0.30
H

0.22
RPO.EX.1
RPO.EX.1.1
RPO.EX.2
Extension on unsilicided OD/PO [RPO width  0.43 μm]
(This check doesn’t include the regions covered by the layer SDI)
OD extension on RPO
RPO.A.1
Area
I

1.00
RPO.A.2
RPO.R.1
Enclosed area
Butted NP/PP on unsilicided OD/PO is not allowed.
J

1.00
RPO.EX.1.2
RPO
H
D
RPO
OD
C
G,
RPO
G1
E
B
PO
A
OD
R P O .R .1
RPO
G,
F
G1
PO or O D
PO
D
RPO
N+
N + /P +
P+
I
RPO
J
J
RPO
RPO
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OD and Poly Resistor Layout Rules
RH layer is required for OD and poly resistors. RH layer is a dummy layer that blocks NLDD or PLDD implants
in the logic operations that generate N1V, N2V, P1V, and P2V.
Unsilicided OD resistor: {{RH AND {RPO AND OD}} AND RPDMY}
Silicided OD resistor: {{{RH AND OD} NOT INTERACT RPO} AND RPDMY}
Unsilicided PO resistor: {{RH AND {RPO AND PO}} AND RPDMY}
Silicided PO resistor: {{{RH AND PO} NOT INTERACT RPO} AND RPDMY}
Rule No.
Description
Rule only for unsilicided resistor
RES.W.1
Width of unsilicided OD/PO resistor.
RES.S.1
RH space to Gate in source or drain direction for the unsilicided OD resistor
RES.L.1
Length of unsilicided OD/PO resistor
Square number (length/width) of unsilicided OD/PO resistor.
RES.R.1
(This check doesn’t include the region covered by RHDMY1 (117;4) for non-precision usage)
RES.R.2
RPO intersecting {(PO AND RH) AND RPDMY} must form two or more POs
RES.R.3
RPO intersecting {(OD AND RH) AND RPDMY} must form two or more ODs
Recommended to use rectangle shape resistor for the SPICE simulation accuracy.
RES.R.15g
DRC can flag {((RH AND OD) AND RPO) AND RPDMY} or {((RH AND PO) AND RPO) AND RPDMY}
which is not a rectangle.
{RPDMY AND {{OD INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{OD
RES.R.16g
INTERACT CO} AND RPO}}, except BJTDMY.
{RPDMY AND {{PO INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{PO
RES.R.17g
INTERACT CO} AND RPO}}
Rule only for silicided resistor
RES.R.18g
Recommend: RPDMY intersecting {(OD AND RH) NOT INTERACT RPO} forms two or more ODs.
RES.R.19g
Recommend: RPDMY intersecting {(PO AND RH) NOT INTERACT RPO} forms two or more POs.
RES.R.20g
{CO BUTTED ((RPDMY AND RH) NOT INTERACT RPO)} is recommended.
Common rule for unsilicided/silicided resistors
RES.S.2
RH space to GATE (overlap is not allowed)
RES.EN.1
RH enclosure of unsilicided/silicided OD/PO resistor
For unsilicided/silicided PO resistor
RES.R.4
{RPDMY AND PO} must be fully covered by RH
For unsilicided/silicided OD resistor
RES.R.5
{RPDMY AND OD} must be fully covered by RH
NP OD resistor is not allowed interacting with NW.
RES.R.21
DRC will flag {(((OD AND NP) AND RH) AND RPDMY) INTERACT NW}
PP OD resistor is only allowed inside NW.
RES.R.22
DRC will flag {(((OD AND PP) AND RH) AND RPDMY) NOT INSIDE NW}
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
Op.
Rule
A
C
B



0.4
0.16
0.4

1


0.08
0.19
D
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RH
D o g - b o n e a t th e e n d o f O D / p o ly
r e s is to r fo r c o n ta c t p ic k u p is N O T
RPO
re c o m m e n d e d !!
RPDM Y
D
O D or PO
C
PO
OD
* P + O D /P o ly r e s is to r w ith R P O ( U n s ilic id e d )
RPO
PP and R H
* P + O D /P o ly r e s is to r w ith o u t R P O ( S ilic id e d )
PP and R H
0 .2 2
D
D
RPDM Y
RPDM Y
O D or PO
D
O D or PO
D
A
W id th
0 .2 2
B
L e n g th
> = 0 .1 4
U n - r e la te d
> = 0 .3
im p la n ta tio n
(N P .S .7 )
U n - r e la te d R P O
(R P O .S .2 /R P O .S .5 )
* N + O D /P o ly r e s is to r w ith R P O ( U n s ilic id e d )
RPO
N P and R H
* N + O D /P o ly r e s is to r w ith o u t R P O ( S ilic id e d )
N P and R H
0 .2 2
D
D
RPDM Y
RPDM Y
O D or PO
O D or PO
D
D
W id th
A
0 .2 2
L e n g th
B
> = 0 .1 4
U n - r e la te d
im p la n ta tio n
> = 0 .3
(P P .S .7 )
U n - r e la te d R P O
(R P O .S .2 /R P O .S .5 )
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
HVMOS_25 Layout Rules
The present design rules are dedicated for 5V HVMOS which is fabricated with 2.5V IO Gox. Please be
reminded that these rules are only for N45LP/N40LP/N40LP+, and can not be used for N40G and N45/40LPG
process.
4.5.24.1
HVD_N Layout Rules for HVMOS_25
HVD_N (91;1) is used to define HVNMOS drain side where sustains high voltage.
Label
Op.
Rule
HVD_N25.W.1
Rule No.
Width
A

0.47
HVD_N25.W.2
Channel width of {Gate INTERACT HVD_N} for SPICE accuracy.
≤ 1.110um are non-shrinkable. The exact shrinkable dimension is 1.115um for N40.
N

1.00
HVD_N25.S.1
Space
B

0.47
HVD_N25.S.2
Space of two HVD_N with different potentials
C

1.37
HVD_N25.S.3
Space to NW
D

1.6
HVD_N25.S.4
Space to PW STRAP (overlap is not allowed)
E

0.3
HVD_N25.S.5
Space to N+ ACTIVE
F

0.6
HVD_N25.S.6
Space to DNW (overlap is not allowed)
G

3.0
Q0

0.52
R
=
1.26
S
=
0.22
T

2.00
W

0.54
X

0.60
U

2.00
HVD_N25.S.7
HVD_N25.S.8
HVD_N25.S.9
HVD_N25.S.10
HVD_N25.S.11
HVD_N25.S.12
HVD_N25.EN.1
Description
{CO INSIDE PO} space to {OD AND HVD_N} in PO end-cap direction.
{CO INSIDE PO} can’t overlap HVD_N.
Gate space in drain direction for a multi-finger HVNMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_N}} INSIDE HVD_N} in one OD.
Gate space in source direction for a multi-finger HVNMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_N}} OUTSIDE HVD_N} in one OD.
{Gate INTERACT HVD_N} space to {NW OR NT_N}.
{Gate INTERACT HVD_N} can’t overlap {NW OR NT_N}.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_25} [INSIDE HVD_N].
0.54 is non-shrinkable. The exact shrinkable dimension is 0.6 for N40.
{PO OR OD} space to {OD INTERACT HVD_N} in PO end-cap direction for high Rs concern
{Gate INTERACT HVD_N} enclosure by OD2.
{Gate INTERACT HVD_N} must be inside OD2.
HVD_N25.EX.1
Extension on N+ ACTIVE (Drain side must be fully inside HVD_N)
I

0.24
HVD_N25.O.1
Overlap of {I/O NMOS GATE}.
0.3 is non-shrinkable. The exact shrinkable dimension is 0.33 for N40.
J
=
0.30
HVD_N25.L.1
Channel length of {GATE INTERACT HVD_N}.
0.8~0.875 are non-shrinkable. The exact shrinkable dimension is 0.88um for N40.
M

0.8
HVD_N25.A.1
Area
K

0.64
HVD_N25.A.2
Enclosed area
L

0.64
HVD_N25.R.1
HVD_N25.R.2
HVD_N25.R.3
HVD_N25.R.4
Overlap of NW is not allowed.
HVD_N edge landing on OD without landing on GATE is not allowed.
HVD_N must be fully inside OD_25.
{(OD NOT PO) INSIDE one HVD_N} must be the same potential
For better Idsat uniformity with single finger gate, HVD_N is recommended to be located at the same side of
the gate.
{{OD OR PO} INTERACT HVD_N} overlap of VAR, NT_N, TCDDMY, {OD AND NWDMY}, SRM, ROM,
BJTDMY, RH, or POFUSE is not allowed.
HVD_N25.R.5® U
HVD_N25.R.7
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whole or in part without prior written permission of TSMC.
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HVD_N for HVMOS_25
NW
PW
D
H VD _N
E
PO
I
OD2
PO
J
OD
OD
I
OD
M
PO
I
DNW
G
F
B ,C
OD
F
K
L
A
L
H VD _N
H VD _N
OD2
H VD _N
A
H VD _N
H VD _N
OD2
PO
PO
H VD _N
Q0
OD
U
PO
PO
H VD _N
PO
HVD_N
H VD _N
OD
U
N
PO
R
R
N
U
T
T
X
S
S o u rc e
D r a in
S o u rc e
W
S
D r a in
X
U
X
{N W O R N T _ N }
OD
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PO
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HVD_N
PO
H V D _ N 2 5 .R .4
OD
m u s t b e th e s a m e p o te n tia l
H V D _ N 2 5 .R .4
m u s t b e th e s a m e p o te n tia l
OD
PO
OD
PO
PO
OD
HVD_N
PO
OD
H V D _ N 2 5 .E X .1
H V D _ N 2 5 .R .5 ®
U
Recom m ended
Not Recom m ended
HVD_
HVD_
PO
PO
N
OD
N
OD
HVD_
HVD_
N
N
PO
OD
OD
Not Recom m ended
Recom m ended
HVD_
HVD_
HVD_
N
N
N
OD
PO
PO
OD
PO
OD
PO
OD
PO
HVD_
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whole or in part without prior written permission of TSMC.
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HVD_P Layout Rules for HVMOS_25
HVD_P (91;2) is used to define HVPMOS drain side where sustains high voltage.
Rule No.
Description
Label Op.
Rule
HVD_P25.W.1
Width
A

0.47
HVD_P25.W.2
Channel width of {Gate INTERACT HVD_P} for SPICE accuracy.
≤ 1.110um are non-shrinkable. The exact shrinkable dimension is 1.115um for N40.
N

1.00
HVD_P25.S.1
Space
B

0.47
HVD_P25.S.2
Space of two HVD_P with different potentials
C

1.2
HVD_P25.S.4
Space to NW STRAP (overlap is not allowed)
E

0.24
HVD_P25.S.5
HVD_P25.S.6
Space to P+ ACTIVE
{NW INTERACT HVD_P} space to NW with different potentials.
{CO INSIDE PO} space to {OD AND HVD_P} in PO end-cap direction.
F
G


0.48
2.00
Q0

0.52
Q1

0.05
R
=
1.26
S
=
0.22
HVD_P25.S.7
HVD_P25.S.8
HVD_P25.S.9
HVD_P25.S.10
{CO INSIDE PO} can’t overlap HVD_P.
{CO INSIDE PO} space to HVD_P in S/D direction.
{CO INSIDE PO} can’t overlap HVD_P.
Gate space in drain direction for a multi-finger HVPMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_P}} INSIDE HVD_P} in one OD.
Gate space in source direction for a multi-finger HVPMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_P}} OUTSIDE HVD_P} in one OD.
HVD_P25.S.11
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_25} [INSIDE HVD_P].
0.54 is non-shrinkable. The exact shrinkable dimension is 0.6 for N40.
W

0.54
HVD_P25.S.12
{PO OR OD} space to {OD INTERACT HVD_P} in PO end-cap direction for high Rs concern
Extension on P+ ACTIVE (Drian side must be fully inside HVD_P)
X

0.60
HVD_P25.EX.1
I

0.24
HVD_P25.EN.1
Enclosure by NW
D

0.6
HVD_P25.EN.2
Enclosure by DNW

0.6
{Gate INTERACT HVD_P} enclosure by NW.
{Gate INTERACT HVD_P} must be inside NW.
{Gate INTERACT HVD_P} enclosure by OD2.
{Gate INTERACT HVD_P} must be inside OD2.
Overlap of {I/O PMOS GATE}
0.25 is non-shrinkable. The exact shrinkable dimension is 0.28 for N40.
T

2.00
U

2.00
J
=
0.25
HVD_P25.L.1
Channel length of {GATE INTERACT HVD_P}
0.6~0.655 are non-shrinkable. The exact shrinkable dimension is 0.66um for N40.
M

0.6
HVD_P25.A.1
Area
K

0.64
HVD_P25.A.2
Enclosed area
L

0.64
HVD_P25.R.1
HVD_P25.R.2
HVD_P25.R.3
HVD_P25.R.4
HVD_P must be inside NW
HVD_P edge landing on OD without landing on GATE is not allowed.
HVD_P must be fully inside OD_25.
{(OD NOT PO) INSIDE the same HVD_P} must be the same potential
For better Idsat uniformity with single gate, HVD_P is recommended to be located at the same side of the
gate.
HVD_P must be inside DNW
Only HV PMOS is allowed in {NW INTERACT HVD_P}.
DRC flags: {(Gate INSIDE (NW INTERACT HVD_P)) NOT INTERACT HVD_P}.
{{OD OR PO} INTERACT HVD_P} overlap of VAR, NT_N, TCDDMY, {OD AND NWDMY}, {NP INTERACT
NWDMY}, SRM, ROM, BJTDMY, RH, or POFUSE is not allowed.
HVD_P25.EN.3
HVD_P25.EN.4
HVD_P25.O.1
HVD_P25.R.5® U
HVD_P25.R.6
HVD_P25.R.8
HVD_P25.R.9
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whole or in part without prior written permission of TSMC.
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HVD_P for HVMOS_25
NW
OD
OD2
PO
NW
T
Q 0 H VD_P
PO
PO
PO
PO
X
G
Q1
OD
OD2
PO
U
N
H VD_P
H VD_P
H VD_P
OD
T
W
U
R
N
U
S
D r a in
X
S o u rc e
D r a in
S o u rc e
T
H V D _ P 2 5 .R .8
R
S
U
OD2
T
PO
X
PO
OD
G
OD
G
NW
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whole or in part without prior written permission of TSMC.
PO
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HVD_P
PO
H V D _ P 2 5 .R .4
OD
m u s t b e th e s a m e p o te n tia l
H V D _ P 2 5 .R .4
m u s t b e th e s a m e p o te n tia l
OD
PO
OD
PO
PO
OD
HVD_P
PO
OD
H V D _ P 2 5 .E X .1
H V D _ P 2 5 .R .5 ®
U
Recom m ended
Not Recom m ended
HVD_
HVD_
PO
PO
P
OD
P
OD
HVD_
HVD_
P
P
PO
OD
OD
Not Recom m ended
Recom m ended
HVD_
HVD_
HVD_
P
P
P
OD
PO
PO
OD
PO
OD
OD
PO
PO
HVD_
P
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whole or in part without prior written permission of TSMC.
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4.5.25
Confidential – Do Not Copy
Document No.
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: 2.6
HVMOS_18 Layout Rules
The present design rules are dedicated for 5V HVMOS_18, which is fabricated with 1.8V IO Gox. HVMOS_18
is only offered for N40LP. None of N45LP, N40LP+, N40G, and N45/N40LPG processes can use HVMOS_18.
4.5.25.1
HVD_N Layout Rules for HVMOS_18
HVD_N (91;1) is used to define HVNMOS drain side where sustains high voltage.
Rule No.
Description
Label
Op.
Rule
HVD_N18.W.1
Width
A

0.47
HVD_N18.W.2
Channel width of {Gate INTERACT HVD_N} for SPICE accuracy.
N

0.67
HVD_N18.S.1
Space
B

0.47
HVD_N18.S.2
Space of two HVD_N with different potentials
C

1.37
HVD_N18.S.3
Space to NW
D

1.6
HVD_N18.S.4
Space to PW STRAP (overlap is not allowed)
E

0.3
HVD_N18.S.5
Space to N+ ACTIVE
F

0.6
HVD_N18.S.6
G

3.0
Q0

0.52
R
=
1.26
S
=
0.22
T

2.00
W

0.6
X

0.60
U

2.00
HVD_N18.EX.1
HVD_N18.O.1
HVD_N18.L.1
Space to DNW (overlap is not allowed)
{CO INSIDE PO} space to {OD AND HVD_N} in PO end-cap direction.
{CO INSIDE PO} can’t overlap HVD_N.
Gate space in drain direction for a multi-finger HVNMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_N}} INSIDE HVD_N} in
one OD.
Gate space in source direction for a multi-finger HVNMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_N}} OUTSIDE HVD_N}
in one OD.
{Gate INTERACT HVD_N} space to {NW OR NT_N}.
{Gate INTERACT HVD_N} can’t overlap {NW OR NT_N}.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_18}
[INSIDE HVD_N].
{PO OR OD} space to {OD INTERACT HVD_N} in PO end-cap direction
for high Rs concern
{Gate INTERACT HVD_N} enclosure by OD2.
{Gate INTERACT HVD_N} must be inside OD2.
Extension on N+ ACTIVE (Drain side must be fully inside HVD_N)
Overlap of {I/O NMOS GATE}.
Channel length of {GATE INTERACT HVD_N}.
I
J
M

=

0.24
0.33
0.88
HVD_N18.A.1
Area
K

0.64
HVD_N18.A.2
HVD_N18.R.1
HVD_N18.R.2
HVD_N18.R.3
HVD_N18.R.4
Enclosed area
Overlap of NW is not allowed.
HVD_N edge landing on OD without landing on GATE is not allowed.
HVD_N must be fully inside OD_18.
{(OD NOT PO) INSIDE one HVD_N} must be the same potential
For better Idsat uniformity with single finger gate, HVD_N is
recommended to be located at the same side of the gate.
{{OD OR PO} INTERACT HVD_N} overlap of VAR, NT_N, TCDDMY,
{OD AND NWDMY}, SRM, ROM, BJTDMY, RH, or POFUSE is not
allowed.
L

0.64
HVD_N18.S.7
HVD_N18.S.8
HVD_N18.S.9
HVD_N18.S.10
HVD_N18.S.11
HVD_N18.S.12
HVD_N18.EN.1
HVD_N18.R.5® U
HVD_N18.R.7
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whole or in part without prior written permission of TSMC.
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HVD_N for HVMOS_18
NW
PW
D
H VD _N
E
PO
OD2
I
PO
J
OD
OD
I
OD
M
PO
I
DNW
G
F
B ,C
OD
F
K
L
A
L
H VD _N
H VD _N
OD2
H VD _N
A
H VD _N
H VD _N
OD2
PO
PO
H VD _N
Q0
OD
U
PO
PO
H VD _N
PO
HVD_N
H VD _N
OD
U
N
PO
R
R
N
U
T
T
X
S
S o u rc e
D r a in
S o u rc e
W
S
D r a in
X
U
X
{N W O R N T _ N }
OD
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PO
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HVD_N
PO
H V D _ N 1 8 .R .4
OD
m u s t b e th e s a m e p o te n tia l
H V D _ N 1 8 .R .4
m u s t b e th e s a m e p o te n tia l
OD
PO
OD
PO
PO
OD
HVD_N
PO
OD
H V D _ N 1 8 .E X .1
H V D _ N 1 8 .R .5 ®
U
Recom m ended
Not Recom m ended
HVD_
HVD_
PO
PO
N
OD
N
OD
HVD_
HVD_
N
OD
N
PO
OD
Not Recom m ended
Recom m ended
HVD_
N
OD
PO
HVD_
HVD_
N
N
OD
OD
OD
PO
PO
PO
PO
HVD_
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whole or in part without prior written permission of TSMC.
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4.5.25.2
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Document No.
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: 2.6
HVD_P Layout Rules for HVMOS_18
HVD_P (91;2) is used to define HVPMOS drain side where sustains high voltage.
Rule No.
Description
Label Op.
Rule
HVD_P18.W.1
Width
A

0.47
HVD_P18.W.2
Channel width of {Gate INTERACT HVD_P} for SPICE accuracy.
N

0.67
HVD_P18.S.1
Space
B

0.47
HVD_P18.S.2
Space of two HVD_P with different potentials
C

1.2
HVD_P18.S.4
Space to NW STRAP (overlap is not allowed)
E

0.24
HVD_P18.S.5
Space to P+ ACTIVE
F

0.48
HVD_P18.S.6
G

2.0
Q0

0.52
Q1

0.05
R
=
1.82
S
=
0.22
W

0.88
X

0.60
HVD_P18.EX.1
{NW INTERACT HVD_P} space to NW with different potentials.
{CO INSIDE PO} space to {OD AND HVD_P} in PO end-cap direction.
{CO INSIDE PO} can’t overlap HVD_P.
{CO INSIDE PO} space to HVD_P in S/D direction.
{CO INSIDE PO} can’t overlap HVD_P.
Gate space in drain direction for a multi-finger HVPMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_P}} INSIDE HVD_P} in one
OD.
Gate space in source direction for a multi-finger HVPMOS device.
DRC checks: {{Space of {Gate INTERACT HVD_P}} OUTSIDE HVD_P} in one
OD.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_18} [INSIDE
HVD_P].
{PO OR OD} space to {OD INTERACT HVD_P} in PO end-cap direction for
high Rs concern
Extension on P+ ACTIVE (Drian side must be fully inside HVD_P)
I

0.24
HVD_P18.EN.1
Enclosure by NW
D

0.6
HVD_P18.EN.2

0.6
T

2.00
U

2.00
HVD_P18.O.1
HVD_P18.L.1
Enclosure by DNW
{Gate INTERACT HVD_P} enclosure by NW.
{Gate INTERACT HVD_P} must be inside NW.
{Gate INTERACT HVD_P} enclosure by OD2.
{Gate INTERACT HVD_P} must be inside OD2.
Overlap of {I/O PMOS GATE}
Channel length of {GATE INTERACT HVD_P}
J
M
=

0.28
0.66
HVD_P18.A.1
Area
K

0.64
HVD_P18.A.2
HVD_P18.R.1
HVD_P18.R.2
HVD_P18.R.3
HVD_P18.R.4
Enclosed area
HVD_P must be inside NW
HVD_P edge landing on OD without landing on GATE is not allowed.
HVD_P must be fully inside OD_18.
{(OD NOT PO) INSIDE the same HVD_P} must be the same potential
For better Idsat uniformity with single gate, HVD_P is recommended to be
located at the same side of the gate.
HVD_P must be inside DNW
Only HV PMOS is allowed in {NW INTERACT HVD_P}.
DRC flags: {(Gate INSIDE (NW INTERACT HVD_P)) NOT INTERACT
HVD_P}.
{{OD OR PO} INTERACT HVD_P} overlap of VAR, NT_N, TCDDMY, {OD
AND NWDMY}, {NP INTERACT NWDMY}, SRM, ROM, BJTDMY, RH, or
POFUSE is not allowed.
L

0.64
HVD_P18.S.7
HVD_P18.S.8
HVD_P18.S.9
HVD_P18.S.10
HVD_P18.S.11
HVD_P18.S.12
HVD_P18.EN.3
HVD_P18.EN.4
HVD_P18.R.5® U
HVD_P18.R.6
HVD_P18.R.8
HVD_P18.R.9
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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HVD_P for HVMOS_18
PW
NW
W /
N
DNW
D
E
H VD _P
OD2
PO
I
PO
J
OD
I
OD
OD
M
PO
I
F
B ,C
OD
F
K
L
L
A
H VD _P
H VD _P
H VD _P
A
H VD _P
H VD _P
NW
OD2
PO
T
OD
Q 0 H VD _P
Q1
OD
U
NW
OD2
PO
G
PO
HVD_P
N
T
PO
PO
PO
X
HVD_P
H VD_P
OD
W
U
U
R
N
S
D r a in
X
S o u rc e
D r a in
S o u rc e
T
H V D _ P 1 8 .R .8
R
S
U
OD2
T
PO
X
PO
OD
G
OD
NW
PO
G
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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HVD_P
PO
H V D _ P 1 8 .R .4
OD
m u s t b e th e s a m e p o te n tia l
H V D _ P 1 8 .R .4
m u s t b e th e s a m e p o te n tia l
OD
PO
OD
PO
PO
OD
HVD_P
PO
OD
H V D _ P 1 8 .E X .1
H V D _ P 1 8 .R .5 ®
U
Recom m ended
Not Recom m ended
HVD_
HVD_
PO
PO
P
OD
P
OD
HVD_
HVD_
P
P
PO
OD
OD
Not Recom m ended
Recom m ended
HVD_
HVD_
HVD_
P
P
P
OD
PO
PO
OD
OD
OD
PO
PO
PO
HVD_
P
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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HVD_GR.R.2U
HVD_GR.R.3U
: T-N45-CL-DR-001
: 2.6
HVMOS Guard-Ring Rules and Guidelines for
HVMOS_25 and HVMOS_18
Rule No.
HVD_GR.R.1
Document No.
Version
Confidential – Do Not Copy
Description
Label
Op.
Rule
A

30
It is not allowed placing HV NMOS and HV PMOS inside the same guard-ring (Either P+ or N+ OD
guard-ring)
Every HV NMOS must be surrounded by the P+/PW guard-ring as PW strap.
The P+ guard-ring must to be connected to Vss.
Every HV PMOS must be surrounded by the N+/NW guard-ring as NW strap.
The N+ guard-ring must to be connected to Vdd.
HVD_GR.R.4U
Please put Contact (CO) as many as possible in the P+ and N+ guard-rings.
HVD_GR.R.5
Any point inside HV NMOS source/drain {(N+ ACTIVE INTERACT (PO INTERACT HVD_N)) NOT
PO} space to the nearest P+/PW guard-ring (PW STRAP) in the same PW.
Any point inside HV PMOS source/drain {(P+ ACTIVE INTERACT (PO INTERACT HVD_P)) NOT
PO} space to the nearest N+/NW guard-ring (NW STRAP) in the same NW.
HVD_GR.R.6
{{HV N/PMOS OR HVMOS guard-ring} INTERACT RPO} is not allowed.
HVD_GR.R.7® U
Recommend reducing the breach region of M1 on guard-ring if using M1 to connect HV N/PMOS
to outside circuits.
G u a r d -r in g (O D )
G u a r d -r in g (O D )
A
A
A
A
A
A
A
A
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: T-N45-CL-DR-001
: 2.6
MOS Varactor Layout Rules (VAR)
N45LP/N40LP
N40LP+
N40LPG
N45LPG
N40G (= N45GS)
VAR
1.1V
1.8V
2.5V
1.1V
2.5V
0.9V
1.1V
3.3V
0.9V
1.1V
1.8V
0.9V
1.2V
1.8V
2.5V
BB NVAR
model PVAR



X
X










X
X
X
X
X
X
X
X
X
X
X

X


NVAR
RF
model PVAR



X
X
X
X
X
X
X
X

X


*
*
*
X
X
X
X
X
X
X
X

X


*: Only offer in N40LP
NVAR: NMOS in NW
PVAR: PMOS in PW
VAR: Customer must provide this layer (CAD layer: 143) to generate LDD masks by logic operations, if the
MOS varactor is used.
Description
Rule No.
Label
Op.
Rule
VAR.W.1
Channel length of {gate AND VAR}
A

0.2
VAR.W.3
Channel length of {(gate AND OD2) AND VAR}
A

0.4
VAR.W.4
Channel width of {gate AND VAR}
G

0.32
VAR.S.1
Space to ACTIVE
Maximum core unit varactor gate area (um2) (varactor gate area = {((OD AND PO)
AND VAR) NOT OD2}) [for N40G process and LPG G device]
Enclosure of OD (Cut is not allowed)
VAR layer must be drawn to fully cover the varactor devices.
DRC only checks VAR fully cover gate.
Overlap of VTL_N, VTL_P, VTH_N, VTH_P, NT_N, or RPO is not allowed.
PP overlap of {(gate AND NW) AND VAR} is not allowed.
NP overlap of {(gate AND PW) AND VAR} is not allowed.
Overlap to {(PO AND ACTIVE) SIZING 0.16 μm} is not allowed
NP must fully cover {(((VAR AND (GATE AND NW)) SIZING 0.19 μm) AND OD)
SIZING 0.13 μm }
PP must fully cover {(((VAR AND (GATE AND PW)) SIZING 0.19 μm) AND OD)
SIZING 0.13 μm }
B

0.13
H

25
D

0.16
VAR.A.1
VAR.EN.1
VAR.R.1
VAR.R.2
VAR.R.3
VAR.R.3.1
VAR.R.4
VAR.R.5
VAR.R.5.1
Table note:

Due to the intrinsic gate leakage, you need to do SPICE simulation carefully while large area of MOS varactor
is designed in the thin oxide area, and it is recommended to design the varactor in the thick oxide area to
reduce the leakage (AN.R.20mg).
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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N
NV
VA
AR
R
VAR
D
VAR
NP
PO
PO
X
X'
NP
OD
OD
G
A
NW
B
NW
X -X ' c r o s s -s e c tio n
PO
PO
OD
0 .1 6
STI
STI
NP
NP
0 .1 6 M O S
NW
VAR
V A R .R .4
VAR.A.1
H
H
H
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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P
PV
VA
AR
R
VAR
D
VAR
PP
PO
PO
X
X'
PP
OD
OD
G
A
PW
B
PW
X -X ' c r o s s -s e c tio n
PO
PO
STI
OD
0 .1 6
STI
PP
PP
0 .1 6 M O S
PW
VAR
V A R .R .4
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Contact (CO) Layout Rules (Mask ID: 156)
Rule No.
Description
Label
Op.
Rule
CO.W.1
Width (maximum = minimum) (Except butted CO in SRAMDMY;0 (186;0) region only)
A
=
0.06
CO.S.1
Space (Except SRAMDMY;0 (186;0) region)
B

0.08
CO.S.2
Space to 3-neighboring CO (distance < 0.11 μm) (Except SRAMDMY;0 (186;0) region)
C

0.10
CO.S.2.1
Space [different net] (Except SRAMDMY;0 (186;0) region)
B1

0.11
CO.S.3
Space to GATE (Overlap of GATE is not allowed) [space  0.035 μm is allowed inside SRAM word line driver
covered by layer 186;5 or 186;4] (Except SRAMDMY;0 (186;0) region)
D

0.04
CO.S.3®
Recommended space to gate to reduce the short possibility caused by particle.
D

0.05
CO.S.4
{CO inside PO} space to OD (Except SRAMDMY;0 (186;0) region)
E

0.05
CO.S.5
{CO inside OD} space to I/O GATE
F

0.08
CO.S.6
Space to butted PP/NP edge on OD (overlap of NP/PP boundary on OD is not allowed.)
G

0.04
CO.S.7®
Maximum effective CO space in Source/Drain of device [channel width1 μm] (This check doesn't include
the regions covered by SR_ESD and SDI.)
Definition of effective CO: (1) CO projection space to GATE0.22 μm (D2). (2) {COs INSIDE {HVD_N OR
HVD_P}} which projection space to GATE 1 μm.
Definition of maximum effective CO space (B3): Channel width – effective CO projection length to GATE.
Besides, if there is no CO in Source/Drain or no CO connected to Source/Drain by OD, it is allowed. {CO
OUTSIDE {HVD_N OR HVD_P}} projection space to PO (without CO shielding) > 0.22 μm or {COs INSIDE
{HVD_N OR HVD_P}} projection space to PO (without CO shielding) > 1 μm for HVMOS drain side will be
flagged on gate.
B3

0.29
CO.EN.0
Enclosure by PO is defined by either {CO.EN.2 and CO.EN.3} or {CO.EN.5 and CO.EN.6}. (Except
SRAMDMY;0 (186;0) region)
Enclosure by OD is defined by either {CO.EN.1 and CO.EN.1.1}, {CO.EN.1 and CO.EN.1.2}, or {CO.EN.1.3}.
CO.EN.0®
Recommended enclosure by OD is defined by {CO.EN.1® and CO.EN.1.1® }.
CO.EN.1
Enclosure by OD (Except SRAMDMY;0 (186;0) region)
H

0.01
CO.EN.1®
Recommended enclosure by OD to avoid high Rc
H

0.03
CO.EN.1.1
Enclosure by OD, except {STRAP NOT VAR} [at least two opposite sides] (Except Butted CO in SRAMDMY;0
(186;0) region only)
H1

0.03
CO.EN.1.1®
Recommended enclosure by OD [at least two opposite sides]
H1

0.04
CO.EN.1.2
Enclosure by OD for {STRAP NOT VAR} [at least two opposite sides]
H3

0.02
CO.EN.1.3
Enclosure by OD [four sides] , except {STRAP NOT VAR} (Except Butted CO in SRAMDMY;0 (186;0) region
only)
L

0.02
CO.EN.2
Enclosure by PO (Except SRAMDMY;0 (186;0) region)
J

0.01
CO.EN.3
Enclosure by PO [at least two opposite sides] (Except SRAMDMY;0 (186;0) region)
K

0.02
CO.EN.3®
Recommended enclosure by PO [at least two opposite sides] to avoid high Rc.
K

0.04
CO.EN.5
Enclosure by PO [0.005 um at one side and the opposite side is 0.015 um] (Except SRAMDMY;0 (186;0)
region)
J1

0.005
/ 0.015
CO.EN.6
Enclosure by PO [at least two opposite sides] (Except SRAMDMY;0 (186;0) region)
K1

0.03
CO.R.2
Overlap of RPO is not allowed.
CO.R.3
45-degree rotated CO is not allowed.
CO.R.4
CO must be fully covered by M1 and {(OD OR PO) OR SR_DPO}.
CO.S.6g
Recommended to put contacts at both source side and butted well pickup side to avoid high Rs. DRC can flag
if the STRAP is butted on source, one of STRAP and source is without CO.
CO.R.1gU
Recommended to put {CO inside PO} space to GATE as close as possible to avoid unexpected resistance
variation.
CO.R.5g
Recommend using redundant CO to avoid high Rc wherever layout allows
1. Recommended to use double CO or more on the resistor connection.
2. Double CO on Poly gate to reduce the probability of high Rc
3. For large transistor, if it is impossible to increase the CO to gate spacing (CO.S.3® ), limit the number of
source/drain CO: have the number of CO necessary for the current, and then spread them uniformly all
over the Source/Drain area.
4. DRC can flag single CO.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: T-N45-CL-DR-001
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CO
D, F
G
C o n ta c t o n N P /P P b o u n d ry
P+
N o n - s a lic id e C o n ta c t
c o n ta c t o n P o ly
PRO
B
4 5 O C o n ta c t
A
N+
E
P+
P+
G
PO
K
K
J
H
J
H1
L
H1
L
K1
K
L
K1
K
J
A
J
J 1 = 0 .0 1 5
[o r 0 .0 0 5 ]
A
A
B
0 .0 0 5 = J 1
[o r 0 .0 1 5 ]
C
C
C
B
C
B
B
B
C
C
B
2 - n e ig h b o r in g C O
C
C
2 - n e ig h b o r in g C O
2 - n e ig h b o r in g C O s
C
C
A
A
A
C
C
C
C
C
C
3 - n e ig h b o r in g C O
C
3 X 3 C O a rra y
C
4 - n e ig h b o r in g C O
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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B
B 1
B
B 1
C O
s p a c e to n e ig h b o r in g C O
in th e
s a m e n e t o r in th e d iffe r e n t n e t
CO.S.7®
S
S
S
S
G
B3
D
P a r tia l-C O
U n ifo r m -C O
 0.29
B3
S
G
D
D
F u lly -C O
S
G
G
G
G
D
P a r tia l-C O
D
P a r tia l-C O
G
D
D
P a r tia l-C O
> 0.29
11
D2
B3
B3
B3
B3
B3
B3
 0.29
1
> 0.29
 0.29
OD
 0.29
>
0.29
O
PO
O
X
X
OD
OD
PO
PO
DRC won’t flag it.
DRC will flag it.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.29
Rule No.
M1.W.1
M1.W.2
M1.W.3
M1.S.1
M1.S.1®
M1.S.1.1
M1.S.2
M1.S.2.1
M1.S.2.2
M1.S.2.3
M1.S.3
M1.S.5
M1.S.6
M1.S.8
M1.S.8.1
M1.S.8.2
M1.S.9
M1.EN.0
M1.EN.0®
M1.EN.1
M1.EN.1®
M1.EN.2
M1.EN.2®
M1.EN.3
M1.EN.3.1
M1.EN.3.2
M1.EN.4
M1.EN.5
M1.EN.5®
M1.A.1
M1.A.1®
M1.A.2
M1.A.3
M1.DN.0
M1.DN.1
M1.DN.1.1
M1.DN.4
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Metal-1 (M1) Layout Rules (Mask ID: 360)
Description
Width
Width of 45-degree bent M1. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer to
the guideline, G.6gU, in section 3.7))
Maximum width
(This check doesn’t include the SEALRING_ALL (162;2) region)
Space
Recommended space to reduce the short possibility caused by particle
Space [any one of Mx connects to > 3.3V and  5V net]
Space [at least one metal line width > 0.17 μm (W1) and the parallel metal run length > 0.27 μm (L1)] (union
projection)
Space [at least one metal line width > 0.24 μm (W2) and the parallel metal run length > 0.27 μm (L2)] (union
projection)
Space [at least one metal line width > 0.31 μm (W3) and the parallel metal run length > 0.4 μm (L3)] (union
projection)
Space [at least one metal line width > 0.62 μm (W4) and the parallel metal run length > 0.62 μm (L4)] (union
projection)
Space [at least one metal line width > 1.5 μm (W5) and the parallel metal run length > 1.5 μm (L5)] (union
projection)
Space at M1 line-end (W < 0.09 μm, Q = 0.07 μm) in a dense-line-end configuration: If M1 has parallel run
length with opposite M1 (measured with T = 0.025 μm extension) along two adjacent edges of M1 [any one
edge < Q distance from the corner of the two edges], then one of the spaces (S1 or S2) needs to be at least
this value
(This check doesn't include small jog with edge length < 0.07 um(R))
(Except SRAMDMY;0 (186;0) region)
Space to 45-degree bent M1
Space to VIA1 [different net, either VIA1 or M1 connects to 1.8V ~ 3.3V net]
Space to VIA1 [different net, either VIA1 or M1 connects to  1.5V and < 1.8V net]
Space to VIA1 [different net, either VIA1 or M1 connects to > 3.3V and  5V net]
This rule is to check the Metal (A) space with the neighboring VIA1 [either VIA1 or M1 connects to > 3.3V and
 5V net].
The DRC methodology to find Metal (A) is as follows:
Find an edge (B) of the metal line-end [edge length  0.12um]
Run length (C) from edge (B) inside metal  0.13um
Jog length (D)  0.01um within 0.13um run length
Extend 0.06um outside from edge (B) to form a polygon metal (A)
Metal (A) is defined if conditions 1~4 are all satisfied.
Enclosure of CO is defined by either {M1.EN.1 and M1.EN.2} or M1.EN.3 or {M1.EN.3.1 and M1.EN.3.2}.
Recommended enclosure of CO is defined by either M1.EN.1® or M1.EN.2® .
Enclosure of CO (Except Butted CO in SRAMDMY;0 (186;0) and CSRDMY (166;0) regions)
Recommended enclosure of CO to avoid high Rc
Enclosure of CO [at least two opposite sides] (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions)
Recommended enclosure of CO [at least two opposite sides] to avoid high Rc.
Enclosure of CO [four sides] (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions)
Enclosure of CO (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions)
Enclosure of CO [at least two opposite sides] (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions)
Enclosure of CO [M1 width > 0.7 μm] (except CSRDMY (166;0) region)
Enclosure of CO [metal width  0.11μm, space < 0.08 μm and parallel run length > 0.27 μm]
(This check doesn't include two or more COs present in the metal intersection)
Recommended Enclosure of CO [metal width  0.11μm, space < 0.08μm] to avoid high Rc
(This check doesn't include two or more COs present in the metal intersection)
Area (Except SRAMDMY;0 (186;0) region)
Recommended area to avoid high Rc (except DMx_O)
Area [with all of edge length < 0.17 μm].
(This check doesn't include the patterns filling 0.07 μm x 0.17 μm rectangular tile) (Except SRAMDMY;0
(186;0) region)
Enclosed area
For the following M1.DN.1, M1.DN.1.1, M1.DN.4, and DM1.R.1, please refer to the "Dummy Metal Rules"
section in Chapter 8 for the details.
Minimum metal density in window 125 μm x 125 μm, stepping 62.5 μm
Maximum metal density in window 125 μm x 125 μm, stepping 62.5 μm
The metal density difference between any two neighboring checking windows including DMxEXCL [window
200 μm x 200 μm, stepping 200 μm]
Anticipate metal density gradient from layout of small cell by targeting density ~40% (this way, it will limit the
risk of low density and of high gradient)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
A
Op.

Rule
0.07
B

0.17
C

4.50
D
D



0.07
0.09
0.09
E

0.08
E1

0.12
E2

0.14
F

0.21
G

0.50
S1/S2

0.08
H




0.17
0.1
0.08
0.18
S

0.15
I
I
J
J
K
K1
K2
L








0.00
0.03
0.03
0.05
0.02
0.005
0.025
0.03
M

0.015
M

0.015
O
O


0.0215
0.0351
O

0.055
Q1

0.2


10%
85%

50%
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Rule No.
M1.DN.6
M1.DN.6®
DM1.R.1
M1.R.1U
M1.R.2
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Metal density  1%must be followed for items (A) to (C).
(A) Metal density [window 80 μm x 80 μm, stepping 40 μm]  1%
(B) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
1%] ≤ 6400um2, except the merged low density windows width ≤ 30um.
(C) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
1%] ≤ 18000um2.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  40um for (A) and
 5um for both (B)/(C).
Recommend metal density  1% for IP level. Items (A) to (C) are recommended.
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm]  1%. This item is applied
for {IP NOT (IP SIZING -40um)} region when the width of IP is  40um.
(B) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
stepping 5um, density < 1%] ≤ 1600um2, except the merged low density windows width ≤ 30um. This item is
applied for {IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
(C) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
stepping 5um, density < 1%] ≤ 4500um2. This item is applied for {IP NOT (IP SIZING -10um)} region when the
width of IP is  10um.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  20um for (A) and
 5um for both (B)/(C).
DM1 is a must. The DM1 CAD layer must be different from the M1 CAD layer.
M1 line-end must be rectangular. Other shapes are not allowed.
Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
Label
Op.
Rule
Table Notes:

Although tsmc provides 5V metal and Via related rules, tsmc does not offer any 5V device for FEOL,
except HVMOS (only drain side can be applied to 5V).

To improve the metal CMP process window, you must fill the DM1 globally and uniformly even if the originally
drawn M1 has already met the density rules (M1.DN.1 and M1.DN.1.1). For sensitive areas with auto-fill operations
blocked by the DM1EXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a
better process window and electrical performance.

During IP/macro design, it is important to put certain density margin to avoid the possibility of high density
violations (M1.DN.1, M1.DN.1.1) during placement. It may have unexpected violation during the IP/macro
placement due to the environment, even if the IP/macro already pass the high density rule check. Therefore, you
need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus), under the proper
high density limit.

M1.DN.6®: For IP level, recommend metal density ≥ 1% to reduce M1.DN.6 DRC violation in chip level.

M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9.
o Make sure to add correct marker layers to let DRC check the high voltage rules correctly.
 Data-types 200 to 218 of each metal layer are reserved for the nets of voltage ranging from 0V to 1.8V in
0.1V step. Data-types 219, 220, and 221 are assigned for I/O voltage 2.5V, 3.3V, and 5V, respectively.
 The net voltage is defined by the corresponding marker layers. The net voltage cannot be recognized by
incorrect marker layers. That means, if a marker layer (33;218) is on M3, then this net will be recognized as
an 1.8V net, but it cannot be recognized if a marker layer (32;218) is on M3.
 Higher voltage marker layers have higher priority, e.g. the M3 net will be recognized as an 1.8V net if there
are two marker layers as (33;215) and (33;218) on it.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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o The DRC methodology for the high voltage check:
 Marker layers have higher priority than MOS connection.
 The M3 net will be recognized as an 1.8V net if there is (33;218), even if this net does not connect to a
MOS inside OD2.
 The M3 net will be recognized as a low-voltage net (
1.2V) if there is a marker layer of
(33;200~212), even if this net connects to a MOS inside OD2.
 The M3 net will be recognized as an 1.8V net if there is (33;218) and this net connects to a MOS inside
OD2 and a core MOS simultaneously.
 M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9 will be checked for the nets with voltage > 1.2V
defined by marker layers. Nets with voltage  1.2V will be excluded.
 If a net without any marker layers,
 M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9 will be checked when the net connects only to a MOS
inside OD2.
 If a net connects to an IO MOS & a core MOS simultaneously,
o
If the DRC option of Mx_S_8_IO_NET is off (default), it will be recognized as low voltage and will
not check M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9.
o
If the DRC option of Mx_S_8_IO_NET is on (not default), it will be recognized as a high voltage net
and will check M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9.
 The following summary tables list the high/low voltage net recognition results for the different combinations
of high voltage marker layers and the DRC option:
Mx net connection if Mx_S_8_IO_NET is OFF
Core MOS IO MOS Metal high voltage markers (Data-types 213~221)
Y
Y
Y
Y
N
Y
N
Y
Y
N
Y
N
Y
Y
N
Y
N
N
Mx net connection if Mx_S_8_IO_NET is ON
Core MOS IO MOS Metal high voltage markers (Data-types 213~221)
Y
Y
Y
Y
N
Y
N
Y
Y
N
Y
N
Y
Y
N
Y
N
N
Voltage net recognition
High voltage
Low voltage
Voltage net recognition
High voltage
Low voltage
 The net without any marker layers will be recognized as a VSS net if there is PW STRAP connected, even
if the PW STRAP is inside OD2. But PW STRAP inside DNW (RW STRAP) will be excluded.
{PW NOT RW} w/o marker
Core
IO
VSS
RW w/o marker
Low voltage
High voltage
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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o For the IP design:
DRC uses the connections of IO MOS devices in OD2 to identify high voltage nets if these nets do not have the
high voltage marker layers. If your high voltage net is not connected to an IO MOS, you have to mark the proper
marker layer manually.
o For the P&R stage:
(1) During P&R, you have to follow the high voltage metal space rules for the high voltage nets.
(2) After P&R, you have to manually define the specific marker layers for the high voltage nets before GDS
stream out.
(3) You have to use the highest-voltage marker layer for the net with a range of voltages.
M3
1 .8 V
N et
V IA 2
M2
1 .8 V
N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3
1 .5 V
N et
V IA 2
M2
1 .5 V
N et
C h e c k M 2 .S .8 .1
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
M3
1 .0 V
N et
V IA 2
M2
1 .0 V
N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 3 1 .0 V M a r k e r L a y e r (3 3 ;2 1 0 )
# T h e N e t v o lta g e is d e fin e d b y c o r r e s p o n d in g m a r k e r la y e r s
M 3 1 .8 V
N et
V IA 2
M 2 1 .8 V
N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M 3 1 .8 V
N et
V IA 2
M 2 1 .8 V
N et
C h e c k M 2 .S .8
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
#
H ig h v o lta g e m a r k e r la y e r h a s h ig h e r p r io r ity
M3
?V
N et
V IA 2
M2
?V
N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 2 1 .8 V M a r k e r L a y e r (3 2 ;2 1 8 )
# O n ly r e la tiv e m a r k e r la y e r c a n b e u s e d to d e fin e th e N e t v o lta g e
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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1 .8 V
N et
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V IA 2
M2
1 .8 V
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: T-N45-CL-DR-001
: 2.6
N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3
1 .8 V
N et
V IA 2
M2
1 .8 V
N et
C h e c k M 2 .S .8
M 2 1 .0 V M a r k e r L a y e r (3 2 ;2 1 0 )
M3
1 .0 V
N et
V IA 2
M2
1 .0 V
N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
# M a r k e r la y e r c o u ld b e u s e d d e fin e th e v o lta g e fo r s e v e r a l N e ts .
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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D A
E /E 1 /E 2 /F /G
M 1
M 1
H
N
A /C
D
> L 1 ,L 2 ,L 3 ,L 4 ,L 5
B
B
H
H
> W 1 ,W 2 ,W 3 ,W 4 ,W 5
D
M 1 .E N .1 / M 1 .E N .2 / M 1 .E N .3 / M 1 .E N .4
I
I
I
I
J
J
I
J
M 1
K, L
K ,L
J
M 1
K ,L
J
J
M 1
M 1
M 1
M 1 .S .5
S1
S1
S1
D
S1
S1
D
R
< Q
S2
T
S2
S2
S2
R e g io n 1 o r 2 c a n n o t h a v e o th e r M 1 p a tte r n s a t
T
th e s a m e tim e . O n e o f th e m w ith o th e r M 1
p a tte r n s is a llo w e d .
S1
T
R e g io n 1
Q = 0 .0 7
R e g io n 2
W < 0 .0 9
T
T
T
M 1 .E N .5
S2
Q = 0 .0 7
S1
W < 0 .0 9
S2
M 1 .A .1 / M 1 .A .2 / M 1 .A .3
M 1 .R .1
> 0 .2 7
Q1
M
Q1
O
O
> = 0 .1 1
M 1
M 1
M 1
< 0 .0 8
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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M 1 .E N .5
M1.S.9
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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VIAx Layout Rules (Mask ID: 378, 379, 373, 374,
375, 376, 377)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
VIAx.W.1
VIAx.S.1
VIAx.S.1.1
VIAx.S.2
VIAx.S.3
VIAx.S.3.1
VIAx.EN.0
VIAx.EN.0®
VIAx.EN.1
VIAx.EN.1®
VIAx.EN.2
VIAx.EN.2®
VIAx.EN.3.1
VIAx.EN.4
VIAx.EN.4.1
VIAx.R.1
VIAx.R.2
VIAx.R.3
VIAx.R.4
VIAx.R.5
VIAx.R.6
VIAx.R.7
VIAx.R.8®
VIAx.R.11
VIAx.R.12
VIAx.R.13
VIAx.R.13.1
VIAx.R.13.2
DVIAx.R.3
VIAx.R.9gU
Description
Label
Width (maximum = minimum) (Except SEALRING_ALL (162;2) and {VIAx bar INSIDE {LOWMEDN NOT
A
(LOWMEDN SIZING -4 µm)}} region)
Space
B
Space [any one of VIAx connects to > 3.3V and  5V different net]
Space to 3-neighboring VIAx (distance < 0.098 μm)
C
Space to neighboring VIAx [different net]
B1
Space to neighboring VIAx [different net and common parallel run length > 0 μm]
B2
Enclosure by Mx or M1 is defined by either {VIAx.EN.1 and VIAx.EN.2} or {VIAx.EN.4 and VIAx.EN.4.1}
Recommended enclosure by Mx or M1 is defined by either VIAx.EN.1® or VIAx.EN.2® .
Enclosure by Mx or M1
D
Recommended enclosure by Mx or M1 to avoid high Rc.
D
Enclosure by Mx or M1 [at least two opposite sides]
E
Recommended enclosure by Mx or M1 [at least two opposite sides] to avoid high Rc.
E
VIA1 Enclosure by M1 [metal width  0.11 μm, space < 0.08 μm and parallel run length > 0.27 μm] (This
F
check doesn't include two or more via1 present in the metal intersection)
Enclosure by Mx or M1
D
Enclosure by Mx or M1 [at least two opposite sides]
E
45-degree rotated VIAx is not allowed.
At least two VIAx with space  0.14 μm (S1), or at least four VIAx with space
 0.63 μm (S1’) are required to connect Mx and Mx+1 when one of these two metals has width and length >
0.21 μm (W1). (Except VIA bar region and VIA1.R.2 except SRAMDMY;0 (186;0) region)
At least four VIAx with space  0.14 μm (S2), or at least nine VIAx with space  0.83 μm (S2’) are required to
connect Mx and Mx+1 when one of these two metals has width and length > 0.55 μm (W2). (Except VIA bar
region)
At least two VIAx must be used for a connection that distance  1.14 μm (D) away from a metal plate (either
Mx or Mx+1) with length > 0.21 μm (L) and width > 0.21 μm (W). (Except VIA bar region and VIA1.R.4 except
SRAMDMY;0 (186;0) region)
At least two VIAx must be used for a connection that distance  2.8 μm (D) away from a metal plate (either
Mx or Mx+1) with length > 1.4 μm (L) and width > 1.4 μm (W). (Except VIA bar region)
At least two VIAx must be used for a connection that distance  7.1 μm (D) away from a metal plate (either
Mx or Mx+1) with length > 7 μm (L) and width > 2.1 μm (W). (Except VIA bar region)
VIAx must be fully covered by Mx and Mx+1.
Recommended maximum consecutive stacked VIAx layer, which has only one via for each VIAx layer to
avoid
high
Rc.
(Except
{LOWMEDN
NOT
(LOWMEDN
SIZING
-4
um)})
(Example: VIA1~VIA4, VIA2~VIA5, VIA3~VIA6, VIA4~VIA7. This rule does not apply to top via. It is allowed to
stack from VIA4 to VIA9 because VIA8 and VIA9 are top via. It is allowed to stack more than four VIAx layers
if two or more vias in each VIAx layer are on the same metal.)
Single VIAx is not allowed in “H-shape" Mx+1 when all of the following conditions come into existence:
(1) The Mx+1 has “H-shape" interact with two metal holes: both two metal hole length  5 μm (L2) and two
metal hole area  5 μm2
(2) The VIAx overlaps on the center metal bar of this “H-shape” Mx+1
(3) The center metal bar length  1 μm (L) and the metal bar width  0.21 μm.
VIAx connected to DMx, DMx_O, DMx+1, DMx+1_O is not allowed.
Maximum area ratio of M1/Mx to upper VIAx in the same net [connects to gate with area > 19200um2, and
does not connect to OD].
This rule is checked by the ANTENNA DRC command file.
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAx in the same net (Except the protection
OD area  0.25 µm2)
This rule is checked by the DRC command files in ANTENNA_DRC directory.
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAx in the same net (Except the protection OD
area  0.25 µm2)
Op.
Rule
=
0.07





0.07
0.2
0.09
0.095
0.11




0.00
0.03
0.03
0.05

0.015


0.01
0.02

4

350000

300000

2000000
This rule is checked by the DRC command files in ANTENNA_DRC directory.
DVIAx is a must for Flip Chip.
To comply tsmc dummy utility, DRC will flag as violation when the area ratio of (DVIAx to DMx) & (DVIAx to
DMx+1) are < 1% at the same time.
Recommend using redundant vias to avoid high Rc wherever layout allows. (Except {LOWMEDN NOT
(LOWMEDN SIZING -4 um)}) Please refer to section “Via Layout Recommendations”
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Table Notes:

Although tsmc provides 5V metal and Via related rules, tsmc does not offer any 5V device for FEOL,
except HVMOS (only drain side can be applied to 5V).
E
D
A
A
A
B
B
B
B
B
B
2 - n e ig h b o r in g V ia
2 - n e ig h b o r in g V ia
2 - n e ig h b o r in g V ia
A
A
C
C
E
C
A
C
3 - n e ig h b o r in g V ia
M 2~7
B
C
C
3 X 3 V ia a r r a y
A
D
C
M 1
E
C
E
A
E
B
C
C
C
C
C
E
B
E
E
C
A
E
C
C
C
4 - n e ig h b o r in g V ia
E
D
C
D
M x /M x + 1
V IA x .E N .3 .1
M 1
B
V IA 1
> 0 .2 7
B1
F
B
B2
> = 0 .1 1
M x /M x + 1
V ia s p a c e to n e ig h b o r in g v ia in th e
< 0 .0 8
s a m e n e t o r in th e d iffe r e n t n e t
From the EM spec, at least two vias are needed. It is strongly suggested
to use  two vias in each VIAx layer for stacked via structures.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Illustration of VIAx.R.8®
M 10
M 10
M 10
M 10
M 10
M 10
M 10
V9
V9
V9
V9
V9
V9
V9
M 9
M 9
M 9
M 9
M 9
M 9
M 9
V8
V8
V8
V8
V8
V8
V8
M 8
M 8
M 8
M 8
M 8
M 8
M 8
V7
V7
V7
M 7
M 7
M 7
V6
V6
M 6
M 6
M 6
V5
V5
V5
M 5
M 5
M 5
V4
V4
V4
M 4
M 4
M 4
V3
V3
V3
M 3
M 3
M 3
V2
V2
V2
M 2
M 2
M 2
M 1
V1
V1
M 1
M 1
S ta c k > 4 V IA x is n o t
re c o m m e n d e d
V7
V7
M 7
V6
V6
M 6
V5
V4
V3
V2
M 2
V1
M 7
V6
M 5
M 3
V2
V7
M 7
M 6
M 4
V3
V7
M 7
V5
M 5
V4
V7
V1
M 1
V6
M 6
M 6
V5
V5
M 5
M 5
V4
V4
V4
M 4
M 4
M 4
V3
V3
M 3
M 3
V2
V2
M 2
M 2
M 2
M 1
M 1
M 3
V1
M 1
> = 2 v ia s in e a c h V IA x la y e r
o n th e s a m e m e ta l is
re c o m m e n d e d .
S ta c k < = 4 V IA x is
re c o m m e n d e d .
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Illustration of VIAx.R.2, VIAx.R.3 Rules
<= W 1
F ig . a n e t w ith
F ig . b n e t w ith
< 4 V ia s
> = 4 V ia s
<= W 1
* a ls o th e c a s e w ith
exchanged M x / M x+ 1
F ig . f3
<=S1
F ig . f1
<=S1'
<=S1
F ig . f2
F ig . e 2
W 1
S1
<= S1
> = 4 V ia s
F ig . e 1
M x+1
F ig . f4
M x
> S1
<= W 1
a llo w e d
> S 1 ' a llo w e d
N o t a llo w e d V ia s
Fig. c net with
< 9 Vias
Fig. d net with
>= 9 Vias
Fig. e3
W1
<=S2'
<=S2
Follow
VIAx.R.4,5,6
>=9 Vias
W2
Follow
VIAx.R.7
>S2' allowed
Rule VIAx.R.2
0.21 μm < W1  0.55 μm
Fig. a
< 4 vias
S1 = 0.14 μm
Fig. b
 4 vias
S1’ = 0.63 μm
Rule VIAx.R.3
W2 μm > 0.55 μm
Fig. c
< 9 vias
S2 = 0.14 μm
Fig. d
 9 vias
S2’ = 0.83 μm
Fig. a. At least two vias with spacing  S1 μm inside the same overlapped metal region (Mx AND Mx+1).
Fig. b. At least four vias with spacing  S1’ μm.
Fig. c. At least four vias with spacing  S2 μm inside the same overlapped metal region (Mx AND Mx+1).
Fig. d. At least nine vias with spacing  S2’ μm.
Fig. e1 A single via is allowed inside metal of width  W1 μm. However, it is a violation if the via is located on the
boundary between metal segments of width  W1 μm and width > W1 μm as shown in fig f1.
Fig. e2 A via or vias located on  W1 (W2) metal but near > W1 (W2) metal can be counted in for the rule.
Fig. e3 A via or vias located on  W1 (W2) metal but near > W1 (W2) metal can be counted in for the rule.
Fig. e3 Indicates the rules that the areas within the vias should follow.
Layout violation examples:
Fig. f2.Two vias with spacing > S1 μm.
Fig. f3.Two vias with spacing  S1 μm but belonging to different nets.
Fig. f4.Two vias with spacing  S1 μm on the same net but not inside the same overlapped metal region (Mx AND
Mx+1).
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Illustration of VIAx.R.4/VIAx.R.5/VIAx.R.6 Rules
Rule No
Wide Metal
Metal connection
W
L
D
VIAx.R.4
VIAx.R.5
VIAx.R.6
Mx or Mx+1 Mx or Mx+1 Mx or Mx+1
Mx+1 or Mx Mx+1 or Mx Mx+1 or Mx
> 0.21 μm > 1.4 μm
> 2.1 μm
> 0.21 μm > 1.4 μm
> 7 μm
> 1.14 μm > 2.8 μm
> 7.1 μm
(a) ~ (f) is ok but (g) ~ (j) is not allowed
(a )
(e )
(b )
(c )
(f)
(d )
M e ta l C o n n e c tio n
D
< = 0 .1 4
< = 0 .1 4
W
< = 0 .1 4
W id e M e ta l
L
(h )
(i)
M e ta l C o n
n c e tio n
(g )
(j)
D
W
W id e M e ta l
L
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Version
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: 2.6
Mx Layout Rules (Mask ID: 380, 381, 384, 385,
386, 387, 388)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
Mx.W.1
Mx.W.2
Mx.W.3
Mx.S.1
Mx.S.1®
Mx.S.1.1
Mx.S.2
Mx.S.2.1
Mx.S.2.2
Mx.S.2.3
Mx.S.3
Mx.S.5
Mx.S.5.1
Mx.S.6
Mx.S.8
Mx.S.8.1
Mx.S.8.2
Mx.S.9
Mx.EN.0
Mx.EN.0®
Mx.EN.1
Mx.EN.1®
Mx.EN.2
Mx.EN.2®
Mx.EN.3
Mx.EN.3.1
Mx.A.1
Description
Width
Width of 45-degree bent Mx. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer to
the guideline, G.6gU, in section 3.7))
Maximum width
(This check doesn’t include the SEALRING_ALL (162;2) region)
Space
Recommended space to reduce the short possibility caused by particle
Space [any one of Mx connects to > 3.3V and  5V net]
Space [at least one metal line width > 0.17 μm (W1) and the parallel metal run length > 0.27 μm (L1)] (union
projection)
Space [at least one metal line width > 0.24 μm (W2) and the parallel metal run length > 0.27 μm (L2)] (union
projection)
Space [at least one metal line width > 0.31 μm (W3) and the parallel metal run length > 0.4 μm (L3)] (union
projection)
Space [at least one metal line width > 0.62 μm (W4) and the parallel metal run length > 0.62 μm (L4)] (union
projection)
Space [at least one metal line width > 1.5 μm (W5) and the parallel metal run length > 1.5 μm (L5)] (union
projection)
Space at Mx line-end (W < 0.10 μm (Q)) in a dense-line-end configuration: If Mx has parallel run length with
opposite Mx (measured with T = 0.035 μm extension) along two adjacent edges of Mx [any one edge <Q
distance from the corner of the two edges], then one of the spaces (S1 or S2) needs to be at least this value
(This check doesn't include small jog with edge length < 0.07 μm(R)) (M2.S.5 except SRAMDMY;0 (186;0)
region)
Space at Mx line-end (W < 0.10 μm (Q)) in a dense-line-end configuration: If Mx has parallel run length with
opposite Mx (measured with T = 0.035 μm extension) along two adjacent edges of Mx [any one edge < Q
distance from the corner of the two edges], and Mx enclose Vx-1 < 0.05 μm at the line-end, then one of the
spaces (S1 or S2) needs to be at least this value.
This check doesn't include the following areas:
(1) Small jog with edge length < 0.07 μm (R).
(2) Two or more VIAx (at least one VIA does not violate this rule , i.e. either one of the two line-end vias follows
the rule, and DRC will treat the other one does not violate this rule) present in the metal intersection.
(3) The following conditions can pass the check flow.
(i) S1/S2  0.12 μm and Mx enclosure Vx-1  0.03 μm
(ii) S1/S2 < 0.12 μm and Mx enclosure Vx-1  0.05 μm
(iii) Sum of S1 and Mx enclosure of Vx-1  0.15 μm with five combinations (S1/Mx enclosure Vx-1):
(a) space  0.120 μm / enclosure 
0.030 μm,
(b) space  0.115 μm / enclosure  0.035 μm,
0.040 μm,
(c) space  0.110 μm / enclosure 
(d) space  0.105 μm / enclosure  0.045 μm,
(e) space 
0.100 μm / enclosure  0.050 μm.
Space to 45-degree bent Mx
Space to {VIAx-1 OR VIAx} [different net, any one of VIAx-1, VIAx or Mx connects to 1.8V ~ 3.3V net]
Space to {VIAx-1 OR VIAx} [different net, any one of VIAx-1, VIAx or Mx connects to  1.5V and < 1.8V net]
Space to {VIAx-1 OR VIAx} [different net, any one of VIAx-1, VIAx or Mx connects to > 3.3V and  5V net]
This rule is to check the Metal (A) space with the neighboring VIAx [either VIAx or Mx connects to > 3.3V and 
5V net].
The DRC methodology to find Metal (A):
Find an edge (B) of the metal line-end [edge length  0.12um]
Run length (C) from edge (B) inside metal  0.13um
Jog length (D)  0.01um within 0.13um run length
Extend 0.06um outside from edge (B) to form a polygon metal (A)
Metal (A) is defined if conditions 1~4 are all satisfied.
Enclosure of VIAx-1 is defined by either {Mx.EN.1 and Mx.EN.2} or {Mx.EN.3 and Mx.EN.3.1}
Recommended enclosure of VIAx-1 is defined by either Mx.EN.1® or Mx.EN.2® .
Enclosure of VIAx-1
Recommended enclosure of VIAx-1 to avoid high Rc.
Enclosure of VIAx-1 [at least two opposite sides] (except SEALRING_ALL (162;2) regions)
Recommended enclosure of VIAx-1 [at least two opposite sides] to avoid high Rc.
Enclosure of VIAx-1 (except SEALRING_ALL (162;2) regions)
Enclosure of VIAx-1 [at least two opposite sides] (except SEALRING_ALL (162;2) regions)
Area (except M2 (M2.A.1) in SRAMDMY;0 (186;0) region)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
A
Op.

Rule
0.07
B

0.17
C

4.50
D
D



0.07
0.09
0.09
E

0.1
E1

0.12
E2

0.15
F

0.21
G

0.50
S1/S2

0.10
S1/S2

0.12
H




0.17
0.1
0.08
0.18
S

0.15
I
I
J
J
I
J
O







0.00
0.03
0.03
0.05
0.01
0.02
0.027
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Rule No.
Mx.A.1®
Mx.A.2
Mx.A.3
Mx.DN.0
Mx.DN.1
Mx.DN.1.1
Mx.DN.4
Mx.DN.5
Mx.DN.6
Mx.DN.6®
Mx.DN.7
Mx.DN.7®
Mx.DN.8®
DMx.R.1
DMx.R.4® U
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Recommended area to avoid high Rc (except DMx_O)
Area [with all of edge length < 0.17 μm]
(This check doesn't include the patterns filling 0.07 μm x 0.17 μm rectangular tile) (except M2 (M2.A.2) in
SRAMDMY;0 (186;0) region)
Enclosed area
For the following Mx.DN.1, Mx.DN.1.1, Mx.DN.4, and DMx.R.1, please refer to the "Dummy Metal Rules" in
Chapter 8 for the details.
Minimum metal density in window 125 μm x 125 μm, stepping 62.5 μm
Maximum metal density in window 125 μm x 125 μm, stepping 62.5 μm
The metal density difference between any two neighboring checking windows including DMxEXCL [window 200
μm x 200 μm, stepping 200 μm].
Anticipate metal density gradient from layout of small cell by targeting density ~40% (this way, it will limit the
risk of low density and of high gradient.)
It is not allowed to have local density > 85% of all 3 consecutive metal (Mx, Mx+1, and Mx+2) over any window
62.5 μm x 62.5 μm (stepping 31.25 μm), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density  85%.
1. The metal layers include M1/Mx and dummy metals.
2. The check does not include chip corner stress relief pattern, SEALRING_ALL (162;2) and top two metals at
the CUP area.
Metal density  1% must be followed for items (A) to (C).
(A) Metal density [window 80 μm x 80 μm, stepping 40 μm]  1%.
(B) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
1%] ≤ 6400um2, except the merged low density windows width ≤ 30um.
(C) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
1%] ≤ 18000um2.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  40um for (A) and
 5um for both (B)/(C).
Recommend metal density  1% for IP level. Items (A) to (C) are recommended.
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm]  1%. This item is applied
for {IP NOT (IP SIZING -40um)} region when the width of IP is  40um.
(B) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
stepping 5um, density < 1%] ≤ 1600um2, except the merged low density windows width ≤ 30um. This item
is applied for {IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
(C) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
stepping 5um, density < 1%] ≤ 4500um2. This item is applied for {IP NOT (IP SIZING -10um)} region when
the width of IP is  10um.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  20um for (A) and
 5um for both (B)/(C).
It is not allowed to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any 30um x
30um (stepping 15um), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local density ≥ 5%.
1. The metal layers include M1/Mx and dummy metals.
2. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is  15 μm.
It is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any
15um x 15um (stepping 15um) for IP level, i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density ≥ 5%.
1. The metal layers include M1/Mx and dummy metals.
2. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is ≥ 7.5μm and for
{IP NOT (IP SIZING -15um)} region when the width of IP is  15um.
Total Mx island (for all Mx layers) density < 6.5E+04 ea/mm2 in whole chip
The definition of counts of small Mx island:
1. Mx width == 0.07um
2. Mx length  0.52um
3. Mx has two segments with space == 0.07um with the parallel run length (0.209  parallel run length < 0.52)
DMx is a must. The DMx CAD layer must be different from the Mx CAD layer.
It is important to insert the DMx & DVIAx uniformly to avoid white space. You should use tsmc standard
backend utility to insert the backend dummy pattern. The usage of DMxEXCL needs to be minimized.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
O
Op.

Rule
0.0351
O

0.06
Q1

0.2


10%
85%

50%
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Rule No.
Mx.R.1U
Mx.R.2gU
Mx.R.3
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Mx line-end must be rectangular. Other shapes are not allowed.
For the small space, recommended to enlarge the metal space, by using Wire Spreading function of EDA tool,
to reduce the wire capacitance and the possibility of metal short. Please refer to section 9.1.1 and TSMC
Reference Flow.
Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
Label
Op.
Rule
Table Notes:

Although tsmc provides 5V metal and Via related rules, tsmc does not offer any 5V device for FEOL,
except HVMOS (only drain side can be applied to 5V).

To improve the metal CMP process window, you must fill the DMx globally and uniformly even if the originally
drawn Mx has already met the density rules (Mx.DN.1 and Mx.DN.1.1). For sensitive areas with auto-fill operations
blocked by the DMxEXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a
better process window and electrical performance.

During IP/macro design, it is important to put certain density margin to avoid the possibility of high density
violations (Mx.DN.1, Mx.DN.1.1, Mx.DN.5) during placement. It may have unexpected violation during the
IP/macro placement due to the environment, even if the IP/macro already pass the high density rule check.
Therefore, you need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus),

under the proper high density limit.
Mx.DN.6®: For IP level, recommend metal density ≥ 1% to reduce Mx.DN.6 DRC violation in chip level.
Mx.DN.7 Layout suggestion: increase the density of all 3 consecutive Mx layers (1 st priority), or increase the
density of the uppermost layer (2nd priority) instead of modifying only the density of the bottom layer to pass the
rule check.

Ex: M4.DN.7 represent the low M4/M5/M6 density violation: the 1st choice is to increase the Mx density of
M4/M5/M6 at violation window, or increase the M6 density at violation window.
Mx.DN.7® : For IP level, it is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1

and Mx+2) over any 15 μm x 15 μm (stepping 15 μm) to reduce Mx.DN.7 DRC violation in chip level.
Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9.


o Make sure to add correct marker layers to let DRC check the high voltage rules correctly.
 Data-types 200 to 218 of each metal layer are reserved for the nets of voltage ranging from 0V to 1.8V in
0.1V step. Data-types 219, 220, and 221 are assigned for I/O voltage 2.5V, 3.3V, and 5V, respectively.
 The net voltage is defined by the corresponding marker layers. The net voltage cannot be recognized by
incorrect marker layers. That means, if a marker layer (33;218) is on M3, then this net will be recognized as
an 1.8V net, but it cannot be recognized if a marker layer (32;218) is on M3.
 Higher voltage marker layers have higher priority, e.g. the M3 net will be recognized as an 1.8V net if there
are two marker layers as (33;215) and (33;218) on it.
o The DRC methodology for the high voltage check:
 Marker layers have higher priority than MOS connection.
 The M3 net will be recognized as an 1.8V net if there is (33;218), even if this net does not connect to a
MOS inside OD2.
 The M3 net will be recognized as a low-voltage net (
1.2V) if there is a marker layer of
(33;200~212), even if this net connects to a MOS inside OD2.
 The M3 net will be recognized as an 1.8V net if there is (33;218) and this net connects to a MOS inside
OD2 and a core MOS simultaneously.
 Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9 will be checked for the nets with voltage > 1.2V
defined by marker layers. Nets with voltage  1.2V will be excluded.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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 If a net without any marker layers,
 Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9 will be checked when the net connects only to a
MOS inside OD2.
 If a net connects to an IO MOS & a core MOS simultaneously,
o
If the DRC option of Mx_S_8_IO_NET is off (default), it will be recognized as low voltage and will
not check Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9.
o
If the DRC option of Mx_S_8_IO_NET is on (not default), it will be recognized as a high voltage net
and will check Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9.
 The following summary tables list the high/low voltage net recognition results for the different combinations
of high voltage marker layers and the DRC option:
Mx net connection if Mx_S_8_IO_NET is OFF
Core MOS IO MOS Metal high voltage markers (Data-types 213~221)
Y
Y
Y
Y
N
Y
N
Y
Y
N
Y
N
Y
Y
N
Y
N
N
Mx net connection if Mx_S_8_IO_NET is ON
Core MOS IO MOS Metal high voltage markers (Data-types 213~221)
Y
Y
Y
Y
N
Y
N
Y
Y
N
Y
N
Y
Y
N
Y
N
N
Voltage net recognition
High voltage
Low voltage
Voltage net recognition
High voltage
Low voltage
 The net without any marker layers will be recognized as a VSS net if there is PW STRAP connected, even
if the PW STRAP is inside OD2. But PW STRAP inside DNW (RW STRAP) will be excluded.
{PW NOT RW} w/o marker
Core
IO
VSS
RW w/o marker
Low voltage
High voltage
o For the IP design:
DRC uses the connections of IO MOS devices in OD2 to identify high voltage nets if these nets do not have the
high voltage marker layers. If your high voltage net is not connected to an IO MOS, you have to mark the proper
marker layer manually.
o For the P&R stage:
(1) During P&R, you have to follow the high voltage metal space rules for the high voltage nets.
(2) After P&R, you have to manually define the specific marker layers for the high voltage nets before GDS
stream out.
(3) You have to use the highest-voltage marker layer for the net with a range of voltages.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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M3
1 .8 V
N et
Confidential – Do Not Copy
V IA 2
M2
1 .8 V
Document No.
Version
: T-N45-CL-DR-001
: 2.6
N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3
1 .5 V
N et
V IA 2
M2
1 .5 V
N et
C h e c k M 2 .S .8 .1
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
M3
1 .0 V
N et
V IA 2
M2
1 .0 V
N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 3 1 .0 V M a r k e r L a y e r (3 3 ;2 1 0 )
# T h e N e t v o lta g e is d e fin e d b y c o r r e s p o n d in g m a r k e r la y e r s
M 3 1 .8 V
N et
V IA 2
M 2 1 .8 V
N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M 3 1 .8 V
N et
V IA 2
M 2 1 .8 V
N et
C h e c k M 2 .S .8
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
#
H ig h v o lta g e m a r k e r la y e r h a s h ig h e r p r io r ity
M 3 ?V N et
V IA 2
M 2 ?V N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 2 1 .8 V M a r k e r L a y e r (3 2 ;2 1 8 )
# O n ly r e la tiv e m a r k e r la y e r c a n b e u s e d to d e fin e th e N e t v o lta g e
M3
1 .8 V
N et
V IA 2
M2
1 .8 V
N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3
1 .8 V
N et
V IA 2
M2
1 .8 V
N et
C h e c k M 2 .S .8
M 2 1 .0 V M a r k e r L a y e r (3 2 ;2 1 0 )
M3
1 .0 V
N et
V IA 2
M2
1 .0 V
N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
# M a r k e r la y e r c o u ld b e u s e d d e fin e th e v o lta g e fo r s e v e r a l N e ts .
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
D A
E /E 1 /E 2 /F /G
M x
M x
H
N
A /C
D
> L 1 ,L 2 ,L 3 ,L 4 ,L 5
B
B
H
H
> W 1 ,W 2 ,W 3 ,W 4 ,W 5
D
M x .E N .1 / M x .E N .2
I
I
I
I
J
J
M x
I
J
J
J
M x
J
M x
M x
M x .S .5
S1
S1
S1
D
S1
D
S1
R
< Q
S2
S2
S2
M x .S .5 .1
T
S2
R e g io n 1 o r 2 c a n n o t h a v e o th e r M x p a tte r n s a t
T
th e s a m e tim e . O n e o f th e m w ith o th e r M x
M x e n c l o su r e
S1
S2
o f V x -1
p a tte r n s is a llo w e d .
S1
T
0 .1 2 0
0 .0 7
0 .0 3 0
0 .1 1 5
0 .0 7
0 .0 3 5
0 .1 1 0
0 .0 7
0 .0 4 0
0 .1 0 5
0 .0 7
0 .0 4 5
0 .1 0 0
0 .0 7
0 .0 5 0
R e g io n 1
Q = 0 .1
R e g io n 2
W < 0 .1
T
T
Q = 0 .1
S1
W < 0 .1
S2
M x .A .1 / M x .A .2 / M x .A .3
0 .1
T
S2
M x .R .1
0 .1 2
Q1
0 .0 5
0 .0 7
0 .0 3
Q1
0 .0 7
O
O
M x
M x
M x
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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An example for condition 2 of Mx.S.5.1:
(2) two or more viax (at least one via does not violate this rule , i.e. either one of the two line-end vias follows the rule, and
DRC will treat the other one does not violate this rule).
Mx.S.9
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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LOWMEDN Layout Rules
This layer, LOWMEDN (255;15), is used for inductor, LOGO, and so on.
Rule No.
LOWMEDN.W.1
LOWMEDN.W.2
LOWMEDN.S.1
LOWMEDN.S.2
LOWMEDN.R.1
LOWMEDN.R.2
LOWMEDN.R.3
LOWMEDN.R.4
LOWMEDN.R.5
LOWMEDN.R.6
LOWMEDN.R.7U
LOWMEDN.R.8® U
VIAx.W.6
VIAx.S.7
VIAx.S.8
VIAx.EN.8
Mx.EN.4
Description
Label
Width of {(M1, DM1, DM1_O) AND LOWMEDN}
A1
Width of {Mx, DMx, DMx_O AND LOWMEDN}
A2
Space of {M1, DM1, DM1_O AND LOWMEDN}
B1
Space of {Mx, DMx, DMx_O AND LOWMEDN}
B2
Protection ring must be inside {LOWMEDN NOT (LOWMEDN SIZING -1 µm)}.
The protection ring must include all Mx/all VIAx/…/V1/M1 layers.
There must be continuous VIAx bar as a ring within {LOWMEDN NOT (LOWMEDN SIZING -4 µm)}.
(except {LOWMEDN INTERACT INDDMY})
VIAx bar is allowed in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)}.
A 0.005 um checking tolerance is allowed for 45-degree protection ring for VIAx.EN.8/ Mx.EN.4.
For {LOWMEDN INTERACT INDDMY}, there must be either only one breach (C-shape ring) of
metal/Via with via space ≤ 4um or VIAx bar must be continuous within {LOWMEDN NOT (LOWMEDN
SIZING -4 µm)}.
Remark: Inductor simulation comparison between with and without protection ring is important.
Especially to account for its impact on the performance and the possibility of resonance.
For C-shape ring, at least 2 protection rings are must in {LOWMEDN INTERACT INDDMY}. At least 2
VIAx bar in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)} for the protection ring with the breach.
Metal/Via breach must be on the opposite sides for double protection rings
Recommend dummy metal is not inserted between protection rings or in the breach of protection ring.
Please use DMxEXCL to aviod dummy metal insertion.
Width of VIAx bar in protection ring [INSIDE LOWMEDN]
Checking tolerance for 45-degree protection ring:
C
0.005um [Width = 0.070um]
0.010um [Width = 0.075um]
Space of VIAx bar in LOWMEDN to VIAx hole
D
Space of VIAx bar in LOWMEDN
E
VIAx bar enclosure by M1/Mx in LOWMEDN
F
Enclosure of VIAx-1 bar in LOWMEDN
G
Op.




Rule
0.14
0.14
0.14
0.14
=
0.070 or
0.075




0.365
0.74
0.21
0.21
L O W M E D N .R .1
LOW M EDN
I f t h e L O W M E D N is b u t t e d , D R C c a n n o t a v o id it t o f la g t h is la y o u t. B u t th is
la y o u t is a llo w e d f o r p r o c e s s .
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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LOWMEDN
LOWMEDN
A1/A2
A1/A2
USG
B1/B2
G
ELK
F
M8
V7
M7
V6
M6
V5
M5
V4
M4
V3
M3
V2
M2
V1
M1
D=0.07 via bar
C
F
LOWMEDN
D
VIAx
{ L O W M E D N in te r a c t IN D D M Y }
V IA b a r
b re a c h
b re a c h
E
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whole or in part without prior written permission of TSMC.
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VIAy Layout Rules (Mask ID: 379, 373, 374, 375,
376, 377, 372, 37A)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
VIAy.W.1
VIAy.S.1
VIAy.S.2
VIAy.EN.1
VIAy.EN.1®
VIAy.EN.2
VIAy.EN.2®
VIAy.R.1
VIAy.R.2
VIAy.R.3
VIAy.R.4
VIAy.R.5
VIAy.R.6
VIAy.R.7
VIAy.R.11
VIAy.R.13
VIAy.R.13.1
VIAy.R.13.2
U
VIAy.R.9g
VIAy.R.10
Description
Width (maximum = minimum), except SEALRING_ALL (162;2) region
Space
Space to 3-neighboring VIAy (distance < 0.175 μm)
Enclosure by Mx or My
Recommended enclosure by Mx or My to avoid high Rc.
Enclosure by Mx or My [at least two opposite sides]
Recommended enclosure by Mx or My [at least two opposite sides] to avoid high Rc.
45-degree rotated VIAy is not allowed.
At least two VIAy with space  0.29 μm (S1), or at least four VIAy with space
 0.57 μm (S1’) are required to connect My and My+1 when one of these two metals has width and length
> 0.42 μm (W1).
(This check doesn’t include the SEALRING_ALL (162;2) region)
At least four VIAy with space  0.29 μm (S2), or at least nine VIAy with space  0.77 μm (S2’) are required
to connect My and My+1 when one of these two metals has width and length > 1.14 μm (W2).
(This check doesn’t include the SEALRING_ALL (162;2) region)
At least two VIAy must be used for a connection that distance  1.4 μm (D) away from a metal plate (either
My or My+1) with length > 0.7 μm (L) and width > 0.7 μm (W).(This check doesn’t include the
SEALRING_ALL (162;2) region)
At least two VIAy must be used for a connection that distance  2.8 μm (D) away from a metal plate (either
My or My+1) with length > 2 μm (L) and width > 2 μm (W).
(This check doesn’t include the SEALRING_ALL (162;2) region)
At least two VIAy must be used for a connection that distance  7.1 μm (D) away from a metal plate (either
My or My+1) with length > 10 μm (L) and width > 3 μm (W).
(This check doesn’t include the SEALRING_ALL (162;2) region)
VIAy must be fully covered by {Mx AND My+1} or {My AND My+1}.
Single VIAy is not allowed in “H-shape" My+1 when all of the following conditions come into existence:
(1) The My+1 has “H-shape" interact with two metal holes: both two metal hole length  5um (L2) and two
metal hole area  5um2
(2) The VIAy overlaps on the center metal bar of this “H-shape” My+1
(3) The center metal bar length  1μm (L) and the metal bar width  0.42um.
Maximum area ratio of Mx/My to upper VIAy in the same net [connects to gate with area > 19200um 2, and
does not connect to OD].
This rule is checked by the ANTENNA DRC command file.
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAy in the same net (Except the
protection OD area  0.25 µm2)
This rule is checked by the DRC command files in ANTENNA_DRC directory.
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAy in the same net (Except the protection OD
area  0.25 µm2)
Label
A
B
C
D
D
E
E
Op.
=






Rule
0.14
0.14
0.16
0
0.045
0.045
0.075

350000

300000

2000000
This rule is checked by the DRC command files in ANTENNA_DRC directory.
Recommend using redundant vias to avoid high Rc wherever layout allows. Please refer to section “Via
Layout Recommendations”
VIAy connected to DMx, DMy is not allowed.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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D
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A
A
B
B
B
2 -n e ig h b o r in g V ia
B
2 -n e ig h b o r in g V ia
A
E
A
A
B
M y
B
B
C
C
2 -n e ig h b o r in g V ia
D
3 -n e ig h b o r in g V ia
A
M x
E
E
A
E
A
E
B
C
C
B
C
E
C
E
D
C
D
C
4 -n e ig h b o r in g V ia
3 X 3 V ia a r r a y
C
C
C
C
C
C
C
C
C
C
From the EM spec, at least two vias are needed. It is strongly suggested
to use  two vias in each VIAx layer for stacked via structures.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Illustration of VIAy.R.2, VIAy.R.3 Rules
<= W 1
F ig . a n e t w ith
F ig . b n e t w ith
< 4 V ia s
> = 4 V ia s
<= W 1
* a ls o th e c a s e w ith
exchanged M x / M x+ 1
F ig . f3
<=S1
F ig . f1
<=S1'
<=S1
F ig . f2
F ig . e 2
W 1
S1
F ig . e 1
M x+1
F ig . f4
M x
<= W 1
<= S1
> = 4 V ia s
> S1
a llo w e d
> S 1 ' a llo w e d
N o t a llo w e d V ia s
Fig. c net with
< 9 Vias
Fig. d net with
>= 9 Vias
Fig. e3
W1
<=S2'
<=S2
W2
Follow
VIAx.R.4,5,6
>=9 Vias
Follow
VIAx.R.7
>S2' allowed
Rule VIAy.R.2
0.42 μm < W1  1.14 μm
Rule VIAy.R.3
W2 μm > 1.14 μm
Fig. a
Fig. b
Fig. c
Fig. d
< 4 vias
<9
vias
 4 vias
 9 vias
S1 = 0.29μm S1’ = 0.57μm S2 = 0.29μm S2’ = 0.77μm
Fig. a. At least two vias with spacing  S1 μm inside the same overlapped metal region (My AND My+1).
Fig. b. At least four vias with spacing  S1’ μm.
Fig. c. At least four vias with spacing  S2 μm inside the same overlapped metal region (My AND My+1).
Fig. d. At least nine vias with spacing  S2’ μm.
Fig. e1 A single via is allowed inside metal of width  W1 μm. However, it is a violation if the via is located on the
boundary between metal segments of width  W1 μm and width > W1 μm as shown in fig f1.
Fig. e2 A via or vias located on  W1 (W2) metal but near > W1 (W2) metal can be counted in for the rule.
Fig. e3 A via or vias located on  W1 (W2) metal but near > W1 (W2) metal can be counted in for the rule.
Fig. e3 Indicates the rules that the areas within the vias should follow.
Layout violation examples:
Fig. f2.Two vias with spacing > S1 μm.
Fig. f3.Two vias with spacing  S1 μm but belonging to different nets.
Fig. f4.Two vias with spacing  S1 μm on the same net but not inside the same overlapped metal region (My AND
My+1).
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Illustration of VIAy.R.4/VIAy.R.5/VIAy.R.6 Rules
Rule No
Wide Metal
Metal connection
W
L
D
VIAy.R.4
VIAy.R.5
VIAy.R.6
My or My+1 My or My+1 My or My+1
My+1 or My My+1 or My My+1 or My
> 0.7 μm
> 2 μm
> 3 μm
> 0.7 μm
> 2 μm
> 10 μm
> 1.4 μm
> 2.8 μm
> 7.1 μm
(a) ~ (f) is ok but (g) ~ (j) is not allowed
(a )
(e )
(b )
(c )
(f)
(d )
M e ta l C o n n e c tio n
D
< = 0 .2 9
< = 0 .2 9
W
< = 0 .2 9
W id e M e ta l
L
(h )
(i)
M e t a l C o n( g n
c e tio n
)
(j)
D
W
W id e M e ta l
L
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The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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My Layout Rules (Mask ID: Second Inter-layer
Metal (385, 386, 387, 388) and Top Metal (381,
384, 385, 386, 387, 388, 389, 38A))
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
My.W.1
My.W.2
My.W.3
My.S.1
My.S.2
My.S.3
My.S.4
My.S.5
My.EN.0
My.EN.0®
My.EN.1
My.EN.1®
My.EN.2
My.EN.2®
My.A.1
My.A.2
My.DN.0
My.DN.1
My.DN.1.a
My.DN.1.1
My.DN.4
DMy.R.1
My.R.1U
My.R.2gU
My.R.3
Description
Label
Width
A
Width of 45-degree bent My. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer to
B
the guideline, G.6gU, in section 3.7))
Maximum width
C
Space
D
Space [at least one metal line width > 0.21 μm (W1) and the parallel metal run length > 0.52 μm (L1)] (union
E2
projection)
Space [at least one metal line width > 1.5 μm (W2) and the parallel metal run length > 1.5 μm (L2)] (union
F
projection)
Space [at least one metal line width > 4.5 μm (W3) and the parallel metal run length > 4.5 μm (L3)] (union
F
projection)
Space to 45-degree bent My
H
Enclosure of VIAy-1 is defined by {My.EN.1 and My.EN.2}
Recommended enclosure of VIAy-1 is defined by either My.EN.1® or My.EN.2® .
Enclosure of VIAy-1
I
Recommended enclosure of VIAy-1 to avoid high Rc.
I
Enclosure of VIAy-1 [at least two opposite sides]
J
Recommended enclosure of VIAy-1 [at least two opposite sides] to avoid high Rc.
J
Area
K
Enclosed area
L
For the following My.DN.1, My.DN.1.a, My.DN.1.1, My.DN.4, and DMy.R.1, please refer to the "Dummy Metal
Rules" in Chapter 8 for the details.
Minimum Metal density in window 125 μm x 125 μm, stepping 62.5 μm. when My as inter-metal. (Except
INDDMY_MD)
The following special regions are excluded while the density checking:
- Chip corner stress relief area and seal-ring
- LOGO/INDDMY/INDDMY_MD
This rule is only applied when the width of (checking window NOT excluded region) is ≥ 1/4 checking window
width (31.25um).
Minimum Metal density in window 125 μm x 125 μm, stepping 62.5 μm when My as top metal.
The following special regions are excluded while the density checking:
- Chip corner stress relief area and seal-ring
- LOGO/INDDMY/INDDMY_MD
This rule is only applied when the width of (checking window NOT excluded region) is ≥ 1/4 checking window
width (31.25um).
Maximum Metal density in window 125 μm x 125 μm, stepping 62.5 μm
The metal density difference between any two neighboring checking windows including DMxEXCL [window
200 μm x 200 μm, stepping 200 μm]
Anticipate metal density gradient from layout of small cell by targeting density ~40% (this way, it will limit the
risk of low density and of high gradient).
DMy is a must. The DMy CAD layer must be different from the My CAD layer.
My line-end must be rectangular. Other shapes are not allowed.
For the small space, recommended to enlarge the metal space, by using Wire Spreading function of EDA tool,
to reduce the wire capacitance. Please refer to section 9.1.1 and TSMC Reference Flow.
Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.

Rule
0.14

0.40


12
0.14

0.19

0.50

1.50

0.40






0
0.045
0.045
0.075
0.07
0.2

10%

20%

85%

50%
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Table Notes:

To improve the metal CMP process window, you must fill the DMy globally and uniformly even if the originally
drawn My has already met the density rules (My.DN.1 and My.DN.1.1). For sensitive areas with auto-fill operations
blocked by the DMxEXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a
better process window and electrical performance.

During IP/macro design, it is important to put certain density margin to avoid the possibility of high-density
violations (My.DN.1, My.DN.1.1) during placement. It may have unexpected violation during the IP/macro
placement due to the environment, even if the IP/macro already pass the high density rule check. Therefore, you
need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus), under the proper
high-density limit.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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M y
D
M y
> L 1 ,L 2 ,L 3 ,L 4
L
L
K
E /E 1 /F /G
> W 1 ,W 2 ,W 3 ,W 4
M y
M y
M y
I
I
J
J
M y
M y .R .1
I
I
I
J
J
>=J
M y
>=J
M y
M y
D A
B
H
H
H
B
D
Illustration of My.EN.1®
B e tte r
0 .0 4 5
0 .0 0
0 .0 4 5
0 .0 4 5
0 .0 4 5
0 .0 4 5
B e tte r
0 .0 4 5
0 .0 4 5
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Top VIAz Layout Rules (Mask ID: 379, 373, 374,
375, 376, 377, 372, 37A)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
Description
Label Op.
Rule
VIAz.W.1
VIAz.S.1
Width (maximum = minimum), except SEALRING_ALL (162;2) region
Space
A
B
=

0.36
0.34
VIAz.S.2
Space to 3-neighboring VIAz (distance < 0.56 μm)
Enclosure by Mx or My or Mz
(This check doesn’t include the SEALRING_ALL (162;2) region)
Enclosure by Mx or My or Mz [at least two opposite sides]
45-degree rotated VIAz is not allowed.
C

0.54
D

0.02
E

0.08

350000

300000

2000000
VIAz.EN.1
VIAz.EN.2
VIAz.R.1
VIAz.R.2
At least two VIAz with spacing  1.7 μm are required to connect Mz and Mz+1 when
one of these metals has a width and length > 1.8 μm.
(This check doesn’t include the SEALRING_ALL (162;2) region)
At least two VIAz must be used for a connection that distance  5 μm (D) away from
a metal plate (either Mz or Mz+1) with length > 10 μm (L) and width > 3 μm (W).
(This check doesn’t include the SEALRING_ALL (162;2) region)
VIAz.R.4
VIAz must be fully covered by Mz and Mz+1.
Recommend using redundant vias to avoid high Rc wherever layout allows.. Please
VIAz.R.5gU
refer to section “Via Layout Recommendations”
VIAz.R.6
VIAz connected to DMx, DMy, DMz, DMu is not allowed.
Maximum area ratio of Mx/My/Mz to upper VIAz in the same net [connects to gate
with area > 19200um2, and does not connect to OD].
VIAz.R.13
This rule is checked by the ANTENNA DRC command file.
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAz in the same
VIAz.R.13.1 net (Except the protection OD area  0.25 µm2)
This rule is checked by the DRC command files in ANTENNA_DRC directory.
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAz in the same net
VIAz.R.13.2 (Except the protection OD area  0.25 µm2)
This rule is checked by the DRC command files in ANTENNA_DRC directory.
VIAz.R.3
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V IA 8 ,9
A
E
A
A
M 9 ,1 0
B
B
: T-N45-CL-DR-001
: 2.6
B
C
B
D
2 - n e ig h b o r in g V ia
C
2 - n e ig h b o r in g V ia
3 - n e ig h b o r in g V ia
V IA 8 ,9
C
A
E
A
A
C
C
C
C
C
B
M 9 ,1 0
C
D
C
3 - n e ig h b o r in g V ia
C
C
C
C
C
V IA 8 ,9
C
D
E
A
C
3 X 3 V ia a r r a y
A
V IA 8
C
E
B
E
C
M8
V IA 8
E
C
D
4 - n e ig h b o r in g V ia
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Illustration of VIAz.R.2 Rule
< = 1 .8
< = 1 .8
F ig . a n e t w ith
* a ls o th e c a s e w ith
< 4 V ia s
e x c h a n g e d M 9 / M 1 0 , M 8 /M 9
F ig . f3
< = 1 .7
F ig . f1
< = 1 .7
F ig . f2
F ig . e 2
1 .7
< = 1 .7
1 .8
F ig . e 1
M 10
F ig . f4
M 9
< = 1 .8
> 1 .7
a llo w e d
N o t a llo w e d V ia s
Fig. a At least two vias with spacing  1.7 μm inside the same overlapped metal region (M8 AND M9) or (M9 AND
M10).
Fig. e1 A single via is allowed inside metal of width  1.8 μm. However, it is a violation if the via is located on the
boundary between a metal segment of width  1.8 μm and a segment of width > 1.8 μm as in Fig. f1.
Fig. e2 A via or vias that are located on  1.8 metal but near >1.8 metal can be counted in for the rule.
Violated layout examples:
Fig. f2 Two vias with spacing > 1.7 μm.
Fig. f3 Two vias with spacing  1.7 μm but belonging to different nets.
Fig. f4 Two vias with spacing  1.7 μm on the same net but not inside the same overlapped metal region (M8 AND
M9) or (M9 AND M10).
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Illustration of VIAz.R.3 Rule
(a) ~ (f) is ok but (g) ~ (j) is not allowed
(a )
(c )
(d )
M 10 or M 9
D =
(f)
(e )
(b )
5
< = 1 .7
< = 1 .7
W > 3
< = 1 .7
M 9 or M 10
L
>
10
(h )
M 10
or M 9
(i)
(g )
(j)
D = 5
W > 3
M 9 or M 10
L > 10
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: 2.6
Top Mz Layout Rules (Mask ID: 381, 384, 385,
386, 387, 388, 389, 38A)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
Mz.W.1
Mz.W.2
Mz.W.3®
Mz.S.1
Mz.S.2
Mz.S.3
Mz.EN.1
Mz.EN.2
Mz.A.1
Mz.A.2
Mz.DN.0
Mz.DN.1
Mz.DN.1.1
Mz.DN.4
DMz.R.1
Mz.R.1U
Mz.R.2
Table Notes:

Description
Width
Maximum width [except bond pad and INDDMY_MD]
(This check doesn’t include the regions covered by layers of LMARK, {INDDMY
SIZING 22 μm}, CB, and {UBM INTERACT CBD}.)
Recommended Mz width [Mz on (((Mz-1 OR DMz 5 μm x 5
μm) SIZING 1 μm)] for CMP dishing concern.
Space
Space [at least one metal line width > 1.5 μm (W1) and the parallel metal run
length > 1.5 μm (L1)]
Space [at least one metal line width > 4.5 μm (W2) and the parallel metal run
length > 4.5 μm (L2)]
Enclosure of VIAz-1
(This check doesn’t include the SEALRING_ALL (162;2) region)
Enclosure of VIAz-1 [at least two opposite sides]
Area
Enclosed area
For the following Mz.DN.1, Mz.DN.4, and DMz.R.1, please refer to the "Dummy
Metal Rules" in Chapter 8 for the details.
Minimum Mz density in window 125 μm x 125 μm, stepping 62.5 μm. The
following special regions are excluded while the density checking:
- Chip corner stress relief area and seal-ring
- LOGO/INDDMY/INDDMY_MD
This rule is only applied when the width of (checking window NOT excluded
region) is ≥ 1/4 checking window width (31.25um).
Maximum Mz density in window 125 μm x 125 μm, stepping 62.5 μm. (This
check doesn’t include bond pad and INDDMY_MD.)
The metal density difference between any two neighboring checking windows
including DMxEXCL [window 200 μm x 200 μm, stepping 200μm] Anticipate
metal density gradient from layout of small cell by targeting density ~40% (this
way, it will limit the risk of low density and of high gradient).
DMz is a must. The DMz CAD layer must be different from the Mz CAD layer.
Mz line-end must be rectangular. Other shapes are not allowed.
Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
Label
A
Op.

Rule
0.4
B

12
J

0.42
C

0.4
D

0.50
E

1.50
F

0.02
G
H
I



0.08
0.565
0.565

20%

85%

50%
For RF/Mixed-signal applications, some metal rules are different from Logic rules. Please refer to RF/Mixedsignal design rules for details.

To improve the metal CMP process window, you must fill the DMz globally and uniformly even if the originally
drawn Mn has already met the density rules (Mz.DN.1 and Mz.DN.1.1). For sensitive areas with auto-fill
operations blocked by the DMxEXCL layer, it is recommended filling dummy pattern evenly by manual operations
to gain a better process window and electrical performance.

During IP/macro design, it is important to put certain density margin to avoid the possibility of high density
violations (Mz.DN.1, Mz.DN.1.1) during placement. It may have unexpected violation during the IP/macro
placement due to the environment, even if the IP/macro already pass the high density rule check. Therefore, you
need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus), under the
proper high density limit.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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M z
A /B
M z
C
> L 1 ,L 2
D /E
I
H
> W 1 ,W 2
Illu s tr a tio n o f M z .W .3 R
I
M 10
<=1 um
M z
M z
M z
F
>=5 um
F
G
M z .R .1
M 9
M 9
J
G
G
M z
>=5 um
M z
M 10
J
M 9
J
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
A /B
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Top VIAr Layout Rules (Mask ID: 375, 376, 377,
372, 37A)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
VIAr.W.1
VIAr.S.1
VIAr.S.2
VIAr.S.2.1
VIAr.EN.1
VIAr.EN.2
VIAr.R.1
VIAr.R.2
VIAr.R.3
VIAr.R.4
VIAr.R.5gU
VIAr.R.6
VIAr.R.13
VIAr.R.13.1
VIAr.R.13.2
Description
Label Op.
Width (square)(maximum = minimum), except SEALRING_ALL (162;2) region
A
=
Space
B

C
Space to 3-neighboring VIAr (distance  0.66 μm)

Rule
0.46
0.44
C1

0.54
D

0.02
E

0.08

350000

300000

2000000
Space of 2*2 array on same net
Enclosure by Mx or Mr
(This check doesn’t include the SEALRING_ALL (162;2) region)
Enclosure by Mx or Mr [at least two opposite sides]
45-degree rotated VIAr is not allowed.
At least two VIAr with spacing  1.7 μm are required to connect Mr and Mr+1
when one of these metals has a width and length > 1.8 μm.
(This check doesn’t include the SEALRING_ALL (162;2) region)
At least two VIAr must be used for a connection that distance  5 μm (D) away
from a metal plate (either Mr or Mr+1) with length > 10 μm (L) and width > 3
μm (W).
(This check doesn’t include the SEALRING_ALL (162;2) region)
VIAr must be fully covered by Mx and Mr.
Recommend using redundant vias wherever layout allows.
VIAr connected to DMx, DMr is not allowed.
Maximum area ratio of Mx/Mr to upper VIAr in the same net [connects to
gate with area > 19200um 2, and does not connect to OD].
This rule is checked by the ANTENNA DRC command file.
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAr in the
same net (Except the protection OD area  0.25 µm2)
This rule is checked by the DRC command files in ANTENNA_DRC
directory.
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAr in the same
net (Except the protection OD area  0.25 µm2)
This rule is checked by the DRC command files in ANTENNA_DRC
directory.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
0.66
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E
V IA r
A
B
M r
B
B
B
D
2 -n e ig h b o r in g V ia
A
A
E
V IA r , B
C
C /C 1 C /C 1
A
C
B
M r
3 -n e ig h b o r in g V ia
3 -n e ig h b o r in g V ia
D
A
C
V IA r ,9
C
C
D
E
C
C
A
V IA r
C
4 -n e ig h b o r in g V ia
3 X 3 V ia a r r a y
C
B
E
C
C
C
M x or M r
V IA r
C
C
E
C
D
C
C
E
C
Illustration of VIAr.R.2, Rule
< = 1 .8
< = 1 .8
F ig . a n e t w ith
* a ls o th e c a s e w ith
< 4 V ia s
e x c h a n g e d M 8 /M 9 , M 7 /M 8
F ig . f3
< = 1 .7
F ig . f1
< = 1 .7
F ig . f2
F ig . e 2
1 .7
< = 1 .7
1 .8
F ig . e 1
M 9
F ig . f4
M 8
< = 1 .8
> 1 .7
a llo w e d
N o t a llo w e d V ia s
Fig. a At least two vias with spacing  1.7 μm inside the same overlapped metal region (M7 AND M8) or (M8
AND M9).
Fig. e1 A single via is allowed inside metal of width  1.8 μm. However, it is a violation if the via is located on
the boundary between a metal segment of width  1.8 μm and a segment of width > 1.8 μm as in Fig. f1.
Fig. e2 A via or vias that are located on  1.8 metal but near >1.8 metal can be counted in for the rule.
Violated layout examples:
Fig. f2 Two vias with spacing > 1.7 μm.
Fig. f3/f4 Two vias with spacing  1.7 μm on the same net but not inside the same overlapped metal region
(M7 AND M8) or (M8 AND M9).
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Illustration of VIAr.R.3 Rule
(a) ~ (f) is ok but (g) ~ (j) is not allowed
(a )
(c )
(d )
M 9 or M 8
D =
(f)
(e )
(b )
5
< = 1 .7
< = 1 .7
W > 3
< = 1 .7
M 8 or M 9
L
>
10
(h
)
M 8
or M 9
(i
)
(g
(j
)
)
D = 5
W > 3
M 8 or M 9
L > 10
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Document No.
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: 2.6
Top Mr Layout Rules (Mask ID: 386, 387, 388,
389, 38A)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Rule No.
Description
Label
Op.
Rule
Mr.W.1
Width
A

0.50
Mr.W.2
Maximum width [except bond pad and INDDMY_MD]
B

12
J

0.55
C

0.50
D

0.65
E

1.50
F

0.02
Mr.EN.2
Recommended Mr width [Mr on (((Mr-1 OR DMr-1) with space  5 μm x 5
μm) SIZING 1 μm)]
Space
Space [at least one metal line width > 1.5 μm (W1) and the parallel metal
run length > 1.5 μm (L1)]
Space [at least one metal line width > 4.5 μm (W2) and the parallel metal
run length > 4.5 μm (L2)]
Enclosure of VIAr-1
(This check doesn’t include the SEALRING_ALL (162;2) region)
Enclosure of VIAr-1 [at least two opposite sides]
G

0.08
Mr.A.1
Area
H

1.0
Mr.A.2
Enclosed area
For the following Mr.DN.1, Mr.DN.4, and DMr.R.1, please refer to the
"Dummy Metal Rules" in Chapter 8 for the details.
Minimum Mr density in window 125 μm x 125 μm, stepping 62.5 μm. The
following special regions are excluded while the density checking:
- Chip corner stress relief area and seal-ring
- LOGO/INDDMY/INDDMY_MD
This rule is only applied when the width of (checking window NOT excluded
region) is ≥ 1/4 checking window width (31.25um).
Maximum Mr density in window 125 μm x 125 μm, stepping 62.5 μm. (This
check doesn’t include bond pad and INDDMY_MD.)
The metal density difference between any two neighboring checking
windows including DMrEXCL [window 200 μm x 200 μm, stepping 200 μm]
Anticipate metal density gradient from layout of small cell by targeting
density ~40% (this way, it will limit the risk of low density and of high
gradient).
Mr line-end must be rectangular. Other shapes are not allowed.
Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
DMr is a must. The DMr CAD layer must be different from the Mr CAD layer.
I

1.0

20%

85%

50%
Mr.W.3®
Mr.S.1
Mr.S.2
Mr.S.3
Mr.EN.1
Mr.DN.0
Mr.DN.1
Mr.DN.1.1
Mr.DN.4
Mr.R.1U
Mr.R.2
DMr.R.1
Table Notes:

To improve the metal CMP process window, you must fill the DMr globally and uniformly even if the originally drawn
Mr has already met the density rules (Mr.DN.1 and Mr.DN.1.1). For sensitive areas with auto-fill operations blocked
by the DMrEXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a better
process window and electrical performance.

During IP/macro design, it is important to put certain density margin to avoid the possibility of high density violations
(Mr.DN.1, Mr.DN.1.1) during placement. It may have unexpected violation during the IP/macro placement due to the
environment, even if the IP/macro already pass the high density rule check. Therefore, you need to carefully design
the dimension of the width/space for wide metal (eg, power/ground bus), under the proper high-density limit.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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A
C
M r .R .1
M r
M r
/B
: T-N45-CL-DR-001
: 2.6
D /E
> L 1 ,L 2
I
H
M r
I
M r
> W 1 ,W 2
M r
G
<=1um
C1
F
J
G
F
M9
G
M r
M8
M8
>=5um
M r
F ig . a
>=5um
F ig . b
5um
M9
M9
J
A /B
J
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whole or in part without prior written permission of TSMC.
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

Document No.
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: T-N45-CL-DR-001
: 2.6
RV Layout Rules (Mask ID: 306)
CB-VD mask (306) is generated by the logical operation of CB (CAD layer: 76) and RV (CAD layer: 85).
It is a must to consider sufficient RV counts to provide enough current for EM and ESD protection.It is
recommended to put as many RV holes as possible.
Rule No.
RV.W.1
RV.S.1
RV.EN.1
RV.R.1
RV.R.2
Description
Label
Op.
Rule
A
=
3 or 2
B

2
C

0.5
B
RV
RV
Width (maximum = minimum) (Except SEALRING_ALL (162;2))
(It is allowed to have both via dimensions in the same chip.)
RV 2μm x 2μm is only allowed in polyimide process. DRC flags RV 2μm x 2μm
without PM layer in chip level, except SEALRING_ALL (162;2).
Space
Enclosure by top metal
A 45-degree rotated RV is not allowed (Except {(INDDMY OR INDDMY_MD)
SIZING 22um})
RV.W.1, RV.S.1, and RV.EN.1 allow 0.01 μm tolerance on 45-degree rotated RV
in (INDDMY OR INDDMY_MD).
RV
C
E
CB/CB2
C
RV
Mtop
C
A
C
C
RV C
B
Mtop
C
C
B
RV
C
A C RV
C
C
A
Mtop
Mtop
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Rule No.
AP.W.1
AP.W.2
AP.W.5
AP.S.1
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Al Redistributional Layer (AP RDL) Layout
Rules (Mask ID: 309)
Description
Label
Op.
Rule
Width (as interconnect)
Maximum width by {{AP/AP-MD SIZING 0.995um} SIZING -0.995um} (as
interconnect) {NOT INSIDE UBM, CB or CB2}
AP hole width for 28KÅ AP, except < 100 inner 90-degrees vertex of AP holes
[width < 3um] within window 100μm x 100μm, stepping 50μm.
Space
(Except following conditions in the same polygon:
1. {{AP AND {AP_PAD SIZING 2 um}} NOT AP_PAD} [INTERACT AP_PAD]
2. Jog length ≤ 1 um
3. AP hole [Width < 2 μm])
A

2
A1

35
H

3
B

2
B1

2.5
C
AP.EN.1
Definition of AP_PAD:
Width of AP [INTERACT {CB2_WB OR CB2_FC}] > 35 um
Space of metal pad, or space of metal pad to metal line [different nets]
The definition of metal pad:
The width of {AP INTERACT CB2_WB} > 35um.
Enclosure of RV

0.5
AP.DN.1
Minimum AP density across full chip

10%
AP.DN.1.1
Maximum AP density across full chip

70%
AP.W.2® U
Recommended total width of BUS line [Connect with bump pad]
AP.W.1, AP.S.1 allow 0.01 μm tolerance on 45-degree bent AP in (INDDMY OR
INDDMY_MD).
AP.EN.1 allows 0.01 μm tolerance on 45-degree rotated RV in (INDDMY OR
INDDMY_MD).

16
AP.S.1.1
AP.R.1
A’
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AP-MD
CB/CB2
C
C
RV
A, A1, A’
AP-MD
C
B
C
Mtop
CB/CB2
AP -MD
C
C
RV
A, A1, A’
C
Waive condition 1: Surround PAD
X
X
2 um (AP.S.1)
Waive condition 2: Jog length <= 1um
<2 um
Jog length
≤ 1 um
Jog length
≤ 1 um
<2 um
Waive condition 3: AP hole < 2um
<2 um
AP Hole
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whole or in part without prior written permission of TSMC.
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Document No.
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: 2.6
Via Layout Recommendations
For better yield and reliability, use of a commercial auto router is recommended to add redundant vias
wherever the layout allows. Please refer to the most updated “T-N45-CL-DR-001-X4, TSMC 45NM CMOS
LOGIC DFM REDUNDANT VIA UTILITY”. You can also download the document from TSMC Online (Design
Portal—Reference Flow) for the reference of redundant via insertion with an auto router.
In the DFM redundant VIA utility, the following layers are excluded to modify redundant vias:
1. DFMEXCL (153;20) is the blockage layer for all DFM layout enhancements.
A user can draw this layer to exclude areas in which an automatic enhancer is not wanted, that is
redundant-vias will not enter this layer.
2. COEXCL(153;0)/VIAxEXCL(153;x), x=1-9, are the blockage layers for via related layout enhancement.
A user can draw these layers to exclude vias which do not want to have a redundant-via. Take VIA1EXCL
as an example, redundant VIA1 will not enter VIA1EXCL region.
3. In addition, this utility does not enhance layout in the following areas:
CB(76), SEALRING(162), CSRDMY(166), LOGO(158), LMARK(109), INDDMY(144), and RMDMY(116;x)
x=1-10. In the area of SRAMDMY(186;0), only VIA1/VIA2 are not enhanced
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MOM is a fringe Metal-Oxide-Metal capacitor. It is based on the capacitance between parallel metal lines
separated by the inter-level dielectric. The device does not require any additional mask.
Although any kind of metal combination, M1/Mx/My/Mz/Mr/Mu/AP, is allowed to build a MOM element in
terms of process, TSMC only provides a specific MOM SPICE model and the associated PDK cell named
RTMOM (Rotated Metal Oxide Metal) which is covered by MOMDMY (CAD layer: 155;0) and FMOM
(Finger Metal Oxide Metal) which is covered by MOMDMY (CAD layer: 155;100).
M1
Mx
My/Mz/Mr/Mu/AP
X
X
X
TSMC MOM structure
SPICE
PDK
Process
X
O
O
X
O
O
X
O
X
O: available X: not available
O
O
X
O
O
O
*Mu is the ultra thick metal for the interconnection and inductor in the MS/RF process. Please refer to
section 2.5 for the thicknesses.
MOMDMY_n (n=1~10/AP) is a dummy layer for DRC/LVS to recognize the MOM region.
Layer name
MOMDMY_1
MOMDMY_2
MOMDMY_3
MOMDMY_4
MOMDMY_5
MOMDMY_6
MOMDMY_7
MOMDMY_8
MOMDMY_9
MOMDMY_10
MOMDMY_AP

: T-N45-CL-DR-001
: 2.6
MOM Layout Rules
Non-TSMC MOM structure
SPICE
PDK
Process

Document No.
Version
CAD layer
155;1
155;2
155;3
155;4
155;5
155;6
155;7
155;8
155;9
155;10
155;20
Description
Non-TSMC MOM structure
TSMC MOM structure
M1 MOM region
M2 MOM region
M3 MOM region
M4 MOM region
M5 MOM region
M6 MOM region
M7 MOM region
M8 MOM region
M9 MOM region
M10 MOM region
AP MOM region
O
O
O
O
O
O
O
O
O
O
O
O
O for Mx
O for Mx
O for Mx
O for Mx
O for Mx
O for Mx
O for Mx
In order to have a good DRC check, you need to draw the MOMDMY_n carefully. The following examples
are for your reference.
M O M DM Y_n
(G o o d )
M O M DM Y_n
(O K )
M O M DM Y_n
( N o t a llo w e d )
M O M DM Y_n
( N o t a llo w e d )
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whole or in part without prior written permission of TSMC.
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You need to pay attention to meet the metal local density rule above/under the MOM element. Therefore,
if you want to design a RF MOM circuit with a large area, it is recommended to connect several smaller
MOM elements. And each element should be surrounded with dummy metals.
The Multi-X Couple layout is recommended for large pair capacitor design to improve the matching
performance (see the section of MOM (Metal Oxide Metal) PDK Capacitor Guidelines).
Use symmetrical dummy metals around the matched pairs instead of automatically generated dummy
metals.
Carefully design wire access to capacitor terminals, and consider access to external metal lines to ensure
an optimal symmetry of the device environment.
Rule No.
MOM.S.2
MOM.A.1**
MOM.DN.1®
MOM.R.1
MOM.R.2
MOM.R.6
Description
Label
Op.
Rule
Space of metal (M1/Mx) line-end in MOMDMY_n
Maximum sidewall area of total metals in MOM without Via.
For the definition of the sidewall area of total metals, please refer to the
following figure
Recommend metal density inside {MOMDMY_n SIZING 10um}. (For M1/Mx
layers)
VIA in MOMDMY is not allowed.
Each MOM cell must be covered by MOMDMY_n (n = 155;0~10/20/21/100).
DRC only flags no MOMDMY_n (n = 155;0~10/20/21/100) in the chip. But if
there is no MOM cell in the chip, the violation can be waived.
B

0.10
C

1.31E+06

30%
Poly shielding and underneath NW or PW must bias at same
potential for reliability consideration. If poly shielding terminal could
not be tied to the underneath NW or PW, customer should keep bias
between poly terminal and underneath well within thin gate oxide
(Without OD2) or thick gate oxide (With OD2) maximum applied
voltage for reliability consideration.
DRC only check following conditions:
{{SR_DPO INTERACT {{OD OR DOD} NOT INSIDE OD2}}
INTERACT {{MOMDMY(155;100) OR MOMDMY(155;0)} NOT
{MOMDMY(155;27) OR MOMDMY(155;28) OR MOMDMY(155;31)
OR MOMDMY(155;32) OR MOMDMY(155;33)}}} [Poly shielding
MOM with dummy OD underneath] and underneath NW or PW must
bias at same potential through metal connection (All resistors and
DNW are treated as broken; all LV N/P well are treated as
connected)
Note for MOM.A.1**:
(1) DRC deck is always turn on (Default) #DEFINE MOM_33V (Turn on if max voltage applied on MOM is
3.3V, or 5.0V). If customer uses different bias range, please turn on related switch.
(2) The rule value of MOM.A.1.a and corresponding space and applied voltage is listed in rule table. If your
layout violates the rule and you apply different operation voltage on MOM, please consult TSMC in
advance if there is any special requirement.
N45
MOM without Via
5.0V
3.3V
1.31E+6
1.31E+6
Applied voltage
2.5V
1.8V
2.27E+07
1.2V
1.1V
0.9V
4.15E+08
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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M O M w ith o u t V ia
M O M .A .1
Z
’
Li
Z
B
Z’
Hi
C = T o ta l m e ta l s id e w a ll a r e a
M O M DM Y_n
Z
n
 Hi x Li
=
i= 1
L i= f in g e r le n g t h
H i= m e ta l t h ic k n e s s
n = t o ta l m e ta l f in g e r n u m b e r - 1
Figure 4.5.42.1
M O M w ith V ia
M O M .A .2
Z
Z’
Vw i
Vhi
Z’
Hi
B
Li
M O M DM Y_n
F = V ia t o ta l s id e w a ll a r e a +
M O M .R .1 g :
Figure 4.5.42.2
R e c o m m e n d e d th e ra n k
o f V I A a r r a y in M O M
M e ta l t o ta l s id e w a ll a r e a
n
n
= Vwi x Vhi x m +  Hi x Li
i= 1
i= 1
r e g io n is r e c ta n g u la r
V w i= v ia w id t h
Z
V h i= v ia h e ig h t
H i= m e ta l t h ic k n e s s
L i= m e ta l le n g t h
m = t o ta l v ia n u m b e r p e r f in g e r
n = t o ta l m e ta l f in g e r n u m b e r - 1
N o t re c o m m e n d e d fo r
M O M .R .1 g
F ig u r e 4 .5 .3 5 .2
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MOM (Metal Oxide Metal) PDK Capacitor
Guidelines
This section lists the guidelines for TSMC offered MOM. The offered MOM is a fringe Metal-Oxide-Metal
capacitor. It is based on the capacitor between parallel metal lines separated by the inter-level dielectric. The
device does not require any additional masks.
1. Although any kind of metal combination, M1/Mx/My/Mz/Mr/Mu/AP, is allowed to build a MOM element in
terms of process, TSMC only provides a specific MOM SPICE model and the associated PDK cell named
RTMOM which is covered by MOMDMY (CAD layer: 155;0) and FMOM which are covered by MOMDMY
(CAD layer: 155;100). (The TSMC offered PDK RTMOM and FMOM are implemented by “Mx” or “Mx/M1”,
at least three layers are required).
Non-TSMC MOM structure
SPICE
PDK
Process
M1
Mx
My/Mz/Mr/Mu/AP
X
X
X
TSMC MOM structure
SPICE
PDK
Process
X
O
O
X
O
O
X
O
X
O: available X: not available
O
O
X
O
O
O
*Mu is the ultra thick metal for the interconnection and inductor in the MS/RF process. Please refer to
section 2.5 for the thicknesses.
2. In order to avoid an OD density violation, PDK MOM cell has pre-inserted dummy OD pattern underneath
MOM to meet design rule requirement.
3. For layout flexibility at I/O region, an option of OD2 enclosing floating dummy OD is also available in MOM
PDK cell.
4. The variables of the PDK MOM structure are listed as the following,
˙Finger Width = the width of metal fingers
˙Finger Space = the space between metal fingers
˙Number of horizontal fingers = the finger number of even metal layer(s) (limited to even number).
˙Number of vertical fingers = the finger number of odd metal layer(s) (limited to even number).
˙Fingers Length = the length of metal fingers (for FMOM)
˙MOM Bottom Metal Layer = the start metal layer of MOM structure.
˙MOM Top Metal Layer = the stop metal layer of MOM structure.
˙Array X = the number of MOM unit on x-direction
˙Array Y = the number of MOM unit on y-direction
5. In order to make sure of the offered MOM SPICE model accuracy, the dummy metal exclusive layers
(DMxEXCL) are adopted below/above MOM to avoid dummy insertion. It is not recommended to manually
place any dummy metal patterns or routing into the regions below/above the MOM. PDK offered MOM also
supports dummy metal insertion in unused M1 and Mx layers by using parameter “dmflag=1” to turn on
dummy metal insertion and “dmflag=0” to turn off. If manually dummy metal or routing (not generated by
PDK itself) is added into the region below/above the PDK generated MOM, the resulting extra parasitic and
model inaccuracy impact must be taken into consideration by designers.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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6. If the metal density rule is violated due to the large empty regions above/below MOM structures, parallel
connected small MOMs array with dummy metals between individual MOM is recommended as shown
below.
L a rg e
S m a ll A r e a
S m a ll A r e a
RTM OM
RTM OM
a re a
D u m m y p a tte rn re g io n
D u m m y p a tte rn re g io n
RTM O M
S m a ll A r e a
S m a ll A r e a
RTM OM
RTM OM
DM xEXCL
FFigure
i g u r e 44.5.42.1.1
.5 .3 9 .1 .1
7. The Multi-X Couple layout is recommended for large-pair capacitor design, which can improve the matching
performance. The Parallel and Multi-X Couple layout for match pairs is illustrated.

The unit cell C1 and the unit cell C2 of the Multi-X Couple MOM are placed in an array with alternate
pattern placement in each row and each column.

If the total capacitance C > 400fF is required, it is recommended to use Multi-X Couple layout type
with unit cell < 200fF, to improve the matching performance. It is not recommended to use 2x200fF
Parallel MOM design.
M u lti - X
P a r a lle l
C1
(+ )
(+ )
u n it c e ll o f C 1
C1
C2
(+ )
(+ )
C1
C2
(+ )
(+ )
u n it c e ll o f C 2
C2
(-)
(-)
Figure
F i g u r e4.5.42.1.2
4 .5 .3 9 .1 .2
(-)
Figure
F i g u r e 4.5.42.1.3
4 .5 .3 9 .1 .3
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8. Figure 4.5.42.1.4 shows the mismatching (one sigma of delta capacitance) versus 1/C0.5 of a parallel MOM
pair with 2um fixed distance. The SPICE model shot on median value of lots will be optimistic compared to
process variation, therefore it is recommended to reserve enough design margins to cover process variation.
Figure 4.5.42.1.4 is for reference only, please refer to the SPICE document, “T-N45-CM-SP-003” for the
most updated figure.
9. The parallel MOM mismatching will increase dramatically with the distance between the MOM pair larger
than 200um, as shown in Figure 4.5.42.1.5. It is recommended to use the MOM pair with distance less than
200um for optimized mismatching performance.
10. It is recommended putting MOM device with surrounding pattern density ≥ 30% (MOM.DN.1® ) checked by
MOMDMY_n sizing 10um area to migrate local pattern density effect.
0.40
0.7
NV/NH=24/24 (lot1)
NV/NH=48/48 (lot1)
NV/NH=72/72 (lot1)
NV/NH=144/144 (lot1)
NV/NH=24/24 (lot2)
NV/NH=48/48 (lot2)
NV/NH=72/72 (lot2)
NV/NH=144/144 (lot2)
Lot 1
0.35
Lot 2
0.6
Lot 3
m odel
0.5
s of (dC/C)(%)
s of (dC/C)(%)
0.30
0.25
0.20
0.15
0.4
0.3
0.2
0.10
0.1
0.05
0.00
0.00
0.0
0.05
0.10
0.15
0.20
1
10
1/(Cmom_mean)0.5(fF-0.5)
Figure
4.5.39.1.4
Figure
4.5.42.1.4
100
1000
10000
Distance (um)
Figure 4.5.39.1.5
Figure 4.5.42.1.5
11. The following guidelines are provided for both modeling accuracy and safe device operation for MOM with
poly shielding usage:

Leaving shielding poly floating is not recommended, it is recommended to connect shielding poly to
AC ground for shielding purpose.

Local OD density must meet the design rule check requirement.

TSMC strongly recommends to tie shielding poly terminal to the underneath well to avoid any
reliability and model accuracy concern.

If shielding poly terminal could not be tied to the underneath well, for reliability consideration,
customer must keep bias between poly terminal and underneath well within thin(Without OD2) or
thick(With OD2) gate oxide maximum applied voltage.
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whole or in part without prior written permission of TSMC.
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Top VIAu Layout Rules (Mask ID: 373, 374, 375,
376, 377, 372, 37A)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
CAD layer datatype of VIAu is “40” (the same as that of VIAz due to the same via size).
VIAu is designed to connect between Mu and Mu-1. This section doesn’t define the VIAu rules specifically. You
have to follow VIAz rules and Mu rules (only Mu.EN.1, Mu.EN.2, Mu.R.1) for VIAu design.
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Mu (Ultra Thick Metal) Layout Rules

Mu (UTM: 35KÅ ) is only allowed as the most top metal layer and only one Mu layer is allowed in a chip.

Mu can not co-exist with other different thickness top metal layer(s) (such as Mz, My or Mr) on the same metal
layer.

Mu above Mr metal (12.5KA) is not allowed.

CAD layer datatype of Mu metal is “60” (that of dummy Mu layer is “61”), and CAD layer datatype of its
associated VIA (VIAu, the VIA under Mu) is “40” (the same as that of VIAz due to the same via size).
Rule No.
Mu.W.1
Mu.W.2
Mu.S.1
Mu.EN.1
Mu.EN.2
Mu.A.1
Mu.A.2
Mu.R.1
Mu.R.2U
Mu.DN.1
Mu.DN.1.1
Mu.DN.2
Mu.DN.2.1
Mu.R.3U
Mu.R.4
Mu.R.5
DMu.R.1
Description
Label
Op.
Rule
Width
Maximum width [except bond pad and INDDMY_MD]
(This check doesn’t include the regions covered by layers of LMARK, {INDDMY
SIZING 22 μm}, CB, and {UBM INTERACT CBD}.)
Space
Enclosure of VIAu
Mtop-1 enclosure of VIAu
(This check doesn’t include the SEALRING_ALL (162;2) region)
Area
Enclosed area
A

2.00
B

12.00
C
D, E


1.00
0.30
F

0.08
G
H


9.00
9.00
I

1.70


20%
50%

20%

85%
At least 2 VIAu with space  1.7 µm are required to connect [Mu to Mz], [Mu to
top My(2XTM)], [Mu to inter My] or [Mu to Mx] (Please put as many vias as
possible for reliability and RF applications).
Mu line-end must be rectangular. Other shapes are not allowed.
Minimum metal density over the whole chip (include INDDMY)
Maximum metal density over the whole chip (include INDDMY)
Minimum Mu density range in window 125 µm x 125 µm, stepping 62.5 µm. The
following special regions are excluded while the density checking:
- Chip corner stress relief area and seal-ring
- LOGO/INDDMY/INDDMY_MD
This rule is only applied when the width of (checking window NOT excluded
region) is  1/4 checking window width (31.25um).
Maximum Mu density range in window 125 µm x 125 µm, stepping 62.5 µm. The
following special regions are excluded while the density checking:
- Bond pad
- Chip corner stress relief area and seal-ring
- LMARK/LOGO/INDDMY/INDDMY_MD
This rule is only applied when the width of (checking window NOT excluded
region) is  1/4 checking window width (31.25um).
Mu above Mr metal is not allowed.
A 0.06um2 ((3.0*3.0)-(2.99*2.99)) checking tolerance is allowed for the rules
within the region of (INDDMY SIZING 16 µm): Mu.A.1 and Mu.A.2.
Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
DMu is a must. The DMu CAD layer must be different from the Mu CAD layer.
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whole or in part without prior written permission of TSMC.
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A
E
M u .R .2
/B
IN D .R .1 1
C
: T-N45-CL-DR-001
: 2.6
C1
D
E
D
E
H
M u
G
M u
H
Mu
Mu
F ig . b
F ig . a
Mu
F o r p r o d u c t y ie ld c o n c e r n ,
F ig . a is p r e fe r r e d .
M
Muu
Illustration of Mu.R.1, IND.R.2, IND.R.3 and IND.R.4 Rules
I
M9
M9
I
M10  2.0 μm
F
M9
I
M9
I
I
II
III
Isolated single VIAu(VIAz/VIAr) is not allowed.
I: Two Vu space > 1.7 μm.
II: Two Vu space < 1.7 μm but belong to different nets.
III: Two Vu on the same net but not inside the same overlapped metal region (Mtop-1 and Mu).
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Inductor Layout Rules
TSMC offered 3 kinds of inductor rules, including standard low metal density spiral inductor rules
(INDDMY) and logic inductor rules (INDDMY_MD and INDDMY_HD), according to different device/circuit
applications. But TSMC only provided a specific inductor device SPICE model /PDK for Low-density inductor
(identified by INDDMY) design.
Different INDDMY dummy layers are defined to recognize the three types inductors: Low-density,
Medium-density and High-density. In order to have a correct DRC check, you need to draw the corresponding
inductor dummy layers carefully.
Rule Type
SPICE PDK LVS Process
Low-density INDDMY (INDDMY)
○
○
○
○
Medium-density INDDMY (INDDMY_MD)
╳
╳
╳
○
High-density INDDMY (INDDMY_HD)
╳
╳
╳
○
○: available ╳: not available
1. Low-density INDDMY (INDDMY): INDDMY is offered to allow very low metal density within an inductor to
achieve better inductor performance. The dummy generation utility does not insert floating dummy
OD/PO/metal into INDDMY by default and provides an option to generate DOD/DPO within INDDMY. In
the INDDMY layer, the inter-via(both Vx and Vy) and top via Vy(2XTM) are all not allowed. It is required to
refer to section 4.5.32 LOWMEDN layout rules, for the usage of Inductor with protection ring when no
dummy metals (M1/Mx) are filled within INDDMY.
2. Medium-density INDDMY (INDDMY_MD): Special inductor dummy utility provides an option to autogenerate specific dummy metal (DM1 and DMx) and DOD/DPO within INDDMY_MD to lower the inductor
performance degradation caused by dummy fill. In the INDDMY_MD layer, the inter-via(both Vx and Vy)
and top via Vy(2XTM) are all not allowed. Inductor with protection ring and LOWMEDN is not required.
The real inductor performance impact by the extra-added dummy pattern must be taken care by designers.
3. High-density INDDMY (INDDMY_HD): Special inductor dummy utility provides an option to auto-generate
specific dummy metal (DM1, DMx, DMy, DMz, DMr and DMu) and DOD/DPO within INDDMY_HD to lower
the inductor performance degradation caused by dummy fill. In the INDDMY_HD layer, the inter-via(both Vx
and Vy) and top via Vy(2XTM) are allowed on the premise that all the related logic design rules has been
followed well. Inductor with protection ring and LOWMEDN is not required. The real inductor performance
impact by the extra-added dummy pattern must be taken care by designers.
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whole or in part without prior written permission of TSMC.
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INDDMY_MD
INDDMY_HD
Table 4.5.45 Inductor Rule Summary
Rule Type
INDDMY
Metal Dummy inserted by dummy
NO
DM1/DMx
generation utility
DOD/DPO inserted by dummy
YES
YES
generation utility
Dummy Via inserted by dummy
NO
NO
generation utility
Inter-via(both Vx and Vy) and top via
Not Allowed
Not Allowed
Vy(2XTM)
Not allowed except the Mx or My
layer (one layer only) directly
Inter-metal layer (Mx/My)
Allowed
below [Mz, Mr or Mu],
ACTIVE device, ACTIVE OD/PO
Not Allowed
Not Allowed
and interconnection OD/PO
Protection ring and LOWMEDN
Required
Not Required
DM1, DMx, DMy,
DMz, DMr and DMu
YES
NO
Allowed
Allowed
Allowed
Not Required
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whole or in part without prior written permission of TSMC.
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4.5.45.1
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
INDDMY Layer Identified Inductor Layout Rules
 For eddy current reduction to achieve better inductor performance, a special metal (and OD/PO) dummy block layer
called “INDDMY” (CAD layer: 144) is offered to allow very low metal density within an inductor, provided a proper
surrounding (dummy) metal scheme requirement is satisfied. When an “INDDMY” layer is used to construct inductors,
one must follow the additional process-related design rules listed below. Please note that “INDDMY” can only be used
for inductor devices, TSMC does not support non-inductor devices constructed with “INDDMY”.
 Inductor devices offered in TSMC PDK can fit the design rules listed below.
 For the INDDMY layer identified low metal density inductor regions, the inter-via (both Vx and Vy) and top via Vy
(2XTM) are all not allowed. Please refer to the rules below for details.
Rule No.
IND.W.1
IND.W.2
IND.W.3
IND.W.4
IND.W.5
IND.W.6
IND.W.7
IND.W.8
IND.W.9
IND.W.10
IND.S.1
IND.S.2
IND.S.3
IND.S.4
IND.S.5
IND.S.6
IND.S.7
IND.S.8
IND.S.9
IND.S.10
IND.R.1
IND.R.2
IND.R.3
IND.R.4
IND.R.5
IND.R.6U
IND.R.7U
IND.R.8
Description
Label
M1, DM1, DM1_O width in (INDDMY SIZING 16 µm)
A1
Mx, DMx, DMx_O width in (INDDMY SIZING 16 µm)
A2
My, DMy width in (INDDMY SIZING 16 µm)
A3
Mz, DMz width in (INDDMY SIZING 16 µm)
A4
Mr, DMr width in (INDDMY SIZING 16 µm)
A5
Mu, DMu width in (INDDMY SIZING 16 µm)
A6
M1, DM1, DM1_O/Mx, DMx, DMx_O maximum width in (INDDMY SIZING 16 µm)
B1
My, DMy maximum width inside (INDDMY SIZING 22 µm) (for inductor application only)
B2
Mz, DMz/Mr, DMr/Mu, DMu maximum width inside (INDDMY SIZING 22 µm) (for inductor application only)
B3
Maximum dimension (either width or length) of an INDDMY region
C
M1, DM1, DM1_O space in (INDDMY SIZING 16 µm)
D1
Mx, DMx, DMx_O space in (INDDMY SIZING 16 µm)
D2
My, DMy space in (INDDMY SIZING 16 µm)
D3
Mz, DMz space in (INDDMY SIZING 16 µm)
D4
Mr, DMr space in (INDDMY SIZING 16 µm)
D5
Mu, DMu space in (INDDMY SIZING 16 µm)
D6
M1, DM1, DM1_O/Mx, DMx, DMx_O/My, DMy/Mz, DMz space in (INDDMY SIZING 16 µm) [at least one metal
E1
line width > 1.5 µm (W1) and the parallel metal run length > 1.5 µm (L1)]
Mr, DMr space in (INDDMY SIZING 16 µm) [at least one metal line width > 1.5 µm (W2) and the parallel metal
E2
run length > 1.5 µm (L2)]
My, DMy/Mz, DMz/Mr, DMr space in (INDDMY SIZING 16 µm) [at least one metal line width > 4.5 µm (W3) and
E3
the parallel metal run length > 4.5 µm (L3)]
Mu, DMu space in (INDDMY SIZING 16 µm) [at least one metal line width > 12 µm (W4) and the parallel metal
E4
run length > 12 µm (L4)]
In the region of (INDDMY SIZING 16 µm), inter-via Vx, Vy and top via Vy (2XTM) are all not allowed. (Except
TLDMY region and Vx in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)})
At leastfour VIAz with space  1.7 µm are required to connect [two Mz layers], [Mz to inter-My] or [Mz to Mx] in
I1
(INDDMY SIZING 16 µm).
At leastfour VIAu with space  1.7 µm are required to connect [Mu to Mz], [Mu to inter-My], [Mu to top My
I2
(2XTM)] or [Mu to Mx] in (INDDMY SIZING 16 µm).
At leastfour VIAr with space  1.7 µm are required to connect [two Mr layers] or [Mr to Mx] in (INDDMY SIZING
I3
16 µm)
In the INDDMY identified region “a”, except the inter-metal Mx or My layer (one layer only) directly below [top
My, Mz, Mr or Mu], any other inter-metal layer (Mx/My) is not allowed. (e.g. for a 1P6M process with 0.9 µm of
M6 (Mz), then Mx of M5 is allowed, but other lower Mx metal layers are not allowed for the INDDMY identified
inductor.) (Except TLDMY region and Mx in {(LOWMEDN NOT (LOWMEDN SIZING -5 µm)) INTERACT VIAx
bar})
In the INDDMY identified region “a”, except the needed patterns for inductor structure itself (such as OD, PO,
PP, CO, M1, VIAz, Mz,…), any active device, active OD/PO, interconnection OD/PO or resistance sensitive
metal routing is not allowed. (This rule cannot be checked by DRC.)
In the ring region “b” of {(INDDMY SIZING 16µm) NOT INDDMY} with 16 µm in width, except the straight metal
line (metal port leading) that connects the inductor to the circuits outside INDDMY region and the needed
patterns for inductor structure itself (such as OD, PP, CO and M1 for guard-ring…), any active device, active
OD/PO, interconnection OD/PO or resistance sensitive metal routing is not allowed in this region. The metal port
leading is defined as the metal line that goes through the region “a” and 16 µm wide ring region “b” for
interconnect. (This rule cannot be checked by DRC.)
A 45-degree rotated RV is allowed inside (INDDMY SIZING 22 µm)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.
















Rule
0.28
0.28
0.40
0.40
0.55
2.0
4.5
12.00
30.00
600.00
0.28
0.28
0.40
0.40
0.55
1.0

0.5

0.65

1.5

2.0

1.70

1.70

1.70
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Rule No.
IND.R.9U
IND.DN.1
IND.DN.2
IND.DN.3
IND.DN.5U
IND.DN.7
IND.DN.8®
IND.DN.9®
IND.R.10
IND.R.14
IND.R.15gU
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Label
Guard-ring enclosure of inductor metal spirals.
1. The larger distance (such as 50 µm) from inductor metal spirals to guarding-ring would make better inductor
electrical performance and reduce the coupling on/between components nearby. Please take the impact of the
guard-ring enclosure of inductor metal spirals into consideration.
2. Keep the INDDMY regions of separate inductors located as uniform as possible over the whole chip area to
maintain CMP uniformity.
Maximum density of {(INDDMY OR INDDMY_MD) OR TLDMY} on a whole chip
Maximum M1/Mx/Inter-My density within (INDDMY SIZING 16 µm) in window 125 µm x 125 µm, stepping 62.5
µm
M1/Mx/My/Mz/Mr metal density over the whole chip (include INDDMY)
The metal density difference between any two neighboring checking windows including DMxEXCL (window 200
µm x 200 µm, stepping 200 µm). Anticipate metal density gradient from layout of small cell by targeting density
~60% (this way, it will limit the risk of low density and high gradient.)
Maximum density of (INDDMY OR INDDMY_MD) in window 1600 µm x 1600 µm, stepping 800 µm
Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY
Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY
A 0.01um checking tolerance is allowed for the rules: IND.W.1, IND.W.2, IND.W.3, IND.W.4, IND.W.5, IND.W.6,
IND.W.7, IND.W.8, IND.W.9, IND.W.10, IND.S.1, IND.S.2, IND.S.3, IND.S.4, IND.S.5, IND.S.6, IND.S.7,
IND.S.8, and IND.S.9.
A 0.01 μm checking tolerance in the region of [INDDMY SIZING 22 μm] is allowed for the rules of RV.W.1,
RV.S.1, RV.EN.1, AP.W.1, AP.W.2, AP.S.1, and AP.EN.1.
Note: DRC implement 0.01 μm tolerance on Vertical, Horizontal and 45-degree bent.
Recommend putting NT_N to fully cover the inductor (metal) region to achieve high quality factor.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.
Rule

5%

85%

20%

60%



14%
20%
15%
209 of 600
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Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Table Notes:
1.
The INDDMY layer blocks the automated dummy pattern generation.
2.
The dummy generation utility inserts floating dummy OD/PO/metal patterns into the region outside INDDMY.
3.
For TSMC PDK offered inductor, a native substrate region is created under the inductor coil to minimize eddy
currents. This region is specified/implemented by the implant blocking NT_N layer (CAD layer:11). The NT_N
drawn layer adds no process cost and no extra mask.
4.
TSMC offered PDK inductor is an octagonal type, the square type inductor in the following figure is only for rule
illustration.
5.
If designers want to design the inductors with inter-layer metal and/or inter-layer via, all the related regular logic
design rules must be followed well, especially for the inter-layer metal density rules.
6.
For an inductor to be inserted into dummy OD/PO/Metal patterns , the INDDMY dummy layer should be removed
to allow the dummy utility’s dummy pattern generation.
7.
Please put in as many vias as possible for reliability and RF applications for IND.R.2, IND.R.3 and IND.R.4.
8.
The following inductor rule description is based on the concept of different regions (a and b) from center to edge to
achieve the flexibility of design easiness and maintaining density for uniformity. See the following figure.
9.
IND.DN.8® and IND.DN.9® : Inductor PDK has already added OD/PO into INDDMY.
10. It is important to refer to section 4.5.32, LOWMEDN Layout Rules, for the usage of inductor with protection ring.
1 6 u m (r e g io n “ b ” )
IN D D M Y
M e ta l
IN D D M Y
IN D .S .7 ~ 1 0
In d u c to r (m e ta l)
C o r e c ir c u it
A /B
D
> L 1 /L 2 /L 3 /L 4
E 1 /E 2 /E 3 /E 4
R e g i o n " a” "
> W 1 /W 2 /W 3 /W 4
16um
M e ta l p o r t le a d in g :
1 61 6 u m ( r e g i o n “ b ” )
C : M a x im u m d im e n s io n o f IN D D M Y
m e ta l c o n n e c ts th e in d u c to r
to c ir c u its o u ts id e IN D D M Y .
1 6 u m (r e g io n “ b ” )
D u m m y g e n e r a tio n u tility in s e r ts flo a tin g d u m m y
O D /P O /M e ta l p a tte r n s in to th e r e g io n o u ts id e IN D D M Y .
R e g io n “ b ” w ith 1 6 u m in w id th
Figure 4.5.45.1
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.45.2
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
INDDMY_MD Layer Identified Inductor Layout
Rules
For better process uniformity and reliability, a special dummy layer called “INDDMY_MD” (CAD layer: 144;42)
is offered to generate specific dummy metal (DM1 and DMx) and DOD/DPO within INDDMY_MD. When
“INDDMY_MD” layer is used to construct inductors, one must follow the additional process-related design rules
listed below. Please be noted that “INDDMY_MD” can only be used for inductor devices, and TSMC does not
support for non-inductor devices constructed with “INDDMY_MD ”. Please take care the SPICE model /LVS
flow by yourselves when using INDDMY_MD layer to design inductor.
Rule No.
IND_MD.W.1
IND_MD.W.2
IND_MD.W.3
IND_MD.W.4
IND_MD.W.5
IND_MD.W.6
IND_MD.W.7
IND_MD.W.8
IND_MD.W.9
IND_MD.W.10
IND_MD.S.1
IND_MD.S.2
IND_MD.S.3
IND_MD.S.4
IND_MD.S.5
IND_MD.S.6
IND_MD.S.7
IND_MD.S.8
IND_MD.S.9
IND_MD.S.10
IND_MD.R.1
IND_MD.R.2
IND_MD.R.3
IND_MD.R.4
IND_MD.R.5
IND_MD.R.6U
IND_MD.R.7U
Description
Label
M1, DM1, DM1_O width in (INDDMY_MD SIZING 16 µm)
A1
Mx, DMx, DMx_O width in (INDDMY_MD SIZING 16 µm)
A2
My, DMy width in (INDDMY_MD SIZING 16 µm)
A3
Mz, DMz width in (INDDMY_MD SIZING 16 µm)
A4
Mr, DMr width in (INDDMY_MD SIZING 16 µm)
A5
Mu, DMu width in (INDDMY_MD SIZING 16 µm)
A6
M1, DM1, DM1_O/Mx, DMx, DMx_O maximum width in (INDDMY_MD SIZING 16 µm)
B1
My, DMy maximum width inside (INDDMY_MD SIZING 22 µm) (for inductor application only)
B2
Mz, DMz/Mr, DMr/Mu, DMu maximum width inside (INDDMY_MD SIZING 22 µm) (for inductor application
B3
only)
Maximum dimension (either width or length) of an INDDMY_MD region
C
M1, DM1, DM1_O space in (INDDMY_MD SIZING 16 µm)
D1
Mx, DMx, DMx_O space in (INDDMY_MD SIZING 16 µm)
D2
My, DMy space in (INDDMY_MD SIZING 16 µm)
D3
Mz, DMz space in (INDDMY_MD SIZING 16 µm)
D4
Mr, DMr space in (INDDMY_MD SIZING 16 µm)
D5
Mu, DMu space in (INDDMY_MD SIZING 16 µm)
D6
M1, DM1, DM1_O/Mx, DMx, DMx_O/My, DMy/Mz, DMz space in (INDDMY_MD SIZING 16 µm) [at least
E1
one metal line width > 1.5 µm (W1) and the parallel metal run length > 1.5 µm (L1)]
Mr, DMr space in (INDDMY_MD SIZING 16 µm) [at least one metal line width > 1.5 µm (W2) and the
E2
parallel metal run length > 1.5 µm (L2)]
My, DMy/Mz, DMz/Mr, DMr space in (INDDMY_MD SIZING 16 µm) [at least one metal line width > 4.5 µm
E3
(W3) and the parallel metal run length > 4.5 µm (L3)]
Mu, DMu space in (INDDMY_MD SIZING 16 µm) [at least one metal line width > 12 µm (W4) and the
E4
parallel metal run length > 12 µm (L4)]
In the region of (INDDMY_MD SIZING 16 µm), inter-via Vx, Vy and top via Vy (2XTM) are all not allowed.
(Except TLDMY region and Vx in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)})
At least four VIAz with space  1.7 µm are required to connect [two Mz layers], [Mz to inter-My] or [Mz to
Mx] in (INDDMY_MD SIZING 16 µm).
At least four VIAu with space  1.7 µm are required to connect [Mu to Mz], [Mu to inter-My], [Mu to top My
(2XTM)] or [Mu to Mx] in (INDDMY_MD SIZING 16 µm).
At least four VIAr with space  1.7 µm are required to connect [two Mr layers] or [Mr to Mx] in (INDDMY_MD
SIZING 16 µm)
In the INDDMY_MD identified region “a”, except the Mx or My layer (one layer only) directly below [Mz, Mr
or Mu], any other inter-metal layer (Mx/My) is not allowed. (e.g., for a 1P6M process with 0.9 µm of M6
(Mz), then Mx of M5 is allowed, but other lower Mx metal layers are not allowed for the INDDMY_MD
identified inductor.)
Except the following condition:
1. TLDMY region
2. Mx in {{LOWMEDN NOT {LOWMEDN SIZING –5 μm}} INTERACT VIAx bar}
3. Inter-metal Mx in INDDMY_MD is allowed if the metal density of all M1/Mx layer in region "a" are all
larger than 10% in window 125um x 125um, stepping 62.5um (M1.DN.1 and Mx.DN.1)
4. Inter-metal My in INDDMY_MD is allowed if the metal density of all M1/Mx/My layer in region "a" are all
larger than 10% in window 125um x 125um, stepping 62.5um (M1.DN.1, Mx.DN.1 and My.DN.1)
In the INDDMY_MD identified region “a”, except the needed patterns for inductor structure itself (such as
OD, PO, PP, CO, M1, VIAz, Mz,…), any active device, active OD/PO, interconnection OD/PO or resistance
sensitive metal routing is not allowed. (This rule cannot be checked by DRC.)
In the ring region “b” of {(INDDMY_MD SIZING 16µm) NOT INDDMY_MD} with 16 µm in width, except the
straight metal line (metal port leading) that connects the inductor to the circuits outside INDDMY_MD region
and the needed patterns for inductor structure itself (such as OD, PP, CO and M1 for guard-ring…), any
active device, active OD/PO, interconnection OD/PO or resistance sensitive metal routing is not allowed in
this region. The metal port leading is defined as the metal line that goes through the region “a” and 16 µm
wide ring region “b” for interconnect. (This rule cannot be checked by DRC.)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.








Rule
0.28
0.28
0.40
0.40
0.55
2.0
4.5
12.00

30.00







600.00
0.28
0.28
0.40
0.40
0.55
1.0

0.5

0.65

1.5

2.0
211 of 600
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Rule No.
IND_MD.R.8
IND_MD.R.9U
IND_MD.DN.1
IND_MD.DN.2
IND_MD.DN.3
IND_MD.DN.5U
IND_MD.DN.7
IND_MD.DN.8®
IND_MD.DN.9®
IND_MD.R.10
IND_MD.R.14
IND_MD.R.15gU
IND_MD.R.18
IND_MD.R.19
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Label
A 45-degree rotated RV is allowed inside (INDDMY_MD SIZING 22 µm)
Guard-ring enclosure of inductor metal spirals.
1. The larger distance (such as 50 µm) from inductor metal spirals to guarding-ring would make better
inductor electrical performance and reduce the coupling on/between components nearby. Please take
the impact of the guard-ring enclosure of inductor metal spirals into consideration.
2. Keep the INDDMY_MD regions of separate inductors located as uniform as possible over the whole chip
area to maintain CMP uniformity.
Maximum density of {INDDMY_MD OR TLDMY OR INDDMY} on a whole chip
Maximum M1/Mx/Inter-My density within (INDDMY_MD SIZING 16 µm) in window 125 µm x 125 µm,
stepping 62.5 µm
M1/Mx/My/Mz/Mr metal density over the whole chip (include INDDMY_MD OR INDDMY)
The metal density difference between any two neighboring checking windows including DMxEXCL (window
200 µm x 200 µm, stepping 200 µm). Anticipate metal density gradient from layout of small cell by targeting
density ~60% (this way, it will limit the risk of low density and high gradient.)
Maximum density of (INDDMY_MD OR INDDMY) in window 1600 µm x 1600 µm, stepping 800 µm
Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY_MD
Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY_MD
A 0.01um checking tolerance is allowed for the rules: IND_MD.W.1, IND_MD.W.2, IND_MD.W.3,
IND_MD.W.4, IND_MD.W.5, IND_MD.W.6, IND_MD.W.7, IND_MD.W.8, IND_MD.W.9, IND_MD.W.10,
IND_MD.S.1, IND_MD.S.2, IND_MD.S.3, IND_MD.S.4, IND_MD.S.5, IND_MD.S.6, IND_MD.S.7,
IND_MD.S.8, IND_MD.S.9 and IND_MD.S.10.
A 0.01 μm checking tolerance in the region of [INDDMY_MD SIZING 22 μm] is allowed for the rules of
RV.W.1, RV.S.1, RV.EN.1, AP.W.1, AP.W.2, AP.S.1, and AP.EN.1.
Note: DRC implement 0.01 μm tolerance on Vertical, Horizontal and 45-degree bent.
Recommend putting NT_N to fully cover the inductor (metal) region to achieve high quality factor.
INDDMY overlap with (INDDMY_HD OR INDDMY_MD) is not allowed.
INDDMY_HD overlap with INDDMY_MD is not allowed.
Op.
Rule

5%

85%

20%

60%



14%
20%
15%
IND_MD.R.15gU
Table Notes:
1. Special inductor dummy utility provides an option to auto-generate specific dummy metal (DM1 and DMx)
and DOD/DPO within INDDMY_MD to lower the inductor performance degradation caused by dummy fill.
The real inductor performance impact by the extra-added dummy pattern must be taken care by designers.
2. Inductor with protection ring and LOWMEDN is not required.
3. Please put in as many vias as possible for reliability and RF applications for IND_MD.R.2, IND.R_MD.3
and IND_MD.R.4
4. The following inductor rule description is based on the concept of different regions (a and b) from center to
edge to achieve the flexibility of design easiness and maintaining density for uniformity. See the following
figure.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: T-N45-CL-DR-001
: 2.6
Figure 4.5.45.2
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.45.3
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
INDDMY_HD Layer Identified Inductor Layout
Rules
For better process uniformity and reliability, a special dummy layer called “INDDMY_HD” (CAD layer:
144;43) is offered to generate specific dummy metal (DM1, DMx, DMy, DMz, DMr and DMu) and DOD/DPO
within INDDMY_HD to lower the inductor performance degradation caused by dummy fill. The real inductor
performance impact by the extra-added dummy pattern must be taken care by designers. Please be noted that
“INDDMY_HD” can only be used for inductor devices, and TSMC does not support for non-inductor devices
constructed with “INDDMY_HD ”. Please take care the SPICE model /LVS flow by yourselves when using
INDDMY_HD layer to design inductor.
All the layout rules for Inductors identified with INDDMY_HD follow general logical rules, for example, to
follow 10% minimum metal density rule in INDDMY_HD.
Table Notes:
1. For the INDDMY_HD layer identified inductor region, the inter-via(both Vx and Vy) and top via Vy(2XTM)
are allowed on the premise that all the related logic design rules has been followed well.
2. Inductor with protection ring and LOWMEDN is not required.
3. When other device, patterns or metal routing are put within INDDMY_HD, the extra parasitic, device
couplings and model accuracy issue also must be taken into consideration by designers.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
4.5.46
Introduction of Inductor and Transmission Line
4.5.46.1
INDDMY Layer Identified TSMC PDK Inductor
Introduction
TSMC offered a variety of ways to construct inductor devices for RF/MS circuit design need:
1. To achieve lower inductor series resistance, a thickness larger than 3 µm ultra thick Cu metal (Mu) process
is offered and its associated process design rule is listed in the section 4.5.46.1.
2. In section 4.5.46.1 below, we used the inductor offered in TSMC PDK as examples to briefly illustrate the
basic guidelines and elements for constructing various inductors such as standard (simple spiral),
symmetric and center-tap inductors.
4.5.46.1.1 Introduction to PDK Inductor
1. TSMC PDK offered octagonal inductor varieties in the 45nm/40nm technology node mainly include three
different layout configurations for different top metal schemes (as summarized in the section of RTMOM
(Rotated Metal Oxide Metal)): standard (STD), symmetric (SYM) and center-tap (CT).
2. The offered inductors are fabricated on top of P-substrate that specified/implemented by an NT_N
implantation-blocking layer (CAD layer:11, that adds no extra mask/process cost). The offered inductor is 3Terminal including two signal terminals and the third terminal for grounded guard-ring (Center-tap inductor
has the fourth terminal for center-tap connection).
3. The INDDMY dummy layer(s) (CAD layer:144) is needed to identify the inductor with very low metal density
within the inductor, the DRC (design rule check) deck will check the INDDMY identified region by inductor
related/specific rules (the section of INDDMY Layer Identified Inductor Layout Rules). The INDDMY layer
cannot be used for other applications (for inductor only), and allowed maximum density of INDDMY in
whole chip is 5% (rule IND.DN.1).
4. The INDDMY dummy layer blocks the automated generation of dummy OD/PO/Metal patterns (dummy AlRDL patterns will not be generated).
5. The dummy OD/PO/Metal patterns make better pattern uniformity and better metal CMP uniformity over the
silicon wafer.
6. From the inductor model accuracy point of view, other devices or metal patterns is not allowed to be placed
below/above the offered inductors, as the magnetic flux and the resulted inductor performance will be
affected by the extra-added parts. If other devices, patterns or metal routing (not generated by PDK itself)
are added into the region below/above the PDK inductor, the resulted extra parasitic and model inaccuracy
must be taken into consideration by designers.
7. Table 4.5.46.2 shows the TSMC PDK inductor layout parameters. The corresponding temperature effect
and corner cases are also included; please refer to the model documents for model scope and other details.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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S ta n d a rd
S y m m e tr ic
C e n te r-T a p
P o rt2
P o rt1
P o rt2
P o rt1
N=3
N=3
N = 3 .5
: T-N45-CL-DR-001
: 2.6
G D IS
2R
P o rt1
W
G D IS
P o rt2
2R
2R
s
IN D D M Y e d g e
CT
GND
GND
GND
Figure 4.5.46.1 PDK inductor top-view illustration
Table 4.5.46.1 TSMC offered three kinds of Mz, Mz+Mu, Mu inductor structure options
T o p M e ta l S c h e m e
Type
S p ir a l C o il
C ro s s P a s s
Mz
s p ir a l_ s td _ m z _ a
Nam e
STD
M z ( M to p )
M z ( M to p ) / A L - R D L
C ta p
Mz
s p ir a l_ s y m _ m z _ a
SYM
M z ( M to p )
M z ( M to p ) / A L - R D L
Mz
s p ir a l_ s y m _ c t_ m z _ a _ x
CT
M z ( M to p )
M z ( M to p ) / A L - R D L
Mz
s p ir a l_ s td _ m z a _ a
STD
M z ( M to p ) / / A L - R D L
M z ( M to p ) / A L - R D L
Mz
s p ir a l_ s y m _ m z a _ a
SYM
M z ( M to p ) / / A L - R D L
M z ( M to p ) / A L - R D L
Mz
s p ir a l_ s y m _ c t_ m z a _ a _ x
CT
M z ( M to p ) / / A L - R D L
M z ( M to p ) / A L - R D L
Mz
s p ir a l_ s y m _ m z _ a x
SYM
M z ( M to p )
M z ( M to p ) / [ M x ( M to p -1 ) / / A L - R D L ]
Mz
M x ( M to p -1 )
M x ( M to p -1 )
s p ir a l_ s y m _ c t_ m z _ a x _ a
CT
M z ( M to p )
M z ( M to p ) / [ M x ( M to p -1 ) / / A L - R D L ]
Mz + Mz
s p ir a l_ s td _ m 2 z a _ z a
STD
M z ( M to p -1 ) / / M z ( M to p ) / / A L - R D L
[ ( M z ( M to p ) / / A L - R D L ] / M z ( M to p -1 )
Mz + Mz
s p ir a l_ s y m _ m 2 z a _ z
SYM
M z ( M to p -1 ) / / M z ( M to p ) / / A L - R D L
M z ( M to p ) / M z ( M to p -1 )
Mz + Mz
s p ir a l_ s y m _ c t_ m 2 z a _ z _ a
CT
M z ( M to p -1 ) / / M z ( M to p ) / / A L - R D L
M z ( M to p ) / M z ( M to p -1 )
Mu
s p ir a l_ s td _ m u _ x
STD
M u ( M to p )
M u / M x ( M to p -1 )
Mu
s p ir a l_ s y m _ m u _ x
SYM
M u ( M to p )
M u / M x ( M to p -1 )
Mu
s p ir a l_ s y m _ c t_ m u _ x _ a
CT
M u ( M to p )
M u / M x ( M to p -1 )
Mz + Mu
s p ir a l_ s td _ m u _ z
STD
M u ( M to p )
M u / M z ( M to p -1 )
Mz + Mu
s p ir a l_ s y m _ m u _ z
SYM
M u ( M to p )
M u / M z ( M to p -1 )
Mz + Mu
s p ir a l_ s y m _ c t_ m u _ z _ x
CT
M u ( M to p )
M u / M z ( M to p -1 )
A L -R D L
A L -R D L
A L -R D L
M x ( M to p -2 )
Table 4.5.46.2 TSMC offered inductor structure geometry parameters
W (w )(u m )
s p ir a l tr a c k w id th
N (n r)
n u m b e r o f tu rn s
R (ra d )(u m )
in n e r r a d iu s
S (s p a c in g )(u m )
s p a c in g o f s p ir a l tr a c e s
G D IS (g d is )(u m )
d is ta n c e fr o m s p ir a l o u te r e d g e to [g u a r d -r in g o u te r e d g e + 2 .5 u m )]
C T a p W (c ta p w )(u m )
C T a p L a y (c ta p la y )(u m )
1 P x M (la y )
r a tio o f c e n te r -ta p w id th o v e r s p ir a l tr a c k w id th
c e n te r -ta p s ta c k la y e r n u m b e r (s )
to p m e ta l la y e r
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.46.2
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
TLDMY Layer Identified TSMC PDK T-line
Introduction
TSMC offered a variety of ways to construct transmission line (T-line) devices for RF/MS circuit design need:
1. To achieve lower T-line series resistance, a thickness larger than 3 µm ultra thick Cu metal (Mu) process is
offered. Since a T-line structure will be regarded as another type of inductors and its associated process
design rule is listed in the section 4.5.45.
2. We used the T-line offered in TSMC PDK as examples to briefly illustrate the basic guidelines and elements
for constructing various T-lines such as coplanar waveguide (CPW), and microstrip lines (MS).
4.5.46.2.1 Introduction to PDK T-line
1. TSMC PDK offered two T-line configurations, including coplanar waveguide (CPW), and microstrip lines
(MS), as shown in Figure 4.5.46.2.
2. The offered T-lines are fabricated on top metal, and are 3-terminal devices including two signal terminals
and the third grounded terminal.
3. The INDDMY dummy layer(s) (CAD layer: 144) is needed to identify the T-line with very low metal density
within the T-line, as illustrated in Figure 4.5.46.3. The DRC (design rule check) deck will check the INDDMY
identified region by inductor related/specific rules (the section of INDDMY Layer Identified Inductor Layout
Rules). The INDDMY layer cannot be used for other applications (for inductor and transmission line only),
and the allowed maximum density of INDDMY in whole chip is 5% (rule IND.DN.1).
4. The TLDMY dummy layer(s) (CAD layer: 116) is needed to identify the T-line as illustrated in Figure 4.5.46.3.
The DRC (design rule check) deck will check the TLDMY identified region by T-line rules. The TLDMY layer
cannot be used for other applications (for transmission line only).
5. The INDDMY dummy layer blocks the TSMC automated generation of dummy Metal patterns (TSMC utility
does not support dummy Al-RDL patterns). TSMC utility will insert dummy OD/PO patterns into INDDMY
regions, if neither ODBLK dummy layer nor POBLK dummy layer is drawn to overlap INDDMY and the
related switch is turned ON (default).
6. However, dummy OD/PO/Metal patterns should be taken care, since the dummy OD/PO/Metal patterns
make better pattern uniformity and better metal CMP uniformity over the silicon wafer.
7. From the T-line model accuracy point of view, other devices or metal patterns are not allowed to be placed
below/above the offered T-lines, as the magnetic flux and the resulted T-line performance will be affected by
the extra-added parts. If other devices, patterns or metal routing (not generated by PDK itself) are added
into the region below/above the PDK T-line, the resulted extra parasitic and model inaccuracy must be taken
into consideration by designers.
8. CPW and MS T-lines cannot share the same ground line and T-lines cannot overlap with each other. If the
customers violate the above recommendations, the designers must take the model inaccuracy into
consideration.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
9. Table 4.5.46.3 shows the TSMC PDK T-line layout parameters.
CPW
MS
Figure 4.5.46.2 PDK T-line schematic illustrations
IN D D M Y
CPW
TLDM Y
IN D D M Y
MS
TLDM Y
Figure 4.5.46.3 PDK T-line top-view illustrations
Table 4.5.46.3 TSMC offered transmission line structure geometry parameters
W id t h ( u m )
S ig n a l lin e w id t h
S p a c e ( u m ) S p a c in g b e t w e e n a s ig n a l lin e a n d g r o u n d lin e s
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.47
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
SRAM Rules
This section contains the SRAM truth tables for N40G/N45LP/N45LPG/N40LP/N40LP+/N40LPG.
The following provides a legend for the following SRAM truth table.
0 Restrict to use the layer inside its array.
1 Must contain the layer inside its array.
* Depends on LP/LP+/LPG and GS process
a. (186;4) is for LP/LP+/LPG and (186;5) is for GS.
b. For (50;1/2) usage in 0.374/0.741um^2 cells, GS process must contain (50;1/2) and LP/LPG
process is based on which cell you choose (with cell implant or without cell implant).
SRAM special layer truth table
Table 4.5.47.1 lists SRAM cells used in CLN45 official offering. Each individual cell should contain and restrict
those listed layers inside its array. Using HD 0.299um^2 array for example (Recognition layer: 80;14), it must
contain SRM;0 and restrice to SRM_RP inside 80;14. TSMC offering cells must meet to the layer usage in
truth table. Any violation is not allowed.
Please refer section 3.4 “Special Recognition CAD Layer Summary” for detailed special layer information.
Table 4.5.47.1 SRAM Truth Table in TSMC offering cells
Special Layer
Name
SRM;0
SRM;1
SRM;2
SRM_RP
ROM
SRAM_HS
NPreDOSRM
SRAMDMY;0
SRAMDMY;1
SRAMDMY;4 *
SRAMDMY;5 *
CO;11
DPSRM
PRSRM
SRM_UHD
SRM_HC
SRM_HD
SRM_LV
SRM_HCDP
SRM_8TTP
SRM_10TTP
DUMMYOD1
~
DUMMYOD16
TSMC
Default
CAD Layer
50;0
50;1
50;2
50;5
50;6
50;7
50;21
186;0
186;1
186;4
186;5
30;11
80;0
80;11
80;12
80;13
80;14
80;15
80;16
80;17
80;18
82;1
82;2
82;3
82;4
82;5
82;6
82;7
82;8
82;9
82;10
82;11
82;12
82;13
82;14
82;15
82;16
DRC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Tape out
required layer
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
HD
0.299um^2
80;14
1
1
1
0
0
0
1
1
1
0
0
1
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
HC
0.374um^2
80;13
1
1/0*
1/0*
0
0
0
1
1
1
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
DP
0.589um^2
80;0
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
HCDP
0.741um^2
80;16
1
1/0*
1/0*
0
0
0
1
1
1
0
0
1
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
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Special Layer
Name
DUMMYPO1
~
DUMMYPO7
CO2
IP
RODMY
Document No.
Version
Confidential – Do Not Copy
TSMC
Default
CAD Layer
83;1
83;2
83;3
83;4
83;5
83;6
83;7
100;0
63;63
49;0
DRC
Tape out
required layer
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
HD
0.299um^2
80;14
1
1
1
1
1
0
1
1
1
1
V
: T-N45-CL-DR-001
: 2.6
HC
0.374um^2
80;13
1
1
1
1
1
0
1
1
1
1
DP
0.589um^2
80;0
1
1
1
1
1
0
1
1
1
1
HCDP
0.741um^2
80;16
1
1
1
1
1
0
1
1
1
1
Mask information

N45LP/LPG-LP: NCI SRAM PMOS follows core-PMOS LVT setting. If no core-PMOS LVT in the mask
tape out, there will need additional PLDD mask for SVT-PMOS delta-dose (11C).

N40G (0.9V) and N40GL (0.8V):
● 11C is a must if N40G 0.9V and N40GL 0.8V SRAM cells are both used.
● The mix run of the same SRAM cells is forbidden (For example, N40G HC and N40GL HC), i.e. the
same SRAM cell of N40G and N40GL cannot co-exist in one chip. Please refer to the following table in
details.
N40G (0.9V)
N40G and N40GL SRAM Cell
D299 (HD)
D374 (HC)
D589 (DP)
D741 (HCDP)
D374 (HC)
O
X
O
O
D741 (HCDP)
O
O
O
X
N40GL (0.8V)
Note:
O: Can co-exist in one chip.
X: Can NOT co-exist in one chip.
Warning: There are two ways for SRAM design.
1. Use TSMC standard SRAM array. None of FEOL and BEOL layouts for TSMC
SRAM is allowed to be changed (SRAM.R.1U).
2. Complying with the logic rules and using logic SPICE model to design SRAM
are only allowed when you want to design SRAM cell by yourself (SRAM.R.2U).
Warning: You can’t design SRAM layout just by complying with the following the rules. The
SRAM rules in this document are used to prevent unexpected layout errors during
macro or chip implementation, but not used for SRAM design.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Rule No.
SRAM.W.1
SRAM.S.1
SRAM.S.2
SRAM.BTC.S.1
SRAM.BTC.S.2
SRAM.BTC.S.3
SRAM.EN.1
SRAM.EN.2
SRAM.EX.1
SRAM.A.1
SRAM.O.1
SRAM.R.1U
SRAM.R.2U
SRAM.R.5U
SRAM.R.6U
SRAM.R.7U
SRAM.R.12
SRAM.R.13
SRAM.R.14
SRAM.R.15
SRAM.R.16U
SRAM.R.17
SRAM.R.19
SRAM.R.20
SRAM.R.21
SRAM.R.22
SRAM.R.23
SRAM.R.24
SRAM.R.25
SRAM.R.26
SRAM.R.27
SRAM.R.28
SRAM.R.29
SRAM.R.30U
SRAM.R.31
SRAM.R.32
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
SRM width. The SRM edge should be aligned to the boundary of the cell array, which may include storage,
strapping, and dummy edge cells.
SRM space
SRM space to {GATE NOT INTERACT SRM}
BTC space [different nets]
BTC space to M1 [different nets]
BTC space to CO [different nets]
SRM enclosure of GATE in S/D direction.
SRM enclosure of GATE in PO endcap direction.
SRM extension on NW (INTERACT with OD). Extension = 0 is allowed.
SRM;0 (50;0) Area
SRM overlap of NW (INTERACT with OD) (for VTC_N, VTC_P). Extension = 0 is allowed.
TSMC SRAM array is forbidden to be changed: It is required to use the standard TSMC SRAM array
including edge cells, strap cells, and etc. None of FEOL and BEOL layouts for TSMC SRAM is allowed to
be changed.
Customer-designed SRAM cell designed by logic rules: Complying with logic rules (186;0 and 50;0
can’t be used) and using logic SPICE model to design SRAM are only allowed when you want to design
SRAM cell by yourself.. For the SRAM layout designed by logic rules, it must be review by TSMC’s PE.
[Customer's product: need silicon to verify its function, performance, speed and Vccmin before product
tape-out.]
Array delay-tracking bit cells: This kind of bit cell should be embedded inside an array. If a delay-tracking
cell is to be placed outside an array, it should be fully surrounded by dummy bit cells.
Dummy layouts for embedded SRAM: To minimize proximity and loading effects during processing, you
must add dummy layouts to provide a similar surrounding for every cell.
To add dummy layouts, please refer to SRAM cell layout documents listed in section 1.2, Reference
Document, for the guidelines and GDS examples. Those documents provide instructions for adding
dummy layouts in both columns and rows, at array edges, and at the connection/tap in-between arrays.
SRAMDMY;5 (186;5)/ SRAMDMY;4 (186;4): Can only use in the word-line driver of TSMC SRAM. This
layer is only to waive CO.S.3 and G.1.
SRAMDMY;5 (186;5)/ SRAMDMY;4 (186;4) overlap of SRAMDMY;0 (186;0) is not allowed.
SRM must fully cover GATE.
SRAMDMY;0 (186;0) is a must for any SRAM cell with rule pushed layout.
It waives SRAM DRC violations in {(SRAMDMY;0 (186;0) NOT RAM1TDMY (160;0))} as listed in table
4.5.47.2.
CO;11 (30;11) is a must for CO mask tape-out in SRAM. (Except RAM1TDMY (160;0) region)
1. If CO;11 exists, it must cover CO;0
2. CO;11 must be 0.06μm x 0.06μm
3. CO;11 must be exactly the same as CO;0.
4. CO;11 must be fully covered by SRM (50;0) and SRAMDMY;0 (186;0)
5. Square CO;0 in SRAM must cover CO;11 in 50;0 region
SRAM IP tag name and hierarchy should follow TSMC layout such as strap cell, strap_edge cell, column
edge cell and row edge cell. The detail is described in SRAM cell layout and model documents listed in
section 1.2, Reference Document.
SRAMDMY;0 (186;0) and SRM (50;0) must fully cover OD, CO, VIA1.
SRAM dummy layers can exist only in SRM (50;0) region. And in logic region, no SRAM dummy layer can
be used. SRAM dummy layers are listed below :
DMMYOD1~16, DUMMYPO1~7, SRM;1~2, NPreDOSRM, SRAMDMY;0~1, CO;11, CO2, DPSRM,
PRSRM, SRM_LOP;12~14, LV_LOP, HCDP_LOP, 8TTP_LOP and 10TTP_LOP.
Inside of SRAM array, SRM (50;0), SRAMDMY;0 (186;0) can not have any holes in them.
SRM (50;0) and SRAMDMY;0 (186;0) must be drawn identically (Except RAM1TDMY (160;0) region)
(80;x) must overlap PRSRM (80;11). x = 0, 12~18.
if PRSRM (80;11) interacts (80;x). It must be fully covered by (80;x). x = 0, 12~18.
(80;x) interact SRM (50;0) must be identical to SRM;0 (50;0), except SRM_LV (80;15) and SRM_8TTP
(80;17), x = 0, 12~18.
(80;x) can’t interact each other, x = 0, 12~18. Only SRM_LV (80;15) interacting with SRM_8TTP (80;17) is
allowed.
SRM;0 (50;0) must cover NMOS gate and PMOS gate at the same time.
DRC will check the following two conditions at the same time.
(1) {SRM NOT INTERACT (NP AND GATE)}
(2) {SRM NOT INTERACT (PP AND GATE)}
For GS, SRM;0(50;0) must include both SRM;1(50;1) and SRM;2(50;2).
For LP/LPG, {SRM;0(50;0) AND SRM_HD(80;14)} must include both SRM;1(50;1) and SRM;2(50;2).
For LPG, {SRM;0(50;0) AND DPSRM(80;0)} must include both SRM;1(50;1) and SRM;2(50;2).
The same SRAM cell for N40G and N40GL SRAM can not coexist in one chip.
At least two VIAx with space ≤ 0.14 μm (S1), or at least four VIAx with space ≤ 0.63 μm (S1') are required
to connect Mx and Mx+1 when one of these two metals has width and length > 0.3 μm (W1). [INSIDE
SRAMDMY;0 (186;0)]
At least two VIAx must be used for a connection that distance ≤ 1.14 μm (D) away from a metal plate
(either Mx or Mx+1) with length > 0.3 μm (L) and width > 0.3 μm (W). [INSIDE SRAMDMY;0 (186;0)]
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
Op.
Rule
A

0.19
B
C
S1
S2
S3
E
E1
D










0.19
0.14
0.090
0.055
0.067
0.14
0.09
0.19
11
0.19
F
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Rule No.
SRAM.R.33
SRAM.R.34
SRAM.R.35
SRAM.R.36
SRAM.R.37
SRAM.R.38
SRAM.R.39
SRAM.R.40
SRAM.R.41
SRAM.R.42
PO.R.7
SRAM.R.9gU
SRAM.R.11gU
SRAM.WARN.1
SRAM.WARN.2

Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
(80;X) must fully cover CO;11 (30;11), (50;0), (50;21),(82;Y); (83;Z), (186;0), (186;1), and (100;0).
X = 0,14,16.
Y = 1,2,9,10,11,12,16.
Z = 1,2,3,4,5,7.
(80;X) must not have SRM_RP (50;5), (50;7), (82;15), (83;6), (186;4), (186;5) x = 0, 13, 14, 16.
(80;X) must fully cover (82;Y). X = 0, 13, 14. Y = 3,4,5,6,7,8
(80;16) must not have (82;Y). Y = 3,4,5,6,7,8
No ROM (50;6) can be used in SRAM region (SRM(50;0)).
(80;X) must fully cover DUMMYOD13 (82;13) and DUMMYOD14 (82;14)
X = 0;14;16
(80;13) must not have DUMMYOD13 (82;13) and DUMMYOD14 (82;14)
(80;13) must fully cover CO;11 (30;11), (50;0), (50;21),(82;Y); (83;Z), (186;0), (186;1), and (100;0).
Y = 1,2,9,10,11,12,16
Z = 3,4,5,7.
NMOS gate in SRM (50;0) must be fully covered by NPreDOSRM (50;21) (Except RODMY (49;0) region)
BTC in NW in one unit cell must be a pair, except DPSRM (80;0), SRM_HCDP (80;16), and SRM_10TTP
(80;18) cells.
DRC only checks: {{{{BTC AND NW} NOT {{DPSRM OR SRM_HCDP} OR SRM_10TTP}} SIZING 0.05
μm} INTERACT BTC} = 2
Poly gates of all SRAM cells (50;0 OR 186;0) must be uni-directional in a chip.
(This check doesn’t include the regions covered by layer 49 (RODMY) and RAM1TDMY (160;0))
Chips on MPW or shuttles may be rotated due to this rule
Sense-amp and decoder redundancy: In addition to bit-row and/or bit-column redundancy design,
redundancy in peripheral array elements, such as sense amplifiers and decoders, is recommended.
Architectural efficiency can minimize the added overhead area entailed by this additional redundancy.
Peripheral element redundancy is especially important for high-density memory blocks.
Guardring: It is recommended to have an additional VSS (PW) guardring around the memory circuit block.
Warning: It is important to add different redundancies according to different memory densities, if the total
SRAM area for only N40GL (Vnom = 0.8V usage) in one chip is > 3,231,000um2 (e.g. 8Mb of N40GL
0.374um2 cell), or if the total SRAM area for all cells (including N40GL 0.8V usage) in one chip is >
5,168,000um2 (e.g. 16Mb of 0.299um2 cell).
Please refer to T-000-CL-RP-002, TSMC EMBEDDED SRAM REDUNDANCY IMPLEMENTATION RULE
AND ECC GUIDELINE, for the details.
DRC only flags the total SRM (50;0) area in one chip > 5,168,000um2.
Warning: It is important to add ECC (Error Correcting-Code), if the total SRAM area for all cells in one chip
is > 10,336,000μm2 (e.g. 32Mb of 0.299um2 cell).
Please refer to T-000-CL-RP-002, TSMC EMBEDDED SRAM REDUNDANCY IMPLEMENTATION RULE
AND ECC GUIDELINE, for the details.
DRC only flags the total SRM (50;0) area in one chip > 10,336,000μm2.
For ECC implementation, please consult TSMC QR based on product operation spec.
Label
Op.
Table 4.5.47.2 Rule List Waived by SRAMDMY;0 (186;0)
Layout Rule
Grid Rule
OD Layout Rule
NW Layout Rule
DCO Layout Rule
OD2 Layout Rule
PO Layout Rule
PP Layout Rule
NP Layout Rule
CO Layout Rule
M1 Layout Rule
Via1 Layout Rule
M2 Layout Rule
Via2 Layout Rule
M3 Layout Rule
Rule List Waived by SRAMDMY;0 (186;0)
G.4 for PP and NP layer only
OD.W.1, OD.W.2, OD.S.1, OD.S.3, OD.S.3.1, OD.A.1, and OD.A.2.
OD.S.1® , and OD.W.1®
NW.W.1, NW.S.6, NW.S.6.1, NW.EN.1, and NW.EN.2.
DCO.S.8, DCO.O.1
OD2.W.2
PO.W.6, PO.S.1, PO.S.4, PO.S.6, PO.EX.1, PO.EX.2, PO.EX.3, PO.S.2, and PO.S.2.1.
PO.S.1® , PO.S.2.LP® , PO.S.5.LP® , PO.S.5.GS® , PO.S.6.LP® , PO.S.6.GS® ,
PO.EX.1® , and PO.EX.2® Only waive PO.S.2.1.1, PO.EX.2.1 and PO.R.4 in RODMY
(49;0) region.
PP.S.1, PP.S.2, PP.EN.1, PP.EX.1, PP.EX.2, PP.A.1, and PP.R.1.
NP.W.1, NP.S.2, NP.S.4, NP.EX.1, NP.A.2, and NP.R.1.
CO.S.1, CO.S.2, CO.S.2.1, CO.S.3, CO.S.4, CO.EN.1, and CO.EN.0 for square CO
CO.W.1, CO.EN.1.1, CO.EN.1.3, and M1.EN.1 for butted CO only
CO.S.3® , CO.EN.1® , CO.EN.1.1® , CO.EN.3® , and CO.R.5g
M1.S.5, M1.EN.2, M1.EN.3, M1.EN.3.1, M1.EN.3.2, M1.A.1, and M1.A.2.
M1.S.1® , M1.A.1® , M1.EN.1® , M1.EN.2® , and M1.EN.5®
VIA1.R.2 and VIA1.R.4
VIA1.EN.1® ,and VIA1.EN.2®
M2.S.5, M2.A.1, and M2.A.2.
M2.S.1® , M2.A.1® , M2.EN.1® , and M2.EN.2®
VIA2.EN.1® , and VIA2.EN.2®
M3.S.1® , M3.A.1® , M3.EN.1® ,and M3.EN.2®
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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A
SR M
A
N W
SR M
SR M
B
N W
D
F
N W
C
<D
D
D
O D
SR M
E1
D
E
S R A M .R .1 7
SR M
SR M
<A
N P
E1
G
O D
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whole or in part without prior written permission of TSMC.
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SRAM cell array
Dummy layouts
Dummy layouts
Dummy layouts
SRAM cell array
Dummy layouts
Dummy layouts
S R A M .R .2 3
SRAM cell array
Dummy layouts
Dummy layouts
S R A M .R .2 2
SRAM cell array
Dummy layouts
Dummy layouts
: T-N45-CL-DR-001
: 2.6
Dummy layouts
Dummy layouts
Dummy layouts
Document No.
Version
Dummy layouts
Confidential – Do Not Copy
Dummy layouts
Dummy layouts
Dummy layouts
tsmc
S R A M .R .2 4
S R A M .R .2 5
M u s t b e d r a w n id e n tic a lly
(8 0 ; x )
5 0 ;0
8 0 ;x
80;x
8 0 ;1 7
(8 0 ;1 1 )
5 0 ;0
80;x'
5 0 ;0
X=0; 12~18
X=0, 12~18
e x c e p t (8 0 ;1 5 ) a n d (8 0 ;1 7 )
X’ =0, 12~18
8 0 ;1 5
X is n o t e q u a l to X ’
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whole or in part without prior written permission of TSMC.
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: 2.6
NPreDOSRM (50;21) Layout Rules
NPreDOSRAM is a drawn layer in SRAM region to generate N+ predoping mask (mask ID 196). The
NPreDOSRM (50;21) layout rules are nearly identical to NP layout rules. It exists only in SRM (50;0) region
and is forbidden in logic region. Neither changing NPreDOSRM of TSMC SRAM nor designing NPreDOSRM
by logic rules is allowed.
Warning: None of FEOL and BEOL layouts for TSMC SRAM is allowed to be changed. You
can’t design SRAM layout just by complying with the following the rules. The SRAM
rules in this document are used to prevent unexpected layout errors during macro
or chip implementation, but not used for SRAM design.
Rule No.
Description
Label
Op.
Rule
NPre.W.1
Width
A

0.2
NPre.S.1
Space
B

0.18
NPre.S.2
Space to P+ ACTIVE (non-butted)
C

0.08
NPre.S.3
Space to {P+ ACTIVE OR PW STRAP} (butted)
D

0
NPre.S.4
Space to PW STRAP (non-butted)
E

0.02
NPre.S.5
{NPre edge on OD} space to PMOS GATE
F

0.23
NPre.S.7
H

0.14
M

0.03
NPre.O.1
Space to P-type unsilicided OD/PO resistor
{NPre edge on OD} extension on NMOS GATE in SRM (50;0) (Except
RODMY (49;0) region)
Overlap of OD
N

0.01
NPre.A.1
Area
O

0.11
NPre.A.2
NPre.R.2
NPre.L.1
Enclosed area
Overlap of PP is not allowed.
45-degree edge length
P

0.11

0.5
NPre.EX.4
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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N P re D O S R M
R
PO
P
O
P
J
N P re D O S R M
N
P
A
N P re D O S R M
N P re D O S R M
+
P
OD
+
OD
B
P+
OD
I
E
D
I
I
I
M
N+
PO
N+
OD
I
PO
PO
OD
NW
PW
N ty p e
P lo y
r e s is to r
P
+
OD
J1
N P re D O S R M
PO
D
L
H
C
F
N
+
OD
P+
OD
P ty p e P lo y
r e s is to r
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whole or in part without prior written permission of TSMC.
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4.5.49
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: 2.6
SRAM Periphery (Word Line Driver) Rules
The following rules only apply to word line driver covered by SRAMDMY (186;5) or (186,4).
Rule No.
WLD.R.2
WLD.R.3
WLD.R.6
WLD.R.7
WLD.R.8
WLD.R.9
Description
Label
Op.
Rule
{CO AND SRAMDMY (186;4/5)} space to PO.
CO space on the same OD [(inside SRAMDMY;4 (186;4) or
SRAMDMY;5 (186;5)) and CO space to gate = 0.035um]
SRAMDMY (186;4/5) edge cut CO is not allowed.
SRAMDMY;0 (186;0) SIZING 100 μm must cover SRAMDMY;5 (186;5)
or SRAMDMY;4 (186;4)
Gate direction on the WL driver must be same as gate on the SRAM
(Unique direction)
At least 2 COs are required at both source and drain side on WL driver
(186;4/5) region
B

0.035

0.10
C O a rra y m x n
W o r d L in e D e c o d e r
S R A M D M Y (1 8 6 ;5 ) o r (1 8 6 ,4 )
OD
C O a rra y 1 x n
B
C O a rra y 1 x n
B
CO
PO
C O a rra y 1 x n
W L D .R .6
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whole or in part without prior written permission of TSMC.
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Document No.
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: 2.6
SRAM CO2 (100;0) Layout Rule for Embedded
DRAM (eDRAM) Process
In the TSMC eDRAM process, capacitor and CO2 modules are inserted between contact and M1 layers
of the TSMC logic process.
For eDRAM related IP/Macro design or products with eDRAM IP/Macro, please notice contact-contact
capacitance and contact resistance are higher than those in pure logic process. You need to use the
eDRAM SPICE model and RC extraction deck to specially handle the extra CT-CT coupling capacitance
and resistance from eDRAM process for both eDRAM and non-eDRAM portions.
You have to add CO2 (100;0) layout in SRAM bit cell if your product has SRAM designed by logic rules
and eDRAM at the same time. TSMC SRAM bit cell already has this option.
Rule No.
Description
CO2.W.1
CO2 (100;0) width (maximum=minimum)
CO2.R.1
CO2 (100;0) layout must exist in the SRAM bit cell for the eDRAM process.
CO2.R.2
BTC must overlap CO2, and CO2 must overlap BTC.
CO2 (100;0) must be inside {M1 AND SRM} and BTC ((30;0 NOT 30;11) AND
50;0). The following conditions can be waived.
a. Butted contact (BTC) without interacting with M1.
b. The area of {CO2 NOT M1} is smaller than or equal to 0.015 x 0.005 um2 in
SRM_LV (80;15). In the other SRAMs, CO2 must be fully inside M1 (the
area of {CO2 NOT M1} should be equal to 0um2).
CO2.R.3U
Customer-designed SRAM bit cell designed by logic rules: It is required
to be reviewed by TSMC’s PE before using a customer-designed SRAM bit
cell designed by logic rules for the eDRAM process.
Label
Op.
Rule
A
=
0.06
B T C (3 0 ;0 N O T 3 0 ;1 1 )
M 1 (3 1 ;0 )
C O 2 (1 0 0 ;0 )
C O (3 0 ;0 A N D 3 0 ;1 1 )
A
S R M (5 0 ;0 )
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whole or in part without prior written permission of TSMC.
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: 2.6
ROM Rules
ROM (CAD layer: 50;6) is used for ROM circuit design and is a tape-out required layer for N40G. ROM can
only be designed by SVT NMOS, and not allowed for other VTs.
Rule No.
ROM.W.1
ROM.W.2
ROM.R.1U
ROM.R.2® U
ROM.R.3®
ROM.R.4
Description
Channel width
Channel length
All ROM cells must be covered by 50;6.
Recommend to insert dummy PO between two ROM bits on different OD.
Each ROM cell must be covered by ROM(50;6).
DRC only flags no ROM(50;6) in the chip. But if there is no ROM cell in the
chip, the violation can be waived.
Only SVT NMOS is allowed in the ROM region for SPICE model support.
DRC flags that ROM overlaps {NW AND OD}/{HVD_N AND OD}/{VTH_N
AND OD}/{VTL_N AND OD}.
Label
A
B
Op.
=
=
Rule
0.12~0.35
0.045, 0.05
R O M C e ll
A
PO
B
OD
In T S M C R O M c e ll, th is d u m m y p o ly is
D u m m y P o ly
d r a w n b y a p o ly la y e r (1 7 ;0 ) w h ic h fo llo w s
p o ly r e la te d r u le s .
PO
OD
5 0 ;6
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whole or in part without prior written permission of TSMC.
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: 2.6
Antenna Effect Prevention (A) Layout Rules
A protection OD means diode, STRAP, source, drain, and so on.
Rule No.
A.R.0
A.R.1
A.R.2
A.R.3
A.R.4
A.R.6
A.R.6.1
Description
Antenna prevention without protection ODrules: A.R.1, A.R.2, A.R.3, A.R.4, A.R.6, A.R.6.1,
A.R.6.2, A.R.9, A.R.10, AR.11
Antenna prevention with protection ODrules: A.R.7, A.R.8, A.R.8.1, A.R.8.3, A.R.8.3.1,
A.R.8.3.2, A.R.8.7, A.R.12, A.R.13
Drawn ratio of the poly top area to the active poly gate area that is connected directly to it
Drawn ratio of the poly sidewall area to the active poly gate area that is connected directly to it
Drawn ratio of the poly contact area to the active poly gate area that is connected directly to it
Single-layer drawn ratio of a via area to the active poly gate area that is connected directly to it
Ratio of cumulative metal top area (from M1 to M10) to an active poly gate area [1.8V IO in OD2/
except 1.8V IO in OD2/ NOT in OD2]
Ratio of the cumulative metal top area (from M1 to top metal ) to the cumulatively connected
GATE area [I/O in OD2, 4000 μm2 < Gate area ≤ 1000K μm2]
Maximum cumulative IO gate [in OD2] area in same connection
Label
Op.
Rule




250
500
10
20

1000/5000/5000


A.R.6.2
A.R.9
A.R.10
A.R.11
A.R.7
A.R.8
A.R.8.7
A.R.8.1
A.R.8.3
6E5 x (GATE area)(-0.767)
1000000
This rule is checked by the cumulative connections (from M1 to top metal respectively)
Ratio of cumulative via area (from VIA1 to VIA9) to an active poly gate area [in OD2/ NOT in
OD2]
Drawn ratio of RV area to the active poly gate area that is connected directly to it [in OD2/ NOT in
OD2]
Drawn ratio of AP sidewall area to the active poly gate area that is connected directly to it [in
OD2/ NOT in OD2]
Drawn ratio of cumulative via area (from VIA1 to VIA9) to the active poly gate area with a
protection OD.
Drawn ratio of cumulative metal top area (from M1 to Last Metal-1) to the active poly gate area
with a protection OD.
Mn_pad_floating space to Mn [connects to OD ,from M1 to AP] ≤ 0.100 µm is not allowed

50/NA

20/200

1000/2000

OD area x 210 + 900

OD area x 456 + 43000

OD area x 8000 + 50000


OD area x 83 + 400
OD area x 8000 + 30000
Definition of Mn_pad_floating: the metal (from M1 to AP) follows the following conditions:
(1) does not connect to OD, and
(2) connect to AP_PAD [width of AP interact {CB2_WB OR CB2_FC} > 35 um]
This rule is checked from M1 to AP respectively
Drawn ratio of last metal top area to the active poly gate with a protection OD.
Risk_Floating_net space to Mn (from M1 to Mtop) [connects to OD] < 0.17 μm, ≥ 0.07 μm is not
allowed
Definition:
1. Risk_Floating_net: cumulative floating metal and VIA top area [cumulative area > 7.50E+05
μm2, from M1 to top metal and VIA1 to top VIA, and does not connect to OD]
2. floating metal and VIA: metal and VIA does not connect to OD
This rule is checked by the cumulative connections (from M1 to top metal and VIA1 to top VIA
respectively)
Risk_Floating_net space to Mn (from M1 to Mtop) [connects to OD] < 0.23 μm, ≥ 0.17 μm is not
allowed
A.R.8.3.1
Definition:
1. Risk_Floating_net: cumulative floating metal and VIA top area [cumulative area > 1.20E+06
μm2, from M1 to top metal and VIA1 to top VIA, and does not connect to OD]
2. floating metal and VIA: metal and VIA does not connect to OD
This rule is checked by the cumulative connections (from M1 to top metal and VIA1 to top VIA
respectively)
Risk_Floating_net space to Mn (from M1 to Mtop) [connects to OD] < 0.5 μm, ≥ 0.23 μm is not
allowed
A.R.8.3.2
A.R.12
A.R.13
Definition:
1. Risk_Floating_net: cumulative floating metal and VIA top area [cumulative area > 2.20E+06
μm2, from M1 to top metal and VIA1 to top VIA, and does not connect to OD]
2. floating metal and VIA: metal and VIA does not connect to OD
This rule is checked by the cumulative connections (from M1 to top metal and VIA1 to top VIA
respectively)
Drawn ratio of RV area to the active poly gate area with a protection OD.
Drawn ratio of AP sidewall area to the active poly gate area with a protection OD.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Table Notes:
1. It is recommended having OD connection to the poly gate through metal lines for all devices.
2. All N+ OD and P+ OD areas connected to metal or via do contribute to the OD area. (Including source or drain
diffusion of MOSFET and Strap areas)
3. If a large OD is needed, it is recommended having one big diffusion area with multiple contacts. Avoid covering
the entire OD area with metal.
4. The Antenna rules apply separately to both thin (core) and thick (I/O) gate oxides.
5. RDL designs should take antenna rules into account.
6. Gate poly thickness is 800 angstrom (Å ) for both core and I/O gates.
7. All of the ODs in the same net can be treated as effective protection OD(s) against plasma charging.
8. In order to avoid the antenna ratio mismatch between the paired devices, metal lines need to be as symmetry as
possible.
9. The transistors in mismatch sensitive configurations shall be tied to an active region by M1 to prevent processinduced damage.
10. When an error is detected at DRC, antenna ratio can be reduced by the following suggestion; connect the node to
a protection OD, connect the gate to the highest metal level as close to the gate as possible, or connect the node
to the output of the driver with a lower metal level.
11. DRC implementation for calculations of metal to gate area ratio in cumulative antenna rules,

“Cumulated Ratio” of A.R.4 and A.R.6 rules is defined as:
Area(Mx(n))/Area(GATE(n)) + Area(Mx-1(n-1))/Area(GATE(n-1)) + ... + Area(M1(1))/Area(GATE(1))

Where GATE(n) is the total GATE area in a particular net constructed by the incremental connections up
to current nth stage.


Mx(n) is the whole area of metal x (x = 1~ top) in the same net.
Definition of the protection OD for antenna rules:
Total area of (OD NOT POLY) INTERACT CONTACT on the same net
12. Failure Criterion

Tailing percentage of 20% changes in gate current in Log-normal distribution (which is expressed with the
following equation) is less than 5%.
 Ig (%)

Ig(n)
 Ig(n
Ig(n
 1)
 1)
 100%
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whole or in part without prior written permission of TSMC.
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4.5.52.1
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Poly Antenna Ratio
The definition of the poly top area antenna ratio for each layer is:
ratio = (Lp x Ld + Lpe x Wpe) / (Wd x Ld)
The definition of the poly sidewall area antenna ratio for each layer is:
ratio = 2 x [(Lpe +Wpe + Lp ) x t ] / (Wd x Ld)
Lp:
length of field poly connected to gate
Wp:
width of field poly connected to gate
Lpe:
length of field poly extension connected to gate
Wpe: width of field poly extension connected to gate
t:
poly thickness
Wd:
transistor channel width
Ld:
transistor channel length
4.5.52.2
M1-M10 Antenna Ratio
The definition of the M1-M10 antenna ratio for each layer is:
ratio = (Wm x Lm ) / (Wd x Ld)
Lm:
length of metal line connected to gate
Wm:
width of metal line connected to gate
Wd:
transistor channel width
Ld:
transistor channel length
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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CO Via1 – Via9 Antenna Ratio
4.5.52.3
The definition of CO, VIA1-VIA9 antenna ratio is:
ratio = {total contact (via) area}/ Wd x Ld
Wd:
transistor channel width
Ld:
transistor channel length
Lm
M e t a l_ 1
W m
Lpe
W pe
t
Lp
W d
P o ly
STI
STI
Ld
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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4.5.53
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: T-N45-CL-DR-001
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Product Labels and Logo Rules
1. Use any of the following product labels:
 Copyright and year
 Company logo
 Part number
 Mask level names
 Other similar labels
2. Make sure there is a dummy layer LOGO (CAD layer no. 158) to do DRC for product labels.
Product labels must be fully covered by LOGO dummy layer.
3. Form the product labels for the CO/Via layer by using squares with minimum width.
A big CO/Via polygon for a character (or a numeral) is not allowed.
4. Don’t use minimum rules for the product labels, except for CO/Vias.
It is best to have greater than, or equal to, 1μm of width and space. If the minimum width and space is
greater than 1μm in the rule (for example, 30K thick metal) please use at least the minimum width and
space.
5. To protect the product labels, do not use a dummy Metal in the LOGO demarcated regions.
For process uniformity, keep the LOGO layer and the corresponding product labels at least 10μm distant
from the OD/PO/Metal geometry. Add dummy fill in this 10μm border region. (The TSMC dummy pattern
utility will insert dummy pattern geometry in the 10μm LOGO border region to minimize the process impact
on the circuit OD/PO/Metal geometry that is near the LOGO.)
Rule No.
Description
Label
Op.
Rule
A

10
Space to OD, PO, or Metals (non-dummy patterns, and non-dummy TCD)
(This check doesn’t include the M1/ Mx protection ring inside {LOWMEDN NOT
(LOWMEDN SIZING -4 um)} region, seal-ring region, and CSR region)
LOGO.O.1 Overlap of CB, CBD, PM, UBM is not allowed.
LOGO.R.1U A circuit in the LOGO is not allowed.
The rules of OD.DN.4® , OD.DN.5® , OD.DN.6® , OD.DN.7® , PO.DN.4® ,
PO.DN.5® , PO.DN.6® , PO.DN.7® , PO.EX.1, PO.EX.1® , PO.EX.2, PO.EX.2® ,
LOGO.R.2
PO.EX.3, PO.R.1, PO.R.4, PO.W.6, OD.W.2.1, OD.W.2.2, and OD.R.1 can be
exempted from DRC in LOGO area.
LOGO.S.1
O D /P O L Y /M e ta l
A
LO G O
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: 2.6
Seal Ring Overview

The general N45 seal ring structure consists of three major parts: (i) assembly isolation; (ii) corner stress
relief (CSR) pattern; and (iii) seal ring wall. In addition, the seal ring is surrounded by 8-μm-wide scribe
line dummy bar (SLDB). Fig. 4.5.54.1 shows the details.

The seal ring structure can protect the chip from the die saw damage in order to manage the saw quality.
It can reduce the impact of damage induced by thermal stress during packaging and field applications.

To add a seal ring, triangle empty areas (74 μm) at four chip corners must be reserved and no layout is
allowed inside. The triangle empty rule, CSR.R.1, must be folowed.

The DMV described in this section means dummy metal and VIA in seal ring, assembly isolation, and
SLDB region.
Warning: Violation of this rule, CSR.R.1, may result in serious
layout mistakes, thus the corrections of many masks may be
required!
Fig. 4.5.54.1. Three major parts of the seal ring and the scribe line dummy bar: (i) assembly isolation;
(ii) seal ring wall; (iii) corner stress relief (CSR) pattern; (iv) scribe line dummy bar (SLDB).
CSR
C S R .R .1 :
T r ia n g le e m p ty a r e a
6um
10um
8um
A s s e m b ly
Seal
S c r ib e lin e
is o la tio n
r in g
dum m y bar
w a ll
(S L D B )
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.1
Document No.
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: 2.6
Guidelines for Placing Seal Ring
There are two ways to mount the seal ring structure into your design:
1. Added by TSMC: Customers can request TSMC to add the seal ring and the SLDB during post tape out
data preparation. CSR.R.1 must be followed if this option is selected.
2. Added by Customer: Customers can choose to add the seal ring and SLDB before tape out. Four sample
GDS files (archived along with this document) are prepared for this purpose. Please select the proper GDS
layers matching with the metal scheme of your design by following the seal ring rules and SLDB rules in the
following.
1P10M sample GDS file for using Mz as top metal: TSMC_N45_SRDRM_BIB_Mz_AP_4um_PBO1_4D3.gds
1P10M sample GDS file for using My as top metal: TSMC_N45_SRDMB_BIB_My_20090923_AP plus 4.0.gds
1P10M sample GDS file for using Mr as top metal: TSMC_N45_SRDRM_BIB_Mr_AP_4um_PBO1_4D3.gds
1P10M sample GDS file for using Mu as top metal: TSMC_N45_SRDRM_BIB_Mu_AP_4um_PBO1_4D3.gds


Sealring structures can be used in WLCSP/Flip chip/Wire bond packages.
Mask combination CB (mask ID:107)/ AP (mask ID: 307)/ CB (mask ID:107) is not allowed for WLCSP
process.
Warning: A seal ring different from the TSMC standard one requires a special approval
from TSMC to mitigate risk during die saw and packaging. Please contact TSMC to get
assistance if an approval process is needed.
The following CAD layers are required for seal ring structure and SLDB in addition to
Via and Metal layers. Please keep these layers in the your chip GDS:
Layer Name
CAD Layer #/Datatype
Flip Chip required
Wire Bond required
OD
6;0
V
V
PP
25;0
V
V
CO
30;0
V
V
CBD#a
169;0
V
X
CB
76;0
X
V
CB2_FC
86;0
V
X
CB2_WB
86;20
X
V
PM
5;0
V
Optional
LMARK
109;0
V
V
SEALRING
162;0
V
V
SEALRING_DB
162;1
V
V
SEALRING_ALL#b
162;2
V
V
CSRDMY
166;0
V
V
CSRBIB1DMY
166;1
V
V
CSRBIB2DMY
166;2
V
V
a. CBD is a required layer in the seal ring region for CB-VD mask (passivation-1) generated from (RV or CBD).
b. Layer SEALRING_ALL (162;2) is used to waive logic rule violations in the seal ring, SLDB, CSR, and assembly
isolation regions.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Metallization Options
The general 45 nm logic process is offered up to 1P10M. Please refer to the following tables to assemble the
metallization option that fits your design.
For any metal combination, a marker “(1+X+Y+Z+R)M_XxYyZzRr” can be used to represent the metal
combination of Mx, My, Mz and Mr.
The marker is interpreted as one layer of M1, X layers of Mx, Y layers of My, Z layers of Mz, and R
layers of Mr. The total metal layer number is (1+X+Y+Z+R).
Naming for different metal types
Code
M1
Mx
My
Mz
Mr
Data Type
0
0
20
40
80
Naming for different Via types
Code
Vx
Vy
Vz
Vr
Data Type
0
20
40
80
Metallization CAD layers
Layer
Metal-1
Via-1
Metal-2
Via-2
Metal-3
Via-3
Metal-4
Via-4
Metal-5
Via-5
Metal-6
Via-6
Metal-7
Via-7
Metal-8
Via-8
Metal-9
Via-9
Metal-10
CAD Layer ID
31
51
32
52
33
53
34
54
35
55
36
56
37
57
38
58
39
59
40
For example, in a 10M_5x2y2z scheme, the Via-6, Metal-7, Via-7, and Metal-8 should use layer (56;20),
(37;20), (57;20), and (38;20), respectively, for My and Vy layers. The Via-8, Metal-9, Via-9, and Metal-10
should use layer (58;40), (39;40), (59;40), and (40;40), respectively, for Mz and Vz layers. The Metal-1 through
Metal-6 should follow their respective CAD layer ID with data type 0.
If customers want to add the seal ring and SLDB before tape out (option 2), please use the TSMC sample
GDS file for seal ring and SLDB as a starting file, and follow the descriptions below to select the related metal
and via layers for your design.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.1.1 For Metallization Options Using Mz as the Top Metal
1.
Start with “N45_TSMC_SRDMB_BIB_Mz.gds” sample gds file. Select the metallization layers from
the table below based on the target metallization scheme. Delete from the sample GDS any metal
and via layers that are not listed in the column.
Metallization Options using Mz as Top Metal
Metal
scheme
1P3M
1P4M
1P5M
1P6M
1P7M
1x1z
2x1z
3x1z
2x2z
4x1z
3x2z
3x1y1z
5x1z
4x1y1z
3x2y1z
4x2z
3x1y2z
M1
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
VIA1
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
M2
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
VIA2
52;40*
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
M3
33;40*
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
VIA3
53;40*
53;0
53;40*
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
M4
34;40*
34;0
34;40*
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
VIA4
54;40* 54;40*
54;0
54;40*
54;20*
54;0
54;0
54;20*
54;0
54;20*
M5
35;40* 35;40*
35;0
35;40*
35;20*
35;0
35;0
35;20*
35;0
35;20*
VIA5
55;40* 55;40*
55;40*
55;0
55;20*
55;20*
55;40*
55;40*
M6
36;40* 36;40*
36;40*
36;0
36;20*
36;20*
36;40*
36;40*
VIA6
56;40*
56;40*
56;40*
56;40*
56;40*
M7
37;40*
37;40*
37;40*
37;40*
37;40*
VIA7
M8
VIA8
M9
VIA9
M10
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Metallization Options using Mz as Top Metal
Metal
scheme
1P8M
1P9M
1P10M
6x1z 5x1y1z 4x2y1z 5x2z 4x1y2z 3x2y2z 7x1z 6x1y1z 5x2y1z 6x2z 5x1y2z 4x2y2z 7x2z 6x1y2z 5x2y2z
M1
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
31;0
VIA1
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
M2
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
VIA2
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
M3
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
VIA3
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
M4
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
VIA4
54;0
54;0
54;0
54;0
54;0
54;20* 54;0
54;0
54;0
54;0
54;0
54;0
54;0
54;0
54;0
M5
35;0
35;0
35;0
35;0
35;0
35;20* 35;0
35;0
35;0
35;0
35;0
35;0
35;0
35;0
35;0
VIA5
55;0
55;0
55;20* 55;0 55;20* 55;20* 55;0
55;0
55;0
55;0
55;0
55;20* 55;0
55;0
55;0
M6
36;0
36;0
36;20* 36;0 36;20* 36;20* 36;0
36;0
36;0
36;0
36;0
36;20* 36;0
36;0
36;0
VIA6
56;0 56;20* 56;20* 56;40* 56;40* 56;40* 56;0
56;0
56;20* 56;0 56;20* 56;20* 56;0
56;0
56;20*
M7
37;0 37;20* 37;20* 37;40* 37;40* 37;40* 37;0
37;0
37;20* 37;0 37;20* 37;20* 37;0
37;0
37;20*
VIA7 57;40* 57;40* 57;40* 57;40* 57;40* 57;40* 57;0 57;20* 57;20* 57;40* 57;40* 57;40* 57;0 57;20* 57;20*
M8
38;40* 38;40* 38;40* 38;40* 38;40* 38;40* 38;0 38;20* 38;20* 38;40* 38;40* 38;40* 38;0 38;20* 38;20*
VIA8
58;40* 58;40* 58;40* 58;40* 58;40* 58;40* 58;40* 58;40* 58;40*
M9
39;40* 39;40* 39;40* 39;40* 39;40* 39;40* 39;40* 39;40* 39;40*
VIA9
59;40* 59;40* 59;40*
M10
40;40* 40;40* 40;40*
2.
Re-assign the layers marked with “*” by the appropriate CAD layers to match with the CAD ID for
that layer.
Example: For a design with 6M_3x1y1z.
Step 1: Locate the “3x1y1z” column under “1P6M” in the metallization options table above. Delete unused
metal and via layers: (54;0), (35;0), (55;0), (36;0), (56;0), (37;0), (57;0), (38;0), (56;20), (37;20),
(58;40) and (39;40) .
Step 2: Re-assign CAD ID for the layers denoted with “*”, from (57;20), (38;20), (59;40) and (40;40),
respectively, to (54;20), (35:20), (55:40) and (36:40) to match with your metallization scheme.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.1.2 Metallization Options Using My as the Top Metal
1.
Start with “N45_TSMC_SRDMB_BIB_My.gds” sample GDS file. Select the metallization layers from
the table below based on the target metallization scheme. Delete from the sample GDS any metal
and via layers that are not listed in the column.
Metal
1P3M
scheme
1x1y
M1
31;0
VIA1
51;0
M2
32;0
VIA2 52;20*
33;20*
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
2.
1P4M
2x1y
31;0
51;0
32;0
52;0
33;0
53;20*
34;20*
Metallization Options using My as Top Metal
1P5M
1P6M
1P7M
1P8M
3x1y
2x2y
4x1y
3x2y
5x1y
4x2y
6x1y
5x2y
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;20*
35;20*
31;0
51;0
32;0
52;0
33;0
53;20*
34;20*
54;20*
35;20*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;20*
36;20*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;20*
35;20*
55;20*
36;20*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;20*
37;20*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;20*
36;20*
56;20*
37;20*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;20*
38;20*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;20*
37;20*
57;20*
38;20*
1P9M
6x2y
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;20*
38;20*
58;20*
39;20*
1P10M
7x2y
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;0
38;0
58;20*
39;20*
59;20*
40;20*
Re-assign the layers marked with “*” by the appropriate CAD layers to match with the CAD ID for
that layer.
Example: For a design with 6M_3x2y.
Step 1: Locate the “3x2y” column under “1P6M” in the metallization options table above. Delete unused
metal and via layers: (54;0), (35;0), (55;0), (36;0), (56;0), (37;0), (57;0) and (38;0).
Step 2: Re-assign CAD ID for the layers denoted with “*”, from (58;20), (39;20), (59;20) and (40;20),
respectively, to (54;20), (35;20), (55;20) and (36;20) to match with your metallization scheme.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.1.3 Metallization Options Using Mr as the Top Metal
1. Start with “N45_TSMC_SRDMB_BIB_Mr.gds” sample GDS file. Select the metallization layers from
the table below based on the target metallization scheme. Delete from the sample GDS any metal
and via layers that are not listed in the column.
Metallization Options using Mr as Top Metal
Metal scheme
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
1P7M
1P8M
1P9M
1P10M
5x1r
4x2r
6x1r
5x2r
7x1r
6x2r
7x2r
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;80*
37;80*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;80*
36;80*
56;80*
37;80*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;80*
38;80*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;80*
37;80*
57;80*
38;80*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;0
38;0
58;80*
39;80*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;80*
38;80*
58;80*
39;80*
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;0
38;0
58;80*
39;80*
59;80*
40;80*
2. Re-assign the layers marked with “*” by the appropriate CAD layers to match with the CAD ID for
that layer.
Example: For a design with 7M_5x1r.
Step 1: Locate the “5x1r” column under “1P7M” in the metallization options table above. Delete unused
metal and via layers: (56;0), (37;0), (57;0), (38;0), (58;80), (39;80)
Step 2: Re-assign CAD ID for the layers denoted with “*”, from (59;80) and (40;80), respectively, to (56;80)
and (37;80) to match with your metallization scheme.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.1.4 Metallization Options Using Mu as the Top Metal
The possible metal option in Mu scheme is different from Section 4.5.54 in the seal ring. No Mr option is
allowed when Mu structure is introduced.
The general 45 nm logic process with Mu scheme is offered up to 1P10M. Please refer to the following
tables to assemble the metallization option that fit your design.
Naming for Different Metal Types
Code
M1
Mx
My
Mz
Mu
Data Type
0
0
20
40
60
Naming for Different Via Types
Code
Vx
Vy
Vz
Vu
Data Type
0
20
40
40
Metallization CAD Layers
Layer
Metal-1
Via-1
Metal-2
Via-2
Metal-3
Via-3
Metal-4
Via-4
Metal-5
Via-5
Metal-6
Via-6
Metal-7
Via-7
Metal-8
Via-8
Metal-9
Via-9
Metal-10
CAD Layer ID
31
51
32
52
33
53
34
54
35
55
36
56
37
57
38
58
39
59
40
For example, in a 10M_6x1y1z1u scheme, the Via-7, and Metal-8 should use layer, (57;20), and (38;20),
respectively, for My and Vy layers. The Via-8, Metal-9, should use layer (58;40), (39;40), respectively, for Mz
and Vz layers. The Via-9, and Metal-10 should use layer (59;40), and (40;60), respectively, for Mu and Vu
layers. The Metal-1 through Metal-7 should follow their respective CAD layer ID with data type 0.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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If customers want to add the CSR patterns and the seal ring before tape out (option 2), please use the TSMC
sample GDS file for seal ring and CSR as a starting file, and follow the descriptions below to select the related
metal and via layers for your design.
For Metallization Options Using Mu as the Top Metal
Start with “N45_TSMC_SRDMB_BIB_Mu.gds” sample GDS file. Select the metallization layers from the
table below based on the target metallization scheme. Delete from the sample GDS any metal and via
layers that are not listed in the column.
Example: For a design with 7M_5x1u.
Step 1: Locate the first column under “1P7M” in the metallization options table above. Delete unused
metal and via layers: (56;0), (37;0), (57;0), (38;0), (58;40), (39;40)
Step 2: Re-assign CAD ID for the layers Via9 and M10, from (59;40) and (40;60), respectively, to (56;40)
and (37;60) to match with your metallization scheme.
Metallization Options (Mu with second inter-layer metal/via (My/Vy) are used, where the dielectric film
material for inter-layer My/Vy is “Low-K”.)
Total Number of Metal Layers
Metal/
1P4M
Via
2x1u
M1
1P5M
1P6M
1P7M
1P8M
1P10M
1P9M
3x1u 2x1z1u 4x1u 3x1z1u 3x1y1u 5x1u 4x1y1u 4x1z1u 3x1y1z1u 6x1u 5x1y1u 5x1z1u 4x1y1z1u 7x1u 6x1y1u 6x1z1u 5x1y1z1u 7x1z1u 6x1y1z1u
31;0 31;0
31;0
31;0
31;0
VIA1 51;0 51;0
32;0 32;0
51;0
51;0
51;0
32;0
32;0
32;0
31;0
31;0
31;0
31;0
31;0
31;0
51;0
51;0
32;0
32;0
51;0
51;0
32;0
32;0
51;0
51;0
51;0
51;0
51;0
51;0
51;0
32;0
32;0
32;0
32;0
32;0
32;0
32;0
VIA2 52;0 52;0
33;0 33;0
52;0
52;0
52;0
33;0
33;0
33;0
52;0
52;0
33;0
33;0
52;0
52;0
33;0
33;0
52;0
52;0
52;0
52;0
52;0
52;0
52;0
33;0
33;0
33;0
33;0
33;0
33;0
33;0
VIA3 53;40 53;0 53;40 53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
53;0
34;60 34;0 34;40 34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
34;0
VIA4
54;0
54;20
54;0
54;0
54;0
54;0
54;0
54;0
54;0
54;0
54;0
54;0
M5
35;0
35;20
35;0
35;0
35;0
35;0
35;0
35;0
35;0
35;0
35;0
35;0
VIA5
55;40 55;40 55;40 55;0 55;20 55;40
55;40
55;0
55;0
55;0
55;20
55;0
55;0
55;0
55;0
55;0
55;0
M6
36;60 36;60 36;60 36;0 36;20 36;40
36;40
36;0
36;0
36;0
36;20
36;0
36;0
36;0
36;0
36;0
36;0
VIA6
56;40 56;40 56;40
56;40
56;0 56;20 56;40
56;40
56;0
56;0
56;0
56;20
56;0
56;0
37;0 37;20 37;40
37;40
37;0
37;0
37;0
37;20
37;0
37;0
VIA7
57;40 57;40 57;40
57;40
57;0 57;20 57;40
57;40
57;0
57;20
M8
38;60 38;60 38;60
38;60
38;0 38;20 38;40
38;40
38;0
38;20
VIA8
58;40 58;40 58;40
58;40
58;40
58;40
M9
39;60 39;60 39;60
39;60
M2
M3
M4
M7
31;0
31;0
31;0
31;0
31;0
51;0
51;0
32;0
32;0
51;0
51;0
32;0
32;0
52;0
52;0
33;0
33;0
52;0
52;0
33;0
33;0
53;0
53;0
53;0
34;0
34;0
34;0
54;40 54;40 54;0 54;40 54;20 54;0
54;0
35;60 35;60 35;0 35;40 35;20 35;0
35;0
37;60 37;60 37;60
37;60
31;0
31;0
31;0
31;0
39;40
39.40
VIA9
59;40
59;40
M10
40;60
40;60
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Metallization Options (Mu with top metal/via (My/Vy, 2XTM) are used, where the dielectric film material for top
My/Vy is “USG”.)
Metal/
Via
M1
VIA1
M2
VIA2
M3
VIA3
M4
VIA4
M5
VIA5
M6
VIA6
M7
VIA7
M8
VIA8
M9
VIA9
M10
1P5M
2x1y1u
31;0
51;0
32;0
52;0
33;0
53;20
34;20
54;40
35;60
Total Number of Metal Layers
1P6M
1P7M
1P8M
1P9M
3x1y1u 4x1y1u 5x1y1u 6x1y1u
31;0
31;0
31;0
31;0
51;0
51;0
51;0
51;0
32;0
32;0
32;0
32;0
52;0
52;0
52;0
52;0
33;0
33;0
33;0
33;0
53;0
53;0
53;0
53;0
34;0
34;0
34;0
34;0
54;20
54;0
54;0
54;0
35;20
35;0
35;0
35;0
55;40
55;20
55;0
55;0
36;60
36;20
36;0
36;0
56;40
56;20
56;0
37;60
37;20
37;0
57;40
57;20
38;60
38;20
58;40
39;60
1P10M
7x1y1u
31;0
51;0
32;0
52;0
33;0
53;0
34;0
54;0
35;0
55;0
36;0
56;0
37;0
57;0
38;0
58;20
39;20
59;40
40;60
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Chip Corner Stress Relief (CSR) Pattern
Rule No.
CSR.R.1
Document No.
Version
Description
Label
Triangle empty areas (74 μm) at four chip corners must be
reserved and no layout is allowed inside, as shown in Fig.
4.5.54.2.1.
Warning: Violation of this rule may result in a serious layout
mistake thus the corrections of many masks may be
required! Please jobview the mask data after adding CSR
and seal-ring by tsmc.
Op.
Rule
=
74
74 um
e m p ty a re a
C h ip c o r n e r
74 um
e m p ty a re a
CSR.R.2
CSR.R.4
C S R in 4
c h ip c o r n e r s
F i g . Fig.
4 . 5 4.5.54.2.1
. 5 0 . 2 . 1 . TTriangle
r i a n g l e empty
e m p tareas
y a r e at
a s4achip
t 4 ccorners.
h ip c o r n e r s .
The CSR structure must include PM, CB2_FC or CB2_WB, AP,
{{CB OR CBD} OR RV}, Mtop/Mtop-1 (top metal),
VIAtop/VIAtop-1, M8, VIA7…VIA1, M1, CO, PP, OD layers.
The CSR pattern includes an additional 2/6 μm width seal-ring
and reinforced metal structure, as shown in Fig. 4.5.53.2.2.
CSRDMY layer (CAD layer: 166;0), CSRBIB1DMY (166;1) and
CSRBIB2DMY (166;2) are musts if customers add a seal-ring by
themselves. DRC does not check CSR and BiB related rules w/o
those dummy layers.
CSR.W.1
Width of reinforced metal structure
a
=
9~10
CSR.L.1
Length of reinforced metal structure
b
=
24~25
CSR.R.3
Distance between 45-degree outer seal-ring and seal-ring corner
d
=
18~20
Rule No.
Description
Label
DMV pattern in CSR must include Mtop/VIAtop/Mtop-1/VIAtopCSR.R.5
1/Mtop-2/VIAtop-2/…/V1/M1, except for Mr and Mu design (DMV
pattern: metal/via dummy pattern)
For Mu design, DMV pattern in CSR must include Mtop-1/MtopCSR.R.6
2/VIAtop-2/…/V1/M1, not including Mtop (Mu), VIAtop, and VIAtop1. (DMV pattern: metal/via dummy pattern)
CSR_DM.W.1 Metal width of DMV in CSR region
S
CSR_DM.S.1 Metal space of DMV in CSR region
T
CSR_DM.S.2 Metal space of DMV to CSR metal bar
R
CSR_DM.O.1 Overlay of two adjacent DMV metal layers, except Mr and Mu.
U
CSR_DV.W.1 Via width of DMV in CSR region
P
CSR_DV.S.1 Via space of DMV in CSR region
Q
DMV via enclosure by DMV metal in CSR region.
CSR_DV.EN.1
V
DMV via must be inside DMV metal.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.
Rule
=


=
=

Table. 4.5.54.2.1.
Table. 4.5.54.2.1.
Table. 4.5.54.2.1.
Table. 4.5.54.2.1.
Table. 4.5.54.2.1.
Table. 4.5.54.2.1.

Table. 4.5.54.2.1.
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Remark:
Chip corner stress relief pattern and seal ring structures are based on the 1P10M process:
*CSRDMY is a dummy layer aligned to the boundary of stress relief pattern in regionΙ for DRC. Please refer
to Fig. 4.5.54.2.3 in the following.
*Please be careful with the non-generic logical operation or non-TSMC standard seal ring on the drawn
dimensions of stress relief pattern and seal ring. It needs to be reviewed by TSMC.
* Dummy metal/via is implemented in no pattern area to strengthen CSR structure. Please follow the sample
gds file and use correct CAD layers with correct datatypes for DMV on the CSR area.
* Seal ring is surrounded by 8 um (7.2um for N40 on-silicon dimension) scribe line dummy bar to enhance die
saw quality against laser and mechanical die saw alike for a wider package reliability margin. Please refer to
the scribe line dummy bar layout rule in Section 4.5.54.5.
* The seal ring wall structure includes the outer and inner seal ring walls with 2um and 6um width, respectively.
The outer seal ring is 2 um wide (for N45; 1.8um for N40 on-silicon dimension) and adjacent to the scribe line;
the inner seal ring is 6 um wide (for N45; 5.4um for N40 on-silicon dimension) and far away from the scribe
line. Please refer to Fig. 4.5.54.4.1. for an example.
For wire bond product,
* PM (mask code 009, CAD layer: 5;0).
* Polyimide is an optional layer and only covers inner seal_ring; no polyimide coverage over the outer
seal_ring. Please refer to Fig. 4.5.54.4.1.1 for the details. If PM mask is generated by LOP, tsmc will remove
polyimide on sealring to avoid peeling risk from the specific layouts.
For flip-chip product,
* Polyimide only covers inner seal_ring; no polyimide coverage over the outer seal_ring. Please refer to Fig.
4.5.54.4.1.1 for the details.
* CBD (mask code 306) layout is the same as CB.
* Do not draw UBM (mask code 020) layout on the seal ring (chip corner stress relief pattern, seal ring
wall, and assembly isolation) and SLDB. No UBM metal is left in these regions.
* AP (mask 309) must be drawn on seal ring according to the rules.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Chip Corner Stress Relief Pattern (Fig. 4.5.54.2.2)
The scribe line dummy bar is not drawn in this figure.
Top View Fig. 4.5.54.2.2.a
CSR Layout Fig. 4.5.54.2.2.b
CSR additional seal ring
a
a
a
b
a
Reinforced
Metal
structure
d
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Chip Corner Stress Relief pattern (Fig. 4.5.54.2.3)
Chip corner stress relief pattern can reduce the impact of damage induced by thermal stress during packaging and field
application. Please refer to regionΙas an example.
74um
CSR
T r ia n g le e m p t y a r e a
d u m m y m e ta l/v ia
C h ip
c o rn e r
6um
74um
6um
C h ip e d g e
6um
10um
8um
A s s e m b ly
S e a l S c r ib e lin e
is o la tio n
r in g
dum m y bar
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Dummy metal/via (DMV) in the CSR region (Fig. 4.5.54.2.4.)
CSR
d u m m y m e ta l/v ia
Table. 4.5.54.2.1. Rule summary of DMV in CSR for items P~V.
Label
P
Q
R
S
T
U
V
M1
-
-
0.5 0.8 0.4 0.7
-
VIAx/Mx 0.07 0.11 0.5 0.8 0.4 0.7 0.135
VIAy/My 0.14 0.14 0.5 0.8 0.4 0.7
0.14
VIAz/Mz 0.36 0.84 0.5 0.8 0.4 0.7
0.17
VIAr/Mr 0.46 0.74 0.5
1
0.5
-
0.12
VIAu/Mu 0.36
3
3
-
0.33
3
3
C S R Layout
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: 3um X3um M u dum m y
C S R Layout
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whole or in part without prior written permission of TSMC.
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Box in Box (BiB) Pattern inside CSR
1. To meet extremely tight requirement of overlay control for critical layers (OD, PO, CO), the box-in-box
patterns are put into the CSR region for overlay monitoring.
2. CSRBIB1DMY(166;1) and CSRBIB2DMY(166;2) are dummy layers aligned to the boundary of the stress
relief pattern in region-Ι for DRC.
CSRBIB1DMY(166;1) -- DRC recognition layer for location at left-top and right-bottom CSR region
CSRBIB2DMY(166;2) -- DRC recognition layer for location at right-top and left-bottom CSR region
Rule No.
Description
Label
Op.
Rule
BiB.W.1
PO_OD, CO_OD and CO_PO BiB patterns must inside CSR
 PO_OD BiB pattern is formed by [OD ring + PO ring inside OD ring]
 CO_PO {CO_OD} BiB pattern is formed by [PO {OD} ring + CO ring
inside PO {OD} ring (inner and outer)]
Left-top & right-bottom CSR region must has CO_OD and CO_PO BIB
pattern
Right-top & left-bottom CSR region must has PO_OD, and CO_PO BIB
pattern
Width of OD ring and PO ring
A
1.1
BiB.W.2
Width of CO (maximum = minimum)
B
BiB.W.3
Width of ((CO SIZE 0.05) SIZE -0.05) of CO ring
L
=
=
=
0.965
C
=
4
D

=
=
=
=
=
=
=
=
-
1.5
BiB.R.1
BiB.S.2
Space of {OD ring or PO ring} to sealring OD
DRC only select one side of OD ring or PO ring for space check
Space of {OD ring OR PO ring} corner to 45-degree seal-ring OD edge
BiB.S.3
Space of CO to CO [in the same ring]
BiB.L.1
Length of OD ring inner edge
F
BiB.L.2
Length of PO ring inner edge [in PO_OD BiB pattern]
G
BiB.L.3
Length of PO ring inner edge [in CO_PO BiB pattern]
H
BiB.L.4
Length of ((CO SIZE 0.05) SIZE -0.05) of CO ring
M/N
BiB.EN.1
Enclosure of PO to OD [opposite edge in PO_OD BiB pattern]
BiB.EN.2
Enclosure of outer CO ring to OD [opposite edge in CO_OD BiB pattern]
J
BiB.EN.3
Enclosure of outer CO ring to PO [opposite edge in CO_PO BiB pattern]
K
BiB.R.4
Overlap of OD ring, PO ring, CO patterns are not allowed
-
BiB.S.1
E
I
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
0.17
0.095
16.5
7.7
16.5
6.265, 6.53
3.3
4.0
4.0
-
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The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.4
Seal Ring Layout Rules
Document No.
Version
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: 2.6
The seal ring wall rules, DMV (dummy metal/via) in assembly isolation rules, and CDU (critical dimension
uniformity) placement rules are decribed in this section.
Please follow exactly the schematic diagram below (as in the GDS example) for seal ring layout. DRC cannot
fully check these dimensions. Any seal ring design different from the TSMC standard offer cannot be accepted
in product tape out due to unknown risk for die saw and packaging. Please contact TSMC for a special
approval of a non-TSMC standard seal ring.
If the seal ring is added by TSMC, TSMC will add assembly isolation and seal-ring structure at the same time.
Only DMV and CDU are allowed in the assembly isolation region. Please use the sample gds file for DMV and
follow the DMV rules in this region.
AlCu pad (AP)/Polyimide (PM) can be generated by logic operation for wire-bond non-RDL products.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.4.1 Seal Ring Wall Layout Rules
The seal ring wall structure includes the outer and inner seal ring walls with 2um and 6um width, respectively.
The outer seal ring is 2 um wide for N45 (1.8um for N40) and adjacent to the scribe line; the inner seal ring is 6
um wide for N45 (5.4um for N40) and far away from the scribe line. Please refer to Fig. 4.5.54.4.1. for an
example.


If a customer wants to connect a circuit to the seal ring through M1~Mtop, only allow connecting to the
two most inner seal rings. Besides, the DMV pattern must be removed from the connection path in the
assembly isolation region.
If a customer wants to connect a circuit to the seal ring through AP, only allow connecting to the inner
most seal ring.
Rule No.
SR.R.1
SR.R.7
SR.R.8U
SR.R.9
CO.W.2
M1.W.4
M1.W.5
VIAx.W.2
VIAx.W.3
VIAx.EN.5
VIAx.EN.6
VIAx.S.4
VIAx.S.5
VIAx.S.9
Mx.W.4
Mx.W.5
VIAy.W.2
VIAy.W.3
VIAy.EN.5
VIAy.EN.6
VIAy.S.4
VIAy.S.5
VIAy.S.8
My.W.4
My.W.5
VIAz.W.2
VIAz.W.3
VIAz.EN.5
VIAz.EN.5.1
VIAz.EN.6
Description
SEALRING layer (CAD layer: 162;0) and SEALRING_DB layer (CAD layer: 162;1) are musts if customers
add a seal-ring by themselves. 162;0 is used to cover the outer seal-ring (2um) and inner seal-ring
(6um);162;1 is used to cover SLDB (3.5um duplicate).
SEALRING layer (162;0) and SEALRING_DB layer (162;1) must exist.
All the drawings of seal-ring and SLDB structures must be inside of SEALRING (162;0) and
SEALRING_DB (162;1). (except Mu)
Please follow the CAD layers usage of 162;0 and 162;1.
DRC does not check seal-ring related rules w/o those layers.
CO bar and VIA (x,y,z,r,u), CB/CBD/RV bar must be continuous as a ring.
Only tsmc standard seal-ring is allowed.
Width of assembly isolation = 6 um (layout forbidden area.)
Only M1~AP, DMV pattern, and CDU are allowed in the assembly isolation region.
(DMV pattern: metal/via dummy pattern)
Each M1~AP patterns in the assembly isolation region must follow the following conditions:
1. Each M1~Mtop must be connected to seal ring wall
2. Each AP can only connect to the inner seal ring wall
3. Each M1~AP overlap SLDB is not allowed
Width of CO bar in seal-ring.
Width of M1 metal line in outer seal-ring.
Width of M1 metal line in inner seal-ring.
Width of VIAx bar in seal-ring.
Width of VIAx hole in seal-ring.
Enclosure of VIAx bar by Mx in seal-ring.
Enclosure of VIAx hole by Mx in seal-ring.
Space of VIAx hole in seal-ring.
Space of VIAx hole to VIAx bar in seal-ring.
Maximum space of VIAx hole [INSIDE SEALRING]
DRC flags: {SEALRING AND Mx} must be fully covered by {{SEALRING AND VIAx holes} SIZING 6um}
Width of Mx metal line in outer seal-ring.
Width of Mx metal line in inner seal-ring.
Width of VIAy bar in seal-ring.
Width of VIAy hole in seal-ring.
Enclosure of VIAy bar by My in seal-ring.
Enclosure of VIAy hole by My in seal-ring.
Space of VIAy hole in seal-ring.
Space of VIAy hole to VIAy bar in seal-ring.
Maximum space of VIAy hole [INSIDE SEALRING]
DRC flags: {SEALRING AND My} must be fully covered by {{SEALRING AND VIAy holes} SIZING 6um}
Width of My metal line in outer seal-ring.
Width of My metal line in inner seal-ring.
Width of VIAz bar in seal-ring.
Width of VIAz hole in seal-ring.
Enclosure of VIAz bar by Mz in seal-ring, except Mu design
Enclosure of VIAz bar by Mz in seal-ring in Mu design
Enclosure of VIAz hole by Mz in seal-ring.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
Op.
Rule

6
P
Q
R
B
D
A
I
G
C, H
=
=
=
=
=




0.06
2
6
0.5
0.07
0.21
0.22
0.35
0.365
G

12
Q
R
B
D
A
I
G
C, H
=
=
=
=




2
6
0.5
0.14
0.21
0.15
0.34
0.3
G

12
Q
R
B
D
A
A
I
=
=
=
=



2
6
0.5
0.36
0.21
0.30
0.21
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Rule No.
VIAz.S.4
VIAz.S.5
VIAz.S.8
Mz.W.4
Mz.W.5
VIAr.W.2
VIAr.W.3
VIAr.EN.5
VIAr.EN.6
VIAr.S.4
VIAr.S.5
VIAr.S.8
Mr.W.4
Mr.W.5
VIAu.W.2
VIAu.W.3
VIAu.EN.5
VIAu.EN.6
VIAu.S.4
VIAu.S.5
VIAu.S.8
Mu.W.4
Mu.W.5
CB.W.3
CB.EN.2
SR.AP.W.3
AP.EN.2
CB2.W.5
PM.R.3
SR.R.4
SR.R.5
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Space of VIAz hole in seal-ring.
Space of VIAz hole to VIAz bar in seal-ring.
Maximum space of VIAz hole [INSIDE SEALRING]
DRC flags: {SEALRING AND Mz} must be fully covered by {{SEALRING AND VIAz holes} SIZING 6um}
Width of Mz metal line in outer seal-ring.
Width of Mz metal line in inner seal-ring.
Width of VIAr bar in seal-ring.
Width of VIAr hole in seal-ring.
Enclosure of VIAr bar by Mr in seal-ring.
Enclosure of VIAr hole by Mr in seal-ring.
Space of VIAr hole in seal-ring.
Space of VIAr hole to VIAr bar in seal-ring.
Maximum space of VIAr hole [INSIDE SEALRING]
DRC flags: {SEALRING AND Mr} must be fully covered by {{SEALRING AND VIAr holes} SIZING 6um}
Width of Mr metal line in outer seal-ring.
Width of Mr metal line in inner seal-ring.
Width of VIAu bar in seal-ring.
Width of VIAu hole in seal-ring.
Enclosure of VIAu bar by Mu in seal-ring.
Enclosure of VIAu hole by Mu in seal-ring.
Space of VIAu hole in seal-ring.
Space of VIAu hole to VIAu bar in seal-ring.
Maximum space of VIAu hole [INSIDE SEALRING]
DRC flags: {SEALRING AND Mu} must be fully covered by {{SEALRING AND VIAu holes} SIZING 6um}
Width of Mu metal line in outer seal-ring.
Width of Mu metal line in inner seal-ring.
Width of CB/CBD/RV line opening in inner seal-ring. (Tolerance 0.01 μm)
Enclosure of CB/CBD/RV by AP in inner seal-ring. (Tolerance 0.01 μm)
Width of AP bar [overlaps with inner seal-ring and SREZ]
(Except AP connect to inner seal-ring from Prime Chip)
(DRC tolerance at 45-degree turning: ±0.02 μm)
Enclosure of AP bar [overlaps with inner seal-ring and SREZ] by inner seal-ring
(DRC tolerance at 45-degree turning: ±0.02 μm)
Width of CB2_WB/CB2_FC line opening in outer seal-ring.
Polyimide is prohibited over outer seal-ring and SLDB regions. It only covers inner seal-ring area
(6um/5.4um for N45/N40). Please see Fig. 4.5.54.4.1.1. (PM drawn pattern must cover outer seal-ring and
SLDB regions.)
Please add as many VIA holes as possible in metal lines of inner and outer seal-rings.
DRC flags: {SEALRING NOT INTERACT VIAx, VIAy, VIAz, VIAu, and VIAr holes, respectively}
LMARK must be inside SEALRING_ALL
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
G
C, H
Op.


Rule
0.54
0.34
G

12
Q
R
B
D
A
I
G
C, H
=
=
=
=




2
6
0.5
0.46
0.08
0.08
0.44
0.44
G

12
Q
R
B
D
A
I
G
C, H
=
=
=
=




2
6
0.5
0.36
0.30
0.30
0.54
0.34
G

12
Q
R
U
X
=
=
=

2
6
2
1
V
=
8
EN
=
1
W
=
2
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Fig. 4.5.54.4.1.1. Cross-sectional view of seal ring
Before LOP:
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Post LOP:
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Top view of seal ring
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Before LOP:
Post LOP:
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Top view of seal ring
(Adjacent via array)
A
D
B
H
A
I
A
H
G
B
B
D
C
Assembly
F
VIAx
isolation
G
Cad Layer 162
(Seal Ring)
Cad Layer 162;0
F
2um
(Seal Ring)
6um
2um
(Inner seal ring wall)
(Outer seal ring wall)
I
A
D
B
(Adjacent via array)
H
A
A
H
G
B
B
D
C
Assembly
F
isolation
VIAy
G
Cad Layer 162
Cad Layer 162;0
(Seal Ring)
(Seal Ring)
F
* Recommended value, DRC only checks min. value.
Layer
A
B
VIAx
0.21
0.5
VIAy
0.21
0.5
C
1*
1*
D
0.07
0.14
F
0.175
0.17
G
0.35
0.34
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
H
0.365
0.3
I
0.22
0.15
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Top view of seal ring
A
I
H
A
(Adjacent via array)
G
D
B
B
C
A
H
B
D
Assembly
F
VIAz
isolation
G
Cad Layer 162
Cad Layer 162;0
(Seal Ring)
(Seal Ring)
F
A
I
H
A
D
B
B
C
A
(Adjacent via array)
G
H
B
D
Assembly
F
VIAr
isolation
G
Cad Layer 162
Cad Layer 162;0
(Seal Ring)
(Seal Ring)
F
* Recommended value, DRC only checks min. value.
Layer
A
B
C
D
F
G
H
I
VIAz
0.21
0.5
0.72*
0.36
0.38
0.6*
0.67*
0.21
VIAr
0.21*
0.5
0.62*
0.46
0.4
0.8*
0.8*
0.21*
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Top view of seal ring (VIAz and VIAu)
When using Mu design
A
I
H
A
(Adjacent via array)
G
D
B
B
C
A
H
B
D
Assembly
F
isolation
G
Cad Layer 162
Cad Layer 162
(Seal Ring)
(Seal Ring)
F
* Recommended value, DRC only checks min. value.
Layer
A
B
C
D
F
G
H
I
VIAz / VIAu
0.33
0.5
0.48*
0.36
0.38
0.68*
0.43
0.33
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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4.5.54.4.2 DMV in Assembly Isolation Layout Rules
All DMV rules bypass CDUDMY (165;0) region.
Rule No.
Description
Label
Op.
SR_DM.W.1
Metal width of DMV in assembly isolation
S
=
SR_DM.S.1
Metal space of DMV in assembly isolation
T

SR_DM.S.2
Metal space of DMV to seal-ring metal bar
R

SR_DM.O.1
Overlay of two adjacent DMV metal layers, except Mr and Mu.
U
=
SR_DV.W.1
Via width of DMV in assembly isolation
P
=
SR_DV.S.1
Via space of DMV in assembly isolation
Q

V

SR_DV.EN.1
SR.R.2
SR.R.3
Enclosure of DMV via by DMV metal in assembly isolation
DMV via must be inside DMV metal.
DMV pattern in assembly isolation region must include Mtop/VIAtop/
Mtop-1/VIAtop-1/Mtop-2/VIAtop-2/…/V1/M1, except Mr and Mu design.
(DMV pattern: metal/via dummy pattern)
For Mu design, DMV pattern in assembly isolation region must include
Mtop-1/Mtop-2/VIAtop-2/…/V1/M1, not including Mtop(Mu), VIAtop, and
VIAtop-1. (DMV pattern: metal/via dummy pattern)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Rule
Table.
4.5.53.4.2.1
Table.
4.5.53.4.2.1
Table.
4.5.53.4.2.1
Table.
4.5.53.4.2.1
Table.
4.5.53.4.2.1
Table.
4.5.53.4.2.1
Table.
4.5.53.4.2.1
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Top view of DMV in assembly isolation
(Mz, My, Mr as top metal)
Table. 4.5.54.4.2.1. Rule summary of DMV in assembly isolation for items P~V.
Label
P
Q
R
S
T
U
V
M1
0.4
0.8
0.4
0.7
VIAx/Mx
0.07
0.11
0.4
0.8
0.4
0.7
0.135
VIAy/My
0.14
0.14
0.4
0.8
0.4
0.7
0.14
VIAz/Mz
0.36
0.84
0.4
0.8
0.4
0.7
0.17
VIAr/Mr
0.46
0.74
0.4
1
0.5
0.12
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Top view of DMV in assembly isolation
When using Mu design
For Mu design, DMV pattern in assembly isolation is without Mu_(Mtop)/VIAu/VIAz.
Table. 4.5.54.4.2.2. Rule summary of DMV in assembly isolation.
Label
R
S
T
U
Mz
0.5
0.8
0.4
0.7
4.5.54.4.3 CDU (Critical Dimension Uniformity) pattern in Assembly Isolation
Rules
CDU pattern is unnecessary. If you want to add a CDU pattern, please place in a 6 μm assembly isolation
beside a seal ring.
Rule No.
CDU.R.1
CDU.R.2
Description
Label
Op.
Rule
CDUDMY must be inside the assembly isolation, beside the seal-ring.
OD/Poly/NP/CO/M1/Vx/Mx must be inside the CDUDMY.
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whole or in part without prior written permission of TSMC.
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: 2.6
Scribe Line Dummy Bar Layout Rules
Scribe line dummy bar (SLDB) is a structure surrounding the seal ring to enhance die protection against the
die saw damage. Laser grooving or mechanical saw during dicing is not allowed to damage SLDB. 8um
(7.2um for N40) extra space outside the original seal ring structure is needed for SLDB. Please follow exactly
the schematic diagram below (as in GDS example) for SLDB. DRC cannot fully check these dimensions. If you
do not use these dimensions as below, please consult with TSMC. Scribe line dummy bar includes two
duplicates of 3.5 um wide structures. Please refer to Fig. 4.5.54.5.1 for details.
Rule No.
CO.W.3
M1.W.6
VIAx.W.4
VIAx.W.5
VIAx.EN.7
VIAx.S.6
Mx.W.6
VIAy.W.4
VIAy.W.5
VIAy.S.6
VIAy.S.7
My.W.6
VIAz.W.4
VIAz.W.5
VIAz.S.6
VIAz.S.7
Mz.W.6
VIAr.W.4
VIAr.W.5
VIAr.S.6
VIAr.S.7
Mr.W.6
Mu.W.6
VIAu.W.4
VIAu.W.5
VIAu.EN.7
VIAu.S.6
VIAu.S.7
CB.W.4
CB.EN.3
AP.W.4
CB2.W.6
SR.R.5U
Description
Width of CO bar in SLDB.
Width of M1 metal line in SLDB.
Width of VIAx bar in SLDB.
Width of VIAx hole in SLDB.
Enclosure of VIAx hole by Mx in SLDB.
Space of VIAx hole in SLDB.
Width of Mx metal line in SLDB.
Width of VIAy bar in SLDB.
Width of VIAy hole in SLDB.
Space of VIAy hole in SLDB.
Space of VIAy hole to VIAy bar in SLDB
Width of My metal line in SLDB.
(DRC tolerance at 45-degree turning: ±0.02)
Width of VIAz bar in SLDB.
Width of VIAz hole in SLDB.
Space of VIAz hole in SLDB.
Space of VIAz hole to VIAz bar in SLDB
Width of Mz metal line in SLDB.
(DRC tolerance at 45-degree turning: ±0.02)
Width of VIAr bar in SLDB.
Width of VIAr hole in SLDB.
Space of VIAr hole in SLDB.
Space of VIAr hole to VIAr bar in SLDB
Width of Mr metal line in SLDB.
(DRC tolerance at 45-degree turning: ±0.02)
Width of Mu metal line in SLDB
(DRC tolerance at 45-degree turning: ±0.02)
Width of VIAu bar in SLDB.
Width of VIAu hole in SLDB.
Enclosure of VIAu hole by Mu in SLDB.
Space of VIAu hole in SLDB.
Space of VIAu hole to VIAu bar in SLDB
Width of CB/CBD/RV line opening in SLDB. (Tolerance 0.01 μm)
Enclosure of CB/CBD/RV by AP in SLDB. (Tolerance 0.01 μm)
Width of AP bar in SLDB.
Width of CB2_WB/CB2_FC line opening in SLDB.
Please add VIA holes in metal lines of SLDB as many as possible.
Label
P
Q
B
D
J
G
Q
B
D
G
E
Op.
=
=
=
=


=
=
=


Rule
0.06
0.5
0.5
0.07
0.015
0.35
0.5
0.5
0.14
0.34
0.68
R
=
3.5
B
D
G
E
=
=


0.5
0.36
0.54
0.54
R
=
3.5
B
D
G
E
=
=


0.5
0.46
0.44
0.44
S
=
3
T
=
6
B
D
I, H
G
E
U
X
V
W
=
=



=

=
=
0.5
0.36
0.3
0.54
0.54
2
1
4
2
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
Fig. 4.5.54.5.1. Cross-sectional view of scribe line dummy bar
(Mz, My as top metal)
Before LOP:
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Post LOP:
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
Cross-sectional view of scribe line dummy bar
(Mr as top metal)
Before LOP:
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Post LOP:
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
Cross-sectional view of scribe line dummy bar
When using Mu design (Mu as top metal, Mz as top-1 metal)
For Mu design, the structure of scribe line dummy bar (SLDB) is different from the general one in
Mtop/VIAtop/VIAtop-1 when using Mu/Mz as Mtop/Mtop-1. Please see the following figure highlighted in the
green circle.
Before LOP:
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Post LOP:
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whole or in part without prior written permission of TSMC.
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Cross-sectional view of scribe line dummy bar
When using Mu design (Mu as top metal, My as top-1 metal)
For Mu design, the structure of scribe line dummy bar (SLDB) is different from the general one in Mtop/VIAtop
when using Mu/My as Mtop/Mtop-1. Please see the following figure highlighted in the green circle.
Before LOP:
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Post LOP:
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Top view of scribe line dummy bar
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Before LOP:
Scribe line
Chip
Scribe line dummy bar
Assembly
isolation
Seal ring
Outer
SR
Wall
Inner
SR
Wall
Grid: 0.005um
AP
AP
Metal
8 um
4 um
CB/CBD
CB/CBD
CB2
CB/CBD
CB2
2 um
2 um
CB2_FC/CB2_WB
AP
Post LOP:
2 um
2 um
X’(X-section)
X
Contact
0.29 um
0.06
um
0.06
um
2.62 um
0.97 um
0.5um
3.5 um
0.5um
3.5 um
2 um
2 um
6 um
6 um
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whole or in part without prior written permission of TSMC.
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Top view of scribe line dummy bar (Mx/Vx)
* Recommended value, DRC only checks min. value.
Layer
B
C
D
G
J
K
L
M
N
VIAx
0.5
0.5
0.07
0.35
0.215*
0.5
2.86
0.17
0.5
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Top view of scribe line dummy bar (My/Vy and Mz/Vz)
* Recommended value, DRC only checks min. value.
Layer
VIAy
VIAz
B
0.5
0.5
C
0.5
0.5
D
0.14
0.36
E
0.68
0.57*
F
0.86
0.64
G
0.34
0.76*
M
0.17
0.56
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whole or in part without prior written permission of TSMC.
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Top view of scribe line dummy bar (Mr/Vr)
* Recommended value, DRC only checks min. value.
Layer
B
C
D
E
F
G
M
VIAr
0.5
1
0.46
0.52*
0.54
0.8*
0.63
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Top view of scribe line dummy bar (Mu/Vu)
* Recommended value, DRC only checks min. value.
Layer
B
C
D
E
F
G
H
I
M
VIAu / VIAz
0.5
0.5
0.36
0.57*
0.64
0.76*
1.07*
0.57*
0.56
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4.5.55 Resistor Warning Rules
RMDMYn (CAD layer 116;x , x = 1~10) and RMDMYAP (116;16) are dummy layers for DRC/LVS to recognize
the metal resistor. RMDMY breaks the connection in LVS, but DRC does not break the connection.
Rule No.
RM.WARN.1
RM.WARN.2
RM.WARN.3
RM.WARN.4
RM.WARN.5
Mn
Description
CO overlap {NWDMY AND NW} is not allowed
CO overlap silicided PO/OD resistor is not allowed
CO overlap {RMDMY1 AND M1} is not allowed
{VIAn OR VIAn-1} overlap {RMDMYn AND Mn} is not allowed. (n = 1~top)
RV overlap {{RMDMYAP AND AP} OR {RMDMYn AND Mn}} is not allowed. (n = top)
RMDMY
Mn
RMDMY
Mn
RMDMY
Label
Op.
VIAn-1
VIAn-1
X
Mn
RMDMY
VIAn-1
VIAn-1
X
Mn
RMDMY
X
VIAn-1
RM.WARN.4
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4.5.56 DRM and DRC Completeness
Rule No.
Description
Label
Value
DRM.R.1 is a rule created to remind you that the following DRM and DRC must be
checked before tape-out.
DRM.R.1
1. T-N45-CL-DR-003 & T-N45-CL-DR-017 is pad and assembly related design rule that
is not included into this design rule. Please make sure the DRC of T-N45-CL-DR-003 &
T-N45-CL-DR-017 has been executed before tape-out.
2. Antenna deck is seperated from the main. Please make sure the Antenna deck has
been executed before tape-out.
V
If the above items have been checked, this violation can be ignored. (please refer to the
following Figure)
Figure 4.5.56.1 DRM.R.1 handing flow
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5 Layout Guidelines for the Device
Geometry Effect
This chapter provides information about the following:
5.1 Layout Rules for the WPE (Well Proximity Effect)
5.2 Layout Guidelines for LOD (Length of the OD region) Effect
5.3 Layout Guidelines for OSE (OD Space Effect)
5.4 Layout Guidelines for PSE (Poly Space Effect)
5.5 Layout Guidelines for d-CESL Effect
5.1
Layout Rules for the WPE (Well Proximity
Effect)
NMOS or PMOS very close to well edge will exhibit a difference in threshold voltage (Vt) and drive current (Id)
from that of the device located remotely from the well edge. As well edge and gate spacing gets smaller, the Vt
of MOS device is raised and the Id is degraded.
This WPE phenomenon occurs to every MOS: standard Vt, high Vt, low Vt , thin oxide MOS, and thick oxide
MOS.
SPICE model has included the WPE effect. Users need to input SCA, SCB, and SCC in the netlist to activate
these new features. (SCA, SCB, and SCC can be treated as geometry factors derived from device geometry
and its well environment –distances from Well edge(s) to gate.)
For the sensitive circuit, e.g. constant current source or differential input pair, which needs precise device
parameter control (e.g. ΔVt <5mV and ΔId<2%,) please use SPICE model to calculate the required controls
then design accordingly.
Rule No.
PO.S.14.GSm®
PO.S.14.LPm®
PO.EN.1.GSm®
PO.EN.1.LPm®
PO.EN.2.GSm®
PO.EN.2.LPm®
PO.EN.3.GSm®
PO.EN.3.LPm®
Device
Gate space to (OD2 OR (NW OR NT_N)) in Core NMOS
Gate space to (OD2 OR (NW OR NT_N)) in Core NMOS
Gate enclosure by ((NW NOT OD2) NOT NT_N ) in Core PMOS
Gate enclosure by (NW NOT NT_N ) in Core PMOS
Gate enclosure by (OD2 NOT (NW OR NT_N)) in IO NMOS.
Gate enclosure by (OD2 NOT (NW OR NT_N)) in IO NMOS.
Gate enclosure by ((NW AND OD2) NOT NT_N) in IO PMOS
Gate enclosure by (NW NOT NT_N) in IO PMOS
Label
Op.








The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Rule
0.8
1.4
1.0
1.4
3.7
2.0
2.3
1.8
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1. The OD2 layout will change the Well pattern on mask due to logic operation. Therefore, not only NW layout
but also OD2 layout will impact WPE effect. Please refer to the figure 5.1.1 and logic operation of the
above four recommendations.
2. For the dimension smaller than the above rules, the Vt of MOS device is raised as well as the Id is
degraded. This effect increases with the reduction of the space or enclosure dimension.
3. The WPE phenomenon occurs to every MOS: standard Vt, high Vt, low Vt , thin oxide MOS, and thick oxide
MOS.
4. If the above dimension is impossible to comply with in the critical circuit requiring tight matching in
threshold voltage or Id, identical layouts with identical well enclosure dimension should be kept. (Figure
5.1.1)
5. If the distance between gate and well is the same, the WPE impact from the poly end cap direction is
smaller than that from the source/drain direction.
6. SPICE model has included the WPE effect. Users need to input SC in the netlist to activate these new
features. During post-simulation, LPE will automatically extract the SC from layout, and add the extracted
SC to the netlist, then activate the model properly. (SC is the distance between gate to Well edge, please
refer to the Appendix in the SPICE document). Not only NW layout but also OD2 layout will impact WPE
calculation. Please refer to the 4 WPE recommendations in this section and the Figure 5.1.1.
NW
SC1
SC1
SC4
SC2
SC2
SC4
SC3
SC3
SC1
SC1
SC2
SC4
OD2
SC2
SC3
Figure 5.1.1 Both NW layout and OD2 layout are related to WPE. (For LP process, only NW layout will
impact both core and IO PMOS WPE calculation)
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7. The detailed information regarding the device parameter impact by one side neighboring Well, or two sides
or four sides is as follows.
Core N/PMOS
(N45GS=N40G)
ΔVt < 5mV
ΔId < 2%
IO N/PMOS
(N45GS=N40G)
ΔVt < 5mV
ΔId < 2%
1 side
0.5/0.4
0.6/0.7
2.0/ 1.2
0.7/0.4
2 sides
0.6/0.8
0.7/0.8
2.8/1.8
1.6/1.1
4 sides
0.7/0.9
0.8 /1.0
3.7/2.3
2.1/1.5
Core N/PMOS
(N45LP/LPG, N40LP/LPG)
ΔVt < 5mV
ΔId < 2%
IO N/PMOS
(N45LP/LPG, N40LP/LPG)
ΔVt < 5mV
ΔId < 2%
1 side
0.8/0.6
0.8
1.0/0.8
0.6/0.4
2 sides
1.2/1.0
1
1.4
0.8
4 sides
1.4
1.2/1.4
2.0/1.8
1.2
Well edge
Well edge
Well edge
One side
gate space to well edge
in other three sides ≥ 10um
Well edge
Two sides
gate space to well edge
in other two sides ≥ 10um
Four sides
Figure 5.1.2 One/two/four side for WPE
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F o r e x a m p le , t o m e e t Δ V t < 5 m V in c o r e N / P M O S ,
p le a s e k e e p g a t e s p a c e t o w e ll e d g e  2 . 0 u m in 4
poor
s id e s .
 2 .0 u m
W e ll e d g e
OK
 2 .0 u m
 2 .0 u m
 2 .0 u m
 2 .0 u m
W e ll e d g e
OK
 2 .0 u m
W e ll e d g e
W e ll e d g e
Figure 5.1.3 Device Placement for Matching Pairs
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5.2
Layout Guidelines for LOD (Length of the
OD region) Effect
5.2.1
What is LOD?
1.
The device performance (Vt or Id) will be impacted by LOD effect. It is due to the different levels of
mechanical stress induced by the different OD length.
2.
SPICE model has included the LOD effect. Users need to input SA and SB in the netlist to activate
these new features. (SA and SB are the distance between gate to OD edge). (Figure 5.2.1.1)
SA
SA
SB
1
1
SB
SA
2 SA
3
SB
2
SB
3
Figure 5.2.1.1 Example of SA and SB
5.2.2
How to have a precise LOD Simulation
1. For pre-sim cases
-
PDK: Every MOS device in PDK has a layout view. So, when you use TSMC PDK to do design, the
corresponding pcell layouts are also ready. TSMC PDK includes Skill code which can estimate the SA
and SB values from the corresponding pcell before real layouts. The pre-sim netlist will include the
accurate SA and SB parameters.
-
If you do not use PDK cell, you need to estimate the SA and SB first, and put them into the netlists as
transistor instance parameters.
SA and SB are 0.29μm for core devices and 0.48μm for IO devices in the layout of test structure for
TSMC SPICE model generation. If you use the above dimensions precisely during layout design, the
LPE will not do any LOD correction.
2. For post-sim cases (layouts are ready), designers need to use TSMC LPE deck to extract the SA and SB
directly from layouts. The LPE will automatically add the extracted SA and SB to the netlists and thus the
simulators will then activate the models properly.
3. Avoid irregular OD layout due to model accuracy concerns. (Figure 5.2.2.1)
Figure 5.2.2.1
Irregular OD
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5.3
Layout Guidelines for OSE (OD Space Effect)
5.3.1
What is OSE?
1.
2.
The MOS characteristics will be impacted by OSE. This is due to the varying levels of STI mechanical
stress induced by differences in OD space.
The MOS characteristics depend on the surrounding OD space in both the “L-direction” (OD-SL) and the
“W-direction” (OD-SW). (Figure 5.3.1.1)
O D -S W
O D -S L
L -d ir e c tio n
W -d ir e c tio n
Figure 5.3.1.1 Example of OD-SL and OD-SW
5.3.2
Id change on device due to OSE
1.
The drain current of MOS core or IO device shows complex OD-SL (or OD-SW) dependence. (Figure
5.3.2.1)
2.
The closer the actual OD space of your layout to the SPICE structure (reference point in Figure 5.3.2.1),
the less impact.
r e fe r e n c e
P MO S
+%
0
I/ O O D - S W ( N 4 0 G )
 Id s a t ( % )
 Id s a t( % )
I/ O O D - S L ( N 4 0 G )
r e fe r e n c e
PM O S
+%
0
NMO S
-%
NM O S
-%
0.1
1
L D ir O D S p a c e (u m )
10
0.1
1
W
10
D ir O D S p a c e ( u m )
Figure 5.3.2.1 Id shift (%) due to different OSE in core and I/O NMOS/PMOS
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1.
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How to reduce the differences between presimulation and post-simulation
Standard cell:

OD space to standard cell boundary: 0.05~0.07um in the L-direction

OD inside the FILLER cell is highly recommended. (Figure 5.3.3.1)

FILLER cell with fixed 0.07um OD space to standard cell boundary is recommended. (Figure 5.3.3.1)

Accurate cell characterization with OD on all four sides. (Figure 5.3.3.2)

i.
Complete the cell layout
ii.
Add 2nd PO outside the cell (refer to PSE)
iii.
Add dummy pattern outside the cell
1.
Left/right: add FILLER cell
2.
Top/down: add OD
iv.
LPE netlist extraction with OSE
v.
Post-simulation with OSE
Standard cell array
i.
No empty area inside the cell array. FILLER cell is must.
ii.
Add OD/PO FILLER cells and {OD OR Dummy OD} on all four sides of the block boundary
(Figure 5.3.3.2)
Filler 1
Filler 2
Filler 3
OD
PO
0.14
OD
0.09
OD
OD
0.24 um~
0.12 um~
0.12 um ~
0.28 um
0.14 um
0.14 um
OD
OD
Figure 5.3.3.1 TSMC FILLER cell example with fixed 0.07um OD space to standard cell boundary.
Consecutive Filler 1 is not recommended.
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Dum m y O D
Dum m y O D
O D /P O F IL L E R c e lls
Dum m y O D
O D /P O F IL L E R c e lls
O D /P O F IL L E R c e lls
O D /P O F IL L E R c e lls
Dum m y O D
Figure 5.3.3.2 Add OD/PO FILLER cells and Dummy OD on four sides
2.
Large IP:

Recommend to insert SR_DOD by TSMC utility within IP to reduce the pre-/post-simulation difference.

If no SR_DOD, recommend to insert a guard ring with ≥ 0.5um OD, to define the IP boundary.

DOD/DPO is still needed, at > 2um distance to main OD, to meet the OD and PO density rule.

LPE netlist extraction with OSE.

Post-simulation with OSE.
3.
DOD/DPO utility:

N45 utility, with SR_ DOD and SR_DPO (Figure 5.3.3.3), is provided to match the SPICE test key with
0.1um L-direction OD space and 0.88um W-direction OD space.
SR_DO D/
SR_DPO
D O D /D P O
Figure 5.3.3.3 example of SR_ DOD and SR_DPO
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To optimize model simulation accuracy, avoid irregular OD layout in either the L-direction or the Wdirection. (Figure 5.3.3.4)
Figure 5.3.3.4 Irregular OD
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5.4
Layout Guidelines for PSE (Poly Space
Effect)
5.4.1
What is PSE?
Poly space will impact the MOS characteristics. Besides the 1st poly space, the 2nd poly space also impacts the
MOS characteristics. But the PSE by the 2nd poly space is smaller than that by the 1st poly space. (Figure
5.4.1.1)
1
2
nd
st
p o ly
p o ly
1
st
p o ly
Ta rg e t g a te
1
2
nd
p o ly
2
nd
st
p o ly
p o ly
1
st
p o ly
Ta rg e t g a te
2
nd
p o ly
Figure 5.4.1.1 Example of the 1st poly and the 2nd poly
5.4.2
Id change on device due to PSE
1.
PSE affects the drain current of core devices. (Figure 5.4.2.1)
2.
The closer the actual PO space of your layout to the SPICE structure, the less impact.
P M O S (N 4 0 G )
(N 4 0 G )
 Id s a t ( % )
 Id s a t ( % )
NM OS
+%
+%
0 .0
0 .0
0 .1 0
0 .1 5
0 .2 0
0 .2 5
P o ly S p a c e ( u m )
0 .1 0
0 .2 0
0 .3 0
P o ly S p a c e ( u m )
Figure 5.4.2.1 Id shift (%) due to PSE in NMOS/PMOS
5.4.3
How to reduce the differences between presimulation and post-simulation on N40G circuit?
1. Make sure to insert the 1st poly to meet the poly space rule (PO.S.2). And follow PO.S.18.GS® carefully.
2. During the characterization, add a 2nd SR_DPO (you can use TSMC’s DOD/DPO utility) next to the 1st
SR_DPO on both sides of the cell boundary, to reduce the difference between pre-simulation and postsimulation.
3. Add a 2nd SR_DPO on both sides of the IP boundary before characterization as well.
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5.5
Layout Guidelines for d-CESL Effect
5.5.1
What is d-CESL effect?
N40G uses d-CESL to enhance the device performance. However, additional differences between presimulation and post- simulation have been observed on the core devices near the stress liner boundary.
(Figure 5.5.1.1)
Figure 5.5.1.1 Example of d-CESL stress liner boundary
5.5.2
Id change on the N40G device due to d-CESL
1.
d-CESL effect affects the drain current of N40G core devices. (Figure 5.5.2.1)
2.
The closer the actual d-CESL of your layout to the SPICE structure, the less impact.
N M O S EN X
N M O S EN Y
0
－ %
－ %
 Id s a t ( % )
 Id s a t ( % )
0
0 .1 0
1 .0 0
1 0 .0 0
0 .0 1
E N X (u m )
0 .1 0
1 .0 0
1 0 .0 0
E N Y (u m )
PM O S EN X
PM O S EN Y
0
＋ %
－ %
 Id s a t ( % )
 Id s a t ( % )
0
0 .1 0
1 .0 0
－ %
1 0 .0 0
E N X (u m )
0 .0 1
0 .1 0
1 .0 0
1 0 .0 0
E N Y (u m )
Figure 5.5.2.1 Id shift (%) due to d-CESL in NMOS/PMOS
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whole or in part without prior written permission of TSMC.
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How to reduce the differences between presimulation and post-simulation on N40G circuit?
1. Standard cell:

X direction: keep continuous, aligned NW and PW structure, like a standard cell row. Avoid N/P well
interleaving. (Figure 5.5.3.1)

Y direction: keep regular N-N-P-P well structure, like a standard cell row. (Figure 5.5.3.1)

Keep the same distance from gate to well boundary for the matching devices, no matter source/drain
or endcap direction (same approach as WPE).
2. IP:

With N+/NW guard ring (OD width ≥ 0.1um) surrounded.

P+ ACTIVE in this IP space to OD of the N+/NW guardring ≥ 0.86um.

IP boundary keeps 1.2um space with other IP boundary.

Recommend: without empty area
i.
Move the white space to be between the different types of MOS in both the X and Y directions,
not between the same types of MOS.
ii.
The well boundary should be in the middle, for the X direction.
3. Chip implementation:

Expected <3% performance difference (worse case) between pre-simulation and post-simulation for
all IPs and standard cells with the above guidelines.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Not Good
Y - d ir e c t io n
NW
X - d ir e c t io n
NW
PW
NW
PW
PW
NW
Not Good
PW
NW
PW
NW
NW
PW
NW
PW
Figure 5.5.3.1 Example of NW/PW placements
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6 N40LP/LPG Design Information
This chapter contains the following N40LP/LPG design information:
6.1 Non-shrinkable Layout Rules
6.2 Design Flow For Tape-Out
In the following, “Drawn dimension” is used for describing dimension of schematics and layout before
shrinking, which are usually seen in customers’ design environment.
“Post-shrink dimension” is used for describing dimension of schematics and layout after shrinking, which are
used in TSMC mask database processing after tape-out.
6.1
Non-shrinkable Layout Rules
6.1.1
Purpose:
A set of non-shrinkable rules are defined to meet the below requirements:
1. The limitation of the silicon process step, testing probing, and assembly.
2. Prevent DRC false errors from 110% (or any other finer scale up ratio like 111%) size up steps.
These rules are mainly for migrating existing 45LP IP to 40LP technology by layout re-use approach.
6.1.2
Non-shrinkable Rules
Rule No.
PO.S.2.LP.S
OD25_33.W.1.LP.S
OD25_33.W.2.LP.S
HVD_N25.W.2.S
HVD_N25.S.11.S
HVD_N25.O.1.S
HVD_N25.L.1.S
HVD_P25.W.2.S
HVD_P25.S.11.S
HVD_P25.O.1.S
HVD_P25.L.1.S
Description
The poly gate space range to neighboring poly [for channel length <
0.06μm], and allow the violation with length ratio < 30% on one side
and one segment.
The length ratio = violation length / device width.
This rule is for poly gate CDU control
Channel length of 2.5V NMOS overdrive to 3.3V (NMOS Gate AND
OD25_33).
Channel length of 2.5V PMOS overdrive to 3.3V (PMOS Gate AND
OD25_33).
Channel width of {Gate INTERACT HVD_N} for SPICE accuracy.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_25}
[INSIDE HVD_N].
Overlap of {I/O NMOS GATE}.
Channel length of {GATE INTERACT HVD_N}.
Channel width of {Gate INTERACT HVD_P} for SPICE accuracy.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_25}
[INSIDE HVD_P].
Overlap of {I/O PMOS GATE}
Channel length of {GATE INTERACT HVD_P}
Label
Op.
Rule
G
=
0.13 ~ 0.22
or 0.32
A

0.55
B

0.44
N

1.115
W

0.60
J
M
=

0.33
0.88
N

1.115
W

0.60
J
M
=
0.28
0.66
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

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
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Stress Migration and Wide Metal Spacing Rules
Adjustment (Rule Relaxing)
The rules listed in the below table are adjusted to avoid DRC false alarm on 110% size-up circuits.
Except 110% size-up circuits, other circuits have to follow the stress migration and wide metal
spacing rules in CLN45 logic DRM. However, the following rules will be met automatically as
long as CLN45 rules are met.
Rule No.
OD.L.1.S
OD.L.2.S
PO.L.1.S
M1.W.3.S
M1.S.2.S
M1.S.2.1.S
M1.S.2.2.S
M1.S.2.3.S
M1.S.2.4.S
M1.S.2.5.S
M1.S.2.6.S
M1.S.2.7.S
M1.S.3.S
VIAx.R.2.S
VIAx.R.3.S
VIAx.R.4.S
VIAx.R.5.S
VIAx.R.6.S
VIAx.R.11.S
Mx.W.3.S
Mx.S.2.S
Mx.S.2.1.S
Mx.S.2.2.S
Mx.S.2.3.S
Mx.S.2.4.S
Mx.S.2.5.S
Description
Maximum length of {ACTIVE (source) [width < 0.12 µm] interacts with butted_STRAP} if no CO in M region.
Maximum OD length [OD width < 0.12µm] between two contacts as well as between one contact and the OD lineend. (except {RFDMY AND RFIP_DMY} and {MOMDMY(155;21) SIZING 1.2um})
Maximum PO length between two contacts, as well as the length from any point inside PO gate to nearest CO
when the PO width is < 0.08μm. (This check doesn’t include ESD protection devices.)
Maximum width
(This check doesn’t include the SEALRING_ALL (162;2) region)
Space [at least one metal line width > 0.19μm (W1) and the parallel metal run length > 0.3μm (L1)] (union
projection)
Space [at least one metal line width > 0.265μm (W2) and the parallel metal run length > 0.3μm (L2)] (union
projection)
Space [at least one metal line width > 0.345μm (W3) and the parallel metal run length > 0.44μm (L3)] (union
projection)
Space [at least one metal line width > 0.685μm (W4) and the parallel metal run length > 0.685μm (L4)] (union
projection)
Space [at least one metal line width > 0.17 μm (W1) and the parallel metal run length > 0.3μm (L1)] (union
projection)
Space [at least one metal line width > 0.24μm (W2) and the parallel metal run length > 0.3μm (L2)] (union
projection)
Space [at least one metal line width > 0.31μm (W3) and the parallel metal run length > 0.44μm (L3)] (union
projection)
Space [at least one metal line width > 0.62μm (W4) and the parallel metal run length > 0.685μm (L4)] (union
projection)
Space [at least one metal line width > 1.65μm (W5) and the parallel metal run length > 1.65μm (L5)] (union
projection)
At least two VIAx with space  0.16μm (S1), or at least four VIAx with space  0.7μm (S1’) are required to connect
Mx and Mx+1 when one of these two metals has width and length (W1) > 0.235μm.
At least four VIAx with space  0.16μm (S2), or at least nine VIAx with space  0.92μm (S2’) are required to
connect Mx and Mx+1 when one of these two metals has width and length (W2) > 0.605μm.
At least two VIAx must be used for a connection that is  1.14μm (D) away from a metal plate (either Mx or Mx+1)
with
>
1.26μm (D) away from a metal plate)
 2.8μm (D) away from a metal plate (either Mx or
Mx+1) with length > 1.54μm (L) and width > 1.54μm (W). (It is allowed to use one VIAx for a connection that is >
3.08μm (D) away from a metal plate (either Mx or Mx+1) with length > 1.54μm (L) and width > 1.54μm (W).)
At least two VIAx must be used for a connection that is  7.1μm (D) away from a metal plate (either Mx or Mx+1)
with length > 7.7μm (L) and width > 2.31μm (W). (It is allowed to use one VIAx for a connection that is > 7.81μm
(D) away from a metal plate (either Mx or Mx+1) with length > 7.7μm (L) and width > 2.31μm (W)).
Single VIAx is not allowed in “H-shape" Mx+1 when all of the following conditions come into existence:
(1) The Mx+1 has “H-shape" interact with two metal holes: both two metal hole length 
(L2) and two metal
hole area  5um²
(2) The VIAx overlaps on the center metal bar of this “H-shape” Mx+1
(3) The center metal bar length  1um (L) and the metal bar width
 0.235 um.
Maximum width
(This check doesn’t include the SEALRING_ALL (162;2) region)
Space [at least one metal line width > 0.19μm (W1) and the parallel metal run length > 0.3μm (L1)] (union
projection)
Space [at least one metal line width > 0.265μm (W2) and the parallel metal run length > 0.3μm (L2)] (union
projection)
Space [at least one metal line width > 0.345μm (W3) and the parallel metal run length > 0.44μm (L3)] (union
projection)
Space [at least one metal line width > 0.685μm (W4) and the parallel metal run length > 0.685μm (L4)] (union
projection)
Space [at least one metal line width > 0.17 μm (W1) and the parallel metal run length > 0.3μm (L1)] (union
projection)
Space [at least one metal line width > 0.24μm (W2) and the parallel metal run length > 0.3μm (L2)] (union
projection)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
Op.
Rule

0.44

66

19.8

4.95

0.08

0.12

0.14

0.21

0.075

0.085

0.13

0.15

0.5

4.95

0.1

0.12

0.15

0.21

0.075

0.11
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Rule No.
Mx.S.2.6.S
Mx.S.2.7.S
Mx.S.3.S
VIAy.R.2.S
VIAy.R.3.S
VIAy.R.4.S
VIAy.R.5.S
VIAy.R.6.S
VIAy.R.11.S
My.W.3.S
My.S.2.S
My.S.2.1.S
My.S.3.S
My.S.4.S
VIAz.R.2.S
VIAz.R.3.S
Mz.W.2.S
Mz.S.2.S
Mz.S.3.S
VIAr.R.2.S
VIAr.R.3.S
Mr.W.2.S
Mr.S.2.S
Mr.S.3.S
Confidential – Do Not Copy
Document No.
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: T-N45-CL-DR-001
: 2.6
Description
Label
Space [at least one metal line width > 0.31μm (W3) and the parallel metal run length > 0.44μm (L3)] (union
projection)
Space [at least one metal line width > 0.62μm (W4) and the parallel metal run length > 0.685μm (L4)] (union
projection)
Space [at least one metal line width > 1.65μm (W5) and the parallel metal run length > 1.65μm (L5)] (union
projection)
At least two VIAy with space 
 0.63μm (S1’) are required to
connect My and My+1 when one of these two metals has width and length (W1) > 0.465μm.
At least four VIAy with space  0.32μm (S2), or at least nine VIAy with space  0.85μm (S2’) are required to
connect My and My+1 when one of these two metals has width and length (W2) > 1.255μm.
At least two VIAy must be used for a connection that distance  1.4μm (D) away from a metal plate (either My
or My+1) with length > 0.77μm (L) and width > 0.77μm (W). (It is allowed to use one VIAy for a connection that is
> 1.54μm (D) away from a metal plate (either My or My+1) with length > 0.77μm (L) and width > 0.77μm (W).)
At least two VIAy must be used for a connection that distance  2.8μm (D) away from a metal plate (either My
or My+1) with length > 2.2μm (L) and width > 2.2μm (W). (It is allowed to use one VIAy for a connection that is >
3.08μm (D) away from a metal plate (either My or My+1) with length > 2.2μm (L) and width > 2.2μm (W).)
At least two VIAy must be used for a connection that distance  7.1μm (D) away from a metal plate (either My or
My+1) with length > 11μm (L) and width > 3.3μm (W). (It is allowed to use one VIAy for a connection that is >
7.81μm (D) away from a metal plate (either My or My+1) with length > 11μm (L) and width > 3.3μm (W)).
Single VIAy is not allowed in “H-shape" My+1 when all of the following conditions come into existence:
(1) The My+1 has “H-shape" interact with two metal holes: both two metal hole length  5um (L2) and two metal
hole area  5um²
(2) The VIAy overlaps on the center metal bar of this “H-shape” My+1
 0.465um.
(3) The center metal bar length  1um (L) and the metal bar width
Maximum width
Space [at least one metal line width > 0.235μm (W1) and the parallel metal run length > 0.575μm (L1)] (union
projection)
Space [at least one metal line width > 0.21μm (W1) and the parallel metal run length > 0.575μm (L1)] (union
projection)
Space [at least one metal line width > 1.65μm (W2) and the parallel metal run length > 1.65μm (L2)] (union
projection)
Space [at least one metal line width > 4.95μm (W3) and the parallel metal run length > 4.95μm (L3)] (union
projection)
At least two VIAz with spacing  1.87μm are required to connect Mz and Mz+1 when one of these metals has a
width and length > 1.98μm.
At least two VIAz must be used for a connection that is  5μm (D) away from a metal plate (either Mz or Mz+1)
with length > 11μm (L) and width > 3.3μm (W). (It is allowed to use one VIAz for a connection that is > 5.5μm (D)
away from a metal plate (either Mz or Mz+1) with length > 11μm (L) and width > 3.3μm (W)).
Maximum width [except bond pad]
Space [at least one metal line width > 1.65μm (W1) and the parallel metal run length > 1.65μm (L1)]
Space [at least one metal line width > 4.95μm (W2) and the parallel metal run length > 4.95μm (L2)]
At least two VIAr with spacing  1.87 μm are required to connect Mr and Mr+1 when one of these metals has a
width and length > 1.98 μm.
At least two VIAr must be used for a connection that is  5 μm (D) away from a metal plate (either Mr or Mr+1)
with length > 11 μm (L) and width > 3.3 μm (W). (It is allowed to use one VIAr for a connection that is > 5.5 μm
(D) away from a metal plate (either Mr or Mr+1) with length > 11 μm (L) and width > 3.3 μm (W)).
Maximum width [except bond pad]
Space [at least one metal line width > 1.65 μm (W1) and the parallel metal run length > 1.65 μm (L1)]
Space [at least one metal line width > 4.95 μm (W2) and the parallel metal run length > 4.95 μm (L2)]
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.
Rule

0.13

0.165

0.5

13.2

0.19

0.15

0.5

1.5



13.2
0.5
1.5



13.2
0.65
1.5
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

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: 2.6
Pad Rule for Wire Bond
Please refer to T-N45-CL-DR-003 “TSMC 45NM/ 40NM WIRE BOND, EUTECTIC FLIP CHIP AND
INTERCONNECTION DESIGN RULE” for the detailed rules and guidelines.
Since the pad rule is limited by testing and assembly capability, customer has to check the drawn
layout dimension, i.e. dimesnion before 90% shrink.
6.1.4.1
Non-shrinkable Rules:
Rule
Rule No.
Description
Pad pitch that allows 90% shrink

Length of CB/CB2 (the edge perpendicular to nearby
#CB2.W.2

prime chip edge)
#CB2.P.1
Single In-line
40 ≤ Pitch
45
Staggered
50 ≤ Pitch < 60
50
55 ≤ Pitch < 60
88
Table notes:
All numbers are drawing dimensions before 90% shrink.
Minimum pad pitch that allows 90% shrink: 45um (single inline); 55um (staggered).
Items denoted by “#” depend on the capability of each individual probing/ assembly house.
6.1.5



Flip Chip Bump Rules
Please refer to the following flip chip design rule manuals for the detailed rules and guidelines.
DRM No.
DRM title
T-N45-CL-DR-003
TSMC 45 NM/ 40 NM WIRE BOND, EUTECTIC FLIP CHIP AND INTERCONNECTION
DESIGN RULE
T-N45-CL-DR-017
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD UP SUBSTRATE
(FCBGA, FLIP CHIP BALL GRID ARRAY) AND INTERCONNECTION DESIGN RULE
T-N45-CL-DR-022
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH LAMINATE SUBSTRATE
(FCCSP, FLIP CHIP CHIP SCALE PACKAGE) AND INTERCONNECTION DESIGN RULE
The bumping rules for flip-chip design are critical on the bumping ball formation. Customers must meet
the non-shrinkable rules before 90% linear shrink.
The bump height and diameter would decrease due to UBM shrinking. Customers must evaluate this
bump height change by themselves.
6.1.5.1
Non-shrinkable Rules:
Rule No.
Description
#UBM.P.1
UBM.EN.1t
#UBM.EN.2
BP.W.4t
#BP.W.6t
BP.EN.5t
BP.EN.7t
Bump pitch
UBM enclosure by prime chip edge
Enclosure by AP
Width of CBD/CB2_FC under UBM area
Width of UBM
CBD/CB2_FC enclosure by UBM
CBD enclosure by Mtop
Rule







167
55.6
2.2
55.6
88.9
11.1
2.2
Table notes:
Items denoted by “#” depend on the capability of each individual probing/ assembly house.
Items denoted by “t” applied for tsmc bumping only.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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6.2
Design Flow For Tape-Out
6.2.1
How to design for CLN40LP/LPG shrink
technology
 Designers must consider the following items since CLN40LP/LPG are required 90% scaling on the
drawn layout:
 IP libraries and chip are required to run timing and power characterization by
1. CLN40LP/LPG spice models with an embedded scaling factor, 0.9
2. CLN40LP/LPG BEOL RC extraction technology files with as embedded scaling factor,
0.9
 Perform full-chip timing analysis and power simulation to ensure chip functionality and
robustness.
 Since scaling factors are all set in process design kits, shrink technology CLN40LP/LPG
and its corresponding design flow is transparent to designers. Check if versions of EDA
tools – P&R, RC extractor, circuit simulator are able to support transparent shrink
design flow.
 The layout for CLN40LP/LPG must follow the related non-shrinkable rules. (Please refer
to section 6.1 “Non-shrinkable Layout Rules”.)
6.2.2
How to prepare a new design of CLN40LP/LPG
To start a whole new CLN40LP/LPG design (that is, there is no existing CLN45LP/LPG product to
shrink from), please follow the design flow in Figure 6.2.2.1.
 TSMC provides SPICE models, standard cell libraries, I/Os, and SRAM models in CLN40LP/LPG.
 Circuit designers should simulate their IP as described in section 6.2.4, paying attention on critical
circuits. Chip designers should follow the same physical design and timing sign-off flow as
CLN45LP/LPG.
Figure 6.2.2.1 Start a CLN40 new tape-out.
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whole or in part without prior written permission of TSMC.
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CLN45LP/LPG Design Migration to
CLN40LP/LPG Technology
 SRAM replacement: Designers must replace the CLN45LP/LPG SRAM cell by CLN40LP/LPG
one. The following SRAM cells are proven by TSMC.
Process Type
SRAM
Cell Size (Before shrunk)
CLN40LP/LPG
HD
HC
DP
HCDP
0.299um^2
0.374um^2
0.589um^2
0.741um^2
(N45 drawn dimension)
Also, designers must replace the dummy, strapping, boundary and twist cells with
CLN40LP/LPG unit-cells.
 When legacy CLN45LP/LPG IP re-usage is preferred for CLN40LP/LPG design, in order to
maintain CLN45LP/LPG IP design performance in CLN40LP/LPG technology, besides layout
size-up procedures (introduced as follows), it’s nice to add a marker layer (LP_IP_MIG:
63;45) on CLN45LP/LPG layout area for differentiating them from most CLN40LP/LPG circuit
layout area.
 110% size-up: Silicon validated N45LP analog circuits (for example: matching circuits,
current-driving at I/O circuits) layout might be preferred to be re-used. Designers may
consider 110% layout size-up relatively to other CLN40LP/LPG shrinkable circuit layout in
order to keep post-shrink dimension as close as possible to original size.
 It’s recommended to re-run simulation on legacy CLN45LP/LPG IP by CLN40LP/LPG spice
model for confirming performance acceptable. Although re-use layout approach could keep
silicon dimension quite close, due to N40LP/45LP process technology differences, there
could be some performance differences.
 For a reference layout size-up utility, please consult TSMC Design and Technology Platform
in details.
 Traditional layout 110% size-up approach would require snapping polygon grids and flattening
design hierarchies. Even with finer design grid 1nm, there could still be device layout mismatch risk.
 IP preparation phantom size-up approach:
I. Pre-requisite: Given CLN45LP/LPG layout GDSII, which is clean on CLN45LP/LPG DRC/LVS check.
II. Layout size-up: Size up CLN45LP/LPG IP GDS 110% (or 111%) and perform snapping to 1nm.
III. Size down GDSII CO/VIA layers back to their original dimension (100%) to meet N40LP drawn rules.
Modify size-up layout by swapping BJT with original BJT. Layout fixing will be necessary due to BJT
routing reconnect and size-up induced DRC violation. Add a marker CAD layer (LP_IP_MIG: 63;45) on
top of IP layout for later mask processing.
IV. Re-characterization: Run LPE/RC extraction and simulation on size-up GDSII.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Layout check and post simulation
When the layout is ready, the designer should run DRC/LVS check first. Figure 6.2.4.1 shows the
sequence.
 Once it passes DRC and LVS, perform RC extraction by scaling commands given in Figure 6.2.4.1.
Perform full-chip simulation and timing analysis on the extracted net-list (with parasitic).
 If timing closure is achieved, it is ready for tape-out. Otherwise, re-design, re-layout or make other
adjustments as needed to meet the timing goals.
By embedded scale factor (0.9) in RC extractor technology, the output of the CLN40LP/LPG RC
extractor will be CLN40LP/LPG parasitics. Please refer to section “RC extraction guideline” setting of
IP-level and chip-level extraction.
Figure 6.2.4.1 Layout check and post simulation.
N45
Library
design
Handling
Retune Chip
Layout
Interconnect
&
Layout
checking
& post-sim
Dummy
Timing Utility
closure
achieved
Tape-out
Timing N40 GDS
closure
achieved
No
Layout checking & post-simulation
N40
(N40
deckDRC with
non -shrinkable
rules + N40 LVS)
Layout checking
(DRC, LVS)
RC extraction commands:
Fire&Ice: setvar layout_scale 0.9
Star-RCXT: magnification_factor: 0.9
Full chip
SPF, netlist
Timing
with parasitic
Analysis
No
N40 SPICE
N40 SRAM
N40 Libraries
Timing closure achieved
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SPICE Guidelines for Library IP Development

TSMC provides N40LP/LPG logic and SRAM models, which could be used for circuit
pre-sim and post-sim.
 Outline for CLN40LP/LPG design
1. If using spice model with embedded scale factor =0.9, thus, at pre-sim stage, spice
net-list device size is in N45 dimension (drawn layout dimension). Otherwise,
designers need to set .option scale=0.9 in spice net-list by themselves.
2. At post-sim stage, LPE will extract device size based on drawn layout dimension and
RC extractor will take care of parasitic extraction scaling. The device size is in drawn
dimension but parasitics is extracted based on 90% shrunk layout. As a result, spice
model with embedded scale=0.9 will be used for CLN40LP/LPG simulation since it
only impacts on MOS, DIO geometric parameters but not on parasitics and electrical
parameters. With this extraction flow, both pre-sim and post-sim scale settings are
the same. Thus, it’s easier for design integration and LVS back-annotation for
debugging.
 Simulation Syntax for scaling (HSPICE only):
1. The Following is an example of embedded scaling for MOS and DIODE lib.
.option geoshrink=0.9
2.
For macro model devices resistors and varactors, scale factors are put in spice model
usage file header. It’s suitable for both pre-layout and post-layout simulation. Please
refer to the example below.
***** Macro Model Resistor and Capacitor (or Varactor) *****
.LIB scale_option_res
.param scale_res= 0.9
.ENDL scale_option_res
.LIB scale_option_cap
.param scale_cap=0.9
.ENDL scale_option_cap
.LIB scale_option_cap25
.param scale_cap25=0.9
.ENDL scale_option_cap25
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3.
There are also flags in SPICE model header for parasitic estimation in pre-layout
simulation stage.
***** Contact-to-poly parasitics *****
.LIB CCO_pre_simu
.param ccoflag=1
.ENDL CCO_pre_simu
.LIB CCO_pre_simu_hvt
.param ccoflag_hvt=1
.ENDL CCO_pre_simu_hvt
.LIB CCO_pre_simu_25
.param ccoflag_25=1
.ENDL CCO_pre_simu_25
.LIB CCO_pre_simu_na
.param ccoflag_na=1
.ENDL CCO_pre_simu_na
.LIB CCO_pre_simu_na25
.param ccoflag_na25=1
.ENDL CCO_pre_simu_na25
4.
BJT model is not a scalable model, so users can’t specify “area” in the net-list. The
model is not affected by value of scale and has already been extracted from a shrunk
size.
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whole or in part without prior written permission of TSMC.
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RC Extraction Guidelines
 For IP libraries extraction, there are WPE , DFM switches on transistors parameters for more
accurate circuit simulation. Default RC extraction technology file will scales down layout for
parasitics extraction but NOT scale on device geometric parameters.
 Full-chip timing and power simulation/characterization are required to ensure chip functionality and
robust yields.
 Layout extraction procedure (Figure 6.2.4.2.1):
Figure 6.2.4.2.1 Layout Extraction Flow
TSMC Online
CLN40LP/LPG
LPE/RCX Techfile
CLN40LP/LPG
SPICE Model
IP level
GDSII
Device & RC
Extraction
Characterize Delay,
Power
by SPICE simulation
Full-chip
DEF or
Milkyway
RC
Extraction
Full-chip
Timing, Power,
IR-drop, SI analysis
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whole or in part without prior written permission of TSMC.
IP Library
Timing
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7 Layout Rules and Recommendations for
Analog Circuits
This chapter provides information about the following topics:
7.1 User guides
7.2 Layout rules, recommendations and guidelines for the analog design
7.3 Layout rules and guidelines for device placement
7.4 Burn-in Guidelines for Analog Circuits
7.1
User Guides
1. Use these rules, recommendations, and guidelines to achieve better analog device performance and
matching. In analog circuits, good device matching provides good performance margin and production
yield.
2. The examples of analog circuits:
o
Operational Amplifier: includes differential input pair, bias circuit and current mirror.
o
DAC: includes constant current source, amplifier using external Rset to adjust full range current
and bias circuit.
o
ADC: includes comparator, amplifier, sample/hold switches, switching capacitor, and reference
voltage resistor ladder.
o
PLL: includes VCO (delay stage) and charge pump (current mirror, buffer/opamp)
o
Bandgap: BJT, current mirror, bias circuit, differential amplifier and ratioed resistor.
o
LNA and mixer
o
Sense amplifiers in memories.
o
Matching pair includes active and passive devices.
3. If your circuit has concern about the rules, recommendations, and guidelines, TSMC DRC deck can
help you to flag the violations. Analog DRC deck is bundled in the TSMC logic DRC deck. The following
two methods can specify the region to run analog part. Please also refer to the user guide in the DRC
deck.
o
Dummy layer:
 RRuleAnalog (CAD layer: 182;3): for the layout rules, recommendations, and guidelines of the
analog designs.
o
Cell selection based on the following variable:
 CellsForRRuleAnalog: only check the cells in the variable
 ExclCellsForRRuleAnalog: don’t check the cells in the variable
4. A registered symbol “U“ is marked after the rule number as the rule is not checked by DRC.
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whole or in part without prior written permission of TSMC.
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7.2
Layout Rules, Recommendations and
Guidelines for the Analog Designs
7.2.1
General Guidelines
Rule No.
Description
AN.R.1mgU
If possible, use devices with large widths. Do not use minimum widths and
lengths for performance-critical device.
Using current source device as an example, designer should refer to the device
I-V curve to check at which W/L range, the drain saturation current reaches
constant.
AN.R.2mgU
Use larger areas for transistors, resistors, and capacitor devices for better
mismatch.
AN.R.44mgU
AN.R.45mgU
AN.R.46mgU
Label
Op.
It is recommended to adopt all the advisory number of the DFM ActionRequired Rules, and also adopt all the parametric/systematic related DFM
Recommendations/Guidelines.
It is recommended not to use a very long channel device in the design. In order
to ensure the channel relaxation time of the MOS device is enough to build up
charge to the steady state, it is recommended to use <10 times of minimum
channel length at the high operation frequency range. The operating frequency
shall be below 0.2 * gm / Cgate, where gm is the transconductance of the
transistor and Cgate is the gate-oxide capacitance.
Draw the dummy pattern manually and uniformly, surrounding the matching
pair for both the source/drain direction and the poly end-cap direction. (Figure
7.3.2.6)

The dummy patterns should be identical in the shape, the dimension, the
space to the main circuit, and from the source/drain direction and the poly
end-cap direction, respectively.

The dummy OD and dummy PO should be 100% cover the projection
edge of the matching devices.
AN.R.47mgU
Avoid using irregular OD for the matching pair. Use simple rectangle to have
precisely SPICE simulation accuracy. Refer to figure 7.2.1.1.
AN.R.34mgU
Prefer simple shapes (rectangles) of OD and Poly.
AN.R.35mgU
Avoid OD routing (Prefer using metals and CO) to limit the number of corner
OD (risk of OD rounding), and to limit the number of narrow OD connections
(risk of OD Rs variation)
Figure 7.2.1.1 Example of irregular ODs
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whole or in part without prior written permission of TSMC.
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7.2.2
Rule No.
PO.S.5m®
PO.S.6m®
PO.S.6.1m®
PO.EX.1m®
PO.EX.2mgU
AN.R.71mgU
Document No.
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MOS Recommendations
Description
Label
Recommended PO space to L-shape OD when PO and OD are in the same MOS for model accuracy
J
Recommended L-shape PO space to OD when PO and OD are in the same MOS
E
Recommended L-shape PO space to OD when PO and OD are in the same MOS [channel width < 0.3 um
E
and L-shape PO length > 0.1 um (L)] (Figure 7.2.2.2)
Recommended PO extension on OD (end-cap)
G
For current mirror devices using common OD, please pay attention to LOD effect (please refer to LOD effect
section), eg. when using common OD, please follow the following items: (Figure 7.2.2.1)
(1) Keep the same SA/SB
(2) Enlarge extension (F1) to put dummy gate at both source/drain sides with the same channel width,
length, pitch and count, as possible.
Recommend putting dummy gate in the STI edge on the same OD. (Figure 7.2.2.3)
F1
Op.


Rule
0.2
0.1

0.18

0.11
F1
G
E
OD
OD
PO
J
p
p
p
pD u m m y P O g a tpe w i t h s a m e p it c h p
Figure 7.2.2.1
Analog Circuit Layout
L
E
W id th
Figure 7.2.2.2
PO.S.6.1m®
Figure 7.2.2.3 Dummy GATE placement of analog circuit
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Bipolar Transistor (BJT) Rules and
Recommendations
1. Two kinds of vertical bipolar are provided, PNP bipolar (P+/NW/PSUB) and NPN bipolar (N+/PW/DNW).
2. SPICE and PDK offer 3 kinds of emitter size and base size:
PNP10 and NPN10
PNP5 and NPN5
PNP2 and NPN2
10x10
5x5
2x2
Emitter size
3. In order to have precise SPICE model prediction, it is strongly recommended that users should apply the standard
TSMC bipolar layouts (PDK cells) in their designs.
4. The entire device needs to be covered with an BJTDMY (CAD layer: 110) which is used for DRC and LVS check.
Rule No.
Description
RPO needs to cover 0.3μm on the Emitter OD edge for both OD and STI
sides, i.e. RPO= ((Emitter OD SIZING 0.3 µm) NOT (Emitter OD SIZING
-0.3 µm))
BJTDMY enclosure of Emitter OD
OD (Emitter size) is small 2 μm x 2 μm, middle 5 μm x 5 μm, big 10 μm x
10 μm,
BJTDMY overlap of NT_N, PO, VTH_N, VTH_P, VTLN, VTL_P, VAR,
and SRM is not recommended.
BJT.R.1
BJT.R.8
BJT.R.2®
BJT.R.7®
Figure 7.2.3.1
Label
Op.
Rule
F
=
0.6
G

0.13
Layout of bipolar device
B JTD M Y
G
E m itte r
OD
R P O (F )
OD
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whole or in part without prior written permission of TSMC.
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Resistor Rules
Rule No.
Description
Label
Op.
Rule
R P O  1.8 μm (W’), length  20 μm (L’), and square number  5 (L’/W’)
Width
for NW resistor within OD.
LWidth  1.8 μm (W”), length  20 μm (L”), and square number  5 (L”/W”)
C
R E S .2 m
NWRSTI.R.1m
W
for NW
resistor under STI.
NWROD.R.1m
O
P O /O D
R PO
O D
OD
W ’
OD
W ”
L’
L”
N W
NW
N P
N P
NP
N W D M Y
N W r e s is t o r w it h in O D
N W R O D .R .1
m
Figure 7.2.4.1
NP
NW DMY
N W r e s is t o r u n d e r S T I
N W R S T I.R .1 m
Resistors layout
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Capacitor Guidelines
Rule No.
Description
AN.R.36mgU
It is recommended not to use a very long channel device in the design. In order to
ensure the channel relaxation time of the MOS capacitor (excluding varactor) is
enough to build up charge to the steady state, it is recommended to use proper
channel length at the high operation frequency range. The operating frequency
shall be below 0.2 * gm / Cgate, where gm is the transconductance of the
transistor and Cgate is the gate-oxide capacitance.
AN.R.37mgU
Varactor (NMOS capacitor in NW) is the best choice as MOS capacitor. And the
NW should have a P-type guard ring tied to ground.
7.2.5.1
Label Op.
Rule
Design Guidelines for Capacitor Connections -for the Estimation of Minimum Metal Width and
Minimum Via Number
Id e a l c u rre n t c u rv e
R e a l c u rre n t c u rv e
T
Figure 7.2.5.1
Transient peak current
For the estimation of minimum metal line width and minimum number of via connecting to capacitor terminals,
we assume that the charging up or discharge time is a quarter of clock period T.
In calculation:
△t=T/4 to charge up to VDD or discharge from VDD to ground.
T=1/f, f is the clock frequency.
The current to charge or discharge capacitor is
Imax=Cdv/dt=C* VDD/(1/4f)=4f*VDD*C
C is the capacitance extracted from layout
f (is the clock frequency) and VDD are provided by designer.
The minimum metal line width is
W(metal width in μm)= Imax/Jmax, where Jmax= EM current density for metal line per μm.
The minimum number of via is
N(Via number)= Imax/Jvia, Jvia= EM current density for each Via.
Both Jmax and Jvia are provided by process specifications to avoid EM (electro migration)
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whole or in part without prior written permission of TSMC.
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7.3
Layout Rules and Guidelines for Device
Placement
7.3.1
General Rules and Guidelines
Rule No.
Description
Label Op.
You need to insert the dummy patterns in the empty area, even if the OD, PO, metal
density has already met the density rules.
Insert the dummy patterns properly.
AN.R.3mU
AN.R.4mgU
The recommendation steps for this AN.R.3m:
1st Insert same geometric dummy cells manually to minimize the proximity effect
(Figure 7.3.1.1)
2nd Using TSMC’s utility to fill dummy patterns on the rest of the empty space, and
leave 4um white space to insert SR_DOD & SR_DPO.
3rd In TSMC’s utility, Analog (CAD layer: 182;3) layer can’t avoid DOD, SR_DOD
DPO, SR_DPO, or DM1/DMx/DM1_O/DMx_O insertion in the region. Please
use ODBLK, POBLK, or DM1EXCL/DMxEXCL layer to cover your analog
circuit, which will exclude DOD, SR_DOD, DPO, SR_DPO, or
DM1/DMx/DM1_O/DMx_O insertion during chip level.
4th Do electrical or silicon characterization
Avoid having sparse poly gate. Please refer to the item 3 in the section of
Improvement of poly CD uniformity
D u m m y p a tte r n s
(b lu e )
A c ti v e c i r c u i t
Figure 7.3.1.1
Example of manual DOD, DPO, or unit cell
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7.3.2
Rule No.
AN.R.5mU
AN.R.6mU
AN.R.7mU
AN.R.8mgU
AN.R.9mgU
AN.R.10mgU
AN.R.11mgU
AN.R.12mgU
AN.R.38mU
AN.R.39.mgU
AN.R.45mgU
AN.R.46mgU
AN.R.47mgU
AN.R.60mgU
AN.R.67mgU
AN.R.61mgU
AN.R.65mgU
AN.R.66mgU
AN.R.52mgU
AN.R.53mgU
AN.R.54mgU
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Matching Rules and Guidelines
Description
Make certain that the areas and shapes of matching pairs are identical.
Do not use matching pairs with different proximities (iso/dense), nor with different widths and areas, and
different shape of equal area.
Elements of the matching pair should have the same orientation (Figure 7.3.2.1).
Avoid routing metal over a matching pair. M1 is the most critical. If it is unavoidable, then use identical routing
metal with same potential over the matching pair. (Figure 7.3.2.2).
Place the matching devices close together and, if possible, use “common-centroid” or “inter-digitated”
placement for better matching.
“Common-centroid” architecture is recommended for those devices that cannot be placed close together
(Figure 7.3.2.3).
Regardless of any device dimensions of matching pairs with consistent resistance concerns, use the
symmetrical number of contacts (please refer to the CO.R.5g) and the same CO to PO gate space.
The layout of interconnection routing should be symmetrical with respect to each branch.
Pay attention on the associated routing layout, as well as the associated pattern density, of the matching pair,
to minimize the Rs difference. (Figure 7.3.2.4) All the routing should be symmetrical to avoid mismatch.
Pay attention on the matching topology of the resistor layout (Figure 7.3.2.5)
PO gate must connect to a protection diode by M1 to reduce the antenna effects in matching pairs.
Make certain that the local pattern density of, and nearby, the matching pair should be identical. Use enough
dummy cells surrounding the matching pair is highly recommended.
In order to avoid the drift of electrical parameter matching, it is important to maintain identical DC bias on the
each matching-transistor (NMOS or PMOS) at all operation conditions (eg, standby conditions). If the DC bias
is not identical, please evaluate the impact of matching performance.
It is recommended not to use a very long channel device in the design. In order to ensure the channel
relaxation time of the MOS device is enough to build up charge to the steady state, it is recommended to use
<10 times of minimum channel length at the high operation frequency range. The operating frequency shall be
below 0.2 * gm / Cgate, where gm is the transconductance of the transistor and Cgate is the gate-oxide
capacitance.
Draw the dummy pattern manually and uniformly, surrounding the matching pair for both the source/drain
direction and the poly end-cap direction. (Figure 7.3.2.6)

The dummy patterns should be identical in the shape, the dimension, the space to the main circuit, and
from the source/drain direction and the poly end-cap direction, respectively.

The dummy OD and dummy PO should be 100% cover the projection edge of the matching devices.
Avoid using irregular OD for the matching pair. Use simple rectangle to have precisely SPICE simulation
accuracy. Refer to figure 7.2.1.1.
Recommend to put at least two dummy gate with the same channel length in the same OD. (Figure 7.3.2.7)
Recommend to match antenna diode and their metal routing. (Figure 7.3.2.8)
For analog matching pair, recommend to use the same poly endcap size, even for the dummy poly (Figure
7.3.2.9)
Recommend to equivalent drain and source orientation. Total numbers of D/S and S/D orientations need to
match. (Figure 7.3.2.10)
Recommend to equalize interconnect and gate loading for matched transistors and tap the gate connection
from both ends. (Figure 7.3.2.11)
Recommend the following items for MOS capacitor matching (Figure 7.3.2.12)
- Small identical geometry
- Common centroid layout
- Dummy capacitor
- No on-top metal routing
- Away from power source
Recommend the following items for resistor matching (Figure 7.3.2.13)
- Interdigital configuration
- Equal structure
- Suitable dimension
- No corner turning (connection with M1. Not to use OD/PO)
- Dummy pattern
- Away from different power source
- Put more contacts
Recommend the following items for MOM matching (Figure 7.3.2.14)
- Uniform metal density
- Common centroid layout
- Dummy MOM
- Away from different power domain
- Need to take care RC extraction carefully during IP placement
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whole or in part without prior written permission of TSMC.
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Rule No.
AN.R.74mgU
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Description
Recommend the following items for varactor matching (Figure 7.3.2.15)
- Use I/O varactor
- Interdigital unit cell layout
- Common centroid layout
- Dummy varactor cell
- Away from different power domain
Label
Op.
In a multiplier ( 1: N, N>2) function design (MOS,PO/OD resistor,MOS CAP), the metal coverage
AN.R.86mgU above target devices (single or multiple) should keep clean as possible, the non-uniform metal
coverage would induces unexpected mismatch performance
V
Better matching layout : the same orientation
PO gates are all along x-direction (or y-direction) Poor matching layout : different orientation
Figure 7.3.2.1
Poor
OD M 1
Example of same or different orientation for matching pairs
G ood
Poor
G ood
R e s is t o r
R e s is t o r
OD
PO
P
O
M 1 o v e r M O S a ff e c t in g V t
Figure 7.3.2.2
M 1 o v e r r e s is t o r a ff e c t in g r e s is ta n c e
Example of avoiding routing metal over a matching pair
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whole or in part without prior written permission of TSMC.
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b e tte r m a t c h in g la y o u t
: T-N45-CL-DR-001
: 2.6
n o t s u ita b le f o r c r it ic a l
m a tc h in g p a ir s
c o m m o n - c e n tr o id
in te r d ig it a te d
d is c r e te O D ( A B B A )
c o m m o n O D (A B A B )
A
A
A
B
B
A
B
A
B
A
A
B
B
B
A
A
or
B
B
B
A
D u m m y a r r a y ( b lu e )
 C e n tr o i d M O S l a y o u t i s u se d fo r d e v i c e m a tc h i n g i n
3 D d i r e c ti o n w i th r o u ti n g / c o m p l e x i ty tr a d e -o ff :
 C e n t r o id
in d i v id u a l M O S c o n f i g u r a t io n is u s e d f o r t y p ic a l
la y o u t
 C e n t r o id
a b u t t e d M O S s t y le e n h a n c e s d e v ic e p e r f o r m a n c e
w it h s m a lle r a r e a ( p r e f e rr e d )
Figure 7.3.2.3
Example of common-centroid or inter-digitated layout for matching pairs
Poor
G ood
M a t c h in g p a ir s
M a t c h in g p a ir s
Figure 7.3.2.4
Example of the associated routing layout of the matching pair
Poor
G ood
G ood
B e tte
r
R
R
R
R
2R
R
R
R
R
R
R
R
R
Figure 7.3.2.5
Example of matching topology of resistor layout for matching pairs
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  A c t i v e d e v i c e s a r e s u r r o u n d e d b y d u m m y o n e i n a ll d i r e c t i o n s w i t h i n s h o r t d i s t a n c e
  A l l d u m m y d e v i c e s a r e i n c l u d e d i n c i r c u i t c h a r a c te r i z a ti o n
  D u m m y u ti l i ty i s n o t r e c o m m e n d e d fo r d e v i c e c h a r a c te r i z a ti o n
A c t iv e d e v ic e
D u m m y d e v ic e
Figure 7.3.2.6
Dummy pattern for matching pairs
nxx
m 1
m 2
A
B
Figure 7.3.2.7
Example of dummy poly beside matching parirs
Figure 7.3.2.8
Example to match antenna diode and their metal routing
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Figure 7.3.2.9
Example of the same poly endcap size in the same OD
Figure 7.3.2.10
Example to equivalent drain and source orientation
Figure 7.3.2.11
Example to tap the gate connection from both ends of the gate
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Capacitor matching
 Small identical geometry
Main capacitor
 Large unit y capacitance
 Common centroid la yout
 Dummy capacitor
 Capacitor shielding
 No on-top metal routing
 Aw ay from pow er source
Dummy capacitor
Figure 7.3.2.12
Example of capacitor matching
 R e s is t o r m a t c h i n g
M1
 In t e r d ig it a l c o n f ig u r a t io n
 E q u a l s tru c t u re
M a i n r e s i s to r
 S u it a b le
N o
c o r n e r t u r n in g
D um m y
D u m m y p a t te r n
Figure 7.3.2.13
Example of resistor matching
Figure 7.3.2.14
Example of MOM matching
Figure 7.3.2.15
Example of Varactor matching
d im e n s i o n
Awa y
p a tte rn
fro m p o w e r s o u rc e
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Figure Example of a multiplier ( 1: N, N>2) function design
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7.3.3
Rule No.
AN.R.13mU
AN.R.14mgU
AN.R.15mgU
AN.R.16mgU
AN.R.17mg
AN.R.18mgU
AN.R.20mg
AN.R.21mgU
AN.R.40mgU
AN.R.72mgU
AN.R.73mgU
AN.R.55mgU
AN.R.56mgU
AN.R.68mgU
AN.R.69mgU
AN.R.76mgU
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Electrical Performance Rules and Guidelines
Description
Label
Op.
Rule
Avoid placing the matching pairs or performance-critical devices at the
prime chip corner and prime chip edge. (Figure 7.3.3.1)
Avoid using silicided-OD connected between well strap and the MOS
source node (butted junction) in analog, matching and performancecritical devices. (Figure 7.3.3.2)
Optimize the CO number at both source and drain sides of performancecritical devices. (Figure 7.3.3.3)
Do not use maximum latch-up rule near narrow ravine between wells.
(Figure 7.3.3.4)
Place unsilicided PO resistor or MOM (without ground shielding) on an Nwell for better noise immunity.
A P+ PO resistor is recommended for overall performance.
Do not use single via for high current or resistance sensitive wire. (Figure
7.3.3.5)
Use thick oxide (OD2) MOS varactor and capacitor to reduce gate oxide
leakage. DRC can not check capacitor.
CB and CBD are not recommended to put on the top of matching pairs or
performance-critical devices.
For the matching sensitive circuits with DC bias at low Vgs regions; the
layout style effects (such as LOD, WPE and device orientation) should
be carefully reviewed.
For less device offset and variation of Id_analog (Ids at Vds = Vgs =
0.5*Vdd) of core device, recommend to use merged-OD than separateOds or use common centroid layout style. (Figure 7.3.3.6)
For less mean offset of Id_analog (Ids at Vds = Vgs = 0.5*Vdd) of core
device, recommend to surround MOSFETs with same type of MOSFETs,
or use TSMC dummy insertion utility to fill the blank area. (Figure 7.3.3.7)
The environment of the critical metal routing should have similar metal
density (Figure 7.3.3.8)
Recommend to consider interconnect routing in device performance
analysis. Symmetrical routing is critical for device matching. Distributed
RC network is constructed differently dependent on interconnect routing.
Asymmetrical interconnect routing results in device mismatch. For timing
concern circuit, recommend to run RCC (resistor/capacitor/coupling)
extraction. (Figure 7.3.3.9)
Nwells at different potentials should be separated by Pwell strap to
enhance the separation. Surrounding PW guard-ring will be the best.
(Figure 7.3.3.10)
Recommend to use common central layout for BJT diodes (Figure
7.3.3.11)
In order to reduce the Id_analog (Ids at Vds = Vgs = 0.5*Vdd) gap
between Si and simulation for the MOS in core region, it is not
recommend to use opposite-type MOS with area ≥ 5um * 5um size
abutted the target MOS.
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A = d ie w id t h
B = d ie le n g th
C = d ie d i a g o n a l l e n g t h
L e n g t h a n d w id t h o f d i e i n c l u d e s s e a l r in g
P ro p o s e d z o n e
a *B
b
*C
a *B
C
B
a n d p a r t o f s c r ib e l in e a f t e r d ie s a w
A
a *A
a *A
F o r t h e b o t t o m d ie in a s t a c k e d - d ie w ir e b o n d P B G A p a c k a g e
1)
a : a w a y f r o m d ie e d g e  1 0 % o f t h e c h i p e d g e le n g t h
2)
b : a w a y f r o m d ie c o r n e r  1 5 % o f t h e c h ip d i a g o n a l d i m e n s io n
F o r a s in g le - d ie w ir e b o n d P B G A p a c k a g e
1)
a : a w a y f r o m d ie e d g e  3 % o f t h e c h i p e d g e le n g t h
2)
b : a w a y f r o m d ie c o r n e r  5 % o f t h e c h i p d ia g o n a l d im e n s io n
F o r a s in g le - d ie f lip c h ip P B G A p a c k a g e
1)
a : a w a y f r o m d ie e d g e  1 % o f t h e c h i p e d g e le n g t h
2)
b : a w a y f r o m d ie c o r n e r  3 % o f t h e c h i p d ia g o n a l d im e n s io n
T h e a b o v e n u m b e r s m a y b e c h a n g e d b y s e v e r a l f a c t o r s , e . g . d ie s i z e , d ie t h ic k n e s s , p a c k a g e t y p e ,
p a c k a g e m a t e r ia l , p a c k a g e s i z e , a n d c ir c u it d e s i g n m a r g in , p l e a s e c o n t a c t T S M C f o r m o r e d e t a ils .
Figure 7.3.3.1
The proposed zone for matching pairs or performance-critical devices
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G ood
S o u rc e
W e ll S t r a p
W e ll S t r a p
W e ll S t r a p
S o u rc e
S o u rc e
Figure 7.3.3.2 Example of avoiding using silicided-OD connected between well strap and the MOS
source node
Poor
G ood
Figure 7.3.3.3 adequate CO number to enlarge the space of CO-to-gate and CO-to-CO extension
D o n o t u s e m a x im u m la t c h - u p
NM O S
PM O S
r u le ( r e d u c e t h e s p a c e )
NW
PW
NW
PW
N a r r o w w e ll s p a c e
W e ll S t r a p
W e ll S t r a p
( n a r r o w r a v in e )
Figure 7.3.3.4 Example of maximum latch-up rule near narrow ravine between wells
G ood
Poor
V ia x
M x+1
V ia x
M x
M x+1
M x
Figure 7.3.3.5 Example of not using single via for high current or resistance sensitive wire
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Figure 7.3.3.6 Example for common centroid, merged OD and separate OD.
S u rro u n d M O S F E T s w ith s a m e ty p e o f
M O S F E Ts,
o r u s e T S M C d u m m y in s e rtio n u tility to fill
th e b la n k a re a
Figure 7.3.3.7 Example to Surround MOSFETs with same type of MOSFETs, or use TSMC dummy
insertion utility to fill the blank area.
Figure 7.3.3.8 The environment of the critical metal routing should have similar metal density
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Figure 7.3.3.9 Example of metal routing
N W a t s a m e p o t e n t ia l
S u r r o u n d in g P W g u a r d r in g
N W a t s a m e p o t e n t ia l
N W a t d if f e r e n t p o t e n t ia l
Figure 7.3.3.10 Example of NWs at different potentials should be separated.
Figure 7.3.3.11 Example of common central layout for BJT diodes.
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Noise
7.3.4.1
Power and Ground
Rule No.
AN.R.22mgU
AN.R.23mgU
AN.R.24mgU
AN.R.25mgU
AN.R.26mgU
AN.R.27mgU
AN.R.28mgU
Description
Label
Op.
Rule
For the low noise circuit, a P-Well ring, which is tied to VSS, is
recommended to surround all PMOS devices in each analog circuit block.
For the low noise circuit, a N-Well ring, which is tied to VDD, is
recommended to surround all NMOS devices in each analog circuit block.
Put NMOS in RW (PW in DNW) is a good practice of isolating critical circuit
from substrate noise (Figure 7.3.4.1.1). Make sure every NW connected to
DNW must be same potential (refer to DNW.R.4).
Use NT_N layer (width ≥ 1μm), as a high resistance region, to isolate two
high frequency circuit, to reduce the noise or signal coupling from substrate
(Figure 7.3.4.1.2).
- minimize the signal lines crossing the high resistance NT_N region
- maximize the distance between metal lines from the substrate above
the NT_N region (use upper level metal).
Use separate power supplies and ground buses for the noisy and sensitive
circuit and also for the analog and digital circuits. (Figure 7.3.4.1.4).
Keep enough distance between the noisy and sensitive area.
Use wide guard ring to stabilize substrate and well potential.
Poor
S e n s it iv e c ir c u it
G ood
N o is y c ir c u it
NM OS
S e n s it iv e c ir c u it
NM OS
N o is y c ir c u it
NM OS
NW
NM OS
NW
DNW
N o is e
N o is e is is o la t e d .
Figure7.3.4.1.1 Example of NMOS in RW
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Poor
NT_N
S e n s it iv e c ir c u it
N o is y c ir c u it
G u a r d r in g
PW
PW
S e n s it iv e c ir c u it
R _PW
G u a r d r in g
N o is e
Good
S e n s it iv e c ir c u it
S e n s it iv e c ir c u it
N o is y c ir c u it
N o s iy c ir c u it
PW
NT_N
(P s u b )
PW
R _P sub
R _P sub
G u a r d r in g
N o is e
G u a r d r in g
B e c a u s e R _ P s u b i s la r g e r t h a n R _ P W , N T _ N i s b e t t e r
t h a n P W in t h e n o i s e i s o l a t i o n .
Figure 7.3.4.1.2
Example of NT_N layeras a high resistance region
b e tte r
best
poor
(if p a d lim ite d )
Vdd1
Vss1
Vdd
N o is y
c ir c u it
Vss
N o is y
c ir c u it
Vdd
N o is y
c ir c u it
Vss
Vdd
Vdd2
Vss2
I/O p a d
Vss
N o is y
N o is y
N o is y
s e n s it iv e
s e n s it iv e
s e n s it iv e
c ir c u it
c ir c u it
c ir c u it
I/O p a d
I/O p a d
Figure 7.3.4.1.4 Example of separated power supplies and ground buses for the noisy and sensitive
circuit
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Signal
Rule No.
AN.R.30mgU
AN.R.31mgU
AN.R.32mgU
AN.R.33mgU
Description
Label
Op.
Rule
Keep high frequency signal in high level metal layer.
Use metal shield for victim line that is noise sensitive.
Use metal and poly shield for attacker line that travels through long
distance.
Prevent from feedback path through chip seal-ring between critical input
and output. Use additional guard ring to isolate the coupling. (Figure
7.3.4.2.1)
F e e d b a c k P a th
S e a l r in g
U s e a d d it io n a l g u a r d
Vdd or
Vss
r in g t o is o la t e t h e
In p u t
c o u p lin g .
O u tp u t
O u tp u t
G u a r d r in g
Vdd or
Vss
S e a l r in g
Figure 7.3.4.2.1 Example of prevention from feedback path through chip seal ring
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Burn-in Guidelines for Analog Circuits
Rule No.
Description
AN.R.41mgU
For the sensitive circuit, e.g. differential input pair, which needs precise device
mismatching parameter control such as △ Vt and △ Isat, it must avoid
unbalanced DC bias stress during burn-in period.
For example, VA=Vdd or GND and VB=1/2Vdd, which causes current supplied
from current source flowing differently on the differential input pair (IAIB). This
will make differential pair matching become worse after burn-in stress. (Figure
7.4.1)
Label
Op.
Be sure that the analog circuit operates at normal operational condition during
burn-in.
AN.R.42mgU
For example, avoid P1 floating (when R is external) and make it be biased at the
normal condition during burn-in. (Figure 7.4.2)
With the protection diode connection in the sensitive circuit to reduce plasma
AN.R.43mgU
induced damage during wafer processing.
Circuit design with state-dependent floating-node must be taken care carefully.
Concern: Accidental over-stress of device may occur and damage or degrade
U the device.
AN.R.50mg For example: DNW/NW indirectly connects to power, and the substrate is biased
negatively. Please simulate to check for potential issues caused by inadvertent
floating wells, and revise design if necessary.
Recommended Floating PAD is not recommended; please add protection diode
to ground.
Floating PAD in the DRC:
FPAD.R.1m (1) {{Mtop OR UTM} INTERACT CB} don’t connect to OD for wire bond.
(2) {{Mtop OR UTM} INTERACT CBD} don’t connect to OD for flip chip without
®U
RDL and flip chip with Cu-RDL.
(3) {{Mtop OR UTM} INTERACT RV} don’t connect to OD for flip chip with APRDL.
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VB
IA
IB
Figure 7.4.1 Example of differential input pair
+
P 1
P 2
P 3
R
Figure 7.4.2 Example of analog circuit
Figure Example of Floating PAD
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8 Dummy Pattern rule and Filling Guideline
This chapter contains the following topics:
8.1
Dummy OD (DOD/SR_DOD) Rules and Guidelines
8.2
Dummy Poly (DPO/SR_DPO) Rules and Guidelines
8.3
Dummy TCD Rule and Filling Guideline
8.4
Dummy TCD Design Information
8.5
In Chip Overlay (ICOVL) Rule And Filling Guideline
8.6
Dummy Metal (DM) Rules
8.7
Dummy VIA (DVIAx) Rules
8.8
Dummy Pattern Fill Usage Summary
8.1
Dummy OD (DOD/SR_DOD) Rules and
Guidelines
1. In order to meet the extremely tight requirement in terms of process control for STI etch, polish,
OSE as well as channel length definition (inter-level dielectric (ILD) planarization), you must fill the
DOD/SR_DOD globally and uniformly even if the originally drawn OD already satisfies the required OD
density rules.
2. It is very important to use TSMC’s auto-fill utilities (documents: T-N45-CL-DR-001-C2 and T-N45-CLDR-001-H2).
． It is important to use the TSMC DOD/DPO utility, which will fill the SR_DOD/SR_DPO/DOD/DPO
correctly, to carefully control the OSE and PSE.
．It is important to perform the utility on the IP level, and the whole chip GDS level.
3. It is recommended to use filler cells with OD/PO to fill a large empty area in the standard-cell-based
block during the P&R stage. It is difficult for the current TSMC DOD/DPO utility to insert DOD shapes into
a standard-cell placed area. For higher PO and OD CD control requirements, it is suggested to layout both
OD and PO into a filler cell (treat OD/PO as a dummy filling, need to follow OD/PO and related rules, and
use the GDS layer of OD/PO).
4. Evaluate the impact on OD masks carefully when any one of the following layouts is revised:
 PO/ DPO/ SR_DPO
 NW/ ODBLK/ NWDMY/ LOGO/ INDDMY
5. Use the dummy layer ODBLK properly. This layer (CAD layer no. 150;20) tells the TSMC utility that the
area covered should be blocked from DOD/SR_DOD fill operations. ODBLK is for excluding DOD and
SR_DOD, not for excluding dummy Poly (DPO/SR_DPO).
6. It is suggested to make sure that the ODBLK layer covers sensitive circuits, such as:
 Pad areas for high frequency signals
 SRAM sensitive functional blocks and bit cell arrays
 Analog/RF circuits (DAC/ADC, PLL, Inductor) and so on
7. It is recommended to manually add DOD/SR_DOD uniformly inside regions covered by the ODBLK
layer, to gain better process window and electrical performance.
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8. Don’t put DOD/SR_DOD in areas covered by the following marker layers:
 Well resistor under STI (NWDMY)
 Regions of chip corner stress relief pattern, seal ring, and CDU pattern
TSMC’s fill generation utility will not add DOD/SR_DOD into these regions, as these layers are well defined.
The ODBLK covered areas should not cover or overlap the above areas for DRC reasons.
9. Please refer to the “Dummy Pattern Fill Usage Summary” section in this chapter for additional
information.
8.1.1
Rule No.
DOD.W.1
DOD.S.1
DOD.S.2
DOD.S.3
DOD.S.5
DOD.S.8
DOD.EN.1
OD.DN.0
OD.DN.1
OD.DN.1.1
OD.DN.2
OD.DN.2.1
OD.DN.2.2
OD.DN.3
OD.DN.3.1
OD.DN.3.2
IND.DN.8®
IND_MD.DN.8®
DOD.R.1
DOD.R.2
DOD.R.3
DOD.S.2gU
DOD Layout Rules
Description
Width
Space
Space to OD (Overlap is not allowed)
Space to PO (Overlap is not allowed)
Space to NW
Space to NWDMY (Overlap is not allowed)
Enclosure by NW (Cut is not allowed)
1. OD.DN.2/OD.DN.2.1/OD.DN.2.2 and OD.DN.3/OD.DN.3.1/OD.DN.3.2 are checked over any
window 150 μm x 150 μm, stepping 75 μm .
2. (outside OD2) means the overlapped width between the checking window and OD2 layer is
smaller than 37.5 μm.
3. For OD.DN.2/OD.DN.2.1/OD.DN.2.2/OD.DN.3/OD.DN.3.1/OD.DN.3.2, the following regions
can be excluded:
- NWDMY/LOGO/INDDMY/INDDMY_MD
- Chip corner stress relief and seal-ring
4. OD.DN.2/OD.DN.2.1/OD.DN.2.2 are applied when the width of (checking window NOT the item
3) is  37.5 μm.
5. OD.DN.3/OD.DN.3.1/OD.DN.3.2 must be followed for every defined ODBLK region. This rule is
only applied when the width of ((checking window AND ODBLK) NOT item 3) is  37.5 μm.
Minimum {OD OR DOD OR SR_DOD} density across full chip
Maximum {OD OR DOD OR SR_DOD} density across full chip
Minimum {OD OR DOD OR SR_DOD} local density (window 150μm x 150 μm, stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density [OUTSIDE OD2] (window 150 μm x 150 μm,
stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density (window 150 μm x 150 μm, stepping 75 μm)
Minimum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm,
stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK [OUTSIDE OD2] (window 150
μm x 150 μm, stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm,
stepping 75 μm)
Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY
Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY_MD
DOD is a must. DOD CAD layer (TSMC default, 6;1) must be different from OD’s. Please refer to
section 8.1.
DOD inside chip corner stress relief area is not allowed [except seal-ring and stress relief patterns
drawn by customers].
Only square (or rectangular) and solid shapes are allowed. A 45-degree shape is not allowed.
Recommended space to OD (C = 0.6)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Label
A
B
C
D
F
I
L
Op.







Rule
0.5
0.4
0.34
0.3
0.3
0.6
0.3



25%
75%
20%

80%

90%

20%

80%

90%


20%
20%
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DOD
NW DM Y
I
NW
F
P
O
D
DO D
DO D
L
C
O D
A
DO D
B
DO D
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
SR_DOD Layout Rules
SR_DOD (CAD layer: 6;7) is used for dummy OD. It is a tape-out required layer and will be OPC treatment.
It is very important to use TSMC dummy utility to insert SR_DOD and SR_DPO around your IP, to close your
silicon performance with simulation result.
SR_DOD (CAD layer: 6;7) is not allowed to form device (MOS, RF, VAR, BJT, resistor, diode…).
Rule No.
SR_DOD.W.1
SR_DOD.W.2
SR_DOD.S.1
SR_DOD.S.1.1
SR_DOD.S.2
SR_DOD.S.3
SR_DOD.S.3®
SR_DOD.S.4
SR_DOD.S.7
SR_DOD.S.8
SR_DOD.S.9
SR_DOD.S.11
SR_DOD.EN.1
SR_DOD.A.1
SR_DOD.L.1
SR_DOD.L.2
SR_DOD.R.1
SR_DOD.R.2
SR_DOD.R.3
SR_DOD.R.4gU
SR_DOD.DN.1®
Description
Width
Maximum width
Space
Space to OD, DOD (Overlap is not allowed)
Space to PO (Overlap is not allowed)
Space to DPO, SR_DPO (Overlap is not allowed)
Recommended space to DPO, SR_DPO
Space to 45-degree bent OD
Space to NW (for both core and I/O)
Space to NWDMY (Overlap is not allowed)
Space to LOGO (Overlap is not allowed)
Space to NT_N (Overlap is not allowed)
NW enclosure of SR_DOD (for both core and I/O)
Area
Length
Maximum length
45-degree bent SR_DOD is not allowed
Overlap of CO is not allowed.
Only rectangle is allowed
It is important to use the TSMC DOD/DPO utility to insert SR_DOD
surrounding and close to the target device before characterization. The
range of the SR_DOD  4um.
Recommended minimum SR_DOD density inside {((((((OD OR PO)
INTERACT GATE) SIZING 2.5um) NOT ((OD OR PO) SIZING 0.4um))
NOT SRAMDMY;0) NOT OD2)} (The GATE doesn't include the regions
covered by layer TCDDMY, CSRDMY, CDUDMY)
Label
A
A
B
C
D
E
E
F
G
H
I
K
L
N
O
O
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.














Rule
0.1
0.5
0.12
0.12
0.05
0.03
0.05
0.17
0.08
0.6
0
0.14
0.08
0.05
0.5
10

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SR_DOD
SR _D PO SR _D PO SR _D PO
(1 7 ;7 )
(1 7 ;7 )
(1 7 ;7 )
A
PO
SR _D PO SR _D PO SR _D PO
PO
PO
PO
(1 7 ;0 )
(1 7 ;0 )
(1 7 ;0 )
(1 7 ;7 )
(1 7 ;7 )
(1 7 ;7 )
(1 7 ;0 )
C
SR _D O D
SR_D O D
B
SR_D O D
SR _D O D SR _D O D
OD
(6 ;0 )
E
C
E
D
DPO
DOD
(1 7 ;1 )
(6 ;1 )
SR_D O D
NW DM Y
LO G O
H
I
N
F
O
SR_DO D
OD
SR_D O D
NT_N
SR _D O D
K
NW
SR_DO D
G
L
SR _D O D
SR_DO D
SR_D O D
OD2
SR_DO D
G
L
NW DM Y
SR _D O D
SR _D O D
IN D D M Y
LOGO
SR_D O D
NT_N
CO
SR _D O D
S R _ D O D .R .1
O D, DO D, PO , SR_DPO
SR_DO D
SR_DO D
S R _ D O D .R .2
S R _ D O D .R .3
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Dummy Poly (DPO/SR_DPO) Rules and
Guidelines
1. Good Poly uniformity is the key to meet the PO CD as well as circuit performance requirement. You
must fill the DPO/SR_DPO globally and uniformly even if the original drawn poly already satisfies the
required poly density rules. The designer may wish to add dummy poly to improve the stability of the poly
line dimension on silicon.
2. It is very important to use TSMC’s auto-fill utilities (documents T-N45-CL-DR-001-C2 and T-N45-CLDR-001-H2).
． It is important to use the TSMC DOD/DPO utility, which will fill the SR_DOD/SR_DPO/DOD/DPO
correctly, to carefully control the OSE and PSE.
．It is important to perform the utility on the IP level, and the whole chip GDS level.
3. It is recommended to use filler cells with OD/PO to fill a large empty area in the standard-cell-based
block during the P&R stage. It is difficult for the current TSMC DOD/DPO utility to insert DOD shapes into
a standard-cell placed area. For higher PO and OD CD control requirements, it is suggested to layout both
OD and PO into a filler cell (treat OD/PO as a dummy filling, need to follow OD/PO and related rules, and
use the GDS layer of OD/PO).
4. Evaluate the impact on the poly mask carefully when any one of the following layouts is revised:
 OD/DOD/SR_DOD
 POBLK/LOGO/INDDMY
5. Use the dummy layer POBLK properly. This layer (CAD layer no. 150;21) tells the TSMC utility that the
area covered should be blocked from DPO/SR_DPO fill operations. POBLK is for excluding DPO and
SR_DPO, not for excluding dummy OD (DOD/SR_DOD).
6. It is suggested to make sure that the POBLK layer covers sensitive circuits, such as:
a. Pad areas for high frequency signals
b. SRAM sensitive functional blocks and bit cell arrays
c. Analog/RF circuits (DAC/ADC, PLL, Inductor) and so on
7. It is recommended to manually add DPO/SR_DPO uniformly inside regions covered by the dummy
fill blocking layer POBLK, to gain better process window and electrical performance.
8. Don’t put DPO/SR_DPO in areas covered by the following marker layers to avoid DRC problems.
 Regions of chip corner stress relief pattern, seal ring, and CDU pattern
TSMC’s fill generation utility will not add DPO/SR_DPO into these regions because these layers are well
defined.
The POBLK covered areas should not cover or overlap the above areas for DRC reasons.
9. Please refer to the “Dummy Pattern Fill Usage Summary” section in this chapter for additional
information.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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PO.DN.2
: T-N45-CL-DR-001
: 2.6
DPO Layout Rules
Rule No.
DPO.W.1
DPO.S.1
DPO.S.2
DPO.S.3
PO.DN.1
PO.DN.1.1
Document No.
Version
Description
Label
Op.
Rule
Width
Space
Space to OD (Overlap is not allowed)
Space to (PO OR SR_DPO) (Overlap is not allowed)
Minimum {(PO OR DPO) OR SR_DPO} density across full chip
Maximum {(PO OR DPO) OR SR_DPO} density across full chip
{OD OR DOD OR SR_DOD OR PO OR DPO OR SR_DPO} local density
1. PO.DN.2 is checked by window 20 μm x 20 μm, stepping 10 μm.
2. For PO.DN.2 rules, the following regions can be excluded:
(1) ODBLK/POBLK/NWDMY/LOGO/INDDMY/INDDMY_MD as default
(2) Chip corner stress relief area if seal-ring and stress relief pattern added
by TSMC.
3. Even in areas covered by {ODBLK OR POBLK}, this pattern density that
follows the PO.DN.2 rules is recommended.
4. The rule is applied when the width of (checking window NOT item 2) is  5
μm.
Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY
A
B
C
D






0.4
0.3
0.2
0.5
14%
40%

0.1%

15%

15%
IND.DN.9®
IND_MD.DN.9
Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY_MD
®
DPO is a must. DPO CAD layer (TSMC default, 17;1) must be a different layer
DPO.R.1
from the PO CAD layer. Please refer to section 8.2.
DPO inside chip corner stress relief area is not allowed [except seal-ring and
DPO.R.2
stress relief patterns drawn by customers].
Only square (or rectangular) and solid shapes are allowed. A 45-degree shape
DPO.R.3
is not allowed.
U
DPO.S.3g
Recommended space to PO (D = 0.5).
DPO.R.4gU
DPO cut DOD is not recommended
DPO
DPO
PO
A
D
B
DPO
C
OD
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
SR_DPO Layout Rules
SR_DPO (CAD layer: 17;7) is used for dummy poly. It is a tape-out required layer and will be OPC treatment.
It is very important to use TSMC dummy utility to insert SR_DOD and SR_DPO around your IP, to close your
silicon performance with simulation result.
Rule No.
SR_DPO.W.1
SR_DPO.W.2
SR_DPO.W.6
SR_DPO.S.1
SR_DPO.S.1®
SR_DPO.S.2
SR_DPO.S.3
SR_DPO.S.4
SR_DPO.S.9
SR_DPO.S.16
SR_DPO.S.17
SR_DPO.S.18
SR_DPO.S.19
SR_DPO.S.20
SR_DPO.EN.1
SR_DPO.EN.2
SR_DPO.EX.1
SR_DPO.EX.2
SR_DPO.L.1®
SR_DPO.L.2
SR_DPO.L.3®
SR_DPO.A.1
SR_DPO.A.2
SR_DPO.A.3
SR_DPO.A.4
SR_DPO.R.1
SR_DPO.R.2U
SR_DPO.R.4
SR_DPO.R.5
SR_DPO.R.6
SR_DPO.DN.1®
Description
Label
Op.
Rule
Width
Width in OD2
Width of 45-degree dummy PO. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer
to the rule, G.6U, in section 3.7))
Space to {PO OR SR_DPO} (SR_DPO overlap with PO is not allowed)
Recommended space to {PO OR SR_DPO} (SR_DPO overlap with PO is not allowed)
The SR_DPO (17;7) gate space to other gate (17;0 OR 17;7), SR_DPO (17;7) only can be used for dummy
patterns.
{((PO OR SR_DPO) AND OD) inside OD2} space in the same OD
Space to OD
Space of {(PO OR SR_DPO) AND RPO}
Space to 45-degree bent {PO OR SR_DPO}
{CO inside SR_DPO} space to OD
{SR_DPO AND OD} space to RPO (overlap is not allowed.)
{SR_DPO AND OD} space to CO (overlap is not allowed.)
{CO inside OD} space to 1.8V, 2.5V, 3.3V {SR_DPO AND OD}
Enclosure of CO
Enclosure of CO [at least two opposite sides]
Extension on OD (end-cap)
OD extension on SR_DPO
Recommended length
Length of 45-degree bent SR_DPO (minimum edge length)
Recommended maximum Length
Area (This check doesn’t include rectangle area with length  0.3 μm)
Area [with all of edge length < 0.21 μm]
Enclosed area
Enclosed area [with all of inner edge length < 0.21 μm]
{SR_DPO AND OD} must be a rectangle orthogonal to grid. (Both bent GATE and GATE with jogs are not
allowed).
SR_DPO line-end must be rectangular. Other shapes are not allowed.
SR_DPO intersecting OD must form two or more diffusions. (except MOMDMY (155;21) region)
Overlap of SRAM is not allowed
SR_DPO(17;7) can not form device, SR_DPO must be placed beside OD edge. (except MOMDMY (155;21)
region).
Recommended minimum SR_DPO density inside {((((((OD OR PO) INTERACT GATE) SIZING 2.5um) NOT
((OD OR PO) SIZING 0.4um)) NOT SRAMDMY;0) NOT OD2)} (The GATE doesn't include the regions
covered by layer TCDDMY, CSRDMY, CDUDMY)
A
B


0.04
0.1
C

0.17
D
D


0.1
0.12
E

0.14
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
R
T
T
U
U



















0.22
0.03
0.18
0.17
0.05
0.38
0.04
0.08
0.01
0.02
0.09
0.03
0.5
0.26
10
0.022
0.055
0.04
0.077

4%
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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SR_DPO
OD2
SR_DPO SR_DPO PO SR_DPO SR_DPO
(17;7)
(17;7) (17;0) (17;7)
(17;7)
OD
(6;0)
SR_DPO SR_DPO SR_DPO PO
(17;7)
(17;7)
(17;7) (17;0)
PO SR_DPO SR_DPO
(17;0) (17;7) (17;7)
SR_DPO SR_DPO
(17;7)
(17;7)
R
E
E
OD
(6;0)
G
A
F
F
D
D
A
B
SR_DPO.S.19
SR_DPO
SR_DPO SR_DPO
(17;7)
(17;7)
SR_DPO
(17;7)
PO
(17;0)
S
I
C
H
SR_DPO OR PO
SR_DPO
SR_DPO
H
H
OD
L
RPO
Q
N
P
O
OD2
SR_DPO
SR_DPO
U
T
PO
OD
M
SR_DPO
SR_DPO
SR_DPO
OD
SR_DPO
RPO
RPO
K
J
SR_DPO
OD
SR_DPO
OD
SR_DPO.R.6
Case-1
SR_DPO
PO
GATE
Case-2
SR_DPO
SR_DPO
PO
GATE
SR_DPO
OD
Allowed
OD
Not Allowed
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whole or in part without prior written permission of TSMC.
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8.3
Dummy TCD Rule and Filling Guideline
8.3.1
Dummy TCD Rules
1. In order to meet the extremely tight requirement in terms of process control for Poly CD, the Dummy
TCD is required within a 2mmX2mm area. If there is not enough space to insert one Dummy TCD for
each 2mmx2mm due to pattern layout, please must ensure the density of Dummy TCD should reach
50%(DTCD.DN.2) in whole chip level.
2. There are two methods to generate dummy TCD. One is the P&R, and another is TSMC’s auto-fill utilities
(documents: T-N45-CL-DR-001-X2): It is important to perform the utility on the whole chip GDS. It is not
recommended to perform the utility only on a single IP.
3. For cyber shuttle case, the gate direction in dummy TCD(TCDDMY_H/ TCDDMY_V) must align to gate
direction in SRAM (DTCD.R.5). For non-cyber-shuttle case, it is no need to align to gate direction in SRAM,
but if possible, recommend to follow gate direction in SRAM.
 For P&R: Please refer to section 8.4.
 For auto-fill dummy utility: There is an utility option, VERTICAL_TCD_PATTERN, to control gate
direction is vertical or horizontal in dummy TCD. The option is default on, and the gate direction of
dummy TCD will be vertical. If this option is turned off, the horizontal gate direction will be generated.
4. Do not rotate or mirror the dummy TCD cell (TCDDMY_H/ TCDDMY_V) except you would like to align gate
direction to SRAM and you can rotate it with clockwise 90 degree and no mirror(DTCD.R.4).
5. Evaluate the impact on OD/NW/PW/NPO/PO/VTL_N/VTL_P/NSSD/NLDD/ PLDD/P+/N+/NILD/PILD/
SSMT masks carefully when any one of the following layouts is revised:
 PO/OD/NP/PP/NW
6. Use the dummy layer POBLK/ODBLK properly. These layers (CAD layer no. 150;20/150;21) tell the
TSMC utility that the area covered should be blocked from Dummy TCD fill operations.
If you do not use TSMC’s dummy utility, please ask for the dummy TCD layout and insert it in your
design flow:
 It is suggested to make sure that the POBLK/ODBLK layer covers sensitive circuits.
 TCDDMY overlaps DOD, SR_DOD, DPO, SR_DPO, OD2, DCO, NT_N, POFUSE, RPO, RH, VAR,
VTH_P, VTH_N, VTL_P, VTL_N, SRM, SRAMDMY, INDDMY, LOGO, BJTDMY, or MOMDMY which is
not allowed.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: 2.6
TCDDMY (CAD layer no: 165;1) relative rules
Rule No.
Description
Label
Op.
Rule
DTCD.W.1
Width of {(TCDDMY NOT TCDDMY_H) NOT TCDDMY_V}
Channel width of gate inside {(TCDDMY NOT TCDDMY_H) NOT
TCDDMY_V}
Channel length of gate inside TCDDMY
Space of poly gate in the same OD inside {(TCDDMY NOT
TCDDMY_H) NOT TCDDMY_V}
Density of DummyTCD (window 2000 μm X 2000 μm is one unit, see
next page for more information)
Density of DummyTCD (window 2000 μm X 2000 μm is one unit, see
next page for more information)
TCDDMY should contain OD/PO/PP/NP/POBLK/ODBLK layer
TCDDMY overlap of DOD, SR_DOD, DPO, SR_DPO, OD2, DCO,
OD_12, NT_N, POFUSE, RPO, RH, VAR, VTH_P, VTH_N, VTL_P,
VTL_N, HVD_N, HVD_P, SRM, SRAMDMY, INDDMY, BJTDMY, or
MOMDMY is not allowed.
TCDDMY (165;1) is a must for any DummyTCD cell.
1. It can waive PO.DN.3, OD.W.2.1GS, OD.W.2.2GS, OD.W.1® , ,
DNW.S.2, PO.EX.2® , OD.S.1® , PO.S.1® , PO.S.6® , PO.EX.1® ,
PO.S.18.GS® , DOD.R.4® , SR_DOD.DN.1® , SR_DPO.DN.1® and
NW.R.1g.
A
=
12, 24, 9.245
=
5, 4, 0.43
=
0.04
=
0.14
B

70%
B

50%
Label
A’
A”
C’
Op.
=
=
=
Rule
5.71X3.57
3.6X6.33
2.4, 0.41, 0.31
D’
=
0.14 or 0.2
D
=
0.14
DTCD.W.2
DTCD.W.3
DTCD.S.1
DTCD.DN.1®
DTCD.DN.2
DTCD.R.1
DTCD.R.2
DTCD.R.3
TCDDMY_H/ TCDDMY_V (CAD layer no: 165;4/165;5) relative rules
Rule No.
DTCD.W.1.1
DTCD.W.1.2
DTCD.W.2.1
DTCD.S.1.1
DTCD.S.1.2
DTCD.R.4
DTCD.R.5
DTCD.R.6
Description
Dimension of TCDDMY_H
Dimension of TCDDMY_V
Channel width of gate inside TCDDMY_H or TCDDMY_V
Gate space to neighboring poly inside TCDDMY_H or TCDDMY_V
[channel width <2.0um]
Gate space to neighboring poly inside TCDDMY_H or TCDDMY_V
[channel width ≥ 2.0um]
TCDDMY_H/ TCDDMY_V must keep block orientation as the
following one of two conditions:
a. No rotation, and no mirror in X, Y direction (DRC option:
VERTICAL_TCD_PATTERN is on by default.)
b. Rotated clockwise 90 degree, and no mirror in X, Y direction. (must
turn off DRC option: VERTICAL_TCD_PATTERN)
Rotated clockwise 90 degree, need to align to SRAM gate direction.
Please refer to DTCD.R.5.
DRC will check relative coordinates of three alignment marks with
squre PO (0.5um x 0.5um) in the TCDDMY_H/ TCDDMY_V.
Poly gates in TCDDMY_H/ TCDDMY_V are uni-directional with gates
in SRAM (50;0 OR 186;0) in a chip for cyber shuttle. (must turn on
DRC option: CYBER_SHUTTLE)
(This check does not include the regions covered by layer
RODMY(49;0) and RAM1TDMY (160;0))
Poly gates in TCDDMY_H/ TCDDMY_V are uni-directional in a whole
chip level.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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A”
6 .3 3
( C A D la y e r : 1 6 5 ; 4 )
D’
TCDDM Y_V
TCDDM Y_H
3 .5 7
( C A D la y e r : 1 6 5 ; 5 )
A’
: T-N45-CL-DR-001
: 2.6
D
D’
D
C’
C /C ’
C’
5 .7 1
D’
3 .6
D’
SR D O D / D O D / N T_N / O D 2/ D C O / O D _12/ D PO / SR D PO /
TCDDMY
V T H _ N / V T H _ P / V T L_N / V T L _ P / R P O / VA R / R H / B JT D M Y /
PO FUSE/ SRM / SRAM DM Y / HVD_N/ HVD_P / M O M DM Y/
IN D D M Y / L O G O
D T C D .R .4
A’
A”
( C A D la y e r : 1 6 5 ; 4 )
6 .3 3
5 .7 1
90
90
o
TCDDM Y_V
3 .5 7
( C A D la y e r : 1 6 5 ; 5 )
TCDDM Y_H
o
3 .6
90
90
o
o
A’
A” TCDDM Y_V
3 .6
TC D D M Y_V
( C A D la y e r : 1 6 5 ; 4 )
6 .3 3
( C A D la y e r : 1 6 5 ; 5 )
TCDDM Y_H
3 .5 7
5 .7 1
5 .7 1
( C A D la y e r : 1 6 5 ; 4 )
A’
TCDDM Y_H
3 .5 7
3 .6
A”
( C A D la y e r : 1 6 5 ; 5 )
6 .3 3
O
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
O
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Dummy TCD
Example for B value calculation
Chip size = 16.5 X 14 mm (8 units X 7 units)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: T-N45-CL-DR-001
: 2.6
Dummy TCD layout Summary
1. The Dummy TCD cell should include layers as below.
Layer
CAD layer
Cell size (um)
Square
dummy TCD
Horizontal
dummy TCD
Vertical
dummy TCD
12X12
5.71X3.57
3.6X6.33
OD
6;0
V
V
V
NW
3;0
V
V
V
Poly (PO)
17;0
V
V
V
PP
25;0
V
V
V
NP
26;0
V
V
V
* Cell boundarya
108;0
V
V
V
*IPb
63;63
-
V
V
* OD block (ODBLK)
150;20
V
V
V
* PO block (POBLK)
150;21
V
V
V
* TCDDMY
165;1
V
V
V
* TCDDMY_H
165;4
-
V
-
* TCDDMY_V
165;5
-
-
V
* : To follow cell size for cell boundary/OD block /PO block/TCDDMY/ TCDDMY_H/ TCDDMY_V
a : Cell boundary is used during the P&R stage that do not generate by dummy utility.
b : It is for IP tagging layer that do not generate by dummy utility.
2. The Dummy TCD cell can abut on the main circuit.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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8.4
Dummy TCD Design Information
8.4.1
Overview
: T-N45-CL-DR-001
: 2.6
This chapter provides the dummy TCD macro insertion methodology.
Dummy TCD insertion is an implementation approach to improve IDU (Intra-Die uniformity) for designs.
Inserting dummy TCD in the chip design planning stage to meet design guidelines, like even distribution, is
recommended. Post-route dummy TCD insertion is only supplemental for uniform distribution improvement.
 Two types of dummy TCD macros are given:
 Horizontal type macro -> 5.71um x 3.57um
 Vertical type macro -> 3.6um x 6.33um
 Both dummy macros are with vertical poly direction
 Choosing either V type or H type would be fine within a window:
For example, one possible scenario could be
 Select H type for insertion first for all windows
 Adjust dummy macro placement incrementally and swap H type to V type when floorplan environment is
more suitable for V type in some window
8.4.2
Design Consideration of Dummy TCD Insertion
 In order to reduce area and timing penalty, dummy TCD macros could be placed in the following areas
first
1. Channel between core, IO, analog IPs
2. Channel between blocks
3. Digital block corner area
4. Channel between core, SRAMs
 It is recommended considering dummy TCD insertion at top level during chip floorplan.
 If dummy TCD inserted in large blocks or circuit IP (~2000umX2000um), please be aware of the
followings.
1. Consistent TCD orientation in whole chip.
2. It’s not allowed to have individual TCD rotation and mirror in X, Y.
3. Placing TCD at least 75um away from block boundary could meet 150um spacing recommendation.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
Dummy TCD Macro Placement
 Minimize dummy macro electrical impact to main pattern circuits like std cell, SRAM, analog IP by
either one of the approaches as below.
 Reserve 2μm space around dummy TCD by placement blockage as Fig 1., to let DPO/DOD utility
insert dummy OD/dummy PO.
 If you do not generate the dummy TCD by tsmc’s dummy OD/PO utility, use std cell fillers size ≥
0.4μm to surround dummy macros as Fig 2
 Dummy TCD contain 2 different types, V and H, your can select one type to insert into window.
 Dummy TCD V and H cannot overlap but it can use V or H simultaneously when insert to different
window.
 Dummy TCD could not overlap with any standard cell, macro, or IPs.
 Dummy TCD is physical only cell, and it doesn’t need to connect power supply.
Placement blockage
Dummy TCD macro
Std cell filler
FILL3
2um
Fig.1
Dummy TCD macro
Fig.2
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
P&R Dummy TCD Rule Check
 Dummy TCD P&R reference utility provided by TSMC could have a summary report for percentage
of window with dummy TCD.
 P&R reference utility could highlight windows without dummy TCD macros in GUI.
 For dummy TCD P&R rule reference utility, please refer to N40 DFM Implementation Flow package.
8.4.5
Dummy TCD Macros Insertion Flow
IO/analog/SRAM
Macro placement
Power Plan
ICOVL Insertion
Floorplan
stages
Dummy TCD insertion
conventional
Block partition
Dummy pattern
Insertion related
Place and Route
Tape-out GDS
Consider dummy
insertion
in a chip globally
before hierarchical chip
block partition.
Dummy TCD could be inserted
by DM utility on GDS.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
: T-N45-CL-DR-001
: 2.6
TCD Library Kits
 Dummy TCD GDSII files

DMY_TCD_H_20100305.gds

DMY_TCD_V_20100305.gds
 P&R implementation kits



LEF macro for dummy TCD

lef/DMY_TCD_H_20100305.lef

lef/DMY_TCD_V_20100305.lef
Milkyway library for dummy TCD

milkway/DMY_TCD_H_20100305/

milkway/DMY_TCD_V_20100305/
Volcano library for dummy TCD

volcano/DMY_TCD_H_20100305/

volcano/DMY_TCD_V_20100305/
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
8.5
In Chip Overlay (ICOVL) Rule And Filling
Guideline
8.5.1
In Chip Overlay (ICOVL) Rules






2 kinds of 36.7um x36.7um square in chip overlays are offered: OVL_PO_OD and OVL_CO_PO.
OVL_PO_OD = ICOVL NOT INTERACT CO
OVL_CO_PO = ICOVL INTERACT CO
ICOVL (CAD layer no.: 165;3) is must for in chip overlay.
Two folders are including in tarball (file name: N40_OVL_library_kits.tar.gz): (1) P&R physical library for
ICOVL and (2) gds.
Total 4 gds files are provided: two single ICOVLs (OVL_PO_OD and OVL_CO_PO) and 2 Combo ICOVLs
(OVL_PO_OD_CO_PO_H and OVL_PO_OD_CO_PO_V).
 OVL_PO_OD: OVL_PO_OD_N40_20101210.gds
 OVL_CO_PO: OVL_CO_PO_N40_20101210.gds
 OVL_PO_OD_CO_PO_H: OVL_PO_OD_CO_PO_H_N40_20101210.gds
 OVL_PO_OD_CO_PO_V: OVL_PO_OD_CO_PO_V_N40_20101210.gds
C o m b o IC O V L
S in g le IC O V L
O VL_PO _O D
O VL_CO _PO
O VL_PO _O D_C O _PO _V
3 6 .7 u m
40um
3 6 .7 u m
1 1 3 .4 u m
40um


O VL_PO _O D_C O _PO _H
1 1 3 .4 u m
OVL_PO_OD and OVL_CO_PO ICOVL can be used individually or combined with 40um spacing as 36.7um
X113.4um or 113.4umX36.7um rectangular in chip overlays.
There are two ICOVL guidelines in chip rotation: Floorplan A and Floorplan B.

Terminologies for 1X1die, 1X2die, 2X1 die and 2X2 die (The following dimensions are before shrink):

Floorplan A for N45GS(=N40G)/N40LP/N40LPG:
1.
2.
3.
4.
1X1 die size: 14.31mm < X and 18.24mm < Y
1X2 die size: 14.31mm < X and 12.13mm < Y  18.24mm
2X1 die size: 9.51mm < X  14.31mm and 18.24mm < Y
2X2 die size: 9.51mm < X  14.31mm and 12.13mm < Y  18.24mm

1.
2.
3.
4.
Floorplan B for N45GS(=N40G)/N40LP/N40LPG:
1X1 die size: 18.24mm < X and 14.31mm < Y
1X2 die size: 12.13mm < X  18.24mm and 14.31mm < Y
2X1 die size: 18.24mm < X and 9.51mm < Y  14.31mm
2X2 die size: 12.13mm < X  18.24mm and 9.51mm < Y  14.31mm
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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
Floorplan A for N45LP/N45LPG:
1.
2.
3.
4.
1X1 die size: 12.88mm < X and 16.42mm < Y
1X2 die size: 12.88mm < X and 10.92mm < Y  16.42mm
2X1 die size: 8.56mm < X  12.88mm and 16.42mm< Y
2X2 die size: 8.56mm < X  12.88mm and 10.92mm< Y  16.42mm

1.
2.
3.
4.

Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
Floorplan B for N45LP/N45LPG:
1X1 die size: 16.42mm < X and 12.88mm < Y
1X2 die size: 10.92mm < X  16.42mm and 12.88mm < Y
2X1 die size: 16.42mm < X and 8.56mm < Y  12.88mm
2X2 die size: 10.92mm < X  16.42mm and 8.56mm < Y  12.88mm
In general, you need to follow ICOVL floorplan A.
 If you know your tapeout will be rotated in tsmc, need to follow ICOVL floorplan B.
 Because when you request to rotate your chip, tsmc EBO will do anti-clockwise 90 degree for mask making.

Please refer to ICOVL.R.3® U ~ ICOVL.R.6® U for floorplan A and B.
Rule No.
ICOVL.S.1®
ICOVL.S.2®
ICOVL.S.3®
ICOVL.S.4®
ICOVL.S.5®
ICOVL.W.1®
ICOVL.W.2®
ICOVL.W.3®
ICOVL.W.4®
ICOVL.W.5®
ICOVL.EN.1®
ICOVL.EN.2®
ICOVL.R.1
ICOVL.R.2® U
ICOVL.R.3® U
ICOVL.R.4® U
ICOVL.R.5® U
ICOVL.R.6® U
ICOVL.R.7®
ICOVL.R.8®
ICOVL.R.9®
ICOVL.R.10®
ICOVL.R.11®
ICOVL.R.12®
ICOVL.R.13®
ICOVL.R.14®
ICOVL.R.15®
ICOVL.R.16®
ICOVL.R.17®
ICOVL.R.18®
ICOVL.R.19®
ICOVL.R.20®
ICOVL.R.21®
ICOVL.R.22®
Description
Label
Recommend OVL_PO_OD space to OVL_CO_PO
A
Recommend space between two OVL_PO_ODs or two OVL_CO_POs
A’
Recommend ICOVL (CAD layer no.: 165;3) space to {(OD OR PO) OR CO}
B
Recommend enclosed OD space inside OVL_PO_OD (maximum = minimum)
D
Recommend space between two COs for OVL_CO_PO [in the same ring]
E
Recommend width of PO ring inside ICOVL (maximum = minimum)
F
Recommend width of M1 ring inside OVL_CO_PO (maximum = minimum)
G
Recommend width of CO inside OVL_CO_PO (maximum = minimum)
H
Recommend width of {OD INTERACT PO} inside OVL_PO_OD (maximum = minimum)
I
Recommend PO hole width inside OVL_CO_PO (maximum = minimum)
J
Recommend {OD INTERACT PO} enclosure by PO inside OVL_PO_OD (maximum = minimum)
K
Recommend M1 ring enclosure by PO ring inside OVL_CO_PO (maximum = minimum)
L
ICOVL is must for any ICOVL cell.
It can waive:
OD.W.2.2GS, PO.DN.3, PO.R.1, RPO.S.3, RPO.S.4, CO.W.1.
Recommend the ICOVL patterns should be as uniform as possible over the chip
Recommend at least 2 OVL_PO_ODs on top row (Floorplan A)/ right row (Floorplan B) by
(1) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for 1X1 die
(2) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 4 segments for 1X2 die
Recommend at least 2 OVL_CO_POs on top row (Floorplan A)/ right row (Floorplan B) by
(1) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for 1X1 die
(2) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 4 segments for 1X2 die
Recommend at least 1 OVL_PO_ODs on top row (Floorplan A)/ right row (Floorplan B) by dividing chip Y
(Floorplan A) / X (Floorplan B) direction into 8 segments for 2X1 die
Recommend at least 1 OVL_CO_POs on top row (Floorplan A)/ right row (Floorplan B) by dividing chip Y
(Floorplan A) / X (Floorplan B) direction into 8 segments for chip size for 2X1 die
Recommend at least 8 OVL_PO_ODs and 8 OVL_CO_POs for 1X1 die
Recommend at least 4 OVL_PO_ODs and 4 OVL_CO_POs for 1X2 die or 2X1 die
Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_PO_OD SIZING +6500um}
Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_CO_PO SIZING +6500um}
Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_PO_OD SIZING +8000um}
Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_CO_PO SIZING +8000um}
Recommend empty space between two OVL_PO_ODs for 1X1 die. DRC flags:
{((Chip NOT OVL_PO_OD) SIZING -8000μm) SIZING +8000μm}
Recommend empty space between two OVL_CO_POs for 1X1 die. DRC flags:
{((Chip NOT OVL_CO_PO) SIZING -8000μm) SIZING +8000μm}
Recommend empty space between two OVL_PO_ODs for 1X2 die or 2X1 die.
DRC flags: {((Chip NOT OVL_PO_OD) SIZING -6500μm) SIZING +6500μm}
Recommend empty space between two OVL_CO_POs for 1X2 die or 2X1 die.
DRC flags: {((Chip NOT OVL_CO_PO) SIZING -6500μm) SIZING +6500μm}
Recommend density of {(OVL_PO_OD SIZING +16500um) SIZING -15500um} for 1X1 die
Recommend density of {(OVL_CO_PO SIZING +16500um) SIZING -15500um} for 1X1 die
Recommend density of {(OVL_PO_OD SIZING +13000um) SIZING -10000um} for 1X2 die or 2X1 die
Recommend density of {(OVL_CO_PO SIZING +13000um) SIZING -10000um} for 1X2 die or 2X1 die
Recommend at least 1 OVL_PO_OD fully inside {Chip SIZING -2380um} for 2X2 die
Recommend at least 1 OVL_CO_PO fully inside {Chip SIZING -2380um} for 2X2 die
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.



=
=
=
=
=
=
=
=
=
Rule
40
2000
2
1.1
0.10
1.1
1.1
0.17
16.5
16.5
3.3
3.92

16000

16000

13000

13000




25%
25%
25%
25%
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S in g le IC O V L
B
CO
A
B
B
OD
PO
M 1 r in g
M e ta l r o u tin g c o u ld b e a c r o s s O V L _ C O _ P O a n d O V L _ P O _ O D
b u t M 1 n e e d s to d e to u r a r o u n d M 1 r in g (O V L _ C O _ P O )
C o m b o IC O V L s
C o m b o IC O V L to S in g le IC O V L s
A’
A
A’
A
A
A’
A
A
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
O VL_PO _O D
K
PO
K
D
F
I
O VL_C O _PO
E
H
M1
PO
F
G
J
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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IC O V L .R .3 ®
Confidential – Do Not Copy
U
a n d IC O V L .R .4 ®
Document No.
Version
: T-N45-CL-DR-001
: 2.6
U
1 X 1 d ie in a r e tic le : A t le a s t 8 O V L _ P O _ O D s
1 X 2 d ie in a r e tic le : A t le a s t 4 O V L _ P O _ O D s
a n d 8 O V L _ C O _ P O s in 1 d ie
a n d 4 O V L _ C O _ P O s in 1 d ie
(1 ) A t le a s t 2 O V L _ P O _ O D s a n d a t le a s t 2
(1 ) A t le a s t 2 O V L _ P O _ O D s a n d a t le a s t 2
O V L _ C O _ P O s o n to p r o w b y d iv id in g c h ip
O V L _ C O _ P O s o n to p r o w b y d iv id in g c h ip Y
Y d ir e c tio n in to 8 s e g m e n ts
d ir e c tio n in to 4 s e g m e n ts
(2 ) P u t r e m a in in g 6 O V L _ P O _ O D s a n d 6
(2 ) P u t r e m a in in g 2 O V L _ P O _ O D s a n d 2
O V L _ C O _ P O s a s u n ifo r m a s p o s s ib le
O V L _ C O _ P O s a s u n ifo r m a s p o s s ib le
F lo o r p la n A
F lo o r p la n A
R o ta te d c lo c k w is e 9 0
o
R o ta te d c lo c k w is e 9 0
o
F lo o r p la n B
F lo o r p la n B
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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ICOVL.R.5® U and ICOVL.R.6® U
2X1 die in a reticle: At least 4 OVL_PO_ODs
and 4 OVL_CO_POs in 1 die
(1) At least 1 OVL_PO_ODs and at least 1
OVL_CO_POs on top row by dividing chip
Y direction into 8 segments
(2) Put remaining 3 OVL_PO_ODs and 3
OVL_CO_POs as uniform as possible
Floorplan A
ICOVL.R.21® and ICOVL.R.22®
2X2 die in a reticle: Select 1 of center 2X2
windows for ICOVL insertion
•
At least 1 OVL_PO_ODs and 1 OVL_CO_POs
inside {Chip SIZING -2380um} for 2X2 Die
Floorplan A
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
Rotated clockwise 90o
2380
2380
2380
Floorplan B
: T-N45-CL-DR-001
: 2.6
Rotated clockwise 90o
Floorplan B
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
2380
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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8.5.2
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
ICOVL layout Summary
1. The ICOVL cell should include layers as below.
Layer
CAD Layer
Size (um)
OVL_PO_OD
(single)
OVL_CO_PO OVL_PO_OD_CO_PO_H OVL_PO_OD_CO_PO_V
(single)
(combo)
(combo)
36.7X36.7
36.7X36.7
113.4X36.7
36.7X113.4
IPb
63;63
V
V
V
V
OD
6;0
V
V
V
V
PO
17;0
V
V
V
V
CO
30;0
-
V
V
V
M1
31;0
-
V
V
V
PP
25;0
V
V
V
V
RPO
29;0
V
V
V
V
*Cell boundarya
108;0
V
V
V
V
DOD
6;1
V
V
V
V
DPO
17;1
V
V
V
V
DM1
31;1
-
V
V
V
*DM1EXCL
150;1
-
V
V
V
*OD block (ODBLK)
150;20
V
V
V
V
*PO block (POBLK)
150;21
V
V
V
V
*ICOVL
165;3
V
V
V
V
* : To follow cell size for cell boundary/OD block /PO block/ DM1EXCL/ ICOVL
a
: Cell boundary is used during the P&R stage.
b : It is for IP tagging layer.
2. The in-chip OVL cell can neighbor on the main circuit.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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8.5.3
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
N40 In-Chip OVL Marker Design Insertion
Methodology
8.5.3.1
Overview
Overlay (OVL) marker insertion is to reduce mask alignment errors by in-chip OVL marker pattern. In N40 technology, it is
very important to insert in-chip OVL (ICOVL) inside your chip for the big chip design (e.g. 1x1, 2x1, 1x2 and 2X2 in a
retile).
8.5.3.2
Combo ICOVL LEF, Placement and Routing
 To generate combo ICOVL LEF, create 2 OBS OVERLAP rectangles on top of OD/PO/CO markers on both sides (as
shown below)
 Cell could be placed inside combo ICOVL, in which area there is no OBS OVERLAP.
 Routing is legal to be across ICOVL when there is no M1 blockage.
 There are two ICOVL guidelines in chip rotation: Floorplan A and Floorplan B.

In general, you need to follow ICOVL floorplan A.

If you know your tapeout will be rotated in tsmc, need to follow ICOVL floorplan B.


Because when you request to rotate your chip, tsmc EBO will do anti-clockwise 90 degree for mask making.
Please refer to ICOVL.R.3® U ~ ICOVL.R.6® U for floorplan A and B.
8.5.3.3
Dummy Patterns Priority
 ICOVL marker priority is higher than TCD dummy for the big chip
 Combo ICOVL priority higher than single ICOVL, if room of a specific window in floorplan is enough. Combo ICOVL
could reduce insertion effort.
 Combo H or V types are of equal priority. Choose either one orientation, which is suitable for floorplan and with less
layout impact.
 Need to consider ICOVL insertion in chip level point of view, because insertion in block or IP might not be able to meet
uniformity requirement (please refer ICOVL.R.2® U ~ ICOVL.R.6® U, ICOVL.R.7® ~ ICOVL.R.8® , ICOVL.R.9® U ~
ICOVL.R.22® U).
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Version
8.5.3.4
Single ICOVL vs. Combo ICOVL
8.5.3.5
ICOVL Insertion Guidelines
: T-N45-CL-DR-001
: 2.6
Die size for mask
1X1 reticle
2X1 reticle
1X2 reticle
2X2 reticle
Window partition
8X8
4X8
8X4
-
Number of ICOVL
required
8® *
4®
4®
1®
Number of ICOVL on
top row
2®
1®
2®
0
*: 8 means 8 for PO_OD and another 8 for OD_CO.
 Select windows for ICOVL to achieve maximum ICOVL placement evenness. For die size for mask definitions, please
refer 1X1 die, 1X2 die, 2X1 die and 2X2 die terminologies in sec.8.5.1.
 In each window partition, choose either a set of single ICOVL (both OD/PO and OD/CO), or a combo ICOVL H or V.

For 1X1 die, please refer ICOVL.R.2® U~4® U, ICOVL.R.7® , ICOVL.R.9® U, ICOVL.R.10® U, ICOVL.R.13® U,
ICOVL.R.14® U, ICOVL.R.17® U and ICOVL.R.18® U for details.

For 1X2 die, please refer ICOVL.R.2® U~4® U, ICOVL.R.8® , ICOVL.R.11® U, ICOVL.R.12® U, ICOVL.R.15® U,
ICOVL.R.16® U, ICOVL.R.19® U and ICOVL.R.20® U for details.

For 2X1 die, please refer ICOVL.R.2® U, ICOVL.R.5® U, ICOVL.R.6® U, ICOVL.R.8® , ICOVL.R.11® U,
ICOVL.R.12® U, ICOVL.R.15® U, ICOVL.R.16® U, ICOVL.R.19® U and ICOVL.R.20® U for details.
 Both combo and single ICOVL placement rotation and mirror in X,Y are legal.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Dummy Pattern Insertion in Design Phase
IO/analog/SRAM
Macro placement
Power Plan
ICOVL Insertion
Floorplan
stages
Dummy TCD insertion
Conventional
Block partition
Dummy pattern
Insertion related
Place and Route
Consider dummy insertion in
a chip globally before
hierarchical chip block
partition.
Consider dummy TCD in
floorplan first.
Tape-out GDS
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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8.6
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Dummy Metal (DM) Rules
(DMx, x = 1,2,3,4,5,6,7,8,9,10)
1.
2.
To improve the metal CMP process window, you must fill the dummy metal globally and uniformly
even if the originally drawn Mx has already met the density rules.
Use either the P&R dummy fill or the utility dummy fill as a method for inserting dummy metal. Two
methods are available for automated dummy metal insertion: commercial P&R tools and a utility from
TSMC:
 The P&R dummy fill is better for dummy metal insertion at the chip level.
 The utility dummy fill is better for IP blocks, library cells, and full custom cells.
 Commercial P&R software inserts rectangular DMx geometry.
 The TSMC utility can insert square DMx uniformly within the original layout. (documents T-N45-CL-DR001-C3 and T-N45-CL-DR-001-H3)
 If you use TSMC’s auto-fill utility to fill the dummy metal on the whole chip GDS, TSMC will waive the
local density violation. If you do not use TSMC’s utility to perform the dummy metal generation, you
must meet the local density rules.
3.
In the TSMC utility, two kinds of dummy metal are generated, DMx and DMx_O.
DMx: dummy metal

No OPC on DMx

DMx for Mx, My, Mz, Mr, and Mu.
DMx_O: OPC dummy of inter-metal.

The rule of DMx_O is the same as real metal, Mx. So, there is no related rule in this section.

There is no DMx_O for My, Mz, Mr, and Mu.

DMx_O receives OPC.
The distinction between Mx, DMx and DMx_O
GDS datatype
Do OPC modification on it
Refer to it during OPC
Follow Mx rule
4.
5.
Mx
DMx
DMx_O
0(x), 20(y), 40(z), 60(u), 80(r)
Yes
Yes
Yes
1(x), 21(y), 41(z), 61(u), 81(r)
No
Yes
No
7(Mx)
Yes
Yes
Yes
Use the dummy layer DMxEXCL properly. This layer tells TSMC’s utility that the area covered should be
blocked from DM fill operations.
It is suggested to make sure that DMxEXCL is drawn over the following:
Sensitive circuits (such as SRAM sensitive function blocks and bit cell array) and analog circuits (such
as DAV/ADC, and PLL)
RF application circuits
Pad areas for high frequency signals
For sensitive areas with auto-fill operations blocked by the DMxEXCL layer, it is recommended filling
dummy pattern evenly by manual operations to gain a better process window and electrical performance.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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6.
7.
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
For DMxEXCL, use the GDS layer numbers 150;n (n = 1,2,3,4,5,6,7,8,9,10).
Revision of the following layers may necessitate re-filling of dummy metal. Because of this, evaluate the
impact on the metal layer mask carefully when any one of the following layouts is revised:
Mx and DMxEXCL layers. This layout revision impacts the Mx mask only.
LOGO/INDDMY. This revision impacts all the metal layer masks.
8.
In order to have an accurate interconnect RC for timing and power analysis, it is important to extract RC
after dummy metal insertion, and extract RC with density based metal thickness variation feature enabled.
9.
Don’t put dummy metal in areas covered by the following marker layers:
Inductor region (INDDMY)
LOGO
Regions of chip corner stress relief pattern, seal ring, and CDU pattern
TSMC’s fill generation utility will not add dummy metal into these regions because these layers are well
defined.
The DMxEXCL covered areas should not cover or overlap the above areas for DRC reasons.
10. Please refer to the “Dummy Pattern Fill Usage Summary” section in this chapter for additional
information.
11. Please consult with TSMC first before you use your own dummy metal rules.
Description
Rule No.
Label
Op.
Rule
DMx.W.1
Width (minimum)
A

DMx.W.2
Width (maximum) (checked by sizing down 1.5 μm)
B

DMx.S.1
DMx.S.2
Space
Space to Mx (Overlap is not allowed)
Space to Mx (Overlap is not allowed) [Mx width > 4.5 μm and the parallel
metal run length > 4.5 μm]
Enclosure of DVIAx-1
Area (minimum)
Area (maximum)
DMx_O INTERACT Mx is not allowed.
C
D


E

1.5



0.01
M
N
DMx.S.3
DMx.EN.2
DMx.A.1
DMx.A.2
DMx_O.R.1
Layer
M1
Mx (thin metal)
My
Mz (thick metal)
Mr
Mu (ultra thick metal)
3.0
Dimension
A
C
D
M
N
0.14
0.14
0.4
0.4
0.8
3.0
0.14
0.14
0.4
0.4
0.8
3.0
0.6 / 1.5 *
0.6 / 1.5 *
0.6
0.6
0.8
3.0
0.16
0.16
0.565
0.565
1.44
9.00
80
80
160
160
160
600
Table Notes:
0.6μm: space to main patterns for DMx smaller than 1μm x 1μm
1.5μm: space to main patterns for DMx larger than 1μm x 1μm
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Rule No.
Mx.DN.1
Mx.DN.1.1
Mx.DN.4
Mx.DN.5
Mx.DN.6
Mx.DN.6®
Mx.DN.7
Mx.DN.7®
Mx.DN.8®
DMx.R.1
DMx.R.2
DMx.R.3
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Label
Minimum metal density in window 125 um x 125 um, stepping 62.5 um
Maximum metal density in window 125 μm x 125 μm, stepping 62.5 μm
1. Mx.DN.1/Mx.DN.1.1 would exclude the following regions:
LOGO/INDDMY for 10% rule
Chip corner stress relief area and seal-ring
2. Mx.DN.1  10% rule is applied when the width of (checking window NOT item 3) is  31.25 μm.
3. Mx.DN.1.1  85% rule is applied when the width of (checking window NOT item 3) is  31.25 μm.
4. Bond pad (Mtop/Mtop-1) is excluded from 85% density check.
The metal density difference between any two neighboring checking windows including DMxEXCL [window 200
μm x 200 μm, stepping 200 μm].
Anticipate metal density gradient from layout of small cell by targeting density ~40% (this way, it will limit the risk
of low density and of high gradient.)
It is not allowed to have local density > 85% of all 3 consecutive metal (Mx, Mx+1, and Mx+2) over any window
62.5 μm x 62.5 μm (stepping 31.25 μm), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density  85%.
1. The metal layers include M1/Mx and dummy metals.
2. The check does not include chip corner stress relief pattern, SEALRING_ALL (162;2) and top two metals at
the CUP area.
Metal density  1% must be followed for items (A) to (C).
(A) Metal density [window 80 μm x 80 μm, stepping 40 μm]  1%.
(B) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density < 1%]
≤ 6400um2, except the merged low density windows width ≤ 30um.
(C) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density < 1%]
≤ 18000um2.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  40um for (A) and 
5um for both (B)/(C).
Recommend metal density  1% for IP level. Items (A) to (C) are recommended.
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm]  1%. This item is applied
for {IP NOT (IP SIZING -40um)} region when the width of IP is  40um.
(B) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
stepping 5um, density < 1%] ≤ 1600um2, except the merged low density windows width ≤ 30um. This item is
applied for {IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
(C) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
stepping 5um, density < 1%] ≤ 4500um2. This item is applied for {IP NOT (IP SIZING -10um)} region when
the width of IP is  10um.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  20um for (A) and 
5um for both (B)/(C).
It is not allowed to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any 30um x
30um (stepping 15um), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local density ≥ 5%.
1. The metal layers include M1/Mx and dummy metals.
2. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is  15 μm.
It is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any
15um x 15um (stepping 15um) for IP level, i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density ≥ 5%.
1. The metal layers include M1/Mx and dummy metals.
2. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is ≥ 7.5μm and for
{IP NOT (IP SIZING -15um)} region when the width of IP is  15um.
Total Mx island (for all Mx layers) density < 6.5E+04 ea/mm2 in whole chip
The definition of counts of small Mx island:
1. Mx width == 0.07um
2. Mx length  0.52um
3. Mx has two segments with space == 0.07um with the parallel run length (0.209  parallel run length < 0.52)
DMx is a must. The DMx CAD layer must be different from the Mx CAD layer.
DMx inside chip corner stress relief area is not allowed [except seal-ring and stress relief patterns drawn by
customers].
DMx must be rectangular
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.


Rule
10%
85%

50%
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Rule No.
DMx.R.4®
U
DMx.W.1gU
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
Description
Label
It is important to insert the DMx & DVIAx uniformly to avoid white space. You should use tsmc standard backend
utility to insert the backend dummy pattern. The usage of DMxEXCL needs to be minimized.
Recommended DMx size (width x length) and space
Square
(Utility Fill)
Width x Length
M1
0.5x0.5~2x2
Mx
0.5x0.5~2x2
My
1x1~2x2
Mz
1x1~2x2
Mr
1.2x1.2~3x3
Mu
3x3
Op.
DMx
D M x
D /E
M x
A /B
H
C
D M xE X C L
D M x
D M x
M /N
M in im u m /M a x im u m
a re a
M x
D M x
O
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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8.7
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Dummy VIA (DVIAx) Rules
(DVIAx, x = 1,2,3,4,5,6,7)
1. To improve the Flip Chip reliability window, you must fill the dummy VIA globally and uniformly.
2. Dummy VIA is only allowed to be inserted between dummy metals (DVIAx.R.2).
3. Use either the P&R dummy fill or the utility dummy fill as a method for inserting dummy VIA. Two
methods are available for automated dummy VIA insertion: commercial P&R tools and a utility from TSMC:
The P&R dummy fill can only insert dummy VIA at the chip level but the filling rate is not good.
The TSMC DMx utility can insert DVIAx with good filling rate. It can support IP blocks, library cells, and
full custom cells. (documents T-N45-CL-DR-001-C3 and T-N45-CL-DR-001-H3).
4. In the TSMC utility, one kind of dummy VIA is generated, DVIAx.
DVIAx: dummy VIA

No OPC on DVIAx

DVIAx for VIAx only, not for VIAy, VIAz, VIAr, VIAu
The distinction between VIAx, DVIAx
GDS datatype
Do OPC modification on it
Refer to it during OPC
Follow VIAx rule
VIAx
0
Yes
Yes
Yes
DVIAx
1
No
Yes
No
5. Use the dummy layer DVIAxEXCL properly. This layer directs TSMC’s utility that the area covered should
be blocked from DVIAx fill operations.
6. It is suggested to make sure that DVIAxEXCL is drawn over the following:
Sensitive circuits (such as SRAM sensitive function blocks and bit cell array) and analog circuits (such
as DAV/ADC, and PLL)
RF application circuits
Pad areas for high frequency signals
For sensitive areas with auto-fill operations blocked by the DVIAxEXCL layer, it is recommended filling
dummy pattern evenly by manual operations to gain a better process window and electrical performance.
7. For DVIAxEXCL, use the GDS layer numbers 150;n (n = 51,52,53,54,55,56,57).
8. Revision of the following layers may necessitate re-filling of dummy VIA. Because of this, evaluate the
impact on the metal/VIA layer mask carefully when any one of the following layouts is revised:
Mx/DMx/VIAx/DVIAx/DMxEXCL and DVIAxEXCL layers. This layout revision impacts the Mx/VIAx/
Mx+1 masks.
LOGO/INDDMY. This revision impacts all the metal/VIA layer masks.
9. Please refer to the “Dummy Pattern Fill Usage Summary” section in this chapter for additional
information.
10. Please consult with TSMC first before you use your own dummy VIA rules.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Rule No.
DVIAx.W.1
DVIAx.S.1
DVIAx.S.2
DVIAx.EN.1
DVIAx.R.1
DVIAx.R.2
DVIAx.R.3
Confidential – Do Not Copy
Document No.
Version
Description
Width (maximum = minimum)
Space
Space to VIAx
Enclosure by DMx
DVIAx must be fully inside DMx and DMx+1.
DVIAx interact Mx, Mx+1, DMx_O, DMx+1_O is not allowed.
DVIAx is a must for Flip Chip.
To comply tsmc dummy utility, DRC will flag as violation when the area
ratio of (DVIAx to DMx) & (DVIAx to DMx+1) are < 1% at the same time.
: T-N45-CL-DR-001
: 2.6
Label
A
B
D
C
Op.
=



Rule
0.12
0.20
0.20
0.01
DVIAx
C
B
D
A
D V IA x
D M x
V IA x
M x
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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8.8
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Dummy Pattern Fill Usage Summary
This section is divided into the following sections:

Dummy pattern filling requirements

Recommended flow for dummy pattern filling

Blockage layer (ODBLK/POBLK/DMxEXCL/DVIAxEXCL) requirements and recommendations

Dummy pattern filling guidelines

Mask revision guidelines

Dummy pattern re-fill evaluation flow chart
8.8.1
Dummy Pattern Filling Requirements
1. OD/PO/Metal pattern density requirements
Local Density Range
Poly
20%~80% for Core region
20%~90% for I/O region
NA
Metal
10%~85% for M1/Mx/My/Mz/Mu
OD
Window check size
Whole Chip Density Range
150 μm * 150 μm
25%~75%
NA
125 μm * 125 μm for
M1/Mx/My/Mz/Mr/Mu
14%~40%
NA
2. DOD/DPO/DMx requirement: The DOD/DPO/DMx must be filled, even if the local or chip density has
already met the density rules
(OD.DN.1/OD.DN.1.1/OD.DN.2/OD.DN.2.1/OD.DN.2.2/OD.DN.3/OD.DN.3.1/OD.DN.3.2/PO.DN.1/PO.DN.1
.1/PO.DN.2/PO.DN.3/Mx.DN.1/Mx.DN.1.1/Mx.DN.4/Mx.DN.5) (x=1~10).
3. Density requirement: It is recommended that you use the TSMC auto-fill utility to generate dummy fill
patterns.
If you use TSMC’s auto-fill utility to fill DOD and DMx, TSMC will waive the low density rule violations
(OD.DN.2, OD.DN.3, Mx.DN.1, and Mx.DN.4) (x=1~10). Both the local density rules and chip density rules
must be met if TSMC’s auto-fill utility is not used to generate the DOD/DPO/DMx fill.
4. Tool recommendation: It is recommended filling dummy patterns using P&R dummy fill (for DMx only)
with TSMC provided settings or using the TSMC’s auto-fill utility.
The TSMC auto-fill utility can fill patterns uniformly. It is structurally and hierarchically optimized to provide
maximum yield and manufacturability improvement with minimum perturbation to the circuit.
5. DVIAx requirement: It is important to add as many DVIAx as possible (DVIAx.R.3) to enhance the Flip
Chip assembly reliability window.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Recommended Flow for Dummy Pattern Filling
IP le v e l
F ill D M x /D V IA x
(G D S )
u tility
b y ro u te r o r u tility ?
ro u te r
F ill D O D /D P O /D M x /
F ill D M x /D V IA x b y ro u te r
D V IA x b y T S M C u tility
(re fe r th e to o l/s e ttin g fro m
F ill D M x /D V IA x
T S M C R e fe re n c e F lo w )
b y T S M C u tility
a n d c o n firm D R C c le a n
Yes
N e w IP
D R C c le a n ?
(G D S )
N o
In c re m e n ta lly fill D M x /D V IA x w ith
P & R a t c h ip le v e l
d iffe r e n t D M x -M x o r D M x -D M x s p a c e
(tim in g , p o w e r… .)
to m e e t lo c a l d e n s ity *
N e tlis t
F ill D O D /D P O b y
T S M C u tility
E v a lu a tio n
(tim in g , p o w e r… .)
N o
D R C c le a n e x c e p t
S o lv e D R C v io la tio n
lo c a l d e n s ity ?
Yes
Yes
D R C c le a n fo r
F ill D M x /D V IA x
lo c a l d e n s ity ?
b y T S M C u tility
N o
u tility
T S M C w a iv e lo c a l
d e n s ity v io la tio n
U s in g T S M C
u tility o r ro u te r?
N o
ro u te r
W a iv e d b y
TSM C?
Yes
F in is h D u m m y fillin g
* If in c r e m e n ta ll y f ill D M x is d o n e m a n y tim e s , i t s till c a n ’t m e e t in g lo c a l d e n s it y, p l e a s e f ill D M x b y T S M C
u t i l i t y o r a s k T S M C ’s c o m m e n t t o w a i v e i t o r n o t .
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Blockage Layer (ODBLK/POBLK/DMxEXCL/
DVIAxEXCL) Requirements and
Recommendations
1. Density requirement: For any area covered by a blockage layer, it is especially critical to meet the local
density rules.
Blockage layers specify sensitive regions (by recommendation or requirement), and P&R dummy fill(for
DMx only) or the TSMC auto-fill utility does not fill dummy patterns for these regions. For details, please
refer to the following sections in this chapter: “Dummy OD Rules,” Dummy Poly Rules,” and “Dummy
Metal Rules.”
Circuit
RF application circuit
Pad metal area for high
frequency signals
Analog block (ADC/DAC/PLL,
and so on)
Blockage Layer
ODBLK
POBLK
DMxEXCL
DVIAxEXCL
Must
Must
Must
Must
Must
Must
Must
Must
Must
Must
Recommended
Not necessary

RF circuits: Draw a blockage layer that covers the entire RF circuit. Designers should consider the
signal coupling impact and keep a suitable distance between the RF circuits and the blockage layer
edge.

High frequency signal pads: Draw blockage layers that are coincident with the outer edge of the
metal pads.

Other sensitive regions: Draw a blockage layer that covers the other sensitive regions, including the
SRAM function block and bit cell array, analog circuits (DAC/ADC/PLL), and so on.
2. Areas excluded from certain dummy fill: Don’t put any dummy patterns into the following regions:
Well resistor under STI region (NWDMY): DOD/SR_DOD
INDDMY region: DOD/DPO/DMx
LOGO region: DMx
Seal ring /CDU /chip corner stress relief pattern region: DOD/SR_DOD/DPO/SR_DPO/DMx
The TSMC utility will not add dummy patterns into these regions unless the correct dummy layer is
specified, or the correct option is turned on (for chip corner).
The ODBLK/POBLK/DMxEXCL covered areas should not cover or overlap the above areas for DRC
reasons.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Dummy Pattern Filling Guidelines
1. Dummy pattern filled by P&R dummy fill (for DMx only) or TSMC’s dummy fill utility.
Put all relevant layers (MUST and OPTION listed in the following table) into one GDS file. If the OPTION
layers are not ready to tape out, draw the blockage layer to avoid dummy pattern fill.
Dummy Pattern
Layer ID
OD
PO
NW
NP
PP
Mx
VIAx
NWDMY
INDDMY
ODBLK
POBLK
DMxEXCL
DVIAxEXCL
LOGO
Description
Diffusion
Poly
N-well
N+ S/D implant
P+ S/D implant
x=1,2,3,4,5,6,7,8,9,10
x=1,2,3,4,5,6,7
N-Well resistor
Inductor dummy layer
DOD blockage layer
DPO blockage layer
DMx blockage layer
DVIAx blockage layer
Product labels
DOD
DPO
MUST
MUST
MUST
MUST
MUST
MUST
MUST
DMx
(x=1,2,3,4,5,6,7,8,9,10)
DVIAx
(x=1,2,3,4,5,6,7)
MUST
MUST
MUST
MUST
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
2. Dummy pattern geometry (DOD/DPO/DMx) generated by P&R tool or TSMC utility: You must place
this fill geometry in a reserved layer (data type 1 as default).
3. Dummy pattern generated by a non-TSMC utility: If the auto-fill utility is not provided by TSMC, it must
meet the DOD/DPO/DMx rule. Also, keep this fill geometry in a reserved layer (data type 1 as default).
4. CAD layer usage: If dummy patterns and active patterns have different GDS layers and data types (such
as data type 0 and 1), the dummy patterns should follow the DOD/DPO/DMx rules.
If dummy geometry and active circuit geometry are placed on the same GDS layers and data types (such
as data type 0), the dummy patterns should follow the appropriate OD/PO/Mx rules. Please note that
placement of dummy geometry on the same CAD layer as circuit geometry will result in longer mask
making cycle times.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Mask Revision Guidelines
When masks or layouts are revised, re-evaluate to modify the filled dummy patterns.
Dummy Pattern
Layer ID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OD
PO
NW
Mx (x=1,2,3,4,5,6,7,8,9,10)
VIAx (x=1,2,3,4,5,6,7)
NWDMY
INDDMY
ODBLK
POBLK
DMxEXCL (x=1,2,3,4,5,6,7,8,9,10)
DVIAxEXCL (x=1,2,3,4,5,6,7)
LOGO
DOD
DPO
DOD














DPO














DMx
(x=1,2,3,4,5,6,7,8,9,10)














DVIAx
(x=1,2,3,4,5,6,7)














 : Needs GDS/mask revision
 : Evaluate GDS/mask revision
 : Doesn’t need GDS/mask revision
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Dummy Pattern Re-fill Evaluation Flow Chart
OD Mask Revision Decision Flow
If NW/PO/NWDRY/INDDMY/ODBLK/
DPO is revised
(Example: PO revised)
Check DOD and DPO rules on the old
DOD layout and newly revised layer.
(Example: Run rule check of DOD.S.3)
Design rule violations?
(EX: Violated DOD.S.3)
NO
There is no need to revise the OD
mask.
(Example: There is no impact
on the OD mask.)
YES
Must revise OD mask.
(Example: The OD is impacted)
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PO Mask Revision Decision Flow
If OD/INDDMY/POBLK/DOD
revised
(Example: OD revised)
Check DOD and DPO rules on the old
DPO layout and newly revised layer.
(Example: Run the rule check of DPO.S.2)
There is no need to revise the PO
Design rule violations?
(Example: Violated DPO.S.2)
NO
mask.
(Example: There is no impact on the
PO mask.)
YES
Must revise PO mask.
(Example: The PO is impacted)
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Mx Mask Revision Flow
If INDDMY/DMxEXCL/LOGO is
revised
(Example: INDDMY revised)
Check dummy metal rules on the old DMx
layout and newly revised layer.
(Example: Check DMx.S.4)
There is no need to revise the
Design rule violations?
(Example: Violate DMx.S.4?)
NO
MX mask.
(Example: There is no impact on
the Mx mask.)
YES
Must revise the Mx mask.
(Example: The Mx is impacted.)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
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VIAx Mask Revision Flow
If Mx/INDDMY/DMxEXCL/
DVIAxEXCL/LOGO is revised
(Example: INDDMY revised)
Check dummy VIA rules on the old DVIAx
layout and newly revised layer.
(Example: Check DVIAx.S.1)
There is no need to revise the
Design rule violations?
(Example: Violate DVIAx.S.1?)
NO
VIAx mask.
(Example: There is no impact on
the VIAx mask.)
YES
Must revise the VIAx mask.
(Example: The VIAx is impacted.)
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whole or in part without prior written permission of TSMC.
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9 Design For Manufacturing (DFM)
This chapter provides information about the following topics:
9.1 Layout guidelines for yield enhancement
9.2 DFM Recommendations and Guidelines Summary
9.3 Mechanical and Thermal Guidelines for FCBGA
9.4 GDA die size optimization kit
9.1
Layout Guidelines for Yield Enhancement
This section provides guidelines for layout optimization to minimize certain potential and unnecessary yield or
timing loss under the condition that they introduce no area penalty.
For a given chip design, first and foremost, efforts should be made to achieve as small a die size as possible.
The guidelines should not be used indiscriminately, which could result in unnecessarily large chip sizes.
This section is divided into the following topics:

Layout tips for minimizing critical areas

Guidelines for optimal electrical model and silicon correlation

Guidelines for mask making efficiency
9.1.1
Layout Tips for Minimizing Critical Areas
Defects are variable in size and therefore follow a size distribution. A critical area of a given layout is an
accumulative area that is susceptible to certain failures (shorts or opens) caused by defects of a certain size.
For example, although the total occupied areas are the same in panels A and B of Figure 9.1.1, the wires in
layout A are more vulnerable to defect-induced shorts because they have a larger critical area.
A
B
Figure 9.1.1 Layout Examples of Critical Areas
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1. Space out the wiring.
Spacing out the wiring, either using Wire Spreading at P&R stage or manually layout modification at cell
level, to take advantage of an empty space can reduce the critical area. This practice has additional
benefits:
It can reduce wire cross coupling.
It can reduce the possibility of pattern short.
It can evenly distribute the local pattern density, thereby creating less variation in wire Rs.
2. Reduce the probability of wiring shorts.
The critical area plays a role in the yield of a given design, but so does the rate of failure that corresponds
to the critical area. Manufacturing experience indicates that a wiring short circuit is a more frequent
problem than an open circuit.
Give priority to increasing wiring space for conductors of non-minimum wiring pitch, second only to wire
resistance or EM considerations. Refer to Figure 9.1.2.
Figure 9.1.2 Reduced Probability of Wiring Shorts
For long and parallel metal or poly lines, use a larger space.
Avoid the use of redundant wiring, except for reliability or performance considerations.
Draw wires in an orthogonal fashion.
Avoid leaving small jogs, especially in the corner areas where metal spacing is at a minimum.
Avoid using 45-degree turns, except for very wide metal buses, where the length of the 45-degree
portion should be sufficiently large. X-metal uses more advanced E-beam writer to generate mask and
no need to consider this recommendation
3. Reduce the risk of open silicided wire or high resistance silicided wire.
To avoid a potential silicide break related to an open circuit or high resistance in narrow lines of poly or OD:
Do not use a long narrow width poly conductor, if possible, as a means of local interconnection. The
length of non-contacted narrow width poly should be kept to a minimum.
If possible, do not use a narrow width OD conductor as a means of interconnection.
Avoid a butted N+OD/P+OD interface in a narrow OD/PO.
Use a sufficient number of contacts when a narrow OD strip is used for substrate tapping.
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4. Reduce the probability of a contact or via open circuit.
Open and soft open (excessively high Rc) of a single contact or via are usually a yield bottleneck, given
their sheer number in a chip. While the manufacturer strives to bring down the failure rate as low as
possible, a designer can contribute to further reduction of the probability.
Whenever possible, include redundant vias and contacts for the following benefits:
Reduces the probability of an open circuit
Reduces via and contact resistance and potential variation.
Potentially increases via stress migration immunity
5. Reduce the probability of open vias in a single-via stack.
Whenever possible, use a larger than minimum sized island metal for stacking a single via. This reduces
the risk of via resistance variation or open vias.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Guidelines for Optimal Electrical Model and
Silicon Correlation
The following sections offer recommended practices to minimize the deviation of processed hardware from
electrical models.
9.1.2.1
Transistors
1. Avoid layout styles that may contribute to silicon-to-model deviation.

Avoid using narrow-width devices and short channel device if they require high precision, such as
current source device.

Due to critical dimension variations in channel length and channel width, the electrical
properties of narrow-width devices and short channel devices vary more than those of larger
devices.

Poly or OD corner rounding may impact the device length or width critical dimension.
Source or drain contacts should be placed symmetrically wherever possible. Avoid using single source
or drain contacts on large width devices, especially for the multi-finger device with large Isat, place use
full contacts or  1/2 full contacts uniformly for channel width  1um (refer to CO.S.7® )

Use the recommendation from DFM rule CO.EN.1® regarding sufficient OD-to-contact enclosure.

The benefits of sufficient OD-to-contact enclosure are less variation of contact resistance and the
avoidance of potentially excessive drain or source leakage.


Use uniform poly and OD densities across a design.
The poly and OD densities in the neighboring area could affect the gate critical dimension. Although
the post-layout insertion of dummy OD, or dummy poly, or both, may patch some empty spaces, it is
best to avoid the problem with careful planning and space filling at the macro levels of layout design
initially. Please refer to these rules in the chapter of Dummy Pattern rule and Filling Guideline: “DOD
Rule“, “SR_DOD Rule”, “DPO Rule”, “SR_DPO Rule” and “Dummy Pattern Fill Usage Summary.” The
poly and OD densities in the neighboring areas could also affect device perfomance, not only gate
critical dimension. So, please avoid putting sensitive circuits near the region of too low/high poly/OD
density (refer to OD.DN.4® ~7® and PO.DN.4® ~7® ).
2. Be aware that thin oxide gate leakage of the 45 nm process is higher than that of previous
generations. Its impact on the functionality of a circuit, which uses thin oxide transistors and/or capacitors
and/or MOS varactors, must be taken into account by using a proper SPICE model that contains the
leakage components.
3. Pay attention to the leakage current for narrow-width devices with a low-Vt option.
Please consult the SPICE model for detailed information.
4. Device behavior is influenced by layout style possibly due to stress distribution induced by STI/OD
edge. Designers should take this length of OD (LOD) effect into consideration during device or cell level
design.
5. Avoid using asymmetrical or single source/drain CO placement on large devices (CO.R.5g).
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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6. For a PMOS device, if the NWELL is tied to the source used as an internal AC node, the NWELL
total area junction capacitance should be included in the circuit simulation by adding the Well
capacitance at the source node.
7. Take NWELL sheet resistance into consideration during simulation, to reflect the transient bias
variation by adding the Well resistance between source node and substrate node.
9.1.2.1.1
Improvement of poly CD uniformity
Further recommendation for improvement of poly CD uniformity (3-sigma) at small channel length:



Insert dummy PO surrounding existing PO gate if this PO gate is the nearest one to the cell
edge and follow the 1st poly space rule (PO.S.2). (S1, S3 in Figure 9.1.3)
For IP design

Add dummy PO/OD manually around sensitive circuits to avoid mismatch caused by layout
effect

Add dummy PO/OD by utility on whole IP to fill the remaining sparse area

Add a dummy PO/OD blockage the same size as the IP cell boundary.

Have dummy patterns in the blockage area as a default and verify with a library
characterization process.

Avoid any open area  1.8 um x 1.8um without any OD/PO patterns inside in the macro cell
area.
During chip integration, a placement blockage could be added on top of IP to avoid std cells
abutment with this IP, thus, there could be white space around IP without PO/OD.

To keep PO/OD pattern density uniformity, please use the dummy PO/OD utility again to insert
dummy PO/OD on the whole chip.
Core device PO gate
OD
S1
S2
S3
Have same parallel run length to
surrounded PO gate
Figure 9.1.3 Reduce sparse poly count

It is recommended placing the gate with uni-direction in a chip.

1nm CD gap is observed between horizontal and vertical poly lines.
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An empty area in the standard cell array is not allowed. Customers need to use a patterned
filler cell to insert the empty area of the standard cell array by P&R.

It is requested to have OD and PO patterns in the filler cell, which provides better gate CD
uniformity.

Need to put dummy PO firstly on sides of both cell edges with < 0.5μm space to nearby cell
edge. A space ( 0.1μm) to nearby cell edge is recommended.

Need to follow the layout rules of DRM.

Put OD and PO uniformly across the whole filler cell. Maximize the length of the OD and PO as
much as you can (to match the cell height). If the space is not enough, put PO first.

A rectangular PO pattern is recommended in the filler cell.

Dummy fillers of floating and fixed voltage are both acceptable from the process point of view.
However, the associated implant layers are a must if the filler cell is connected to a fixed
voltage.

It is also recommended to put a filler cell at the edges of standard cell arrays during P&R.
Figure 9.1.4 Example of filler cell
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
Guidelines for P&R during filler cell insertion at P&R:
o
Flow:
Document No.
Version
: T-N45-CL-DR-001
: 2.6
F lo o r p la n – p o w e r p la n a n d
h a r d m a c r o p la c e m e n t
B o u n d a r y f ille r c e lls
in s e r t io n
S ta n d a r d c e ll p la c e m e n t a n d
o p t im iz a t io n
I n t e r n a l f ille r c e lls
in s e r t io n
o
Layout with filler cells

Boundary filler cells


Before standard cell placement, inserting fillers on block boundary and macro
boundary for occupying the placement locations.
Internal filler cells

After standard cell placement, using original filler insertion command.
Figure 9.1.5 Layout with filler cells
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
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Device impact by CO placement
Asymmetric partial CO design will degrade Isat seriously on a large device (W>1um). LPE cannot
reflect every kind of CO placement layout style due to tool limitation, and will cause silicon slower than
simulation. It is recommended to use fully-CO or uniform-CO design.
 For the fully-CO design, it is recommended to add additional 1ohm R_probe_tip in the simulation
while certifying your IP.

For the asymmetry partial CO design, it is recommended to follow CO.S.7® , or add more design
margin.
S
S
F u lly -C O
S
G
G
D
9.1.2.1.3
S
S
G
D
U n ifo r m -C O
S
G
D
P a r tia l-C O
G
G
D
P a r tia l-C O
D
P a r tia l-C O
G
D
D
P a r tia l-C O
Device impact by local OD/PO density
Isat will increase as the local OD density decreases.
Isat will increase as the local PO density increases.

It is important to follow the layout guidelines for sensitive circuits to reduce the gap between
simulation and silicon. (OD.DN.4® ~7® and PO.DN.4® ~7® )
In the region of (sensitive IP sizing 20um):
OD density: 10~70%, PO density: 5~35%
Avoid abutting your IP to PO resistor, varactor, capacitor, large BJT, and SRAM, which easily leads
to OD density violation
Separate the MOM, capacitor and PO resistor in the IP properly, and insert DOD/DPO between
them
Avoid abutting your IP to MOM, varactor, capacitor, PO resistor, and large diode, which easily to PO
density violations

Wide OD guard rings need to have DPO in between.
It is important not to have a large DCAP surrounding the IP, or not to insert too many DCAPs in the
std cell array

Remove some DCAPs as the IP violates the PO density 35%

Only insert DCAP on the IR sensitive area. Use other filler cells if possible.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Avoid to place the IP close to IO and chip corner if possible

Increase the design margin, if it is unavoidable
In the region of (sensitive IP sizing 100um):
OD density: 20~70%, PO density: 15~35%
Keep your IP away from the Inductor, which easily leads to OD and PO density violations
It is recommended to keep enough space from the sensitive IP to varactor, PO resistor, large diode,
IO, and prime chip edge (hi OD%, low PO%)
9.1.2.1.4
Device impact by OSE/PSE
The DOD/DPO layout style also impacts the Isat

For the sensitive circuit, it is recommended to leave 4um space, and use the TSMCutility to insert
SR_DOD and SR_DPO uniformly surrounding the target device.

For the matching pair, it is recommended to insert with dummy devices with identical
shape/dimension/space surrounding the target device, and then insert the SR_DOD/SR_DPO and
DOD/DPO uniformly.
 Keep dummy device OD space close to 0.88um in W-direction and 0.1um in L-direction


If you can’t manually implement the recommendations (2nd PO space, OD space) for OSE/PSE,
please use TSMC dummy OD/PO insertion utility.
It is very important to use the TSMC utility to make your circuit design more robust.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
Version
Chip design flow
D M d u m m y u t i lit y
IP design flow
S c h e m a t ic s d e s ig n
C h ip H D L d e s i g n
P r e - la y o u t s im u la t i o n
R T L s y n t h e s is / P r e - la y o u t s im u la t io n
F in a l l a y o u t d e s i g n
P la c e & R o u t e l a y o u t
D P O / D O D D u m m y u t i li t y
D P O / D O D / D M D u m m y u t i lit y
D R C /LV S /L P E
D R C /LV S
R C E x tr a c tio n
R C E x tr a c tio n
P o s t - la y o u t s im u la t io n
S T A / P o s t - la y o u t s im u la t i o n
Ta p e -o u t
Ta p e -o u t
D O D /D P O
A n a lo g D e v ic e o r IP
(> 1 0 % )
(> 1 0 % )
1.
W ith o u t d u m m y d e v ic e s & D O D /D P O
2.
O n ly
s u rro u n d e d
by
dum m y
d e v ic e s ,
but
no
D O D /D P O
p ro te c t
3.
A n a lo g D e v ic e o r IP
s u r r o u n d e d w ith
d u m m y d e v ic e s
S R _ D O D /S R _ D P O
N o t r e c o m m e n d (S i to s im u la tio n g a p :)
(> 1 0 % )
: T-N45-CL-DR-001
: 2.6
Recom m end
Recom m end
(< 5 % )
(< 5 % )
IP s u r r o u n d e d
IP s u r r o u n d e d
w ith D O D /D P O
w ith d u m m y d e v ic e s
b y u p d a te d u tility
fir s t, th e n in s e r t
O n ly s u r r o u n d e d b y D O D /D P O , b u t n o S R _ D O D /S R _ D P O
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
D O D /D P O
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: T-N45-CL-DR-001
: 2.6
Resistors
1. For SPICE accuracy it is strongly recommended to put each OD/poly resistor in a dense area.
2. Avoid using small poly and OD width resistor that is critical in performance.
3. In order to have accurate interconnect RC for timing and power analysis, it is important to extract RC
after dummy metal insertion and extract RC with density based metal thickness variation feature enabled.
9.1.2.2.1
Unsilicided PO Resistor impact by local OD/PO density
It is important to follow the layout guidelines for unsilicided PO resistor to reduce the gap between simulation
and silicon.
PO resistor: OD.DN.8® , OD.DN.9® , PO.DN.8® , PO.DN.9® ,
9.1.3
Electrical Wiring
1. Avoid using minimum-width poly or OD where resistance is critical to the circuit performance.
2. Maintain uniform metal density to minimize wire sheet resistance variation.
3. Wherever possible, use two or more narrower metal buses to replace a single bus that uses the
maximum width.
4. Maintain metal density in the mid range of the specification, avoiding the two extreme ends.
5. During IP/macro design, it is important to put certain density margin to avoid the possibility of high density
violations (Mx.DN.1, Mx.DN.4, and Mx.DN.5) during placement. It may have unexpected violations during
the IP/macro placement due to the environment, even if the IP/macro already pass the high density rule
check. Therefore, you need to carefully design the dimensions of the width/space for wide metal (e.g.,
power/ground bus), under the proper high density limit.
6. Need dummy insertion in the library/IP/Macro blockage area:
Either extend hard macro boundary to align with blockage area or minimize the distance (recommended
 3 m) from the blockage edge to the macro cell boundary. Also embed this blockage region in
macro cell.
Have dummy patterns in the blockage area as a default and verify with the library characterization
process.
Need to re-define I/O pin for P&R at new macro cell boundary if you push out hard macro boundary to
align with blockage area.
Avoid any open area  3 m x 3 m without any metal patterns inside in the macro cell area .
9.1.4
Guidelines for Mask Making Efficiency
Please refer to the Chapter 3 sections:

“Design Geometry Restrictions”

“Design Hierarchy Guidelines”
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
9.2 DFM Recommendations and Guidelines
Summary
o
Please use the following advisory/recommended dimensions and guidelines whenever possible, unless
doing so impacts chip size or performance.
o
DFM does not have to comply to the advisory/recommendation value completely. Any change even by one
grid helps.
o
By using DFM recommendations and guidelines, higher precision of models, better reliability, lower timing,
process or yield variation may be expected.
o
If your circuit has concern about the DFM Action-Required rules (refer to the section of Action-Required
Rules) and Recommendations (refer to the section of Recommendations) TSMC DRC deck can help you
to flag the violations. DFM DRC deck is bundled in the TSMC logic DRC deck. The following 2 methods
can specify the region to run DFM recommendations in DFM DRC deck. Please also refer to the “User
Guide” in the DFM deck
1. Dummy layer:

RRuleRequire(CAD layer: 182;1): for the DFM Action Required recommendations.

RRuleRecommend(CAD layer: 182;2): for the DFM Recommended recommendations
2. Cell selection based on the following variables:

CellsForRRuleRequired

CellsForRRuleRecommended
9.2.1
Action-Required Rules
Using minimum dimension of the following rules may have influence on the electrical characteristics (e.g. Idsat)
of a related device. It is required that either the concerned influence be taken into account in a circuit electrical
design if a dimension is less than the advisory point, or the advisory value be used. In order to have precisely
CKT simulation, user needs to turn on the DFM-LPE (RC extraction tool, built in TSMC LVS released package
under the directory “DFM”) option for PO.EX.2® , PO.S.5® , PO.S.6® , to get the optimized device parameter.
Rule No.
PO.EX.2®
PO.S.5.LP®
PO.S.5.GS®
PO.S.6.LP®
PO.S.6.GS®
Description
Recommended OD extension on PO (full and symmetrical contact
placement are recommended at both source and drain side) to
avoid Isat degradation, especially for channel width > 1.5 μm.
When you use poly space = 0.16 um (PO.S.2), please use = 0.13
um for this recommendation.
Recommended space to L-shape OD when PO and OD are in the
same MOS (avoid corner rounding effect) for LP/LPG
Recommended space to L-shape OD when PO and OD are in the
same MOS (avoid corner rounding effect) for GS
Recommended L-shape PO space to OD when PO and OD are in
the same MOS (avoid corner rounding effect) for LP/LPG
Recommended L-shape PO space to OD when PO and OD are in
the same MOS (avoid corner rounding effect) for GS
Op.
Advisory
Min. Rule

0.13
0.09

0.1
0.03 (PO.S.4)

0.06
0.03 (PO.S.4)

0.1
0.04 (PO.S.6)

0.07
0.04 (PO.S.6)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: T-N45-CL-DR-001
: 2.6
Recommendations
Using minimum dimension of the following rules is okay. If a non-minimum recommendation is used, however,
the variation of the related electrical parameter (e.g. contact or via Rc) can be minimized and yield benefit may
be expected. It is recommended that the Recommendations be used wherever possible.
OD.DN.4® ~OD.DN.7® and PO.DN.4® ~7® are only checked within a dummy layer SENDMY for sensitive
circuit. SENDMY (255;8): DRC recognition layer for sensitive circuit
Rule No.
OD.W.1®
OD.S.1®
OD.DN.4®
OD.DN.5®
OD.DN.6®
OD.DN.7®
OD.DN.8®
OD.DN.9®
DOD.R.4®
SR_DOD.S.3®
SR_DOD.DN.1®
DNW.EN.1®
Description
Recommended
Recommended minimum interconnect OD width (except MOMDMY (155;21) region and

0.08
TCDDMY)
Recommended minimum OD space to reduce the short possibility caused by particle

0.1
It is not recommended the gate interact with the region of {(OD local density < 10%)
SIZING 20um}.
The definition of the gate is as follows:

10%
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND
RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(OD local density > 70%)
SIZING 20um}.
The definition of the gate is as follows:
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND

70%
RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(OD local density < 20%)
SIZING 100um}.
The definition of the gate is as follows:
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND

20%
RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 50umx50um, stepping 25um)
It is not recommended the gate interact with the region of {(OD local density > 70%)
SIZING 100um}.
The definition of the gate is as follows:
{(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND

70%
RODMY)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 50umx50um, stepping 25um)
It is not recommended the unsalicided poly resistor interact with the region of {(OD local
density < 20%) SIZING 100um}.
The definition of the unsalicided poly resistor is as follows:

20%
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY*)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 200umx200um, stepping 100um)
It is not recommended the unsalicided poly resistor interact with the region of {(OD local
density > 60%) SIZING 100um}.
The definition of the unsalicided poly resistor is as follows:

60%
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY*)}
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 200umx200um, stepping 100um)
It is important to use TSMC DOD/DPO utility to insert the SR_DOD and SR_DPO properly
surrounding your IP and circuit, and then do post-simulation carefully before chip
implementation.

DRC will flag the empty rectangle area larger than 1.8x1.8um2 inside
{(GATE SIZE 2.8) NOT (((OD OR DOD) OR SR_DOD) SIZE 0.12) NOT ((PO SIZE 0.05)
OR ((DPO OR SR_DPO) SIZE 0.03)) NOT ((NW SIZE 0.08) NOT (NW SIZE -0.08))}
(Except TCDDMY and SEALRING_ALL (162;2))
Recommended space to DPO, SR_DPO

Recommended minimum SR_DOD density inside {((((((OD OR PO) INTERACT GATE)
SIZING 2.5um) NOT ((OD OR PO) SIZING 0.4um)) NOT SRAMDMY;0) NOT OD2)} (The 
GATE doesn't include the regions covered by layer TCDDMY, CSRDMY, CDUDMY)
Recommended enclosure by NW for better noise isolation

Min Rule
0.06
0.08
-
-
-
-
-
-
1.8x1.8um2
-
0.05
0.03
8%
-
1.0
-
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Rule No.
NWROD.S.3®
NWRSTI.EN.2®
PO.W.1®
U
PO.S.1®
PO.S.2.LP®
PO.S.4.1®
PO.S.17®
PO.S.18.GS®
PO.EX.1®
PO.DN.4®
PO.DN.5®
PO.DN.6®
PO.DN.7®
PO.DN.8®
PO.DN.9®
SR_DPO.S.1®
SR_DPO.L.1®
SR_DPO.L.3®
SR_DPO.DN.1®
ESDIMP.EN.1®
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Recommended
Recommended RPO space to CO in NW resistor within OD for SPICE simulation accuracy =
0.3
Recommended OD enclosure of CO in NW resistor under STI for SPICE simulation
=
0.3
accuracy
Recommended minimum interconnect PO width

0.06
Recommended minimum interconnect PO space to reduce the short possibility caused by

0.12
particle
Recommended GATE space in the same OD to avoid Isat degradation for LP/LPG

Recommended gate space [L-shape OD and L-shape PO enclosed area < 0.0196 μm2] for

PO/OD rounding effect
Recommended Gate edge [channel length = 0.04um, channel width ≤ 0.2um] space to
{(PO OR SR_DPO) OR DPO } [width ≥ 0.12um] [projection in S/D direction], and Gate

edge parallel run length (individual projection) in the same gate ≥ 0.1um, for poly gate
CDU control
Recommend to add 2nd poly away from 1st poly [for channel length < 0.08μm] (DRC only
=
check 1st poly space to gate ≤ 0.2um and width < 0.08um)
Recommended extension on OD (end-cap) to avoid line-end shortening.

It is not recommended the gate interact with the region of {(PO local density < 5%) SIZING
20um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um

2. {(((Gate INTERACT SENDMY) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND
RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(PO local density > 35%)
SIZING 20um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um

2. {(((Gate INTERACT SENDMY) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND
RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(PO local density < 15%)
SIZING 100um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um

2. {(((Gate INTERACT SENDMY) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND
RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 50umx50um, stepping 25um)
It is not recommended the gate interact with the region of {(PO local density > 35%)
SIZING 100um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um

2. {(((Gate INTERACT SENDMY) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND
RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 50umx50um, stepping 25um)
It is not recommended the unsalicided poly resistor interact with the region of {(PO local
density < 15%) SIZING 100um}.
The definition of unsalicided poly resistor is as follows:

{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 200umx200um, stepping 100um)
It is not recommended the unsalicided poly resistor interact with the region of {(PO local
density > 40%) SIZING 100um}.
The definition of unsalicided poly resistor is as follows:

{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 200umx200um, stepping 100um)
Recommended space to {PO OR SR_DPO} (SR_DPO overlap with PO is not allowed)

Recommended length

Recommended maximum Length

Recommended minimum SR_DPO density inside {((((((OD OR PO) INTERACT GATE)
SIZING 2.5um) NOT ((OD OR PO) SIZING 0.4um)) NOT SRAMDMY;0) NOT OD2)} (The 
GATE doesn't include the regions covered by layer TCDDMY, CSRDMY, CDUDMY)
Recommended (OD NOT PO) enclosure of ESDIMP.
=
Min Rule
0.04
0.1
0.14
0.12 ~ 0.22 or
0.32
0.14
0.11
0.16
-
0.14~0.2
-
0.11
0.09
5%
-
35%
-
15%
-
35%
-
15%
-
40%
-
0.12
0.5
10
0.11
-
4%
-
0.4
0.4
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Rule No.
HVD_N25.R.5®
U
HVD_P25.R.5® U
HVD_N18.R.5® U
HVD_P18.R.5® U
HVD_GR.R.7® U
CO.S.3®
CO.EN.0®
CO.EN.1®
CO.EN.1.1®
CO.EN.3®
CO.S.7®
M1.S.1®
M1.A.1®
M1.EN.0®
M1.EN.1®
M1.EN.2®
M1.EN.5®
M1.DN.6®
VIAx.EN.0®
VIAx.EN.1®
VIAx.EN.2®
VIAx.R.8®
Mx.S.1®
Mx.A.1®
Mx.EN.0®
Mx.EN.1®
Mx.EN.2®
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Recommended
For better Idsat uniformity with single finger gate, HVD_N is recommended to be located
at the same side of the gate.
For better Idsat uniformity with single gate, HVD_P is recommended to be located at the
same side of the gate.
For better Idsat uniformity with single finger gate, HVD_N is recommended to be located
at the same side of the gate.
For better Idsat uniformity with single gate, HVD_P is recommended to be located at the
same side of the gate.
Recommend reducing the breach region of M1 on guard-ring if using M1 to connect HV
N/PMOS to outside circuits.
Recommended space to gate to reduce the short possibility caused by particle.

0.05
Recommended enclosure by OD is defined by {CO.EN.1® and CO.EN.1.1® }.
Recommended enclosure by OD to avoid high Rc.

0.03
Recommended enclosure by OD [at least two opposite sides]

0.04
Recommended enclosure by PO [at least two opposite sides] to avoid high Rc.

0.04
Maximum effective CO space in Source/Drain of device [channel width1 μm] (This
check doesn't include the regions covered by SR_ESD and SDI.)
Definition of effective CO: (1) CO projection space to GATE0.22 μm (D2). (2) {COs
INSIDE {HVD_N OR HVD_P}} which projection space to GATE 1 μm.
Definition of maximum effective CO space (B3): Channel width – effective CO projection

0.29
length to GATE.
Besides, if there is no CO in Source/Drain or no CO connected to Source/Drain by OD, it
is allowed. {CO OUTSIDE {HVD_N OR HVD_P}} projection space to PO (without CO
shielding) > 0.22 μm or {COs INSIDE {HVD_N OR HVD_P}} projection space to PO
(without CO shielding) > 1 μm for HVMOS drain side will be flagged on gate.
Recommended space to reduce the short possibility caused by particle

0.09
Recommended area to avoid high Rc (except DMx_O)

0.0351
Recommended enclosure of CO is defined by either M1.EN.1® or M1.EN.2® .
Recommended enclosure of CO to avoid high Rc

0.03
Recommended enclosure of CO [at least two opposite sides] to avoid high Rc

0.05
Recommended Enclosure of CO [metal width  0.11μm, space < 0.08μm] to avoid high Rc

(This check doesn't include two or more COs present in the metal intersection)
0.015
Min Rule
0.04
0.01
0.03
0.02
-
0.07
0.0215
0.00
0.03
0.015 [parallel
run length >
0.27 μm]
Recommend metal density  1% for IP level. Items (A) to (C) are recommended.
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm]  1%.
This item is applied for {IP NOT (IP SIZING -40um)} region when the width of IP is 
40um.
(B) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 1600um2, except the merged low
density windows width ≤ 30um. This item is applied for {IP NOT (IP SIZING -10um)}
region when the width of IP is  10um.
(C) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 4500um2. This item is applied for
{IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is
 20um for (A) and  5um for both (B)/(C).
Recommended enclosure by Mx or M1 is defined by either VIAx.EN.1® or VIAx.EN.2® .
Recommended enclosure by Mx or M1 to avoid high Rc.

Recommended enclosure by Mx or M1 [at least two opposite sides] to avoid high Rc.

Recommended maximum consecutive stacked VIAx layer, which has only one via for each
VIAx layer to avoid high Rc. (Except {LOWMEDN NOT (LOWMEDN SIZING -4 um)})
(Example: VIA1~VIA4, VIA2~VIA5, VIA3~VIA6, VIA4~VIA7. This rule does not apply to

top via. It is allowed to stack from VIA4 to VIA9 because VIA8 and VIA9 are top via. It is
allowed to stack more than four VIAx layers if two or more vias in each VIAx layer are on
the same metal.)
Recommended space to reduce the short possibility caused by particle

Recommended area to avoid high Rc (except DMx_O)

Recommended enclosure of VIAx-1 is defined by either Mx.EN.1® or Mx.EN.2® .
Recommended enclosure of VIAx-1 to avoid high Rc.

Recommended enclosure of VIAx-1 [at least two opposite sides] to avoid high Rc.

0.03
0.05
0.00
0.03
4
-
0.09
0.0351
0.07
0.027
0.03
0.05
0.00
0.03
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
382 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Rule No.
Mx.DN.6®
Mx.DN.7®
Mx.DN.8®
DMx.R.4® U
LOWMEDN.R.8® U
VIAy.EN.1®
VIAy.EN.2®
My.EN.0®
My.EN.1®
My.EN.2®
Mz.W.3®
Mr.W.3®
AP.W.2® U
MOM.DN.1®
IND.DN.8®
IND.DN.9®
IND_MD.DN.8®
IND_MD.DN.9®
ROM.R.2® U
ROM.R.3®
DTCD.DN.1®
ICOVL.S.1®
ICOVL.S.2®
ICOVL.S.3®
ICOVL.S.4®
ICOVL.S.5®
ICOVL.W.1®
ICOVL.W.2®
ICOVL.W.3®
ICOVL.W.4®
ICOVL.W.5®
Confidential – Do Not Copy
Document No.
Version
Description
Recommend metal density  1% for IP level. Items (A) to (C) are recommended.
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm] 
1%. This item is applied for {IP NOT (IP SIZING -40um)} region when the width of IP is
 40um.
(B) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 1600um2, except the merged low
density windows width ≤ 30um. This item is applied for {IP NOT (IP SIZING -10um)}
region when the width of IP is  10um.
: T-N45-CL-DR-001
: 2.6
Recommended
Min Rule
(C) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 4500um2. This item is applied for
{IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is
 20um for (A) and  5um for both (B)/(C).
It is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1
and Mx+2) over any 15um x 15um (stepping 15um) for IP level, i.e. it is allowed for either
one of Mx, Mx+1, or Mx+2 to have a local density ≥ 5%.
1. The metal layers include M1/Mx and dummy metals.
2. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding
region) is  7.5μm and for {IP NOT (IP SIZING -15um)} region when the width of IP is 
15um.
Total Mx island (for all Mx layers) density < 6.5E+04 ea/mm2 in whole chip
The definition of counts of small Mx island:
1. Mx width == 0.07um
2. Mx length  0.52um
3. Mx has two segments with space == 0.07um with the parallel run length (0.209 
parallel run length < 0.52)
It is important to insert the DMx & DVIAx uniformly to avoid white space. You should use
tsmc standard backend utility to insert the backend dummy pattern. The usage of
DMxEXCL needs to be minimized.
Recommend dummy metal is not inserted between protection rings or in the breach of
protection ring. Please use DMxEXCL to aviod dummy metal insertion.
Recommended enclosure by Mx or My to avoid high Rc.

Recommended enclosure by Mx or My [at least two opposite sides] to avoid high Rc.

Recommended enclosure of VIAy-1 is defined by either My.EN.1® or My.EN.2® .
Recommended enclosure of VIAy-1 to avoid high Rc.

Recommended enclosure of VIAy-1 [at least two opposite sides] to avoid high Rc.

Recommended Mz width [Mz on (((Mz-1 OR DMz-1) with space  5 um x 5 μm) SIZING 1

μm)] for CMP dishing concern.
Recommended Mr width [Mr on (((Mr-1 OR DMr-1) with space  5 um x 5 μm) SIZING 1

um)]
Recommended total width of BUS line [Connect with bump pad]

Recommend metal density inside {MOMDMY_n SIZING 10um}. (For M1/Mx layers)

Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY

Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY

Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY_MD

Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY_MD

Recommend to insert dummy PO between two ROM bits on different OD.
Each ROM cell must be covered by ROM(50;6).
DRC only flags no ROM(50;6) in the chip. But if there is no ROM cell in the chip, the
violation can be waived.
Density of DummyTCD (window 2000 μm X 2000 μm is one unit, see next page for more

information)
Recommend OVL_PO_OD space to OVL_CO_PO

Recommend space between two OVL_PO_ODs or two OVL_CO_POs

Recommend ICOVL (CAD layer no.: 165;3) space to {(OD OR PO) OR CO}

Recommend enclosed OD space inside OVL_PO_OD (maximum = minimum)
=
Recommend space between two COs for OVL_CO_PO [in the same ring]
=
Recommend width of PO ring inside ICOVL (maximum = minimum)
=
Recommend width of M1 ring inside OVL_CO_PO (maximum = minimum)
=
Recommend width of CO inside OVL_CO_PO (maximum = minimum)
=
Recommend width of {OD INTERACT PO} inside OVL_PO_OD (maximum = minimum)
=
Recommend PO hole width inside OVL_CO_PO (maximum = minimum)
=
0.045
0.075
0
0.045
0.045
0.075
0
0.045
0.42
0.40
0.55
0.50
16
30%
20%
15%
20%
15%
-
70%
-
40
2000
2
1.1
0.10
1.1
1.1
0.17
16.5
16.5
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
383 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Rule No.
ICOVL.EN.1®
ICOVL.EN.2®
ICOVL.R.2® U
ICOVL.R.3® U
ICOVL.R.4® U
ICOVL.R.5® U
ICOVL.R.6® U
ICOVL.R.7®
ICOVL.R.8®
ICOVL.R.9®
ICOVL.R.10®
ICOVL.R.11®
ICOVL.R.12®
ICOVL.R.13®
ICOVL.R.14®
ICOVL.R.15®
ICOVL.R.16®
ICOVL.R.17®
ICOVL.R.18®
ICOVL.R.19®
ICOVL.R.20®
ICOVL.R.21®
ICOVL.R.22®
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Recommended
Recommend {OD INTERACT PO} enclosure by PO inside OVL_PO_OD (maximum =
=
3.3
minimum)
Recommend M1 ring enclosure by PO ring inside OVL_CO_PO (maximum = minimum)
=
3.92
Recommend the ICOVL patterns should be as uniform as possible over the chip
Recommend at least 2 OVL_PO_ODs on top row (Floorplan A)/ right row (Floorplan B) by
(1) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for 1X1 die
(2) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 4 segments for 1X2 die
Recommend at least 2 OVL_CO_POs on top row (Floorplan A)/ right row (Floorplan B) by
(1) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for 1X1 die
(2) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 4 segments for 1X2 die
Recommend at least 1 OVL_PO_ODs on top row (Floorplan A)/ right row (Floorplan B) by
dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for 2X1 die
Recommend at least 1 OVL_CO_POs on top row (Floorplan A)/ right row (Floorplan B) by
dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for chip size for
2X1 die
Recommend at least 8 OVL_PO_ODs and 8 OVL_CO_POs for 1X1 die
Recommend at least 4 OVL_PO_ODs and 4 OVL_CO_POs for 1X2 die or 2X1 die
Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_PO_OD SIZING
+6500um}
Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_CO_PO SIZING
+6500um}
Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_PO_OD
SIZING +8000um}
Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_CO_PO
SIZING +8000um}
Recommend empty space between two OVL_PO_ODs for 1X1 die. DRC flags:

16000
{((Chip NOT OVL_PO_OD) SIZING -8000μm) SIZING +8000μm}
Recommend empty space between two OVL_CO_POs for 1X1 die. DRC flags:

16000
{((Chip NOT OVL_CO_PO) SIZING -8000μm) SIZING +8000μm}
Recommend empty space between two OVL_PO_ODs for 1X2 die or 2X1 die.
DRC flags:

13000
{((Chip NOT OVL_PO_OD) SIZING -6500μm) SIZING +6500μm}
Recommend empty space between two OVL_CO_POs for 1X2 die or 2X1 die.

13000
DRC flags:
{((Chip NOT OVL_CO_PO) SIZING -6500μm) SIZING +6500μm}
Recommend density of {(OVL_PO_OD SIZING +16500um) SIZING -15500um} for 1X1

25%
die
Recommend density of {(OVL_CO_PO SIZING +16500um) SIZING -15500um} for 1X1

25%
die
Recommend density of {(OVL_PO_OD SIZING +13000um) SIZING -10000um} for 1X2

25%
die or 2X1 die
Recommend density of {(OVL_CO_PO SIZING +13000um) SIZING -10000um} for 1X2

25%
die or 2X1 die
Recommend at least 1 OVL_PO_OD fully inside {Chip SIZING -2380um} for 2X2 die
Recommend at least 1 OVL_CO_PO fully inside {Chip SIZING -2380um} for 2X2 die
Min Rule
* CAD layer SENDMY (255;8) is used to check OD.DN.4® ~ OD.DN.9® for sensitive circuits. If your IP is sensitive to
the Isat variation due to low/high OD density, you can cover the SENDMY to perform this check.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
384 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
9.2.3
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Guidelines
The followings are guidelines regarding layout design practice, although they cannot be quantified. These
guidelines should be observed to their maximum in any circuit designs.
Rule No.
G.6gU
OPC.R.2gU
OD.L.2gU
SR_DOD.R.4gU
NW.R.1g
DNW.R.6gU
NWROD.R.3g
NWROD.R.8g
NWRSTI.R.3g
NWRSTI.R.4g
PO.L.1gU
RES.R.15g
RES.R.16g
RES.R.17g
RES.R.18g
RES.R.19g
RES.R.20g
CO.S.6g
CO.R.1gU
CO.R.5g
VIAx.R.9gU
VIAy.R.9gU
VIAz.R.5gU
VIAr.R.5gU
Mx.R.2gU
My.R.2gU
IND.R.15gU
Description
Label
For OD, PO, VTL_N, VTL_P, VTH_N, VTH_P, ULVT_N, ULVT_P, DCO_LPP, NP, PP, M1, Mx, My, all vertices
and intersections of 45-degree polygon must be on an integer multiple of 0.005 um except PO inside the layer
186;5 for GS/GL and 186;4 for LP/LPG.
Avoid small jogs (Figure 3.7.4).
It is recommended to use greater than, or equal to, half of the minimum width of each layer for each segment of
a jog.
It is strongly suggested to limit the max interconnect length (M) to be as short as possible to avoid high Rs
variation.
It is important to use the TSMC DOD/DPO utility to insert SR_DOD surrounding and close to the target device
before characterization. The range of the SR_DOD  4um.
Recommend not using unintentional floating well to avoid unstable device performance. DRC flags {NW
OUTSIDE {N+OD INTERACT CO}}.
Recommended not using floating RW unless necessary to avoid unstable device performance.
Recommended to use rectangle shape resistor for the SPICE simulation accuracy. DRC can flag {NWDMY
AND NW} is not a rectangle.
Recommend: NWDMY intersecting NWROD forms two or more NWs.
Recommended to use rectangle shape resistor for the SPICE simulation accuracy.
DRC can flag {NWDMY AND NW} is not a rectangle.
Recommend: NWDMY intersecting NWRSTI forms two or more NWs.
Recommend to limit the max interconnect PO length (R) as short as possible to avoid high Rs variation.
Recommended to use rectangle shape resistor for the SPICE simulation accuracy.
DRC can flag {((RH AND OD) AND RPO) AND RPDMY} or {((RH AND PO) AND RPO) AND RPDMY} which is
not a rectangle.
{RPDMY AND {{OD INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{OD
INTERACT CO} AND RPO}}, except BJTDMY.
{RPDMY AND {{PO INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{PO INTERACT
CO} AND RPO}}
Recommend: RPDMY intersecting {(OD AND RH) NOT INTERACT RPO} forms two or more ODs.
Recommend: RPDMY intersecting {(PO AND RH) NOT INTERACT RPO} forms two or more POs.
{CO BUTTED ((RPDMY AND RH) NOT INTERACT RPO)} is recommended.
Recommended to put contacts at both source side and butted well pickup side to avoid high Rs. DRC can flag
if the STRAP is butted on source, one of STRAP and source is without CO.
Recommended to put {CO inside PO} space to GATE as close as possible to avoid unexpected resistance
variation.
Recommend using redundant CO to avoid high Rc wherever layout allows
1. Recommended to use double CO or more on the resistor connection.
2. Double CO on Poly gate to reduce the probability of high Rc
3. For large transistor, if it is impossible to increase the CO to gate spacing (CO.S.3® ), limit the number of
source/drain CO: have the number of CO necessary for the current, and then spread them uniformly all over
the Source/Drain area.
4. DRC can flag single CO.
Recommend using redundant vias to avoid high Rc wherever layout allows. (Except {LOWMEDN NOT
(LOWMEDN SIZING -4 um)}) Please refer to section “Via Layout Recommendations”
Recommend using redundant vias to avoid high Rc wherever layout allows. Please refer to section “Via Layout
Recommendations”
Recommend using redundant vias to avoid high Rc wherever layout allows.. Please refer to section “Via Layout
Recommendations”
Op.
Recommend using redundant vias wherever layout allows.
For the small space, recommended to enlarge the metal space, by using Wire Spreading function of EDA tool,
to reduce the wire capacitance and the possibility of metal short. Please refer to section 9.1.1 and TSMC
Reference Flow.
For the small space, recommended to enlarge the metal space, by using Wire Spreading function of EDA tool,
to reduce the wire capacitance. Please refer to section 9.1.1 and TSMC Reference Flow.
Recommend putting NT_N to fully cover the inductor (metal) region to achieve high quality factor.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
385 of 600
Rule
SECURITY B – TSMC RESTRICTED SECRET
tsmc
9.2.4
No.
PO.EX.1®
PO.EX.2®
DNW.EN.1®
OD.W.1®
OD.S.1®
OD.DN.4®
OD.DN.5®
OD.DN.6®
OD.DN.7®
OD.DN.8®
OD.DN.9®
DOD.R.4®
NWROD.S.3®
SR_DOD.S.3®
SR_DOD.DN.1®
SR_DPO.S.1®
SR_DPO.L.1®
SR_DPO.L.3®
SR_DPO.DN.1®
NWRSTI.EN.2®
PO.W.1® U
PO.S.1®
PO.S.2.LP®
PO.S.4.1®
PO.S.5.LP®
PO.S.5.GS®
PO.S.6.LP®
PO.S.6.GS®
PO.S.17®
PO.S.18.GS®
PO.DN.4®
PO.DN.5®
PO.DN.6®
PO.DN.7®
PO.DN.8®
PO.DN.9®
ESDIMP.EN.1®
HVD_N25.R.5® U
HVD_P25.R.5® U
HVD_N18.R.5® U
HVD_P18.R.5® U
HVD_GR.R.7® U
CO.S.3®
CO.S.7®
CO.EN.0®
CO.EN.1®
CO.EN.1.1®
CO.EN.3®
M1.S.1®
M1.A.1®
M1.EN.0®
M1.EN.1®
M1.EN.2®
M1.EN.5®
M1.DN.6®
VIAx.EN.0®
VIAx.EN.1®
VIAx.EN.2®
VIAx.R.8®
Mx.S.1®
Mx.A.1®
Document No.
Version
Confidential – Do Not Copy
: T-N45-CL-DR-001
: 2.6
Grouping Table of Recommendations
1st priority to implement for yield and
performance enhancement
CMP
Systematic
Litho/OPC
Defect
Others
v
v
v
Simulation
Accuracy
v
v
v
v
v
v
v
v
v
v
v
v
v
v*
v
v
v
v*
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
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v
v
v
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
v
v
386 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
No.
Mx.EN.0®
Mx.EN.1®
Mx.EN.2®
Mx.DN.6®
Mx.DN.7®
Mx.DN.8®
DMx.R.4® U
LOWMEDN.R.8® U
VIAy.EN.1®
VIAy.EN.2®
My.EN.0®
My.EN.1®
My.EN.2®
Mz.W.3®
Mr.W.3®
AP.W.2® U
MOM.DN.1®
IND.DN.8®
IND.DN.9®
IND_MD.DN.8®
IND_MD.DN.9®
PO.S.14.GSm®
PO.S.14.LPm®
PO.EN.1.GSm®
PO.EN.1.LPm®
PO.EN.2.GSm®
PO.EN.2.LPm®
PO.EN.3.GSm®
PO.EN.3.LPm®
PO.S.5m®
PO.S.6m®
PO.S.6.1m®
PO.EX.1m®
BJT.R.2®
BJT.R.7®
DTCD.DN.1®
ICOVL.S.1®
ICOVL.S.2®
ICOVL.S.3®
ICOVL.S.4®
ICOVL.S.5®
ICOVL.W.1®
ICOVL.W.2®
ICOVL.W.3®
ICOVL.W.4®
ICOVL.W.5®
ICOVL.EN.1®
ICOVL.EN.2®
ICOVL.R.2® U
ICOVL.R.3® U
ICOVL.R.4® U
ICOVL.R.5® U
ICOVL.R.6® U
ICOVL.R.7®
ICOVL.R.8®
ICOVL.R.9®
ICOVL.R.10®
ICOVL.R.11®
ICOVL.R.12®
ICOVL.R.13®
ICOVL.R.14®
ICOVL.R.15®
ICOVL.R.16®
ICOVL.R.17®
Document No.
Version
Confidential – Do Not Copy
1st priority to implement for yield and
performance enhancement
CMP
v
v
v
Systematic
Litho/OPC
v
v
v
: T-N45-CL-DR-001
: 2.6
Defect
Others
Simulation
Accuracy
v
v
v
v
v
v*
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
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v
v
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v
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v
v
v
v
v
v
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v
v
v
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v
v
v
v
v
v
v
v
v
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v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
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v
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v
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v
v
v
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v
v
v
v
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The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
387 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
No.
ICOVL.R.18®
ICOVL.R.19®
ICOVL.R.20®
ICOVL.R.21®
ICOVL.R.22®
G.6gU
OPC.R.2gU
OD.L.2gU
SR_DOD.R.4gU
NW.R.1g
DNW.R.6gU
NWROD.R.3g
NWROD.R.8g
NWRSTI.R.3g
NWRSTI.R.4g
PO.L.1gU
RES.R.15g
RES.R.16g
RES.R.17g
RES.R.18g
RES.R.19g
RES.R.20g
CO.S.6g
CO.R.1gU
CO.R.5g
VIAx.R.9gU
VIAy.R.9gU
VIAz.R.5gU
VIAr.R.5gU
Mx.R.2gU
My.R.2gU
IND.R.15gU
ROM.R.2® U
ROM.R.3®
Confidential – Do Not Copy
1st priority to implement for yield and
performance enhancement
v
v
v
v
v
CMP
Document No.
Version
Systematic
Litho/OPC
v
v
v
v
v
v
v
: T-N45-CL-DR-001
: 2.6
Defect
Others
Simulation
Accuracy
v
v
v
v
v
v
v
v
v
v
v
v
v
v*
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
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v
v
v
v
v
v
v
v
M1.EN.0® : Recommended enclosure of CO is defined by either M1.EN.1® or M1.EN.2® .
VIAx.EN.0® : Recommended enclosure by Mx or M1 is defined by either VIAx.EN.1® or VIAx.EN.2® .
Mx.EN.0® : Recommended enclosure of VIAx-1 is defined by either Mx.EN.1® or Mx.EN.2® .
VIAy.EN.0® : Recommended enclosure by Mx or My is defined by either VIAy.EN.1® or VIAy.EN.2® .
My.EN.0® : Recommended enclosure of VIAy-1 is defined by either My.EN.1® or My.EN.2® .
*: For chip level.
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
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GDA Die Size Optimization Kit
Gross Die Advisor (GDA) is to optimize die size x-y for higher mask field utilization (MFU) and gross die
(GD) while keep chip area as constant.
The function of GDA is based on user input die size, scribe line width and TSMC generic fabrication
conditions to recommend a list of other die size combinations (X / Y) with higher gross die and MFU.
Based on GDA result, user can survey the advised numbers to adjust your die size in the early design
phase.
Use GDA function from TSMC on-line
 TSMC On-line Directory: Home/Design Portal 2.0/Technology Selection (GDA)/Gross Die Advisor
(MFU calculator)
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What is MFU?
Mask Field Utilization (MFU) is a ratio of mask utilized region which is calculated by (multiple die area+
scribe_line area) / (scanner maximum field area). (Fig. 9.3.1.1)
Low MFU implies low scanner productivity at whole lithography layers. It is important to improve MFU as
possible as you can. MFU > 80% is strong recommended.
Figure 9.3.1.1 Example of MFU
9.3.2


Before design:
 Square shape digital block and IP is preferable.
 For rectangle shape IP, provide 2 orientation types of the same IP with keeping core PO gate in
vertical direction. For example, left/right type IO and top/bottom type IO or horizontal and vertical
type IP shapes.
 Use “Quick MFU Calc” (download from reference flow package) in floorplan design phase.
 Avoid chip size at the borderline with low MFU, and it is strongly recommended to adjust the chip
dimension for higher MFU.
Design is at floorplan stage or floorplan is done:
 Core limited design: IP and blocks size and floorplan adjustment may be needed
 I/O limited design: I/O and interface IP adjustment may be needed
9.3.3

Design Guidelines for Higher MFU
Recommended GDA criteria MFU > 80%
The benefits from GDA:
 Based on the advised die sizes to adjust your chip dimension to gain high MFU and more gross die.
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MFU Reference Table for N45
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MFU Reference Table for N40
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10 Layout Guidelines for Latch-Up and I/O
ESD
This chapter consists of the following two sections:
10.1 Layout rules and guidelines for latch-up prevention
10.2 I/O ESD protection circuit design and layout guideline
Uses and Limitations of latch-up rules:
The Latch-up rules/guidelines are for design reference to achieve the target proposed by TSMC (JESD 78D).
There are no specification or guaranteed levels for final chip/product qualifications, since Latch-up immunity is
absolutely layout and circuit design dependent, including over-driven and substrate bias conditions, floating
body circuits, SCR ESD IPs, and so on. Therefore, product latch-up validation is must before mass production.
Also, note that these rules/guidelines do not cover the conditions such as power surge test, electrical fast
transient test, high-level current injection by inductance load, cable discharge event, transient Latch-up by
special function request or by system-level ESD test, etc.
Uses and Limitations of ESD guideline:
These ESD design guidelines are for reference only, and do not provide specification or guaranteed levels
of product performance and system level ESD. It is believed that ESD devices, which passed device-level ESD
testing, do not guarantee a particular circuit using that device will survive ESD qualifications. Product ESD
validation is must before mass production.
In addition to the dedicated ESD protection device, the final chip/product ESD levels depend on the follows:
1. The normal functional devices in parallel (whose immunity and gate bias during ESD rely on the specific
circuit design),
2. The power clamp protection cell/network, interface, the separation of high (Vdd, Vcc) and low (Vss, GND)
power supply pads/groups,
3. The floor plan/metal bus routing and current density (endurance) of the backend interconnection's design.
Note that TSMC won't review the customer's chip design, so TSMC can not guarantee the customer's success.
Also, product ESD validation is must before mass production.
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10.1
Layout Rules and Guidelines for Latch-up
Prevention
10.1.1
Latch-up Introduction
In explaining the Latch-up, the equivalent circuit of the parasitic components of CMOS inverter is shown in
Figure 10.1.1.1. When the signal at the output node is 0.7V higher than the Vdd (overshooting), the bipolar
VT2 may be turned on first and, similarly, the bipolar LT2 will be turned on while the output signal is lower
than –0.7V (undershooting). For the fact that the collector of each BJT (i. e. Vt2) plays the role as base of the
other transistor (i. e. LT2) and the collected carriers will reduce the potential difference between emitter and
base of the transistor (LT2). Under this situation, the LT2 may be turned on and the collect current of the LT2
will feedback to VT2 at the same time. The positive feedback loop will make the concentration of minority
carrier increased to higher than the doping concentrations of both the NW and PW (Figure 10.1.1.2).
Subsequently, the potential barrier between NW and PW will be disappeared and then obtains a highly
conductivity path between Vdd and Vss. This may result in the circuit malfunction, and destroy the device in
the worst case.
Vin
Vout
Vss
P+
N+
Vdd Overshoot
Vdd
0V
undershoot
N+
P+
P+
N+
NW
PW
RpW
RNW
LT1
LT2
VT2
VT1
P-sub
Fig. 10.1.1.1 Lump element model for an inverter before latch-up
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N+
zzzzz
N+zzzzz
zzzzz
zzzzz
zzzzz
zzzzz
NW
zzzzz . .
zzzzz
PW
.
.
yc
o
re n d u
gi
on ctiv
ity
P+
av
a.
P+
zzzzz
b.
N+
zzzzz
P+
zzzzz
zzzzz
zzzzz
zzzzz
zzzzz
.
zzzzz
zzzzz.
. zzzzz
.
.
He
N+
P+
Fig. 10.1.1.2 Hole concentration (a) before latch-up, (b) after latch-up
The latch-up trigger sources often come from the IO Pad, but both IO circuits and internal circuits might cause
a latch-up if the layout does not follow the latch-up design rules. The following lists the latch-up failure cases
caused by layout rule violations.
Fig. 10.1.1.3 LUP.1 rule violation: (IO without guard-ring)
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Fig. 10.1.1.4 LUP.2 rule violation:
(Within 15um from IO, N/PMOS in the internal circuit without the guard-ring)
Fig. 10.1.1.5 LUP.3 rule violation: (IO N/PMOS spacing is too small)
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10.1.2
Layout Rules and Guidelines for Latch-up
Prevention
10.1.2.1
Special Definition in Latch-up Prevention
Term
Definition
I/O pads
Internal circuit
Guard-ring
N+ guard-ring
P+ guard-ring
Guard-band
N+ guard-band
P+ guard-band
NMOS cluster
PMOS cluster
OD injector
Core MOS/OD injector
1.5V/1.8V MOS/OD
injector
2.5V MOS/OD injector
3.3V MOS/OD injector
5V MOS/OD injector
Do not include Vdd pad and Vss pad.
Include NMOS, PMOS, de-coupling capacitors and varactor that do not connect to an IO pad.
Complete un-broken ring-type OD and M1 with CO as many as possible, connected to Vdd or
Vss.
Complete un-broken ring-type (NP AND OD) and M1 with CO as many as possible,
connected to Vdd.
Complete un-broken ring-type (PP AND OD) and M1 with CO as many as possible, connected
to Vss.
Band-type OD and M1 with CO as many as possible, connected to Vdd or Vss.
Band-type (NP AND OD) and M1 with CO as many as possible, connected to Vdd.
Band-type (PP AND OD) and M1 with CO as many as possible, connected to Vss.
A group of NMOSs
A group of PMOSs
Any OD directly connected to I/O pad. Ex. MOS, HIA diode, diode string (DRC uncheckable),
OD resistor, and well resistor directly connected to I/O PAD.
N+ OD directly connected to I/O pad is N+ OD injector.
P+ OD directly connected to I/O pad is P+ OD injector.
MOS/OD injector NOT INTERACT OD2
(MOS/OD injector INTERACT (OD_18 OR OD25_18) NOT INTERACT (HVD_N OR HVD_P))
((MOS/OD injector INTERACT OD_25) NOT INTERACT (OD25_18 OR OD25_33) NOT
INTERACT (HVD_N OR HVD_P))
MOS/OD injector INTERACT (OD_33 OR OD25_33)
MOS/OD injector INTERACT ((HVD_N OR HVD_P) OR DEHVD_N)
P+ guard-ring
N+ guard-ring
NMOS
NMOS
PMOS
PMOS
NMOS
NMOS
PMOS
PMOS
NMOS cluster: A group of NMOSs
PMOS cluster: A group of PMOSs
Fig. 10.1.2.1 Example of an NMOS cluster and a PMOS cluster
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Latch-up Dummy Layers Summary
10.1.2.2.1 LUPWDMY Dummy Layer (CAD layer: 255;1)
LUPWDMY is a dummy layer to waive these rules, LUP.1, LUP.2, LUP.3.1.1~2, LUP.3.2.1~2, LUP.3.3.1~2,
LUP.3.4.1~2, LUP.3.5.1~2, LUP.4, LUP.5.1.1~2, LUP.5.2.1~2, LUP.5.3.1~2, LUP.5.4.1~2 and LUP.5.5.1~2.
Condition:
It is not recommended to use this layer before silicon is proven at the package.
Please consult TSMC if you would like to follow it as rules and have DRC violations before tapeout.
Usage:
Draw LUPWDMY to fully cover OD injector, including the source, gate, drain, and diode, but not
necessarily to cover Well STRAP, guard-ring.
It is for DRC usage but not a tapeout required CAD layer.
NP/PP
OD
LUPWDMY
Source
PO
Drain
Guard ring
Fig. 10.1.2.2.1 Example of LUPWDMY
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10.1.2.2.2 LUPWDMY_2 Dummy Layer (CAD layer: 255;18)
“LUPWDMY_2 (255;18)” is a DRC dummy layer to trigger the area I/O latch-up rules check.
Please refer to 10.1.2.5 for detailed AAIO I/O latch-up rule introduction.
Usage:
Draw a LUPWDMY_2 pattern to fully cover the OD injector of the area IO cells, including the source, gate,
drain, and diode. However it is not necessary to cover the Well STRAP, or guard-ring.
P+ pick-up ring
OD
PO
N+ active
NP
PP
LUPWDMY_2 (255; 18) needs to cover AAIO OD injector
Figure 10.1.2.2.2 Example of LUPWDMY_2 Usage
10.1.2.2.3 RES200 Dummy Layer (CAD layer: 255;9)
RES200 is a DRC dummy layer and is used to recognize a resistor with resistance larger than 200 ohm. If the
resistance of used resistors between PAD and the OD injector is larger than 200 ohm, the dummy layer
RES200 (255;9) should be covered on the resistor.
 Latch-up rules’ checking connection will be broken by resistors with RES200 layers.
RES200
RES200
Poly RES.
RPDMY
Poly RES.
RPDMY
Figure 10.1.2.2.3
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DRC methodology for Latch-up Rules
10.1.2.3.1 Overview
The critical point in correctly checking lathcup design rules is to accurately recognize OD injector (OD directly
connected to I/O PAD) and VDD/VSS PADs (for potential parasitic SCR [silicon-controlled rectifier] path). With
additional designer input, the accuracy may be improved with the use of optional DRC switches, dummy
layerers, and/or pin texts.
Section 10.1.2.3 covers different aspect of DRC methodology in its sub-sections. They are:
(1)
10.1.2.3.2 General DRC methodology for PAD type
This covers how DRC deck is able to recognize different PAD types (VDD/VSS/IO).
(2)
10.1.2.3.3 General DRC methodology for I/O pad connectivity
This covers how OD injector is recognized with the use of resistor connecting to I/O PAD. RES200
usage and LUP DRC switch for resistor is covered.
(3)
10.1.2.3.5~10.1.2.3.8 DRC methodology for LUP.x
These sub-sections cover DRC methodology for selected LUP design rules.
10.1.2.3.2 General DRC methodology for PAD type
DRC use the following features to distinguish Power and I/O PAD:
1. By default, DRC will recognize power PAD according to the connectivity of AP, CB, CB2, and UBM to
STRAP (except VAR, NW resistor).
2. DRC will also recognize PAD with “power dummy layer” as power PAD.
I.
VDDDMY(255;4): Dummy Layer for Power(Vdd) PAD
II.
VSSDMY(255;5): Dummy Layer for Ground(Vss) PAD
3. Alternatively, with corresponding DRC switch turned-on manually, DRC will recognize PAD with
“power text” as power PAD.
I.
Control by the switch of #DEFINE_PAD_BY_TEXT. The switch is off by default.
II.
Default power text name is “VDD?” “VSS?”
4. All other unrecognized PADs through step 1~3 are I/O PAD.
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OD
OD
VDDDMY
PO
IO
PAD
VDD
PAD
Metal
Metal
PO
Metal
Metal
OD
OD
PO
VDD
PAD
PO
NW strap
Metal
Metal
Metal
VSS Metal
VSS
Metal
PAD
“VSS” is a top level text attached on metal, and
DEFINE_PAD_BY_TEXT option is turned on in DRC
OD
PO
PAD
Metal
Metal
Check LUP.1~5 in Cell level without PAD
1. Attach top-level text on metal. E.g. “PAD”
2. Turn on DEFINE_PAD_BY_TEXT option.
Figure 10.1.2.3.2
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10.1.2.3.3 General DRC methodology for I/O pad connectivity

DRC use the following features to check the device connectivity to I/O pad (OD injector recognition):
1.
Build-up the connection by Metal, Via, RV, AP, CB, CB2, and UBM
2.
Latch-up risk of the junction/OD connects to pad through a resistor:
a. If R >= 200 ohm.  low latch-up risk (as internal circuit)
b. If R <= 50 ohm. High latch-up risk (as OD injector)
c. If 50ohm <R<200ohm design dependent..
RES200 CAD layer is required for recognizing the resistance. If R>200 ohm, the dummy layer
RES200 (255:9) should cover the resistor to disable LU check (because latch-up risk is low).
3.
There are two DRC switches and one required CAD layer (RES200 layer) related to the resistor in
series: "DISCONNECT_ALL_RESISTOR" (1st DRC switch; default OFF),
"CONNECT_ALL_RESISTOR" (2nd DRC switch; default OFF), and RES200 CAD layer (manually
placed).
Only one of the "DISCONNECT_ALL_RESISTOR" and "CONNECT_ALL_RESISTOR" can be
turned ON when in actual use or both DRC switches should be OFF (default). If both DRC switch are
turned ON, "DISCONNECT_ALL_RESISTOR" will now be the override setting (LUP.WARN.1).
Below are possible scenarios for their interactions in between:
1. Consider resistance (default) to recognize circuits behind resistor:
(R<200ohm) => Set both switches to OFF and W/O RES200, circuits after resistor will be
recognized as OD injector.
(R>=200ohm) => Set both switches to OFF and the R>=200ohm resistor is covered by RES200
layer, circuits after resistor will NOT be checked
2. Neglect circuits behind resistor
 Set "DISCONNECT_ALL_RESISTOR" to ON, all circuits after resistor will NOT be recognized
as OD injector (RES200 layer is irrelevant this scenario.)
3. Check circuits behind resistor
 Set "CONNECT_ALL_RESISTOR" to ON, all circuits after resistor will be recognized as OD
injector (RES200 layer is irrelevant this scenario.)
A
RES200
OD
B
OD
C
OD
PO
RES.
PO
IO
PAD
RPDMY
Metal
PO
RES.
RPDMY
Figure 10.1.2.3.3
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Table 10.1.2.3.3
DRC deck setup
A/B/C in Fig. 10.1.2.3.3
Default
Turn ON
Turn ON
OD injector or Internal (DISCONNECT_ALL_RESISTOR: OFF)
DISCONNECT_ALL_RESISTOR CONNECT_ALL_RESISTOR
circuit
(CONNECT_ALL_RESISTOR: OFF)
A
B
C
OD injector
Internal circuit
OD injector
OD injector
Internal circuit
Internal circuit
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whole or in part without prior written permission of TSMC.
OD injector
OD injector
OD injector
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10.1.2.3.4 DRC methodology for LUP.1
DRC use the following features to find out the devices for LUP.1:
OD injector means that any OD is directly connected to I/O pad.
Ex. MOS, STI diode (STI bonded), OD resistor, and well resistor directly connected I/O PAD.
1. The following cases is excluded :
I.
The OD injector is covered by LUPWDMY (255;1).
2. The guard ring can not be shared by different type devices.
10.1.2.3.5 DRC methodology for LUP.2
DRC use the following features to find out the devices for LUP.2:
1. The MOS OD within 15um space from OD injector for LUP.1 check
2. The following cases are excluded:
I.
The MOS OD is floating without any contact over gate and S/D.
II.
The OD injector is covered by LUPWDMY (255;1)
III.
The NMOS is inside DNW, and the NW over DNW is not the same as the NW of relative PMOS,
but these two NWs are connected.
M1
III.
NW
DNW
NMOS
PMOS
Fig. 10.1.9 example of LUP.2 III
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10.1.2.3.6 DRC methodology for LUP.3 group
DRC use the following features to find out the devices for LUP.3 group:
1. Find out the OD injector for LUP.1 check
2. The following cases are excluded:
I.
The excluded case in LUP.1.
II. The NMOS is inside DNW, and the NW over DNW is not the same as the NW of relative PMOS,
but these two NWs are connected.
10.1.2.3.7 DRC methodology for LUP.4
DRC use the following features to check the guard-ring width.
1. Find out the OD injector for LUP.1 and LUP.2 check.
2. The devices should be placed inside a complete guard-ring with width ≥ 0.12um.
Fail
Fail !
≥ 0.12um
! OD
≥ 0.12um
NW
OD
PMOS
PMOS NW
< 0.12um
Pass
Pass
!
OD
≥ 0.12um
< 0.12um
≥ 0.12um
!
≥ 0.12um
OD
PMOS
PMOS
NW
PMOS
PMOS
NW
Fig. 10.1.10 example of LUP.4
10.1.2.3.8 DRC methodology for LUP.5 group
DRC use the following features to find out the devices for LUP.5 group:
1. Find out the OD injector for LUP.1 and LUP.2 check.
2. The excluded cases are “I”, “II”, and “III” in LUP.2.
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Layout Rules and Guidelines for Latch-up
Prevention
The LUP rules are for design reference to achieve the specifications proposed by TSMC. They are
extracted by the standard digital I/O and Area I/O test structures. Note that Latch-up free can not be
guaranteed for all applications such as substrate bias condition, floating body circuits, SCR ESD IPs, and etc.
You can refer to section 10.1.2.3 to understand DRC methodology for Latch-up Rules in detail.
For 5V application, the DRC only check the related latch-up for 5V HVMOS device. Please see section
10.1.2.1 for details.
All pickup ring, gurad ring, and straps described in TSMC LUP rules are required to have appropriate
direct connection to corresponding VDD/VSS with minmum resistance. If any pickup ring, gurad ring, and
straps does not have proper connection and with minimum connection resistance, LUP risk may rise
significantly.
Rule No.
Description
Label
Op.
Rule
A
A
≥
≥
2
3
A
A
≥
≥
2.3
4
A
A
≥
≥
2.6
5
A
≥
4
DRC LUP switch setting conflict detected (refer to section 10.1.2.3.3 for details):
LUP.WARN.1
LUP.1
LUP.2
LUP.2.1U
LUP.3.0
LUP.3.1.0
LUP.3.1.1
LUP.3.1.2
LUP.3.2.0
LUP.3.2.1
LUP.3.2.2
LUP.3.3.0
LUP.3.3.1
LUP.3.3.2
LUP.3.4.0
LUP.3.4.1
Please follow one of the following LUP switch settings:
1. [Default setting: RES200 usage] Turns off both "DISCONNECT_ALL_RESISTOR", and
"CONNECT_ALL_RESISTOR": circuits after RES200 will NOT be recognized as OD injector, or
2. Turns on "DISCONNECT_ALL_RESISTOR" only: circuits after any resistor will NOT recognized as OD
injector, or
3. Turns on "CONNECT_ALL_RESISTOR" only: circuits after any resistor will always be recognized as OD
injector
Please DO NOT turn on both "DISCONNECT_ALL_RESISTOR", and "CONNECT_ALL_RESISTOR" at the same
time, otherwise “DISCONNECT_ALL_RESISTOR” will have higher priority
Any N+ OD injector or an N+ OD injector cluster must be surrounded by a P+ guard-ring. (Figure 10.1.2.4.1)
Any P+ OD injector or a P+ OD injector cluster connected to an I/O pad must be surrounded by a N+ guard-ring.
(Figure 10.1.2.4.1)
Please also refer to LUP.9g for further information.
Within 15um (≤15um) space from the OD injector, a P+ guard-ring is required to surround an NMOS or an NMOS
cluster. And an N+ guard-ring is required to surround a PMOS or a PMOS cluster. (Figure 10.1.2.4.3 and 10.
1.2.4.5)
Rule exclusion: LUP.2 does not apply to NMOS in DNW if both of the following conditions are true (Fig.
10.1.2.4.2):
1. NMOS is inside DNW with voltage (Va) ≥ PMOS NW voltage (Vb).
2. NMOS DNW doesn’t physically interact with PMOS NW.
However, DRC can only flag the different connection.
Within 15um (≤15um) space from the OD injector, a NW in proximity to another NW with different potential and one
P+OD was enclosed by the relative higher potential NW, a P+ STRAP is required to be inserted between these
NWs. (Figure 10.1.2.4.5)
LUP.3.x can be exempted from the following conditions (Figure 10.1.2.4.2):
1. NMOS is inside DNW with voltage (Va) ≥ PMOS NW voltage (Vb)
2. NMOS DNW doesn’t physically interact with PMOS NW.
However, DRC can only flag the different connection.
In LUP.3.1.1 and LUP.3.1.2 for the N/PMOS which connects to an I/O pad, space between the core PMOS and the
NMOS. (Figure 10.1.2.4.1),
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1)
In LUP.3.2.1 and LUP.3.2.2, for the N/PMOS which connects to an I/O pad directly, space between the 1.8V/1.5V
PMOS and the NMOS. (Figure 10.1.2.4.1)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1)
In LUP.3.3.1 and LUP.3.3.2, for the N/PMOS which connects to an I/O pad directly, space between the 2.5V
PMOS and the NMOS. (Figure 10.1.2.4.1)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1)
In LUP.3.4.1 and LUP.3.4.2, for the N/PMOS which connects to an I/O pad directly, space between the 3.3V
PMOS and the NMOS (Figure 10.1.2.4.1)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Rule No.
Description
LUP.3.4.2
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1)
In LUP.3.5.1 and LUP.3.5.2, for the N/PMOS which connects to an I/O pad directly, space between the 5V PMOS
and the NMOS. (Figure 10.1.2.4.1)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1)
Width of the N+ guard-ring and P+ guard-ring for the OD injector, and also MOS within 15um space from the OD
injector. (e. g. width of guard-ring of LUP.1 and LUP.2) (Figure 10.1.2.4.1)
LUP.3.5.0
LUP.3.5.1
LUP.3.5.2
LUP.4
Label
Op.
Rule
A
≥
8
A
A
≥
≥
10
15
B
≥
0.12
C
C
≥
≥
2
3
C
C
≥
≥
2.3
4
C
C
≥
≥
2.6
5
C
C
≥
≥
4
8
C
C
≥
≥
10
15
C1
C1
C1
≥
≥
≥
6
10
15
C1
≥
20
D
≤
30/40
E1
E1
E1
≥
≥
≥
6
10
15
E1
≥
20
LUP.5.x (except LUP.5.6.x) can be exempted from the following conditions (Figure 10.1.2.4.2):
LUP.5.0
LUP.5.1.0
LUP.5.1.1
LUP.5.1.2
LUP.5.2.0
LUP.5.2.1
LUP.5.2.2
LUP.5.3.0
LUP.5.3.1
LUP.5.3.2
LUP.5.4.0
LUP.5.4.1
LUP.5.4.2
LUP.5.5.0
LUP.5.5.1
LUP.5.5.2
LUP.5.6.0U
LUP.5.6.1U
LUP.5.6.2U
LUP.5.6.3U
LUP.5.6.4U
LUP.6
LUP.7.6.0U
LUP.7.6.1U
LUP.7.6.2U
LUP.7.6.3U
LUP.7.6.4U
LUP.9gU
1.
NMOS is inside DNW with voltage (Va) ≥ PMOS NW voltage (Vb)
2. NMOS DNW doesn’t physically interact with PMOS NW.
However, DRC can only flag the different connection.
In LUP.5.1.1 and LUP.5.1.2 for the internal circuits within 15um space from OD injector,
(1) space between the N+OD injector and the core PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the core P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
In LUP.5.2.1 and LUP.5.2.2 for the internal circuits within 15um space from OD injector,
(1) space between the N+OD injector and the 1.8V/1.5V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 1.8V/1.5V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
In LUP.5.3.1 and LUP.5.3.2 for the internal circuits within 15um space from OD injector,
(1) space between the N+OD injector and the 2.5V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 2.5V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
In LUP.5.4.1 and LUP.5.4.2 for the internal circuits within 15um space from OD injector,
(1) space between the N+OD injector and the 3.3V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 3.3V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
In LUP.5.5.1 and LUP.5.5.2 for the internal circuits within 15um space from OD injector,
(1) space between the N+OD injector and the 5V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 5V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
if all of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2)
Space between the P+ OD injector and NW if the P+ OD injector in proximity to another NW are in different
potential, (low potential related to P+ OD injector) need to follow LUP.5.6.1U ~4U:
The guard ring and STRAP width between P+ OD injector and NW should be as larger as possible. (Figure
10.1.2.4.3)
If the voltage potential difference is > 0V, and ≤ 1.8V
If the voltage potential difference is > 1.8V, and ≤ 2.5V
If the voltage potential difference is > 2.5V, and ≤ 3.3V
If the voltage potential difference is > 3.3V, and ≤ 5V
Please consult TSMC if the voltage potential difference is > 5V.
1.
Any point inside NMOS source/drain {(N+ ACTIVE INTERACT PO) NOT PO} space to the nearest PW
STRAP in the same PW. (Figure 10.1.2.4.4)
2.
Any point inside PMOS source/drain {(P+ ACTIVE INTERACT PO) NOT PO} space to the nearest NW
STRAP in the same NW. (Figure 10.1.2.4.4)
In SRAM bit cell region, the rule is relaxed from 30um to 40um.
[In logic region/ In SRAM bit cell region]
For the NW and PMOS within 15 μm space from OD injector,
space between the P+ OD of PMOS and NW if the P+ OD in proximity to another NW are in different potential,
(low potential related to P+ OD) need to follow LUP.7.6.1U ~4U.(Figure 10.1.2.4.5)
If the voltage potential difference is > 0V, and ≤ 1.8V
If the voltage potential difference is > 1.8V, and ≤ 2.5V
If the voltage potential difference is > 2.5V, and ≤ 3.3V
If the voltage potential difference is > 3.3V, and ≤ 5V
Please consult TSMC if the voltage potential difference is > 5V.
Additional one N+ STRAP and one P+ STRAP are required to be inserted between the P+ guard-ring and N+
guard-ring for LUP.1 (Figure 10.1.2.4.1).
1.
NW STRAP should isolate the PW STRAP and the P+ guard-ring (P+ pick-up ring).
2.
PW STRAP should isolate the NW STRAP and the N+ guard-ring (N+ pick-up ring).
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Vss
Document No.
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: 2.6
Vdd
A
N+
P+
N+
P+
NMOS
PW
P+ guard-ring
N+
P+
STRAP
STRAP
NW
PW
N+
P+
P+
N+
PMOS
NW
N+ guard-ring
P+ guard-ring (Vss)
N+ guard-ring (Vdd)
B
B
B
B
N+
P+
STRAP
STRAP
(Vdd)
(Vss)
NMOS
PW
NW
To exchange N+ STRAP and P+ STRAP not recommended (LUP.9g U)
Figure 10.1.2.4.1
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If the NW of the checked
PMOS interacts with the
DNW, the space needs to
follow A or C.
NW
DNW
: T-N45-CL-DR-001
: 2.6
NMOS
A
A
C
C
PW
PMOS
PMOS
If voltage Va ≥ Vb,
the space can be < A or < C
Va
Vb
NW
NW
DNW
PW
P+
STRAP
NMOS
PMOS
N+STRAP
N+STRAP (N+ guard ring)
Vb
Vb
Guard ring is not necessary Va ≥ Vb,
but P+ STRAP is still required.
Va
Vd
P+
PW
N+
P+
NW
P+
N+
PW
N+
d
NW
N+
N+
P+
N+
NW
PW
Guard ring Guard ring and P+ STRAP
DNW
follow A or C.
Guard ring and P+ STRAP are
necessary ifLUP.3.4.1~2,
Va >= Vb. LUP.3.5.1~2, LUP.5.1.1~2,
For LUP.2, LUP.3.1.1~2, LUP.3.2.1~2,not
LUP.3.3.1~2,
LUP.5.2.1~2, LUP.5.3.1~2, LUP.5.4.1~2, LUP.5.5.1~2, if voltage Va ≥ Vb, the above rules allow that
the NMOS is enclosed by a DNW and the NW of the checked PMOS does not interact with the DNW.
However, DRC can only flag the different connection.
Figure 10.1.2.4.2
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P+ guard-ring Vss
Voltage potential is lower than P+ OD injector
NW
C1
B
≤15um
C
B
B
B
N+guard-ring(Vdd)
P+ guard-ringVss)
P+ guard-ringVss)
N+guard-ring(Vdd)
N+guard-ring(Vdd)
P+ strap(Vss)
N+ strap(Vdd)
P+ guard-ringVss)
A
B
B
B
B B
C
Active connects to IO pads directly
Internal circuit
Figure 10.1.2.4.3 Latch-up prevention design for LUP.3.x, LUP.4, LUP.5.x
D
D
N+ S TRAP
D
N+ S TRAP
D
Nwell
P + S TRAP
P+ STRAP
Pwell
N+ S TRAP
N+ S TRAP
Nwell
P+ STRAP
P + S TRAP
P+ OD
Pwell
Figure 10.1.2.4.4 Latch-up prevention design for LUP.6
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whole or in part without prior written permission of TSMC.
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15um
PMOS
N+ guard ring
NW
PW
P+ guard ring
PMOS
N+ guard ring
E1
NW
PW
NMOS
P+ guard ring
NW
15um
OD
Injector
15um
Figure 10.1.2.4.5 Latch-up prevention design for LUP.2, LUP.2.1, and LUP.7.6.x
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Layout Rules and Guidelines for Area I/O(AAIO)
Latch-up Prevention
To increase the number or density of I/Os in VLSI designs, the area-I/O(AAIO) is adopted to achieve a smaller package
size (such as flip-chip), shorter wire length, better signal and power integrity. However, an external injection of minority
carriers from an Area IO cell can trigger a latchup event easily in the parasitic pnpn path of the surrounding CMOS circuits
in the chip’s core area. The Area I/O cell is different from the peripheral type I/O ring (example Fig.10.1.20), it does not
have pre-driver structure between the post driver (carrier injector) and the core CMOS circuits, which can help absorb the
substrate currents or carriers from an external injection. The AAIO latch-up rules need to be applied to the IO cells put in
chip center and next to internal circuit as shown in Fig. 10.1.2.5.1 and Fig 10.1.2.5.2, Fig 10.1.2.5.1~10.1.2.5.4 show the
schematic diagram of the Area I/O structure.
AAIO latchup DRC enablement:
1)
Marker CAD layer based (Regard specific IO which covered by LUPWDMY_2 as AAIO only):
“LUPWDMY_2 (255;18)” is a DRC dummy layer to trigger the AAIO latch-up rules check.
Usage:
Draw a LUPWDMY_2 pattern to fully cover the OD injector. However it is not necessary to cover the Well
STRAP, or guard-ring. (Fig 10.1.2.5.3)
Rule No.
LUP.10
LUP.11U
LUP.12U
LUP.13
LUP.14
Description
Label Op. Rule
For Area I/O, within 75 μm(≤75um, label “A” in Fig. 10.1.2.5.1) sizing of the OD injector
A
(covered by LUPWDMY_2), specific guard rings/guard bands rules and N/P wells
STRAP rules (LUP.11~LUP.14) should be followed to enhance latch up immunity. (Fig
10.1.2.5.1)
Exclusive conditions:
If the spacing between the N+ OD and P+ OD of the core CMOS circuits ≥ 3 μm (Label
“F” in Fig 10.1.2.5.1).
For Area I/O, the minimum total width of the P+ guard band (Fig 10.1.2.5.1)
For Area I/O, the minimum total width of the N+ guard band (Fig 10.1.2.5.1)
For Area I/O,
1. Any point inside NMOS source/drain {(N+ ACTIVE INTERACT PO) NOT PO} space
to the nearest PW STRAP in the same PW. (Figure 10.1.2.5.2)
2. Any point inside PMOS source/drain {(P+ ACTIVE INTERACT PO) NOT PO} space
to the nearest NW STRAP in the same NW. (Figure 10.1.2.5.2)
3. The height of pick-up OD is recommended to be equal to that of source/drain ODs.
For Area I/O,
N+OD injector must be surrounded by P+ guard-ring (P+ pick-up ring).
P+OD injector must be surrounded by N+ guard-ring (N+ pick-up ring).
The PW of N+OD injector must be surrounded by N+ guard-ring.
The NW of P+OD injector must be surrounded by P+ guard-ring.
And all of the guard ring widths >= 0.2
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
B
C
D
≥
≥
≤
2
2
15
E
≥
0.2
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Figure 10.1.2.5.1 Area I/O latchup prevention
D
D
N+ S TRAP
D
N+ S TRAP
D
Nwell
P + S TRAP
P+ STRAP
Pwell
N+ S TRAP
N+ S TRAP
Nwell
P+ STRAP
P + S TRAP
P+ OD
Pwell
Figure 10.1.2.5.2
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OD
LU PW D M Y_2
Figure 10.1.2.5.3 Example of LUPWDMY_2 Usage
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whole or in part without prior written permission of TSMC.
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Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
PAD PAD
Peripheral
IO
AA IO
AA IO
Peripheral
IO
AA IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
LUPWDMY_2(255;18)
AA IO
Core Circuit
Peripheral
IO
PAD PAD PAD PAD PAD PAD PAD
PAD PAD PAD PAD
PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD
PAD PAD PAD PAD PAD PAD PAD
Figure 10.1.2.5.4 IO cells put in the chip center and next to internal circuit need to follow AAIO latch-up.
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Core Circuit
Peripheral
IO
Peripheral
IO
PAD PAD PAD PAD PAD PAD
PAD PAD PAD PAD PAD PAD
Peripheral
IO
PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
Peripheral
IO
PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD
Figure 10.1.2.5.5 The AAIO latch-up rules are not required for this scenario.
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Test Specification and Requirements
TSMC Latch-Up testing is performed at room temperature and 125C by complying the Latch-up test
methodology defined by JEDEC 78. The test items include Input/Output over-voltage/ over-current test (Fig.
10.1.3.1) and supply over-voltage test (Fig. 10.1.3.2). It applies a stepped voltage/current to one pin per device
with all other pins open except Vdd and Vss. Testing was started from Vdd/50mA (positive) or 0V/-50mA
(negative), and the DUT was biased for 0.5 seconds. If the Icc current does not reach the predefined limit
(Idd=200mA), then the voltage was increased by +/-0.1V or +/-50mA and the pin was tested again until +/1.5Vdd or +/-100mA for Input/Output over-voltage/ over-current.
Notes:
1. DUT: Device under test.
Id d
T rig g e r
s o u rc e
Vdd
O v e r -v o lt a g e
Vss
O v e r -c u r r e n t
Fig. 10.1.3.1 Input/Output Over-Voltage/Current Test
Id d
Vdd
O v e r -v o lt a g e
Vss
Fig. 10.1.3.2 Supply Over-voltage Test
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10.2
I/O ESD Protection Circuit Design, Layout
Rules and Guidelines
10.2.1
ESD introduction
During manufacturing, it is inevitable the IC will suffer various kinds of Electrostatic-Discharge (ESD) damage.
Different environments, wafer during CMOS process, package, testing and human handling, will generate
different kinds of ESD’s. Currently, the charge device model (CDM), Human-Body mode (HBM) and Machine
model (MM) are the most common models used to simulate the ESD events generated from various
environments. The main difference between CDM and HBM is that CDM charges come from the substrate
through the internal circuit to the pad, while the ESD’s for HBM and MM come from the external environment
to the pad. So, most ESD protection devices only can be used to protect HBM and MM, but cannot be used to
protect the CDM since the ESD protection device is at the pad and there is no direct current path between the
internal circuit and the ESD protection device.
The discharging behaviors for the three ESD models all can be simplified by the equivalent circuit in Figure
10.2.1 and expressed by the equation:
I ESD
 V ESD
e
(   )t
 e
2Lo
 (   ) t
(1). where =Ro/(2Lo),  
(RoC o )
2
 4 L o C o /( 2 L o C o )
For HBM, the Ro , Co
and Lo is 1.5K, 100pF and 7.4H, respectively. For MM, the Ro , Co and Lo is 10, 200pF and 7.4H,
respectively. Substituting the above values into eq. (1), the measured and theoretical current waveforms for
HBM and MM are shown in Figure 10.2.2. For HBM, the rise time is <10nsec, the decay time is 150nsec
(RoCo=1.5K100pF) and the peak current is equal to VESD/Ro. The period for MM is nearly 90nsec and the
peak current for 100V MM is nearly 1.7A.
Figure 10.2.3 shows the CDM discharging current waveforms vs. Lo and Ro based on eq. (1) for 500V CDM.
The CDM period and peak current are varied with Lo, Co, and Ro. Compared with HBM and MM, the CDM has
a shorter period and a larger peak current.
Lo
VESD
IESD
CESD
Ro
Vss
Fig. 10.2.1.1 The simplified equivalent circuit for ESD
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0.035
a. 0.030
M ea. current
C al. current
)
0.8
0.020
0.015
0.010
: T-N45-CL-DR-001
: 2.6
Mea. current
Cal. current
0.6
Current ( A )
A
(
C u rre n t
b.
0.025
0.4
0.2
0.0
-0.2
-0.4
0.005
0.000
Document No.
Version
Confidential – Do Not Copy
-0.6
0
50
100
150
200
250
Tim e ( nsec )
0
50
100
150
200
Time ( nsec )
Fig. 10.2.1.2 The discharging current waveform for (a) HBM and (b) MM
L=25nH, C=4pF, R=10ohm
L=25nH, C=4pF, R=50ohm
L=50nH, C=4pF, R=10ohm
L=25nH, C=2pF, R=10ohm
L=25nH, C=8pF, R=10ohm
8
Current ( A )
6
4
2
0
-2
-4
-6
0
1
2
3
4
5
Tims ( nsec )
Fig. 10.2.1.3 The CDM discharging current waveforms vs. Lo, Ro, and Co
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Besides the above three models, another kind of ESD, which occurs during wire bonding, has been found. We
call it ball-bonding ESD (BBE). The stress period of the BBE (~20nsec) is shorter than HBM and MM, but
longer than CDM. The stress voltage (~13V) of BBE is much smaller than HBM, MM and CDM. The BBE came
from the charged wire through the pad and device which connect the pad to the substrate. It might induce the
reliability issue and degrade the device ESD performance if the ESD protection device is not robust enough or
the pad is without the ESD protection device. (please refer to JH Lee et. al, “The impact of ball-bonding
induced voltage transient on sub-90nm CMOS technology,” in IRPS, p. 97, 2007.)
Because the pad is the median used to interact with externals for an IC, all pads need ESD protection devices
to protect the ESD coming from various environments to prevent internal circuit damage.
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whole or in part without prior written permission of TSMC.
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TSMC IO ESD layout style introduction
TSMC IO ESD protection scheme is the self-protection scheme that IO is the ESD protection device. No
matter NMOS or PMOS, they all have the snapback phenomena. The snapback mechanism can be described
as the following: As the applied voltage is higher than the device trigger voltage (Vt1 in Fig. 10.2.2.1), a lot of
holes are generated due to a drain junction occurrence Avalanche-breakdown. The hole current (Isub in Fig.
10.2.2.1) flows through the substrate (Rsub in Fig. 10.2.2.1) and raises up the substrate potential (Vsub in Fig.
10.2.2.1), and eventually forward bias the p-n junction (D1 in Fig. 10.2.2.1) between the P-substrate and the
source when the potential becomes higher than 0.7V. Subsequently, a lot of electrons are injected from the
source and flow to the p-n junction between the P-substrate and the drain, which generates more electron-hole
pairs due to impact-ionizations at the high electrical field of the drain junction. The resulting carrier transport
mechanism causes a positive feedback effect to turn on the parasitic n-p-n bipolar transistor (npn in Fig.
10.2.2.1). As the parasitic n-p-n is turned on, it can sink a much higher current level than the initial Avalanchebreakdown current and goes into a stable snapback region as shown in Fig. 10.2.2.1.
ESD (b) 6
(a) Vss
0.12
Vt1
Current
N+
n-
D1
n-
Base
Vsub= ISubRSub
Rsub(x)
N+
npn
ISub(x)
P-substrate
0.10
0.08
4
snapback
0.06
3
Voltage
0.04
2
0.02
1
0.00
0
0
20
40
60
80
100
120
140
Time ( nsec )
Fig. 10.2.2.1 (a) the parasitic components of a Grounded-gate NMOS (GGNMOS), (b). real time IV
characteristics of a GGNMOS under 100 nsec TLP pulse
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The RPO is the silicide blocking layer which is commonly used for an ESD protection device to forbid the
silicide formation on the drain region. The RPO scheme might be not a good solution for IO design due to
larger series resistance, but it can provide a stable ESD performance for an ESD protection device. So, the
device ESD performance does not vary between technology generations or manufacturing fabs. Fig. 10.2.2.2
shows the high current IV characteristics of a RPO N+ OD resistor. The RPO N+ OD resistor has a saturation
region. In the saturation region, the resistor becomes a high impedance resistor, so the increase in the applied
voltage does not increase the stress current. From this characteristic, we can deduce that RPO can be used to
clamp the current to prevent the current being localized in a given region. As a region enters the saturation
point, it becomes a high impedance resistor. Then, the current of this region cannot be increased anymore.
Subsequently, the current will be pushed to flow to other non-saturated regions and the current can distribute
along the junction uniformly.
Current ( mA )
20
Saturation
region
15
10
RPO N+ OD (W/L 1.4/2)
5
0
0
2
4
6
8
Voltage ( V )
Fig. 10.2.2.2 High current IV charactertistics of a RPO N+ OD resistor
The ESD implant is a process scheme to enhance the device ESD performance without changing the device
layout since it only covers the drain region and needs to have 0.4um space from the poly gate. The current
ESD implant recipe is P-type ESD implant. It can reduce the device breakdown voltage and create the higher
electrical field during the snapback region, resulting in better ESD performance. At TSMC, only one dosage
exits for P-type ESD implants. The dosage for ESD implants is higher than the channel implant dosage for
3.3V and 2.5V devices, but lower than the channel implant dosage for below 1.8V devices. So, the ESD
implant is recommended for 3.3V and 2.5V devices, but is no use for devices below 1.8V. For 5V, 3.3V and
2.5V high voltage tolerant I/O, an ESD implant should be used.
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whole or in part without prior written permission of TSMC.
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ESD Implant (ESDIMP) Layout Rules (MASK ID:
111)
ESDIMP (CAD layer: 189;0) is a drawn layer for ESD implant.
The following width, space, area, and enclosed area are based on process concern. Please use larger
dimension for ESD implant.
Recommended ESDIMP in the following NMOS drain side,
2.5V tolerant I/O circuits using a 1.8V I/O device. A 2.5V tolerant I/O is defined by the VIN criterion: VIN >
VDD but VIN ≤ (2.5V +10%)
3.3V tolerant I/O circuits using a 2.5V I/O device. A 3.3V tolerant I/O is defined by the VIN criterion: VIN >
VDD but VIN ≤ (3.3V +10%)
5V tolerant I/O circuits using a 3.3V I/O device. A 5V tolerant I/O is defined by the VIN criterion: VIN > VDD
but VIN ≤ (5V +10%)
Description
Width
Space
(OD NOT PO) enclosure of ESDIMP.
ESDIMP must be fully inside (OD NOT PO).
Recommended (OD NOT PO) enclosure of ESDIMP.
Area
Enclosed area
ESDIMP must be fully inside N+ ACTIVE
Rule No.
ESDIMP.W.1
ESDIMP.S.1
ESDIMP.EN.1
ESDIMP.EN.1®
ESDIMP.A.1
ESDIMP.A.2
ESDIMP.R.1
C
C
C
D
E
=


0.4
1.0
1.0
C
Drain
Drain
ESDIMP
D
A
Rule
0.5
0.5
0.4
C
C
ESDIMP
Op.



C
ESDIMP
C
ESDIMP
C
Label
A
B
C
C
ESDIMP
ESDIMP
E
A
C
C
B
B
C
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SR_ESD device Layout Rules (N40G only)
The SR_ESD layer (CAD layer: 121;0) is ONLY used for N40G core voltage ESD related device, which
features with:
 Core devices with SR_ESD layer will waive following OD/PO rules: OD.W.2.1GS, OD.W.2.2GS,
PO.S.2.1.1GS, PO.EX.2.1GS, and CO.S.7® .
 Additional rules are wavied by SDI layer coverage itself: PO.W.6.GS, RPO.EX.1, RPO.EX.1.1, RPO.EX.1.2
and CO.S.7® .,
 For speed-sensitive circuit design, standard MOS layout with dual-diode protection is the recommended
approach.
 For core voltage MOS, SR_ESD layer can’t cover core PMOS where SiGe is used. Only core NMOS (active
power clamp; Ncs) is allowed to be covered by SR_ESD.
Rule No.
Label
Op.
Rule
SR_ESD.W.1 width
SR_ESD.W.2 Channel length in SR_ESD regions
Description
A
B

0.18
0.1
SR_ESD.W.3 Channel width of core device in SR_ESD regions
SR_ESD.S.1 Space
C
D

=

15 ~ 60
0.18
SR_ESD.EX.1 Extension on ACTIVE
E

0.02
SR_ESD.L.1
Maximum ACTIVE length of core device in SR_ESD regions
F

60
SR_ESD.R.1
SR_ESD can not cover core PMOS
S
D
SD
ES
R__E
SR
SR _ESD
E
OD
SR _ESD
E
C
A
D
F
E
E
B
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ESD Dummy Layers Summary
10.2.5.1

Document No.
Version
SDI Dummy Layer
SDI (CAD layer: 122) is a DRC layer, but not for mask making. It is required to cover all ESD MOS OD
regions (Regular IO, high voltage tolerant I/O, Power clamp) that are connected to the pads. SDI is not
necessary to cover the well STRAP or ESD guard-ring.
This includes the source, gate, and drain, but not necessarily the field PO and well strap OD regions. Refer to
Figure 10.2.5.1, shown below.
NP/PP
OD
SDI
Source
PO
Figure 10.2.5.1
Drain
The SDI dummy layer layout
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ESD circuits Definition
TSMC provides MOS-based (or snapback-based) ESD protection scheme and design guidelines for regular IO
and HV tolerant IO application. Furthermore, the design guidelines for the diode-based protection scheme are
also added.
10.2.6.1
Regular IO
Regular I/O is composed of the NMOS and PMOS and the drains of the NMOS and PMOS connect to the pad
directly (N1/P1 in Figure 10.2.9.1.4).
10.2.6.2
HV tolerant IO
The HV tolerant I/O is composed of the PMOS in floating NW (P2 Figure 10.2.9.3.1) and cascode (stacked
gate) NMOS and the drains of the floating NW PMOS and cascode (stacked gate) NMOS connect to the pad
directly (P2/N2/N3 in Figure 10.2.9.3.1). There are three kinds of HV tolerant IO listed below.
10.2.6.2.1 5V tolerant I/O
5V tolerant I/O circuits using a 3.3V I/O device with VIN criterion: VIN > 3.3V but VIN ≤ (5V +10%).
10.2.6.2.2 3.3V tolerant I/O
3.3V tolerant I/O circuits using a 2.5V I/O device with VIN criterion: VIN > 2.5V but VIN ≤ (3.3V +10%).
10.2.6.2.3 2.5V tolerant I/O
2.5V tolerant I/O circuits using a 1.8V I/O device with VIN criterion: VIN > 1.8V but VIN ≤ (2.5V +10%).
10.2.6.3
IO Buffer
The I/O Buffer includes regular I/O and HV tolerant I/O.
10.2.6.4
Power Clamp Device (Ncs)
The device is used for VDD Pad to VSS Pad protection (Ncs in Figure 10.2.9.1.4 and Figure 10.2.9.3.1). Please
refer to section 10.2.9.4.
10.2.6.5
ESD Device
The ESD Device includes any device (NMOS, PMOS, I/O buffer, power clamp device, diodes, SCR and
resistor) which connects to the pad directly and can be used to discharge the ESD current.
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whole or in part without prior written permission of TSMC.
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Requirements for ESD Implant Masks

For HV tolerant (cascode) I/O NMOS, ESD implant mask is required unless TSMC approves a special
exclusion request. The ESDIMP layer is a drawing layer and you have to draw ESDIMP layer for mask
making. The ESDIMP layer is a drawing layer. Please refer to the section 10.2.3 for the detail.

For customers who use their own ESD design structure, or do not use HV tolerant NMOS, ESD implant is
optional.
Table 10.2.7.1
ESD Implant Masks for HV Tolerant I/O Circuits
I/O Design Style
TSMC-style I/O with HV tolerant IO circuits
TSMC-style I/O without HV tolerant I/O circuits
Non TSMC-style ESD
10.2.8
ESDIMP (CAD layer 189;0)
Requirement
Drawing Required
No need
Depends
ESD mask (no.111)
Requirement
Yes
No need
Depends
DRC methodology for ESD guidelines
10.2.8.1
DRC methodology to identify ESD MOSFET
1. The ESD MOS is defined by MOS covered by SDI (122;0).
2. The Regular ESD N/P MOS is defined in the following:
 ESD N/P MOS with gate partially covered by RPO and without gate fully covered by RPO
3. The HV Tolerance ESD PMOS is defined in the following:

ESD PMOS with gate partially covered by RPO and without gate fully covered by RPO.(same as
Regular ESD PMOS)
4. The HV Tolerance ESD NMOS is defined in the following:
 ESD NMOS with gate partially covered by RPO and with gate fully covered by RPO
5. The Power Clamp ESD NMOS is defined in the following:
 ESD NMOS without RPO overlap
# Note: For other non-TSMC-standard ESD MOSFETs, there is no DRC ESD guidelines check.
Table 10.2.8.1 how to recognize ESD MOSFET
RPO Partially Cover Gate RPO Fully Cover Gate
Y
Y
Y
N
N
N
Y
N
ESD MOS Type
HV Tolerance ESD NMOS
Regular ESD N/P MOS or
HV Tolerance ESD PMOS
No support
Power Clamp ESD NMOS
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DRC methodology to identify ESD MOS Source
and Drain
1.
2.
The S/D region is defined by {MOS_OD NOT POLY}
The S/D region which connected to well pick-up is Source.
 The connectivity is broken by resistor for this check.
3.
The S/D region outside RPO is Source. (except for Power Clamp)
4.
Except for recognized Source, all the others are Drain.
# Note: If the ESD layout structure is not TSMC-standard, this approach will fail.
Figure 10.2.8.2
10.2.8.3
Example of S/D for ESD device
DRC methodology for ESD.1g
1. ESD S/D is covered by OD2, and connected to Core device S/D/G (without OD2).
2. If ESD S/D is connected to P-well pick-up, it is excluded from this rule check.
PAD
1.8V/2.5/3.3V ESD
Fail !
Core Circuit
Figure 10.2.8.3
PAD
1.8V/2.5/3.3V ESD
Fail !
Core Circuit
Example of ESD.1g
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DRC methodology for ESD.4g
1. ESD S/D interact one gate only is defined as edge side OD.
2. The edge side OD is not connected relative well pick-up.
 N-well pick-up works for NMOS, P-well pick-up works for PMOS.
 The connectivity is not broken by resistor for this check.
# Note: This check will fail for stacked ESD circuit.
The Source is not connected to power !
PAD
The Source is not connected to ground !
Figure 10.2.8.4 Example of ESD.4g
10.2.8.5
DRC methodology for ESD.6g
1. Check the space between two ESD MOS in same connection of Drain to PAD.
 The connectivity is not broken by resistor for this check.
2. The space < 2um, and there is a well pick-up between these two ESD MOSs
Figure 10.2.8.5
Example of ESD.6g
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DRC methodology for ESD.7g
1. Check the space < 1.2um between two same type Non-ESD MOSs connected to different Signal PAD.
(Non-ESD MOS: MOS not covered by SDI).
 The connectivity depends on “DISCONNECT_AFTER_RESISTOR” is turned ON or OFF.
2. Check the space < 1.2um between two same type Non-ESD MOSs in the same well, or these two wells
are connected.
 The connectivity is not broken by resistor for this check.
3. Find out the MOSs meet above two criteria at the same time, and there is no different type of OD placed
between these two MOSs.
Signal
PAD
Pass
!
Fail !
Pass
!
>= 1.2um
< 1.2um
< 1.2um
Figure 10.2.8.6
10.2.8.7
Signal
PAD
Example of ESD.7g
DRC methodology for finger width
1. This check is for ESD.16g, ESD.17g, ESD.24g, ESD.25g, ESD.37g, ESD.41g, ESD.48g, and ESD.49g.
2. The total finger width is calculated by the ESD MOS (ESD.16g, ESD.17g, ESD.24g, ESD.25g, ESD.37g,
and ESD.41g) in the same Drain connection.
3. The total width is calculated by the ESD Field Device (ESD.48g, ESD.49g) in the same collector
connection.
 The connectivity is broken by resistor for this check.
Figure 10.2.8.7 Example of finger width
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DRC methodology for ESD.19g and ESD.27g
1. As mentioned in previous, the drain-side is recognized by S/D not outside RPO, so that the check of drainside OD without RPO would be meaningless.
2. DRC only highlight the gate without overlap with RPO.
Figure 10.2.8.8 Example of ESD.19g and ESD.27g
10.2.8.9
DRC methodology for ESD.20g, ESD.28g, ESD.29g,
and ESD.42g
1. For Regular ESD N/P MOS and HV Tolerance ESD PMOS :
 The overlap of RPO and Gate should exactly equal to 0.06um.
 The overlap should occur in one-side only
 Without overlap is not allowed
2. For HV Tolerance ESD NMOS :
 The RPO should fully cover the first Gate.
 The overlap of RPO and second Gate should exactly equal to 0.06um.
 The overlap should occur in one-side only.
 Without overlap is not allowed.
second Gate
first Gate
RPO
Pass
!
Fail !
Fail !
Fail !
RPO
Fail !
Fail !
Pass
!
Figure 10.2.8.8.9 Example of ESD.20g, ESD.28g, ESD.29g, and ESD.42g
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ESD Guidelines

TSMC's ESD target is 2KV for Human Body Model (HBM) and 200V for Machine Model (MM)

These design guidelines are designed to increase ESD protection levels to TSMC specifications.

These guidelines are developed from our test chip silicon data. The test structures in these test chips
include most of the failure cases we have studied. Yet, there might be other weak paths that are not
captured by these guidelines. Thus, chip level ESD testing should be carried out.
10.2.9.1
Rule No.
ESD.NET.1gU
ESD.WARN.1
ESD.WARN.2
ESD.WARN.3U
ESD.1g
ESD.1.1gU
Description
For I/O pin ESD protection scheme, the primary ESD protection (1st ESD) devices are required and it can
be one of following listed devices.
1. Regular I/O P/NMOS (refer to ESD.16g~23g) or HV-tolerant I/O P/NMOS (refer to ESD.24g~35g)
2. HIA diode (refer to HIA.1~6g)
3. Diode with DIODMY (total perimeter >=300um)
SDI is not in whole chip.
If SDI does not exist, the ESD related DRC will not work well.
SDI enclosure of ACTIVE
Avoid gate of core MOS directly tie to Vdd/Vss except decap, GGNMOS/GDPMOS, and footer/header (see
section 10.4.4.1 for details).
For CDM application with peak current < 6A, this rule can be waived.
Use thin oxide transistor for thin oxide power clamp and thin oxide I/O buffers; use thick oxide transistor for
the thick oxide Power Clamp and thick oxide I/O buffers (Figure 10.2.8.3 and 10.2.9.1.1).
DRC will flag the following condition:
((MOS INTERACT OD2) INTERACT SDI) connected to (MOS NOT INTERACT OD2)
DRC will exclude Drain/Source/Gate connected to PW STRAP.
Use thin oxide transistor for thin oxide secondary ESD protection (2nd ESD, N4/P4); use thick oxide
transistor for thick oxide secondary ESD protection (2nd ESD, N4). (Figure 10.2.1.5)
ESD.4g
ESD.5g
ESD.6g
ESD.7g
ESD.8gU
U
Label
Op.
Rule
≥
0
=
15~ 60
≥
1.2
≥
200
For diode based 2nd ESD protection, use thin oxide transistor (Mp/Mn) for thin oxide power clamp (Ncs); use
thick oxide transistor (Mp/Mn) for thick oxide power clamp (Ncs) (Fig 10.2.1.5)
Thick oxide ESD protection or power clamp connect to thin oxide transistor is not allowed.
Both input pin and cross domain 2nd ESD are required to comply with this rule.
Unit finger width of NMOS and PMOS for I/O buffer and Power Clamp Device (Figure 10.2.9.1.2)
The OD area of the edge side of I/O buffer and Power Clamp should be Source or Bulk rather than Drain
(Figure 10.2.8.4 and 10.2.9.1.2), to avoid an unwanted parasitic bipolar effect or an abnormal discharge
path in ESD zapping.
DRC will flag (((OD INTERACT SDI) NOT PO) INTERACT one Gate) does not connect to STRAP. (Please
refer to section 10.2.8.4 in detail)
Same type OD of the I/O buffer and Power Clamp should be surrounded by a guard-ring. All other type ODs
should be placed outside this guard-ring. (Figure 10.2.9.1.2)
DRC will flag the following two conditions,
1. Different type ODs in the most inner guard-ring.
2. OD not inside the most inner guard-ring
Butted STRAP and the STRAP which are between two sources of the N/PMOS in the same I/O buffer and
Power Clamp are strictly prohibited. (Figure 10.2.9.1.3)
DRC will flag Butted STRAP and the STRAP which is within 2um space of two sources of (MOS INTERACT
SDI) connected to same pad. (Please refer to section 10.2.8.5 in detail)
Except the ESD device, either one of the following two conditions must be followed.
the space of two same type ODs
two same type ODs should be separated by different types of OD.
The same type ODs are N+OD and N+OD in the same PW, or P+OD and P+OD in the same NW, which
connect to two different pads. (Please refer to section 10.2.8.6 in detail)
Value of resistor R (ohm) between the gate oxide and IO PAD (Figure 10.2.9.1.4~10.2.9.1.6)
ESD.9.1gU~9.6gU are used to define N/PMOS (N4/P4) and diode (D3/D4) of ESD secondary protection in
Figure 10.2.9.1.5
ESD.3g
ESD.9.0g
General Guideline for ESD Protection
G
The N/PMOS (N4/P4) and diodes (D3/D4) should follow:
1. Either MOS based or diode based secondary protection is required at input pin. (N4 in Figure 10.2.9.1.5
and D3/D4 in Figure 10.2.9.1.5)
2. Should be added after the resistor R (on the far side of R from the pad).
3. NOT in SDI
4. ESD implant and RPO are not needed in these secondary protection devices.
For MOS based secondary protection, the secondary PMOS is “Nice to have”
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Rule No.
U
ESD.9.1g
ESD.9.2gU
ESD.9.3gU
ESD.9.4gU
U
ESD.9.5g
ESD.9.6gU
ESD.12g
ESD.14.3gU
ESD.14.4gU
ESD.15gU
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Description
Channel Length of core voltage MOS for N/PMOS (N4/P4) of MOS based ESD secondary protection in
Figure 10.2.9.1.5.
Channel Length of 1.8V MOS for N/PMOS (N4/P4) of MOS based ESD secondary protection in Figure
10.2.9.1.5.
Channel Length of 2.5V MOS for N/PMOS (N4/P4) of MOS based ESD secondary protection in Figure
10.2.9.1.5.
Channel Length of 3.3V MOS for N/PMOS (N4/P4) of MOS based ESD secondary protection in Figure
10.2.9.1.5.
Channel width of MOS based (N4/P4) ESD secondary protection (for all voltages) in Figure 10.2.9.1.5
Total perimeter of diode based ESD secondary protection (D3/D4) in Figure 10.2.9.1.5
It is not allowed to use OD unsilicided resistors or NW resistors connected to I/O PAD (Figure 10.2.9.1.4
and Figure 10.2.9.1.6).
DRC will use (((RPDMY OR RH) AND OD) AND RPO) to recognize OD unsilicided resistor.
DRC will use (NWDMY INTERACT NW) to recognize NW resistor.
1. Resistance of the power bus line from IO pad to the closest Power clamp. (R1+R2+R4 in Figure
10.2.9.1.7) ()
2. Resistance of the ground bus line from IO pad to the closest Power clamp. (R1+R5+R6 in Figure
10.2.9.1.7) ()
Resistance of the bus line from Power pad to the closest GND pad. (R3+R4+R6+R7 in Figure 10.2.9.1.7)
()
Bypass discharge cells should be inserted between each separate VDD and VSS to avoid ESD damage to
internal circuits.
The suggested bypass discharge cell is back to back diode (Figure 10.2.9.1.8) and it can be either HIA
diode or diode with DIODMY.
1. HIA diode (HIA.3g)
2. Diode with DIODMY (total perimeter >=300um).
The connections are illustrated in Figure 10.2.9.1.
(For more details, please see the “section 10.4.3 Tips for Power-Ground ESD Protection” section in this
chapter.)
Label
Op.
Rule
=
0.07
=
0.15
=
0.27
=
0.42
≥
≥
20
10
≤
1
≤
1
Vdd (core)
core
dec.
cap.
Pad
3.3V/2.5V/1.8V
ESD
core circuit
Vss
3.3V/2.5V/1.8V
power clamp device
Figure 10.2.9.1.1 Use thin oxide transistor for the ESD protection of thin oxide circuits
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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I=I1+I2+…=Metal connection to bond pad>=16um
Metal connecting between Drains and pad
I1
I2
Drain
Drain
>=16um
OD
PO
CO
M1
Via1
M2
Guard ring
G
Source
Source
Figure 10.2.9.1.2 NMOS and PMOS Layouts for I/O Buffer
STRAP
RPO
X
X
X
Source
X
≤ 2um
Source
RPO
X
Z
Z
Drain
Butted STRAP
RPO
Drain
OD
PO
CO
RPO
X
Z
≤ 2um
Source
Source
To the same Pad
Figure 10.2.9.1.3 Butting or Inserted STRAP between two sources of I/O buffer is prohibited
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Vdd
RPO
P1 P1
P4
R (>=200 Ω)
X
Ncs
Trigger
Circuits
Pad
RPO N1 N1
N4
Vss
secondary protection
Figure 10.2.9.1.4 Regular I/O
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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VDD1
Primary
ESD
Mp
P4
RESD
PAD
Primary
ESD
Mn
N4
Active
Trigger
Circuit
Ncs
VSS1
(a) MOS-based secondary ESD protection
VDD1
D4
Primary
ESD
Mp
RESD
PAD
Primary
ESD
Mn
D3
Active
Trigger
Circuit
Ncs
VSS1
(b) Diode-based secondary ESD protection
Figure 10.2.9.1.5 Diode as ESD secondary protection
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whole or in part without prior written permission of TSMC.
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S tru c tu re . I
S tr u c tu r e . II
Document No.
Version
: T-N45-CL-DR-001
: 2.6
S tr u c tu r e . III
Vcc
Vcc
Vcc
R
R
Pad
Vss
Pad
Pad
R
Vss
Vss
Figure 10.2.9.1.6 A resistor before the output transistor
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whole or in part without prior written permission of TSMC.
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R2
: T-N45-CL-DR-001
: 2.6
R3
VDD
PAD
R4
Primary
ESD cell
Power
Clamp
Internal
devices
IO PAD
R1
Primary
ESD cell
R6
R5
R7
VSS
PAD
R1+R2+R4 & R1+R5+R6 <=1ohm
R3+R4+R6+R7 <=1ohm
Figure 10.2.9.1.7 Bus-Lines Design
Db1
VSSA
VSS
Db2
Figure 10.2.9.1.8 Schematic of a back to back (B2B) diode
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whole or in part without prior written permission of TSMC.
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Vdd (comm.)
ESD
conduction
circuit
Circuit I
ESD
conduction
circuit
Vdda
ESD
conduction
circuit
Vddb
ESD
conduction
circuit
Vddc
ESD
Clamp
Circuit II
ESD
Clamp
Circuit III
ESD
Clamp
Vssa
ESD
conduction
circuit
Vssb
ESD
conduction
circuit
Vssc
Vss (comm.)
Figure 10.2.9.1.9 Schematic of a Multiple Power ESD Protection Design
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whole or in part without prior written permission of TSMC.
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: T-N45-CL-DR-001
: 2.6
Regular I/O (3.3V/2.5V/1.8V/1.1V/0.9V RPO Device)

Regular I/O ESD MOS layout style on core voltage MOS is only applicable for non-N40G process. In
N40G, Core voltage MOS can not be drawn with this layout style.

DRC deck uses (N+ ACTIVE AND SDI) AND (some of the related Gate partially overlap RPO but no
related Gate fully inside RPO) to recognize NMOS of Regular I/O.

DRC deck uses (P+ ACTIVE AND SDI) AND (some of the related Gate partially overlap RPO but no
related Gate fully inside RPO) to recognize PMOS of Regular I/O.
Rule No.
Description
Label
Total finger width for NMOS in same connection of drain. (Please refer to
section 10.2.8.7 in detail)
Total finger width for PMOS in same connection of drain. (Please refer to
section 10.2.8.7 in detail)
Channel length: 3.3V Regular I/O (in OD_33)
Channel length: 2.5V Regular I/O (in OD_25)
Channel length: 1.8V Regular I/O (in OD_18)
Channel length: 1.1V/0.9V Regular I/O (not in OD_33, OD_25 and OD_18)
The NMOS and PMOS should have an unsilicided area on the drain side.
That is, the RPO mask should block the drain side of the device (except
the contact region which should remain silicided).
DRC only flags no RPO in this device. (Please refer to section 10.2.8.8 in
detail)
Overlap of RPO on the drain side to the poly gate (N1/P1 in Figure
10.2.9.1.4 and Figure 10.2.9.2.1) (Please refer to section 10.2.8.9 in
detail)
Width of the RPO on the drain side for NMOS. (Figure 10.2.9.2.1)
Width of the RPO on the drain side for PMOS. (Figure 10.2.9.2.1)
Space of poly to CO on the source side (Figure 10.2.9.2.1)
ESD.16g
ESD.17g
ESD.18g
ESD.18.1g
ESD.18.2g
ESD.18.3g
ESD.19g
ESD.20g
ESD.21g
ESD.22g
ESD.23g
Z
Z
Z
Op.
Rule
≥
360
≥
480
L
L
L
L
≥
≥
≥
≥
0.42
0.35
0.2
0.1
Z
=
0.06
X
X
Y



1.0
0.6
0.22
Z
OD
PO
X
X
X
RPO
X
CO
SDI
L
To PAD
L
L
To PAD
L
Figure 10.2.9.2.1 NMOS and PMOS (N1 and P1 in Figure 10.2.9.1.4) for regular I/O
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whole or in part without prior written permission of TSMC.
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10.2.9.3
Confidential – Do Not Copy
Document No.
Version
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: 2.6
HV Tolerant I/O

HV tolerant I/O ESD MOS layout style is only applicable for I/O voltage MOS. Core voltage MOS can not
be drawn with this layout style.

DRC deck uses (N+ ACTIVE AND SDI) AND (some of the related Gate fully inside RPO and some of the
related Gate partial overlap RPO) to recognize the NMOS of HV tolerant I/O.

DRC deck uses (P+ ACTIVE AND SDI) AND (some of the related Gate fully inside RPO and some of the
related Gate partial overlap RPO) to recognize PMOS of HV tolerant I/O, whose layout is the same as
PMOS of Regular I/O.

For 5V and 3.3V tolerant I/O, the ESDIMP is must layer. The detail layout for ESDIMP is shown in section
10.2.3.
Rule No.
ESD.24g
ESD.25g
ESD.26g
ESD.26.1g
ESD.26.2g
ESD.27g
ESD.28g
ESD.29g
ESD.30g
ESD.31g
ESD.32g
ESD.33g
ESD.34g
Description
Label
Total finger width for NMOS in same connection of drain. ESD.24g has been
checked by ESD.16g. (Please refer to section 10.2.8.7 in detail)
Total finger width for PMOS in same connection of drain.
ESD.25g has been checked by ESD.17g. (Please refer to section 10.2.8.7 in
detail)
Channel length: 5V tolerant I/O (in OD_33). N2,N3, P2 in Figure 10.2.9.3.1,
Figure 10.2.9.3.2 and Figure 10.2.9.3.3.
Channel length: 3.3V tolerant I/O (in OD_25). N2,N3, P2 in Figure 10.2.9.3.1,
Figure 10.2.9.3.2 and Figure 10.2.9.3.3.
Channel length : 2.5V tolerant I/O (in OD_18). N2,N3, P2 in Figure 10.2.9.3.1,
Figure 10.2.9.3.2 and Figure 10.2.9.3.3.
The NMOS and PMOS should have an unsilicided area on the drain side. That
is, the RPO mask should block the drain side of the device (except the contact
region which should remain silicided).
DRC only flags no RPO in this device. (Please refer to section 10.2.8.8 in detail)
For NMOS (N2 and N3 in Figure 10.2.9.3.1 and Figure 10.2.9.3.2), the RPO
needs to cover all inactive poly gates and extend to overlap the N3 gate by Z =
0.06um. (Please refer to section 10.2.8.9 in detail)
For PMOS (P2 in Figure 10.2.9.3.1 and Figure 10.2.9.3.3), overlap of RPO on
the drain side to the poly gate. (Please refer to section 10.2.8.9 in detail)
Width of the RPO on the drain side for NMOS. (Figure 10.2.9.3.2)
Width of the RPO on the drain side for PMOS. (Figure 10.2.9.3.3)
Space of poly to CO on the source side (Figure 10.2.9.3.2 and Figure
10.2.9.3.3)
For NMOS (N2 and N3 in Figure 10.2.9.3.1), space of the N2 gate to the N3
gate. (Figure 10.2.9.3.2)
ESDIMP is a required layer for HV tolerant NMOS. Please refer to section
10.2.3
DRC only flags (no ESDIMP INTERACT N+ ACTIVE) for the NMOS of HV
tolerant I/O.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.
Rule
≥
360
≥
480
L
≥
0.42
L
≥
0.35
L
≥
0.2
Z
=
0.06
Z
=
0.06
X
X
≥
≥
1.0
0.6
Y
≥
0.22
S
=
0.22~0.25
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Figure 10.2.9.3.1 The schematic of HV Tolerant I/O buffer
Z
Z
N2
N3
N3
N2
OD
PO
S
X
X
RPO
S
CO
SDI
L
L
To PAD
L
L
Figure 10.2.9.3.2 HV Tolerant NMOS (N2/N3 in Figure 10.2.9.3.1)
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whole or in part without prior written permission of TSMC.
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Z
Z
Z
: T-N45-CL-DR-001
: 2.6
Z
OD
PO
X
X
X
RPO
X
CO
SDI
L
To PAD
L
L
To PAD
L
Figure 10.2.9.3.3 HV Tolerant PMOS (P2 in Figure 10.2.9.3.1)
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10.2.9.4
Confidential – Do Not Copy
Document No.
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: 2.6
Power Clamp Device (Ncs)

DRC deck uses ((N+ ACTIVE AND SDI) NOT INTERACT RPO) to recognize 3.3V/2.5V/1.8V/1.1V/0.9V
fully silicided type Power Clamp.

DRC deck uses ((N+ ACTIVE AND SDI) AND (all of the related gates partially overlap RPO)) to recognize
3.3V/2.5V RPO (unsilicided) type Power Clamp.

RPO mask can be applied for 3.3V/2.5V Power clamp. The 3.3V/2.5V Power Clamp with RPO mask is
3.3V/2.5V RPO (unsilicided) type Power Clamp. The 3.3V/2.5V RPO (unsilicided) type Power Clamp (Ncs
in Figure 10.2.9.4.3) must have an unsilicided area on the drain side. That is, the RPO mask can block
the drain side silicided of the device (except the contact region which should remain silicided).

The Active Power Clamp is required to put between power and ground buses. The Active Power Clamp is
consisted of one trigger circuit and one big FET. The trigger circuit is designed to turn on the big FET
during ESD events and keep the big FET in off state at normal operation. (Figure 10.2.9.4.1)

Care should be taken to prevent potential damage risk to the thin gate oxide. An active power clamp
(VT1~1V) is needed if there are thin-oxide devices whose gates directly connect to power (for example
the NMOS’s and PMOS’s gates connect to VDD and VSS, respectively) like a decoupling capacitor.

Both fully silicided type and RPO (unsilicided) type power clamp must be Active power clamps. (Figure
10.2.9.4.1).
Rule No.
ESD.37g
ESD.37.1g
ESD.38g
ESD.38.1g
ESD.38.2g
ESD.38.3g
ESD.39g
ESD.40g
ESD.41g
ESD.42g
ESD.43g
ESD.45gU
ESD.45.1gU
Description
Total finger width for 3.3V/2.5V/1.8V fully silicided type Power Clamp in
same connection of drain. (Ncs in Figure 10.2.9.4.1) (Please refer to section
10.2.8.7 in detail)
Total finger width for 1.1V/0.9V fully silicided type Power Clamp in same
connection of drain. (Ncs in Figure 10.2.9.4.1) (Please refer to section
10.2.8.7 in detail)
Channel length: 3.3V Power Clamp (in OD_33) for both RPO (unsilicided)
and fully silicided types (Figure 10.2.9.4.2 and Figure 10.2.9.4.3)
Channel length: 2.5V Power Clamp (in OD_25) for both RPO (unsilicided)
and fully silicided types (Figure 10.2.9.4.2 and Figure 10.2.9.4.3)
Channel length: 1.8V Power Clamp (in OD_18) for fully silicided types
(Figure 10.2.9.4.2)
Channel length: 1.1V/0.9V Power Clamp (not in OD_33, OD_25 and
OD_18) for fully silicided types (Figure 10.2.9.4.2)
The total finger width for 3.3V/2.5V RPO (unsilicided) type Power Clamp in
the same connection of drain. (Ncs in Figure 10.2.9.4.1 and Figure
10.2.9.4.3) (Please refer to section 10.2.8.7 in detail)
Overlap of RPO on the drain side to the poly gate (Figure 10.2.9.4.3)
(Please refer to section 10.2.8.9 in detail).
Width of the RPO on the drain side for 3.3V/2.5V RPO (unsilicided) type
Power Clamp (Ncs in Figure 10.2.9.4.3).
Space of poly to CO on the source side for 3.3V/2.5V RPO (unsilicided) type
Power Clamp (Ncs in Figure 10.2.9.4.3).
The big FET of RPO (unsilicided) type Power Clamp is strongly
recommended having ESDIMP. (Figure 10.2.9.4.1).
Each set of Vdd and Vss must have its own power clamp cells and active
power clamp is required (Figure 10.2.9.4.1)
The single stage power clamp (between VDD and VSS ) needs to be
covered by SDI layer (Figure 10.2.9.4.2)
Label
Op.
Rule
≥
1000
≥
1900
L
≥
0.42
L
≥
0.35
L
≥
0.2
L
≥
0.1
≥
1000
Z
=
0.06
X
≥
0.6
Y
≥
0.11
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Active Power Clamp
Gate-grounded Power Clamp
VDD
VDD
Active
Trigger
Circuit
Big FET
Big FET
VSS
VSS
Figure 10.2.9.4.1 The schematic of the Active Power Clamp
Source Drain
L
L
Drain Source
L
L
SDI
Figure 10.2.9.4.2 Ncs Layout in Figure 10.2.9.1.4 and Figure 10.2.9.3.1
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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RPO
OD
Y
Y
X
X
L
Z=0.06
PO
CO
RPO
Y
L
To Pad
L
Z=0.06
SDI
Figure 10.2.9.4.3 RPO (unsilicided) type power clamp Layout for 3.3V and 2.5V RPO (unsilicided) type
Power Clamp in Figure 10.2.9.1.4 and Figure 10.2.9.3.1
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whole or in part without prior written permission of TSMC.
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10.2.9.5


I.
II.
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
5V HVMOS protection (Field Device)
Device usage:
A combination of NFD along with PFD is designed to protected 5V HVMOS based I/O signal PAD.
Please refer to Figure 10.2.9.5.4 for the reference ESD network construction. Please also note that
TSMC ESD protection scheme does not cover this 5V power clamp design.
DRC methodology:
NFD (Figure 10.2.9.5.2)

DRC deck uses ((((N+ ACTIVE NOT INTERACT PO) NOT RPDMY) AND SDI) CUT RPO) to
recognize NFD of 5V HVMOS protection.

DRC deck uses NFD connect to LV PW STRAP to recognize NFD Emitter

DRC deck uses NFD NOT (NFD Emitter) to recognize NFD Collector
PFD (Figure 10.2.9.5.3)

DRC deck uses ((((P+ ACTIVE NOT INTERACT PO) NOT RPDMY) AND SDI) CUT RPO) to
recognize PFD of 5V HVMOS protection.

DRC deck uses PFD connect to LV NW STRAP to recognize PFD Emitter

DRC deck uses PFD NOT (PFD Emitter) to recognize PFD Collector
Rule No.
Description
ESD.47g
ESD.48g
ESD.49g
ESD.50g
ESD.51g
The layer of OD2 (OD_25) is required for 5V protection (NFD and PFD)
Total width for NFD in same connection of collector. (Figure 10.2.9.5.1)
Total width for PFD in same connection of collector. (Figure 10.2.9.5.1)
STI spacing of the NFD and PFD
Unit collector width of NFD and PFD
Unit emitter width of NFD and PFD should be the same as unit collector width
(EW=CW)
Unit emitter length of NFD and PFD
Width of the RPO on the collector side for NFD and PFD
Width of the RPO on the emitter side for NFD and PFD
Space of RPO to CO on the collector and emitter side (Figure 10.2.9.5.1)
Total width of the RPO on the HVMOS protection. (Figure 10.2.9.5.1)
ESD.52g
ESD.53g
ESD.54g
ESD.55g
ESD.56g
ESD.57g
D Y = 0 .2 2
D Y = 0 .2 2
Label
Op.
Rule
DL
CW
≥
≥
=
=
360
360
0.35
15-60
EL
DX
DZ
DY
A
≥
≥
=

≥
0.86
1.95
0.1
0.22
2.4
D Y = 0 .2 2
OD
P P /N P
CO
CW
A
EW
A
RPO
SDI
EL
DX
DX
OD2
DL
E m itte r
E m itte r
D Z = 0 .1
DL
E m itte r
C o lle c to r
To PAD
Figure 10.2.9.5.1
D Z = 0 .1
5V HVMOS protection Layout
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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VSS
PAD
VSS
DZ
DY
DY
RPO
DX
P+
: T-N45-CL-DR-001
: 2.6
N+
N+
N+
E m itte r
C o lle c to r
E m itte r
P+
DL
EL
P -w e ll
P -s u b
Figure 10.2.9.5.2
VDD
NFD cross-section diagram
PAD
DZ
D
D
DY
Z
D
DX
VDD
DY
RPO
Y
X
N+
N
P
+
N
P
P+
Emitter
Emitter
+
D
DL
EL
L
N+
P
P+
Collector
Collector
+
N
P+
P
Emitter
Emitter
+
N+
P
+
N-well
wel
l
P-sub
Figure 10.2.9.5.3
Figure 10.2.9.5.4
PFD cross-section diagram
The schematic of 5V HVMOS protection
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
High Current Diode (HIA_DIO)
10.2.9.6.1 Dual-Diode I/O Protection
HIA_DIO stands for the diode, which can be used for logic, low capacitance or high speed/frequency ESD
protection. For diode-base ESD protection scheme, it should work together with low trigger power clamps,
such as RC-gate driven clamp.
Fig. 10.2.9.6.1 shows the common dual-diode protection scheme. One diode is for pull-up path to the VDD
and the other is for pull-down path to the VSS. There are four current discharge paths between the PAD, VDD
and VSS. The brief descriptions are as follows:
1. For a positive pulse from PAD respect to VDD, the current passes through the pull-up diode to VDD.
2. For a negative pulse from PAD respect to VDD, the current enter the VDD pin, through the power clamp,
and then passes through the pull-down diode,
3. For a positive pulse from PAD respect to VSS, the current passes through the pull-up diode, along the
supply metal bus to through the power clamp and out the VSS.
4. For a negative pulse from PAD respect to VSS, the current passes through the pull-down diode and out the
PAD.
Please note that excellent ESD performance is achieved when the discharge paths are confined to the
design paths as mentioned above. It depends on the low turn-on resistance of the diode, wiring and power
clamp devices. The designer should minimize the I-R drop effect as much as possible. The resistance of metal
bus between the PAD and power clamp should be less than 1 ohm (ESD.14.3gU). Also, both the ESD level
and parasitic capacitance are directly proportional to the diode’s perimeter. Hence, the designer should
consider the parasitic capacitance of the diodes on the I/O PAD and has to balance the ESD and circuit’s
performance.
Figure 10.2.9.6.1 The schematic diagram for diode-base protection
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
10.2.9.6.2 Layout Guidelines for HIA_DIO



HIA_DIO is the diodes both can use for logic, high speed or low capacitance ESD protection. A layout
example is shown Figure 10.2.9.6.3.2 and Figure 10.2.9.6.3.3.
The naming of HIA comes from high current application purposes (High Amp). There is no structural
difference between HIA_DIO and regular core voltage junction diode. The only difference is layout style.
The HBM level is proportion to the diode’s perimeter, however the parasitic capacitance is increasing also.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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10.2.9.6.3 HIA_DIO Layout Guidelines
10.2.9.6.3.1





HIA_Dummy Layer (CAD layer: 168;0)
DRC deck uses (N+ ACTIVE AND HIA_Dummy NOT NW) to recognize N diodes for ESD protection.
DRC deck uses (P+ ACTIVE AND HIA_Dummy AND NW) to recognize P diodes for ESD protection.
Draw HIA_Dummy (CAD layer: 168;0) to fully cover diode’s OD regions that are connected to I/O pads,
including the anode, cathode, and guard-ring. Refer to Figure 10.2.9.6.3.1, and shown below.
It is for DRC usage but not a tapeout required CAD layer.
Diode’s layout (all dimensions of width/length/spacing/overlap) should be exactly identical to the p_cell, or
the RF model’s accuracy will be impacted.
HIA_Dummy
Cathode
Anode
Guard-ring
Fig. 10.2.9.6.3.1 Example of HIA_Dummy
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whole or in part without prior written permission of TSMC.
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10.2.9.6.3.2
Rule No.
U
HIA.1g
HIA.2gU
Document No.
Version
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: T-N45-CL-DR-001
: 2.6
High current diodes protection
Description
Width of N+ Active (N-HIA diode’s cathode) and P+ Active (P-HIA diode’s anode) inside HIA_DUMMY. (Figure
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
Length of N+ Active (N-HIA diode’s cathode) and P+ Active (P-HIA diode’s anode) inside HIA_DUMMY. (Figure
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
Total perimeter of each N+ or P+ ACTIVE inside HIA_dummy in same connection of IO PAD. (Figure
10.2.9.6.3.2 and Figure 10.2.9.6.3.3).
HIA.3gU
HIA.4gU
HIA.5gU
HIA.6gU
The perimeter counts the drawn anode junction parameter region ex. The drawing OD perimeter dimension of
active inside HIA_DUMMY= (A+B)*2*N
The OD spacing between anode and cathode in the width direction (A; longer side of N+/P+ Active) (Figure
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
The OD spacing between anode and cathode in the length direction (B; shorter side of N+/P+ Active) (Figure
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
Cathode width should be larger than anode width for P-diode, and anode width should be larger than cathode
width for N-diode (D≥A). (Figure 10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
Label
Op.
Rule
A
=
0.6-1.6
B
=
5-40
(A+B)*2
*N
≥
300
C1
=
0.3-0.4
C2
=
0.6-0.8
D
D
A
D
C1
Cathode
NOD
POD
CO
B
C2
HIA_Dummy
Anode
Figure 10.2.9.6.3.2 HIA_DIO layout (N-HIA diode)
D
NOD
A
D
C1
Anode
B
C2
Cathode
POD
CO
NW
HIA_Dummy
Figure 10.2.9.6.3.3 HIA_DIO layout (P-HIA diode)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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10.2.9.7
I/O Device
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Version
: T-N45-CL-DR-001
: 2.6
RPO and ESD Implant Summary
NMOS of
3.3V/2.5V/1.8V/ 3.3V/2.5V/1.8V/
5V/3.3V/2.5V
1.1V/0.9V NMOS 1.1V/0.9V PMOS
HV Tolerant
for Regular I/O for Regular I/O
I/O
PMOS of
3.3V/2.5V NMOS
3.3V/2.5V/1.8V/
5V/3.3V/2.5V
for RPO
1.1V/0.9V NMOS
HV Tolerant (unsilicided) type for fully silicided
I/O
Power Clamp
type Power Clamp
Minimum RPO width
on drain side (X)
1.0
0.6
1.0
0.6
0.6
No
RPO-to-N2 (Z) =
Overlap poly by
0.06
Overlap poly by
0.06
Completely
cover N2
Overlap poly
by 0.06
Overlap poly by
0.06
No
First poly-to-N3
space =
No
No
0.25
No
No
No
RPO coverage in the
OD region between
poly gates
No
No
Completely
cover diffusion
No
No
No
RPO-to-N3 (Z) =
No
No
Overlap N3 by
0.06
No
No
No
ESD implant
3.3V/2.5V:
Recommended
1.8V/1.1V/0.9V:
No need
No
Yes
No
Recommended
No
Dummy layer for
DRC
SDI
SDI
SDI
SDI
SDI
SDI
Figure
10.2.9.3.2
Figure
10.2.9.3.3
Figure 10.2.9.4.3
Figure 10.2.9.4.2
Illustration
Figure 10.2.9.2.1 Figure 10.2.9.2.1
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whole or in part without prior written permission of TSMC.
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Document No.
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: 2.6
CDM Protection for Cross Domain Interface
CDM is an increasingly important issue for modern integrated circuits in N45 technology and beyond as
the gate oxide thickness keeps on shrinking and the number of power domains continues increasing. With
respect to the CDM protection, the cross-domain interface is the most crucial situation as compared with the
I/O input gate (defined as ESD.9g in DRM), the gate directly connected to power/ground, and the long signal
path without parasitic junction diode. It is because that the fatal CDM charges are mostly accumulated at the
power/ground metal buses and easily damage the gate oxide at the interface when the discharge current path
crosses the different power domains.
To prevent this kind of CDM damage for the complex power domains, the protection scheme is proposed
as Figure 10.2.9.8.1~3 shown. The protection network consists of a resistor, a pair of gate-ground NMOS and
gate-Vdd PMOS and active power clamp cells. Basically, the CDM protection transistors have to be placed as
close to the receiver gates as possible, and share the same power/ground and well of the receiver cell. A
global active clamp cell should be placed near the cross-domain interface to help conducting the CDM
currents. Additionally, the resistance of power bus between the global active power clamp cells is
recommended to be smaller than 1Ω. The turn-on resistance of “current conducting element” should be as
small as possible to minimize the voltage drop during CDM zapping.
Domain a
Domain b
vdda
vddb
2nd ESD for CDM
Active
clamp
Global
bus
active
clamp
Global
bus
active
clamp
N4
vssa
Active
clamp
vssb
Current conducting element
Global ESD bus
Resistance between two bus active clamp(current conducting element)<1Ω
Figure 10.2.9.8.1 The MOS-based protection scheme for cross-domain CDM
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Domain a
: T-N45-CL-DR-001
: 2.6
Domain b
vdda
vddb
2nd ESD for CDM D2
Active
clamp
Global
bus
active
clamp
Global
bus
active
clamp
D1
vssa
Active
clamp
vssb
Current conducting element
Global ESD bus
Resistance between two bus active clamp(current conducting element)<1Ω
Figure 10.2.9.8.2 The diode-based protection scheme for cross-domain CDM
Domain a
Domain b
vdda
vddb
Active
clamp
Active
clamp
vss
Figure 10.2.9.8.3 Common-grounded cross-domain CDM ESD protection scheme
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whole or in part without prior written permission of TSMC.
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Rule No.
ESD.60.0gU
ESD.61gU
ESD.61.1gU
ESD.62.1gU
ESD.62.2gU
ESD.62.3gU
ESD.62.4gU
ESD.62.5gU
ESD.63gU
Confidential – Do Not Copy
Document No.
Version
Description
: T-N45-CL-DR-001
: 2.6
Label
1. For cross domain with separate grounds (Fig. 10.2.9.8.1~2), either MOS
based or diode based secondary protection with interface resistor is
required at interface. (N4 in Figure 10.2.9.8.1 and D1/D2 in Figure
10.2.9.8.2).
2. If the receiver is the I/O device, the secondary protection is not required.
3. As the cross domain with on-rule power clamp added between vdda to
vssb, the secondary protection is not required.
Total finger width of 3.3V/2.5V/1.8V/1.1V/0.9V cross-domain MOS based
secondary protection. (Figure 10.2.9.8.1)
Total perimeter of cross-domain diode based secondary protection. (D1/D2
in Figure 10.2.9.8.2)
Channel Length of 5V MOS based domain b secondary protection. (Figure
10.2.9.8.1)
Channel Length of 3.3V MOS based domain b secondary protection. (Figure
10.2.9.8.1)
Channel Length of 2.5V MOS based domain b secondary protection. (Figure
10.2.9.8.1)
Channel Length of 1.8V MOS based domain b secondary protection. (Figure
10.2.9.8.1)
Channel Length of 1.1V/0.9V MOS based domain b secondary protection.
(Figure 10.2.9.8.1)
Recommended interface voltage clamping resistor resistance for crossdomain with separated grounds.(resistor in Figure 10.2.9.8.1~2)
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
Op.
Rule
≥
8
≥
10
=
0.8
=
0.42
=
0.27
=
0.15
=
0.07-0.08

200 Ω
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10.3 ESD Back-End Reliability Guidelines
Typically the design purpose within a dedicated ESD protection device is that interconnect will no be the
limitation for the ESD robustness. This section provides information to evaluate the max. current density (CD)
of metal line, via, contact, and resistor under ESD stress condition. According to the ESD back-end reliability
guideline, the customer can optimize their layout and get better ESD performance.
10.3.1
Test Methodology
The TLP is used to extract the maximum ESD current density (CD). The pulse width and rise time of TLP
are 100ns and 10ns, respectively, to simulate the HBM waveform.
The It2 can be extracted by TLP. As below figure shown, the It2 of Metal is about 0.18A and that of Resistor
is 0.06A as shown in Fig.10.3.1
Metal
1E-13
DC leakage (A)
1E-11
0.2
I_TLP (A)
0.16
DC leakage
measurement
|V|
1E-07
1E-05
10
12.5
1E-03
It 2
0.18
TLP
measurement
T r=10ns, Td =100ns
1E-09
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
0
2.5
5
7.5
V_TLP (V)
Resistor
Time
It 2
Figure.10.3.1
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whole or in part without prior written permission of TSMC.
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10.3.2 Failure Mechanism
The measurement is performed by TLP (Td=100ns, Tr=10ns) under 25oC using wafer-level probing. The IESD
means the suggested ESD CD value.
1. For resistor, the resistance will degrade after ESD stress if IESD > ISnapback(It2)
2. The resistance of the resistor will degrade if it goes to snapback after ESD stress. The I ESD is defined as
the maximum current before snapback.
3. For contact, via, and metal, the TLP current density (CD) has chance of degradation after ESD stress if
IESD > 0.5 * It2.
The contact/via/metal ESD failure have the form of an open connection, the change of the sheet resistance,
the degradation of electromigration lifetime. The TLP current density (IESD) is defined as the half of maximum
current before open connection.
10.3.3 Maximum ESD Current Density for Resistor
Below table shows the IESD of resistor.
TLP
(Tr=10ns; Td=100ns)
Specification IESD>12mA
(ESD.CD. 2gU)
IESD
(Normalized by width,
contact and via number )
The suggested metal
width, contact and via
number.
Silicided N+ PO
Resistor (rnpoly)
N/A
N/A
Silicided P+ PO
Resistor (rppoly)
N/A
N/A
Silicided N+ OD
Resistor (rnod)
N/A
N/A
Silicided P+ OD
Resistor (rpod)
N/A
N/A
Unsilicided N+ PO
Resistor (rnpolywo)
7.32 mA/um
1.7 um
Unsilicided P+ PO
Resistor (rppolywo)
3.68 mA/um
3.3 um
Unsilicided N+ OD
Resistor (rnodwo)
8.2 mA/um
1.5 um
Unsilicided P+ OD
Resistor (rpodwo)
24 mA/um
0.5 um
NW Resistor [under
STI) (rnwsti)
N/A
N/A
NW Resistor [under
OD) (rnwod)
N/A
N/A
Resistor ESD
Current Density
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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10.3.4 Maximum ESD Current Density for Via and Metal
Below table shows the IESD of via, contact and metal width for HBM 2KV specification.
TLP
(Tr=10ns; Td=100ns)
Specification IESD>1.3A
(ESD.CD. 1gU)
Specification IESD>12mA
(ESD.CD. 2gU)
IESD
(Normalized by width,
contact and via number )
The suggested metal
width, contact and via
number.
The suggested metal
width, contact and via
number.
M1 (130nm)
75 mA/um
17.4 um
0.16 um
Mx (140nm)
85 mA/um
15.3 um
0.14 um
My (310nm)
N/A
N/A
N/A
Mz (900nm)
425 mA/um
3.06 um
0.028 um
Mr (1250nm)
N/A
N/A
N/A
Mu(3400nm)
N/A
N/A
N/A
AP
N/A
N/A
N/A
Contact (N+ OD)
5.5 mA/CO
237
3
Contact (P+ OD)
4.5 mA/CO
289
3
Contact (Poly)
5.5 mA/CO
none
3
VIAx
(0.07um x 0.07um)
31 mA/via
42
1
VIAy
(0.14um x 0.14um)
N/A
N/A
N/A
VIAz
(0.36um x 0.36um)
240 mA/via
6
1
VIAr
(0.46um x 0.46um)
N/A
N/A
N/A
VIAu
(0.36um x 0.36um)
N/A
N/A
N/A
RV
N/A
N/A
N/A
Metal, via, and
contact ESD
Backend
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whole or in part without prior written permission of TSMC.
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10.3.5 Minimum ESD Current for ESD Device
Rule No.
Description
ESD.CD.1gU
Suggested minimum ESD current (IESD) for the primary ESD discharge path.
(Fig.10.3.5)
Primary ESD devices include dual-diode, ESD MOS in regular I/O, ESD MOS in
HV-tolerant I/O, power clamp, and back to back (b2b) diode.
Label
Primary ESD discharge current path include:
1. Metal line width connecting the bond pad and the primary ESD device.
2. The contact number in the primary ESD device
3. The Via number in the primary ESD device
Suggested minimum ESD current (IESD) for the secondary ESD discharge path.
(Fig.10.3.5)
Secondary ESD devices include ESD resistor, diode based and MOS based
secondary protections.
ESD.CD.2gU
Op.
Rule
≥
1.3A
≥
12mA
Secondary ESD discharge current path include:
1. Metal line width connecting the bond pad and the secondary ESD device.
2. The contact number in the secondary ESD device
3. The Via number in the secondary ESD device
VDD
Pad
1st
pull-up
2nd
pull-up
RESD
IO
Pad
1st
pull-dn
Power
Clamp
2nd
pull-dn
b2b
diode
VSS1
Pad
VSS2
Pad
Figure 10.3.5 ESD current path
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whole or in part without prior written permission of TSMC.
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Tips for the ESD/Latchup design
10.4.1 Tips for General Latchup Design
To enhance Latchup immunity, the following guidelines are recommended.
1) Solid guard ring/STRAP coonection:
 All the guard rings and STRAPs should be connected to VDD/VSS directly with very low parasitic
resistance. Use as many M0_OD and VIAs as possible.
2) Large-size capacitor displacement current induced LUP:
 A P+ guard-ring should separate a large capacitor and MOS to avoid displacement current induce latch-up.
The p+ guard ring width should be enlarger than 0.1 μm.
3) Potential Latchup concern from OD/NW resistor:
If OD/NW resistor is connected to an I/O PAD, this OD/NW resistor may potentially inject substrate current through its
parasitic diode or parasitic BJT during LUP over-current tests. Potential latchup issue may exists if this OD/NW
resistor is nearby parasitic pnpn (SCR).
10.4.2 Tips for General ESD Design
To enhance ESD immunity, the following guidelines are recommended.
1)

2)

Complete ESD protection coverage:
Any Drain/Source/Gate of a transistor connected to a pad should have ESD protection.
Solid back-end in the entire ESD discharge path:
M0_OD and VIAs should be as many as possible in all ESD devices and current paths, including the diode
and metal connection.
3) Robust victim design with use of drain-ballasted NMOS:
 When using drain-ballasted NMOS as I/O ESD protection device, the gate length of post driver should be
larger than the gate length of drain-ballasted NMOS.
4) Pass-gate exists between PAD and internal block:
If a pass-gate (IO device) is added between a PAD and core device, take care if the ESD protection device can
effectively protect the core device. It is not allowed to use IO device to protect the core device (as shown in below
figure). If the pass gate device (I/O device) covered with SDI layer, the DRC will be triggered to check ESD.1g.
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VDD
Pass gate device should be covered with SDI layer
to trigger ESD.1g DRC checking.
PAD
Pass gate
SDI layer
SDI layer
Core
MOS
IO device
VSS

Figure 10.4.2.1

5) Potential ESD concern from OD/NW resistor:
The OD resistor can potentially trigger its parasitic diode /BJT, leading to ESD failure during ESD stress.
To reduce this ESD vulnerability:.
A. For P+ OD resistor, adopt floating NW design when possible.
B. For N+ OD resistor, enclose hot side (connected to I/O PAD) with NW when possible.
C. Surround OD/NW resistor with double guard rings. Avoid local high field and current crowding during ESD by
layout optimization.
Have robust ESD network design with low turn-on voltage and low clamping voltage. The aim is to avoid parasitic
device turn-on.
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10.4.3 Tips for Power-Ground ESD Protection
To avoid ESD damage to internal circuits, it’s critical to arrange robust whole chip ESD protection design. Special
care should be paid to the digital and analog circuits. In the mixed-mode ICs, separate digital and analog powers are used,
and the interface devices between the digital and analog circuits are particularly sensitive to ESD damage. Bellow are
some guidelines for robust power-ground design.
1)
2)
3)
4)
5)
6)
7)
8)
9)
Power protection for each Vdd/Vss domain:
Each set of VDD and VSS must have its own power clamp cells to provide direct discharge path between
VDD and VSS. The number of power clamp cells should be as many as allowed.
Inter-domain power protection design:
Cross-couple power clamps between each power/ground combination are necessary. This includes
Vdd(x) to Vss(y) and Vdd(x) to Vdd(y). The x and y denote different power supply combination.
Recommended power protection design:
The recommended power ESD protection cell is gate-driven NMOS.
Receommended power protection design:
Implement largest total channel width allowed for better ESD immunity. TSMC design rule only represent
a bare minimum requirement on size.
Evenly distributed power protection design:
Use at least one clamping and/or conduction cell for every 1.0Ω of power line resistance.
Power bus design:
Power lines should keep ultra low resistance and avoid disconnection. For different powers or grounds
with the same potential, use bi-directional cell such as back to back diodes to link them together.
Latchup avoidance:
Each component of power clamp and back to back diode cells must be surrounded by double guard
rings to avoid latch up events.
Active clamp trigger circuit design:
Avoid mis-trigger due to power noise or glitch by carefully designing the certain aspects in turn-on
detector circuit, for example, the RC time constant and the junctions acting as minority collectors.
If the detector circuit is RC-inverter trigger circuit design, the ratio between inverter NMOS and PMOS
should be carefully considered to prevent any burn-out issue during reliability (such as burn-in) test
period.
Robust body diode/parasitic diode design:
Guard rings directly connected to VDD or VSS power pad should be as wide as possible, to avoid silicon
burn out on parasitic junction diode during ESD events.
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10.4.4 Tips for MOS gate directly connected to
power/ground/IO PAD
10.4.4.1
MOS gate directly connected to Power/Ground PAD
Gate oxide with direct connection to Power/Ground is a potential ESD weak spot - especially for CDM. The
restriction on direct gate connection to Power/Ground PAD depends on Gate oxide type:
1) No restriction for I/O voltage gate oxide.
2) Core voltage gate can NOT directly connect to power/ground with a few exceptions.
ESD vulnerable gate connection design:
1) Core voltage device gate connects to Power directly and either device source or drain connects to Ground
2) Core voltage device gate connects to Ground directly and either device source or drain connects to Power
VDD
VDD
VDD
VDD
Core NMOS
Not allow
Not allow
DNW
Core PMOS
Not allow
Not allow
Core PMOS
(a)
VSS
(b)
VSS
Core NMOS
(c)
VSS
(d)
VSS
Figure 10.4.4.1.1
Exceptions (core-voltage gate direct connection to power/ground is allowed):
1) Decoupling capacitor (including varactor type; see Figure 10.4.4.1.2)
2) Header/Footer design (see Figure 10.4.4.1.3)
3) GGNMOS/GDPMOS across power/ground design: (see Figure 10.4.4.1.4)
 GGNMOS: Gate, bulk, and either drain or source connect to ground while the leftover drain or source is
connected to power.
 GDPMOS: Gate, bulk, and either drain or source connect to power while the leftover drain or source is
connected to ground.
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P-decap.
VDD
VDD
Core NMOS
Include varactor
allow
allow
VSS
(a)
Core PMOS
include varactor
(b)
VSS
Figure 10.4.4.1.2
Footer Design
Header Design
VDD
VDD
Core NMOS
allow
allow
Core PMOS
(a)
VSS
(b)
VSS
Figure 10.4.4.1.3
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GDPMOS Design
VDD
VDD
allow
: T-N45-CL-DR-001
: 2.6
Core NMOS
allow
(a)
Core PMOS
(b)
VSS
VSS
Figure 10.4.4.1.4
Solutions:
1) Core voltage gate is connected to Power/Ground through tie-high/tie-low cells.
VDD
VDD
VDD
VDD
allow
allow
tie high
allow
tie low
VSS
tie high
Core NMOS
allow
(a)
Core PMOS
Core NMOS
(b)
VSS
Core PMOS
tie low
(d)
VSS
DNW
(d)
VSS
Figure 10.4.4.1.5
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10.5 ESD testing methodology
10.5.1 Stress condition and Measurement condition
The ESD test items include HBM and MM which need to meet MIL-STD 883 and JEDEC standards. The rise time and
decay time of HBM are within 10ns and 150ns, respectively. The rise time and period of MM are within 10ns and 80ns,
respectively. The specification for HBM is 2KV and for MM is 100V. The peak currents of 2KV HBM is1.2A-1.48A and for
MM 100V is 1.4A-1.9A.
The ESD test is performed at room temperature. The sample size for ESD test is three devices and each device are
stressed three times at each voltage level. The DC parametric and functional testing at room temperature is performed on
all devices before ESD testing. The test devices need to meet device data sheet requirements and the DC parameters.
The pin zapping combinations depend on the number of power pin groups like VDD1, VDD2, VSS1, VSS2, GND, etc.
Please refer to MIL-STD 883 and JEDEC standards.
10.5.2 Failure criteria
The DC parametric and functional testing of the device should be characterized after each voltage level to check the
device ESD failure threshold. The device will be defined as a failure if, after exposure to ESD pulses, it no longer meets
the device data sheet requirements using DC parameter and functional testing.
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11 CLN45LP/LPG Reliability Rules
This chapter provides information about the following:
11.1 Terminology
11.2 Front-end process reliability rules and models
11.3 Back-end process reliability rules
The information in this chapter is to help customers meet their product application needs and their design-in
reliability goals. The following sections include descriptions about gate oxide integrity, hot carrier effect
injection (HCI), PMOS negative bias temperature instability (NBTI), EM, and SM specifications.
11.1
Terminology
This section provides definitions for key terms that are included in this chapter.
Table 11.1.1
Term
Definition
MTTF
The lifetime in which 50% of the population has failed
0.1% cumulative failure
The lifetime in which 0.1% of the population has failed
11.2
Front-End Process Reliability Rules and
Models
This section provides information about overdrive voltage, gate oxide integrity, HCI degradation, and negative
bias temperature instability.
11.2.1
I/O Over Drive Voltage
For 2.5V I/O device, it can be overdrived to 3.3V with 10% tolerance. The assumptions are:
1. The device concerns Idsat shift only, not Vt shift. The failure criterion is Idsat shift 10%, and an AC lifetime
of 10 years.
2. Device operated at 3.3V only, and 10% Idsat shift is based on 3.3V Idsat value.
3. And, to meet overdrive requirement, poly channel length must be extended to:
(A) NMOS Lg_minimum extend to 0.5um for 3.3V + 10%.
(B) PMOS Lg_minimum extend to 0.4um for 3.3V + 10%
11.2.2
Gate Oxide Integrity
This section provides information to help customers predict gate oxide reliability and prevent a time dependent
dielectric breakdown (TDDB). TDDB is the breakdown of gate oxide induced by a combination of voltage,
junction temperature, and oxide thickness.
Warning: Following the information in this section ensures a reliability performance of a
0.1% cumulative failure rate for reference conditions as a function of transistor type, oxide
thickness and area, junction temperature, and applied gate voltage. Deviations from the
information could result in a potentially unreliable integrated circuit. For specific memory or
analog capacitor applications, please consult with TSMC to ensure the required product
level reliability specification can be met.
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Gate Oxide Lifetime Prediction Model
For core thin gate oxide and I/O thick gate oxide:
Time to failure  (Vcc)-n  exp (Ea/KT)  (Aox)-1/
Where:
Aox is the total gate oxide area on silicon (unit: m2)
T is the absolute junction temperature (unit: K)
Vcc is the gate voltage (unit: volt)
n is the power law exponent for core thin gate oxide
Ea is the thermal activation energy
k is the Boltzmann’s constant ((8.617  10-5) cV/K)
 is the Weibull shape factor (distribution spread)
11.2.2.2
Failure Mechanism
When an electron current is passed through gate oxide, defects such as electron traps, interface states,
positively charged donor-like traps, and so on, gradually build up in the gate oxide until a conduction path is
formed, followed by thermal run away.
According to the anode hole injection model, injected electrons generate holes at the anode that can tunnel
back into the oxide. Intrinsic breakdown occurs when a critical hole density is reached.
11.2.2.3
Test Methodology
11.2.2.3.1 Measurement Conditions
1. Ig is the gate current with Vb=Vs=Vd=GND. T=125C.
2. Vg is set to 3.6~ 7.0 volts for N45LP/N45LPG (I/O) gate oxide.
3. Vg is set to 3.4 ~ 3.8 volts for N45LP/N45LPG (LP oxide), or 2.5 ~3.0 volts for N45LPG (G oxide) for thin
(core) gate oxide.
11.2.2.3.2 Stress Conditions
At least 50 samples constitute a sample size for core.
At least 30 samples constitute a sample size for I/O.
1. To determine the voltage acceleration factor (n), 3 stress voltages are used at each fixed stress
temperature.
2. To determine the thermal activation energy (Ea), 3 stress temperatures are used at each fixed stress
voltage.
11.2.2.3.3 Failure Criteria
The failure criterion for thin (core) gate oxide is an onset of the first soft breakdown when there is a gate
current (Ig) progressively increasing in noise or variance, and progressive breakdown model will be applied to
extend core oxide lifetime after soft breakdown for overdrive purpose if needed. The failure criterion for thick
(I/O) gate oxide is a hard breakdown.
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11.2.2.3.4 DC Lifetime and Vmax
DC Lifetime and Vmax for 45nm LP/LPG as shown below:
The following tables provide an example of maximum gate voltage (Vccmax) calculations for 45nm LP/LPG core
gate oxide applications. The reference conditions are a gate oxide area of 0.1 cm² for core, 0.01cm² for IO, a
cumulative failure rate of 0.1%, and a duty factor of 100%.
Table 11.2.2.3.4.1 45nm LP 1.1V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
T=
105C
T=
125C
Lifetime
(Years)
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
10
7
5
1.68
1.7
1.71
1.65
1.66
1.67
1.62
1.63
1.64
1.59
1.6
1.62
10
7
5
1.48
1.49
1.5
1.44
1.45
1.46
1.4
1.41
1.43
1.37
1.38
1.4
Table 11.2.2.3.4.2 45nm LP 1.8V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
2.7
2.72
2.74
2.65
2.67
2.69
T=
105C
T=
125C
Lifetime
(Years)
2.6
2.62
2.64
2.56
2.58
2.6
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
3.02
3.04
3.07
2.9
2.93
2.95
2.8
2.82
2.85
2.71
2.74
2.76
Table 11.2.2.3.4.3 45nm LP 2.5V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
4.45
4.49
4.52
4.34
4.38
4.41
T=
105C
T=
125C
Lifetime
(Years)
4.24
4.28
4.31
4.16
4.19
4.23
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
4.81
4.85
4.89
4.69
4.73
4.77
4.58
4.62
4.66
4.49
4.53
4.57
Table 11.2.2.3.4.4 45nm LPG 0.9V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
1.15
1.16
1.17
1.13
1.14
1.15
T=
105C
T=
125C
Lifetime
(Years)
1.1
1.11
1.12
1.08
1.09
1.1
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
1.3
1.32
1.34
1.22
1.25
1.27
1.16
1.18
1.2
1.11
1.13
1.15
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Table 11.2.2.3.4.5 45nm LPG 1.1V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
1.67
1.69
1.7
1.64
1.65
1.67
T=
105C
T=
125C
Lifetime
(Years)
1.61
1.62
1.64
1.59
1.6
1.61
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
1.47
1.49
1.5
1.43
1.44
1.46
1.4
1.41
1.42
1.37
1.38
1.39
Table 11.2.2.3.4.6 45nm LPG 1.8V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
2.71
2.73
2.75
2.66
2.68
2.7
11.2.3
T=
105C
T=
125C
Lifetime
(Years)
2.61
2.63
2.65
2.57
2.59
2.61
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
3.02
3.05
3.07
2.91
2.93
2.95
2.81
2.83
2.85
2.72
2.74
2.76
Hot Carrier Injection Effect
Hot carriers are holes or electrons that have been accelerated to a high energy by a local electric field. Hot
carrier degradation can significantly impact circuit performance and functionality. It is important for circuit
designers to carefully check the lifetime degradation of their designs caused by hot carrier injection (HCI).
Cumulative degradation and process variation must be taken into account for burn-in, field operation, and
overdrive applications.
11.2.3.1
Lifetime Prediction Model for Device Degradation
Owing to the importance of hot carrier injection on circuit operation, customers should employ detailed models
to calculate device degradation during circuit operation and to simulate the impact on circuit operation. The
following is a general model for the degradation of device characteristics:
MTTF = A x f (L, W)  (%)1/n  exp [B  (1/Vds)]  exp [Ea/k (1/T)]
Where:
MTTF is the mean time to failure
L is the drawn channel length (unit: μm)
W is the drawn channel width (unit: μm)
%
Vds is the drain to source bias (unit: volt)
n is the power law factor of time dependent degradation
Ea is the activation energy
k is the Boltzmann constant ((8.617  10-5) cV/K)
T is the absolute junction temperature (unit: K)
A and B are empirical fitting parameters
dsat, 10% Gm)
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Failure Mechanism
A percentage of the energetic hot carriers will impact the lattice and create electron-hole pairs. The created
electron-hole pairs will create even more pairs later on. If the hot carriers have a kinetic energy larger than the
silicon-insulator barrier height, some of the carriers may surmount the barrier and be propelled toward the
insulator that has a moderate or higher gate bias. These carriers can either be trapped in the oxide region or
at the Si-SiO2 interface. The trapped charges from HCI stress have the following effect on the transistors:
1. Shift in the Vt (threshold voltage) of the device
2. Reduced mobility of the conducting carriers
3. Reduced device drain current
4. Increased effective series resistance, from a charge trapped above the S/D extension region
5. Degraded sub-threshold slope
These transistor changes are dependent on the amount of HCI stress that is incurred. The HCI stress in the
transistor is dependent on several factors: Lgate, Vds, Vgs, Vbs, and temperature.
11.2.3.3
Test Methodology
11.2.3.3.1 Measurement Conditions
1.
2.
3.
4.
Idsat is the forward saturation region drain current with Vd=Vg=Vcc, Vs=Vb=GND.
Idlin is the forward linear region drain current with Vd=0.05V Vcc, Vg=Vcc, Vs=Vb=GND.
Gm is the maximum transconductance with Vd=0.1V, Vs=Vb=GND.
Vt is the threshold voltage extrapolated at maximum transconductance.
11.2.3.3.2 Stress Conditions
1.
2.
The core device is stressed at Vd=Vg < 90% device breakdown voltage; Vs=Vb=GND.
The IO device is stressed at a given Vd < 90% device breakdown voltage; Vg is at the maximum substrate
current for a given Vd; Vs=Vb=GND.
11.2.3.3.3 Dimension Ranges of Stress Devices
1.
2.
Channel Length: 0.04um for core N/PMOS devices,
0.15um for 1.8V I/O N/PMOS devices,
0.27um for 2.5V I/O N/PMOS devices,
Channel Width: 10um for core N/PMOS devices,
10um for 1.8/2.5V I/O N/PMOS devices
11.2.3.3.4 Failure Criteria and Spec
The failure criteria for all devices are 10% degradation
1. Spec= AC 10 yrs
2. Spec= DC 0.05 yrs for core device
3. Spec= DC 0.2 yrs for IO device
4. AC/DC factor= 50 for core and IO.
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11.2.3.3.5 DC Lifetime and Vmax: Vcc = 1.1V +- 10% and 1.2V +- 5% for N45LP
DC Lifetime definition: 0.1% cum
Criteria: Idsat shift 10%:
N45LP
1.1V Core (STD): NMOS=0.211 yrs@1.21V. Vmax of NMOS=1.25V for W/L=10/0.04, 125℃
PMOS=0.371yrs@1.21V. Vmax of PMOS=1.28V for W/L=10/0.04, 125℃
1.8V IO: NMOS=0.285yrs@1.98V. Vmax of NMOS= 2V for W/L=10/0.15, 25℃
PMOS=15.24yrs@1.98V. Vmax of PMOS= 2.251V for W/L=10/0.15, 25℃
2.5V IO: NMOS=1.13yrs@2.75V. Vmax of NMOS= 2.9V for W/L=10/0.27, 25℃
PMOS=15.1yrs@2.75V. Vmax of PMOS= 3.3V for W/L=10/0.27, 25℃
2.5V OD 3.3V IO: NMOS=0.2167yrs@3.63V. Vmax of NMOS=3.64V for W/L=10/0.5, 25℃
PMOS=0.39yrs@3.63V. Vmax of PMOS=3.77V for W/L=10/0.4, 25℃
11.2.3.3.6 DC Lifetime and Vmax: Vcc = 1.1V +- 10% and 1.2V +- 5% for
N45LPG_LP, Vcc = 0.9V+10% and 1.0V +- 5% for N45LPG_G
DC Lifetime definition: 0.1% cum
Criteria: Idsat shift 10%:
N45LPG
0.9V Core (STD): NMOS=1.94 yrs@0.99V. Vmax of NMOS=1.085V for W/L=10/0.04, 125℃
PMOS=0.36 yrs@0.99V. Vmax of PMOS=1.057V for W/L=10/0.04, 125℃
1.1V Core (STD): NMOS=0.22 yrs@0.99V. Vmax of NMOS=1.26V for W/L=10/0.04, 125℃
PMOS=0.26yrs@0.99V. Vmax of PMOS=1.266V for W/L=10/0.04, 125℃
1.8V IO: NMOS=0.24yrs@1.98V. Vmax of NMOS=1.99V for W/L=10/0.15, 25℃
PMOS=8.5yrs@1.98V. Vmax of PMOS=2.215V for W/L=10/0.15, 25℃
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Negative Bias Temperature Instability (NBTI)
Negative Bias Temperature Instability (NBTI) is a key reliability item below 65nm technology that is of newer
aging issue in p-channel MOS devices stressed with negative gate voltages. The high temperature and bias
on Gate terminal will cause significantly NBTI effect, which increase in the threshold voltage and decrease in
drain current. It is significant for circuit designers to consider the lifetime degradation ratio of their designs
caused by negative bias temperature instability (NBTI) and must be taken into account for burn-in, field
operation, and overdrive applications from process variation.
11.2.4.1
Lifetime Prediction Model for Negative Bias
Temperature Instability
The lifetime for the negative bias temperature instability (NBTI) is correlated with voltage, temperature,
parametric failure criteria, device length, and device width.
MTTF = A  f (L, W)  (Idsat%)1/n  exp [- xVg]  exp [Ea/k (1/T)]
Where:
MTTF is the mean time to failure
L is the drawn channel length (unit: μm)
W is the drawn channel width (unit: μm)
Idsat
dsat degradation percentage
n is the power law factor of time dependent degradation
Vg is the operation gate bias (unit: volt)
 is the voltage acceleration factor
Ea is the activation energy
k is the Boltzmann constant ((8.617  10-5) cV/K)
T is the absolute junction temperature (unit:K)
A is a constant
11.2.4.2
Lifetime Prediction Model for AC
For an acceptable specification, the AC lifetime must be considered. Currently, TSMC’s proposed standard
is an AC-to-DC factor of 2, based on the assumption that the off-state operation occupies half the product’s
operation time. The accepted AC lifetime is 10 years, with a DC lifetime of 5 years at temperature 125C.
11.2.4.3
Failure Mechanism
The PMOS device has a lower mobility than the NMOS device. Mobility for a PMOS device is decreased
further, and significantly, by negative bias stress on the transistor gate under a high temperature environment.
A hole injected under negative bias into the oxide-substrate interface increases interface states. The
electrochemical reaction induces device instability that is enhanced by boron implanted in the gate poly
engineering process. Logic circuits could suffer from the driving current decrease, and analog circuits could
suffer from the mismatching or shift of threshold voltage.
Negative bias temperature stress under constant voltage (DC) causes the generation of interface trap (N IT)
before the gate oxide and Si substrate, which translate to device Vt shift and Ion loss. The NBTI effect is more
severe for PMOS than NMOS due to the process of holes in the PMOS inversion layer that are known to
interact with oxide state.
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Test Methodology
11.2.4.4.1 Measurement Condition
Idsat is the saturation region of drain current with Vd=Vg=Vcc, Vs=Vb=GND at a stress temperature.
11.2.4.4.2 Stress Conditions
1. Sample size is at least 5 samples for each stress condition.
2. Voltage range is 6~ 10MV/cm for core devices and 6 ~ 10 MV/cm for I/O devices.
3. Temperature range is 125C ~ 175C.
4. Channel Length:
0.04 μm for core N/PMOS devices,
0.15 mm for 1.8V I/O N/PMOS devices,0.27 μm for 2.5V I/O N/PMOS devices,
5. Channel Width:
10 mm for core N/PMOS devices,
10 mm for 1.8/2.5V I/O N/PMOS devices
11.2.4.4.3 Failure Criteria
The failure criterion for NBTI is Idsat 10% degradation for N45LP/N45LPG SVT/LVT device , and 15% for
N45LP HVT device.
Spec=DC 5 years, AC/DC factor=2
11.2.4.4.4 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +-5% for N45LP
DC Lifetime definition: 0.1% cum
N45LP:
1.1V Core (SVT): PMOS=7.99yrs@1.21V. Vmax of PMOS=1.234V for W/L=10/0.04, 125℃
1.1V Core (HVT): PMOS=15.2yrs@1.21V. Vmax of PMOS=1.269V for W/L=10/0.04, 125℃
1.1V Core (LVT): PMOS=51.5yrs@1.21V. Vmax of PMOS=1.327V for W/L=10/0.04, 125℃
1.8V IO: PMOS=6.36 yrs@1.98V. Vmax of PMOS= 2.0V for W/L=10/0.15, 125℃
2.5V IO: PMOS=120yrs@2.75V. Vmax of PMOS= 3.31V for W/L=10/0.27, 125℃
2.5V OD 3.3V IO: PMOS=8.02yrs@2.75V. Vmax of PMOS=3.7V for W/L=10/0.4, 125℃
11.2.4.4.5 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for
N45LPG_LP, Vcc = 0.9V+10% and 1.0V +- 5% for N45LPG_G
DC Lifetime definition: 0.1% cum
N45LPG:
0.9V Core (SVT): PMOS=9.04 yrs@0.99V. Vmax of PMOS=1.016V for W/L=10/0.04, 125℃
1.1V Core (SVT): PMOS=7.08yrs@0.99V. Vmax of PMOS=1.228V for W/L=10/0.04, 125℃
1.8V IO: PMOS=6.26yrs@1.98V. Vmax of PMOS=1.998V for W/L=10/0.15, 125℃
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N45 Poly Current Density
The maximum current density for poly resistor (unsilicided) is 0.50 * Wp mA at a junction temperature of 110C.
This density is calculated using 0.1% point of measurement data at a 5% resistance increase after 100K hours
of continuous operation. Wp (in μm) represents the drawn width of poly line.
Use the following table to calculate Imax if the junction temperature differs from 110C. For a junction
temperature below 105C, use the rule at 105C.
Table 11.2.5.1
Junction temperature
Rating factor of Jmax
105C
1.03
110C
1.00
125C
0.927
For example, Imax (at 125C) = 0.927  Imax (at 110C).
This rule is applicable to N+, and P+ unsilicided poly resistors.
For silicided poly, the maximum DC current density is 6 * Wp mA at a junction temperature of 110C. This
density is calculated using 0.1% point of measurement data at a 5% resistance increase after 100K hours of
continuous operation. Wp (in μm) represents the drawn width of poly line.
11.2.6
N45 Poly EM Joule heating
11.2.6.1
Irms Current
The following table (Table 11.2.6.1) provides the maximum allowed current (Irms or DC) for poly. In this table,
Wp (in μm) represents the drawn width of poly line and ∆ T (C) is the temperature rise due to Joule heating
effect.
Table 11.2.6.1, Wp: poly drawn width
poly
unsilicided
silicided
Irms (mA)
Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]
Table 11.2.6.2 Example for the relationships of Irms (mA), poly width (μm), and joule heating effect (∆T)
Poly width (μm)
0.04
0.5
1
3
Irms for unsilicided poly(mA), Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
ΔT=10 ℃
ΔT=20 ℃
ΔT=30 ℃
ΔT=40 ℃
ΔT=50 ℃
0.038
0.054
0.066
0.076
0.085
0.162
0.230
0.281
0.325
0.363
0.266
0.376
0.461
0.532
0.595
0.655
0.927
1.135
1.310
1.465
ΔT=60 ℃
0.093
0.398
0.652
1.605
Poly width (μm)
0.04
0.5
1
3
Irms for silicided poly (mA), Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]
ΔT=10 ℃
ΔT=20 ℃
ΔT=30 ℃
ΔT=40 ℃
ΔT=50 ℃
0.332
0.470
0.576
0.665
0.743
1.329
1.880
2.303
2.659
2.973
2.092
2.958
3.623
4.183
4.677
4.817
6.812
8.343
9.634
10.771
ΔT=60 ℃
0.814
3.256
5.123
11.799
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Ipeak
The following table provides the Ipeak allowed for poly, In the table, Wp (in μm) represents the drawn width of
poly line.
Table 11.2.6.3
poly
unsilicided
silicided
Ipeak (mA)
1.5* Wp
26* Wp
Ipeak is the current at which a poly line undergoes excessive Joule heating and can begin to melt. This
current should be used infrequently.
11.2.7
N45 OD Current Density
For diffusion (OD) unsilicided resistors and/or silicided interconnect, no Imax rule is given. Since diffusion
(OD) is crystalline silicon with implantation, no electromigration or Joule heating problems occur. If the
design follows contact, metal, and via current density rules, there will be no reliability concern for diffusion
(OD).
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11.3
Back-End Process Reliability Rules
11.3.1
Stress Migration (SM)
The Cu vias are frequently subjected to significant stress. The stress frequently causes voids, commonly
referred to stress migration (SM) or stress-induced voids (SIV).
11.3.1.1
Failure Mechanism
The stress result from the different coefficient of thermal expansion (CTE) between Cu and the surrounding
material will drive micro-vacancy in Cu to diffuse and agglomerate through interfacial surface and grain
boundary. Eventually the stress-induced voids may significantly affect the electrical characteristics and may
cause the semiconductor structure to fail.
11.3.1.2
Test Methodology
11.3.1.2.1 Measurement Condition
The measurement is performed under 25 C using wafer-level probing after oven bake. The baking
temperature ranges between 125C and 250C.
11.3.1.2.2 Failure Criteria
A DUT is considered as failed if 10% resistance increase is reached.
11.3.1.3
SM design rule
Please refer to below rule codes of chapter4.
VIAx.R.2, VIAx.R.3, VIAx.R.4, VIAx.R.5, VIAx.R.6, VIAx.R.8, VIAx.R.11, VIAy.R.2, VIAy.R.3, VIAy.R.4, VIAy.R.5,
VIAy.R.6, VIAy.R.11, VIAz.R.2, VIAz.R.3, VIAr.R.2, VIAr.R.3
11.3.2
Low-k Dielectric Integrity
This section provides information to help customers predict LK dielectric reliability and prevent a time
dependent dielectric breakdown (TDDB). IMD TDDB is the breakdown of LK dielectric induced by a
combination of operation voltage, temperature, and oxide thickness.
11.3.2.1
Low-k Dielectric Lifetime Prediction Model
TTF = A x exp(-r*E0.5) x exp(Ea/kT)
TTF : Time to Failure
A: a constant
r: field acceleration factor
E: electric field
Ea: activation energy
k: Boltzman’s constant
T: temperature
11.3.2.2
Failure Mechanism
While the current passed through LK dielectric and formed a conduction path, it would result in LK dielectric
breakdown.
The possible failure mechanisms after IMD-TDDB test could be as followings.
1. Dielectric interface breakdown (ie: LK dielectric porosity, ESL integration, Cu ions residue…etc.)
2. Dielectric bulk breakdown (ie: trench barrier formation, LK dielectric porosity…etc.)
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Test Methodology
11.3.2.3.1 Measurement Conditions
1. Ig is the leakage current between metal lines at T=125C under Ed (constant stress field).
2. Ed is set to 2 ~ 4 MV/cm.
11.3.2.3.2 Failure Criteria
A DUT is considered as failed if Ig (Tbd) > 100 * Ig (T0).
11.3.2.3.3 Lifetime
0.1% Cum.Fail > 10 years @1.1Vcc, 125C
11.3.2.4
Low-k dielectric integrity design rule
Please refer to below rule codes of chapter4.
M1.S.1, M1.S.8, M1.S.8.1, Mx.S.1, Mx.S.8, Mx.S.8.1
11.3.3
Cu Metal Current Density (EM) Specifications
This section provides information to evaluate the quality of N45 Cu process and to determine the EM lifetime
of metal line, via, stack via, contact under normal operation condition.
11.3.3.1
Electromigration Lifetime Prediction Model
TTF = A x J^(-n) x exp(Ea/kT)
TTF : Time to Failure
A: a constant which contains a factor involving the cross-sectional area of the film
n: exponent of current density ( n =1 )
J: current density flowing in metal
Ea: activation energy ( Ea =0.9eV)
k: Boltzman’s constant
T: temperature
11.3.3.2
Failure Mechanism
When a stress current is applied, Cu ions move from cathode to anode under electromigration, vacancy will
generate at cathode and it will cause resistance increasing.
11.3.3.3
Failure Criteria
A DUT is considered as failed if dR (Tbd) > 10%* R0.
11.3.3.4
Rating factor for Maximum DC Current
Imax is the maximum DC current allowed for metal lines, vias, or contacts. Imax is based on 0.1% point of
measurement data at a 10% resistance increase after 100K hours of continuous operation at 110C. Use the
following table to calculate Imax if the junction temperature differs from 110C.
Table 11.3.3.4.1
Temperature
Rating factor of Imax
105C
1.434
110C
1.000
115C
0.704
120C
0.500
125C
0.358
For example, Imax (at 125C) = 0.358  Imax (at 110C).
The rating factor is 2.077 for the case of temperature below 100℃ for joule heating effect consideration.
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Maximum DC Current for Metal Lines, Contacts
and Vias (Tj = 110C)
11.3.3.5.1 General
The table provides the maximum allowed DC current, Imax for each of the metals, contacts, and vias at junction
temperature of 110C. In the table, w (in m) represents the width of the metal line.
Table 11.3.3.5.1
Metal Wiring Level / Interlevel connection
Imax (mA)
1.104  (w-0.010)
1.196  (w-0.010)
2.686  (w-0.02)
2.686  (w-0.02)
8.096  (w-0.02)
11.316  (w-0.02)
31.08  (w-0.02)
M1
Mx
My(2nd inter-layer metal)
My(2XTM)
Mz
Mr
Mu
Contact (size: 0.06x0.06 μm2)
0.208 per contact
VIAx (size : 0.07  0.07
VIAy (2nd inter-layer metal) (size : 0.14  0.14μm2)
VIAy (2XTM) (size : 0.14  0.14 μm2)
VIAz (size : 0.36  0.36 μm2)
VIAr (size : 0.46  0.46 μm2)
VIAu (size : 0.36  0.36 μm2)
0.072 per via
0.322 per via
0.322 per via
3.077 per via
5.432 per via
3.077 per via
μm2)
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11.3.3.5.2 Imax dependence on metal length (length ≤ 10m)
For a metal line with a length ≤ 10 m, the Imax current limit can be further increased by a factor of 1.5 for 10 ≥
L > 5 and a factor of 4 for L ≤ 5. The detailed Imax specs for various metal lines and vias are described in Table
11.3.3.5.2. In this table, w represents the width of the metal line in m, while L represents the length of the
metal line in m. The junction temperature for these specs is 110°C.
Table 11.3.3.5.2
Metal Wiring Level / Interlevel connection
Metal Length, L (m)
Imax (mA)
1.104  (w-0.010)
L > 10
M1
Mx
My (2nd inter-layer metal)
My (2XTM)
Mz
Mr
Mu
VIA (size : 0.07  0.07 μm2)
VIAy (2nd inter-layer metal) (size : 0.14  0.14 μm2)
VIAy (2XTM) (size : 0.14  0.14 μm2)
VIAz (size : 0.36  0.36 μm2)
VIAr (size : 0.46  0.46 μm2)
VIAu (size : 0.36  0.36 μm2)
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
1.5  1.104  (w-0.010)
4  1.104  (w-0.010)
1.196  (w-0.010)
1.5  1.196  (w-0.010)
4  1.196  (w-0.010)
2.686  (w-0.02)
1.5  2.686  (w-0.02)
4  2.686  (w-0.02)
2.686  (w-0.02)
1.5  2.686  (w-0.02)
4  2.686  (w-0.02)
8.096  (w-0.02)
1.5  8.096  (w-0.02)
4  8.096  (w-0.02)
11.316  (w-0.02)
1.5  11.316  (w-0.02)
4  11.316  (w-0.02)
31.08  (w-0.02)
31.08  (w-0.02)
31.08  (w-0.02)
0.072 per via
1.5  0.072 per via
4  0.072 per via
0.322 per via
1.5  0.322 per via
4  0.322 per via
0.322 per via
1.5  0.322 per via
4  0.322 per via
3.077 per via
1.5  3.077 per via
4  3.077 per via
5.432 per via
1.5  5.432 per via
4  5.432 per via
3.077 per via
3.077 per via
3.077 per via
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Note: The current enhancement factors (the coefficients in the column of “Imax (mA)”) described in Table
11.3.3.5.2 (length dependence) and Table 11.3.3.5.3 (width dependence) should not be multiplied
together because multiplying them together would be too aggressive. Only one enhancement factor from
either Table 11.3.3.5.2 or Table 11.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
(1) Metal Length Definition (L):
The total length of metal wiring level is from one line-end site to another site line-end site of metal.
L
L
L
M x+ 1
M x+ 1
Vx
Vx
M x+ 1
Vx
M x
L
(2) For the Via length rule, use whichever L is larger between upper_metal and lower_metal.
If L1 is larger than L2, Imax of via for short length is based on L1.
If L2 is larger than L1, Imax of via for short length is based on L2.
L2
M x+ 1
Vx
Mx
L1
For example : Via1 connect to 10um-length M1 and 5um-length M2.
Imax of M1 = 1.5 x1.104 x (w-0.010)
Imax of M2 = 4x 1.196 x (w-0.010)
Imax of Via1= 1.5 x0.072
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11.3.3.5.3 Imax dependence on metal width (width ≥ 0.5 µm)
For a metal line with a width ≥ 0.5 m, the Imax current limit is improved by a factor of 2 compared with a
corresponding narrow metal line (w < 0.5). The detailed Imax specs for various metal lines and vias are
described in Table 11.3.3.3.5.3. In this table, w represents the width of the metal line in m. The junction
temperature for these specs is 110°C.
Table 11.3.3.5.3
Metal Wiring Level / Interlevel connection
M1
Mx
My (2nd inter-layer metal)
Metal width, w (m)
Imax (mA)
w < 0.5
1.104  (w-0.010)
w ≥ 0.5
w < 0.5
w ≥ 0.5
2 x 1.104  (w-0.010)
1.196  (w-0.010)
2 x 1.196  (w-0.010)
2.686  (w-0.02)
w < 0.5
w < 0.5
2 x 2.686  (w-0.02)
2.686  (w-0.02)
2 x 2.686  (w-0.02)
8.096  (w-0.02)
Mr
Mu
w ≥ 0.5
w ≥ 0.5
w ≥ 2.0
2 x 8.096  (w-0.02)
2 x 11.316  (w-0.02)
1 x 31.08  (w-0.02)
Contact (size: 0.06 x 0.06 μm2)
Any metal width
VIAx (size : 0.07  0.07 μm2)
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
My (2XTM)
Mz
VIAy (2nd inter-layer metal) (size : 0.14 x 0.14 μm2)
VIAy (2XTM) (size : 0.14 x 0.14 μm2)
VIAz (size : 0.36  0.36 μm2)
VIAr (size : 0.46  0.46 μm2)
VIAu (size : 0.36  0.36 μm2)
w ≥ 0.5
w < 0.5
w ≥ 0.5
0.208 per contact
0.072 per via
2 x 0.072 per via (Array)
0.322 per via
2 x 0.322 per via (Array)
0.322 per via
2 x 0.322 per via (Array)
3.077 per via
2 x 3.077 per via (Array)
5.432 per via
2 x 5.432 per via (Array)
3.077 per via
1 x 3.077 per via (Array)
Note: The current enhancement factors (the coefficients in the column of “Imax (mA)”) described in Table
11.3.3.5.2 (length dependence) and Table 11.3.3.5.3 (width dependence) should not be multiplied
together because multiplying them together would be too aggressive. Only one enhancement factor
from either Table 11.3.3.5.2 or Table 11.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
The maximum allowed current for per via can be raised together with this wide metal EM rule (w ≧ 0.5) but
via-array is needed.
Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
current flow) must be maximized to increase reliability by providing redundancy in the case of blocked or
resistive vias. (increases as much as the line width permits).
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Required vias
Wide Line
Recommended
Wide Line
11.3.3.5.4 Stacked Vias
Stacked via can decompose to single via, and follow single via rule.
11.3.3.5.5 DC Operation, Required Number of Vias
(1) If space permits, it is preferable to have more contacts or vias than the EM rules require.
(2) At a minimum rule, the EM current rules require one via.
(a) Example 1, if M1 is 0.07 μm and the current density is 1.104 mA/μm; that is, the current is
1.104*(0.07-0.010) = 0.066 mA, only one VIA1 is necessary to ensure the reliability margin.
(b) Example 2, if M2 is 0.07 μm and the current density is 1.196 mA/μm; that is, the current is
1.196*(0.07-0.010) = 0.072 mA, only one VIA1 and one VIA2 are necessary to ensure the reliability
margin.
(3) To determine the required number of vias, please proceed as follow:
(a) From the DC current given in section 11.3.3.5, determine the necessary line width (W-line);
(b) Calculate the Maximum allowed Idc_line for the given line width (W-line).
(c) Calculate the required number of contacts or vias to carry line current Idc_line : Number of vias =
Idc_line/ Idc_via.
(4) Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
current flow) must be maximized to increase reliability by providing redundancy in the case of blocked or
resistive vias. ( increases as much as the line width permits).
N a r r o w L in e
N a r r o w L in e
N a r r o w L in e
N a r r o w L in e
R e q u ir e d v ia s
W id e L in e
R e co m m e n d e d
W id e L in e
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AP RDL Current Density (EM) Specifications
11.3.4.1
Maximum DC Current
Jmax is maximum DC current allowed per um of AP RDL metal line width or per RV via. The number is based
on 0.1% point of measurement data at 10% resistance increase after 100K hours of continuous operation at
110C. Use the following table to calculate Imax if the junction temperature differs from 110C.
Table 11.3.4.1
Temperature
85C
Rating factor of Imax 1.800
90C
1.623
95C
1.466
100C
1.329
105C
1.151
110C
1.000
115C
0.872
120C
0.764
125C
0.671
For example, Jmax (at 125C) = 0.671  Jmax (at 110C).
If the junction temperature is below 85C, please use the rating factor (1.800) at 85C or contact with TSMC
reliability.
11.3.4.2
Maximum DC Current for AP RDL Metal Lines (Tj =
110C)
The table provides the maximum allowed DC current, Imax for each of the metal wiring levels at junction
temperature of 110C. In the table, w (in μm) represents the width of the metal line.
Table 11.3.4.2
Metal Wiring Level
Imax (mA)
AP RDL (14.5KÅ )
2.7  w
AP RDL (28KÅ )
5.21  w
11.3.4.3
Maximum DC Current for AP RDL (RV) Vias (Tj =
110C)
The table provides the maximum allowed DC current, Imax for each of the contact and via at junction
temperature of 110C. In the table, the sizes of contact and via are also noted.
Table 11.3.4.3
Interlevel Connection
Imax (mA)
Size
RV
12.15
per RV
3  3 μm2
RV
5.4
per RV
2  2 μm2
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Cu Metal AC Operation
11.3.5.1
Pulsed Signal Terminology
The general terminology for a pulsed DC or AC signal is:
Period ()
Duration (tD)
For your convenience, you could measure the pulse width of Ipeak at half the peak to define the duration (tD).
The definition of Ipeak is:
I peak
 max
 I (t ) 
I (t)
I (t)
Ipeak
Ipeak 
1/2 Ipeak
tD
Time, t
duration
Time, t
tD
duration
, period
11.3.5.2
, period
Average Value of the Current
Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to
Imax rules. Please refer to the DC EM sections. The temperature de-rating table is also applicable to the Iavg
rule for a junction temperature different from 110C.
The definition of Iavg is:
I avg 
 


I ( t ) dt  / 

  0


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Root-Mean-Square Current
Irms is the root-mean-square of the current through a metal line. The definition of Irms is:
I rms
2
 


 
I ( t ) dt  / 

  0


1/2
The following tables provide the Irms allowed for each of the metal wiring levels at a junction temperature of
110C. In the table, w (in μm) represents the width of the metal line and ∆T (C) is the temperature rise due to
Joule heating.
Note to use IrmsΔT limitation:
The EM lifetime is a function of temperature and current density. The higher temperature will cause EM lifetime
degradation. Table 11.3.5.3 is the degradation factor for EM lifetime. The recommend temperature increase,
ΔT is below < 5 °C. Because a 5 °C temperature increase is sufficient to degrade the EM lifetime by about
30%.
Table 11.3.5.3
ΔT
Temp
TTF
110C
1
5C
115C
0.704
10C
120C
0.500
15C
125C
0.358
20C
130C
0.258
30C
140C
0.138
For M1MxMz combination, please refer to sections 11.3.5.3.1 and 11.3.5.3.2.
For M1MxMyMz, M1MxMr, and M1MxMy combinations, please refer to sections 11.3.5.3.3, 11.3.5.3.4,
11.3.5.3.5, and 11.3.5.3.6.
11.3.5.3.1 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMz
process, no My)
Table 11.3.5.3.1.1
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
0.85
4.73
3.98
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 )
]
]
x ∆ T x(w - 0.01)2 x( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x(w - 0.02)2 x ( w - 0.02 + 2.303 ) / ( w - 0.02 + 0.0443 ) ]
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Table 11.3.5.3.1.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
90.20
24.30
13.65
9.50
7.25
5.90
4.95
4.25
23.65
19.90
Irms (mA)
x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 2.303 ) / ( w - 0.02 + 0.0443 ) ]
11.3.5.3.2 Root-Mean-Square Current for LK Dielectrics (other metallization
options, M1MxMz process, no My)
Table 11.3.5.3.2.1 and Table 11.3.5.3.2.2 apply to 1P8M process. For other metallization options, please use
Irms of M9 and M10 as the first and second Mz, respectively.
For example, 1P8M with M2 ~ M7 as Mx, and M8 as Mz, the Irms rules are:
Table 11.3.5.3.2.1
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
4.73
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 )
Another example, 1P8M with M2 ~ M6 as Mx, M7 and M8 as Mz, the Irms rules are:
Table 11.3.5.3.2.2
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
4.73
3.98
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.303 ) / ( w - 0.02 + 0.0443 ) ]
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11.3.5.3.3 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMz
process)
Table 11.3.5.3.3.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
My2
Mz1
Mz2
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
0.85
2.01
1.55
3.74
3.25
Irms (mA)
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
Table 11.3.5.3.3.2 Example Root-Mean-Square Current for ΔT = 5C
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
My2
Mz1
Mz2
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
90.20
24.30
13.65
9.50
7.25
5.90
4.95
4.25
10.05
7.75
18.7
16.25
x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
]
x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 )
If the metal scheme is 1P10M with M1 + 5x2y2z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1 ~ Mz2.
If the metal scheme is 1P10M with M1 + 6x1y2z, then use Mx1 ~ Mx6, My1, and Mz1 ~ Mz2
If the metal scheme is 1P9M with M1 + 5x2y1z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1.
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11.3.5.3.4 Root-Mean-Square Current for LK Dielectrics (other metallization
options, M1MxMyMz process)
Table 11.3.5.3.4.1 and Table 11.3.5.3.4.2 apply to 1P10M process. For other metallization options, please
use Irms of M9 and M10 as the first and second Mz, respectively. Please refer to the section 2.5 of
Metallization Options for allowed metal schemes.
For example, 1P10M with M1 + 5x2y2z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 ~ M10 as Mz), the Irms
rules are:
Table 11.3.5.3.4.1
Metal level
M1
M2 (Mx1)
M3 (Mx2)
M4 (Mx3)
M5 (Mx4)
M6 (Mx5)
M7 (My1)
M8 (My2)
M9 (Mz1)
M10 (Mz2)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
2.01
1.55
3.74
3.25
Irms (mA)
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
Another example, 1P10M with M1 + 6x1y2z (M2 ~ M7 as Mx, M8 as My, and M9 ~ M10 as Mz), the Irms rules
are:
Table 11.3.5.3.4.2
Metal level
M1
M2 (Mx1)
M3 (Mx2)
M4 (Mx3)
M5 (Mx4)
M6 (Mx5)
M7 (Mx6)
M8 (My1)
M9 (Mz1)
M10 (Mz2)
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
2.01
3.74
3.25
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 )
One more example, 1P9M with M1 + 5x2y1z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 as Mz), the Irms rules
are:
Table 11.3.5.3.4.3
Metal level
M1
M2 (Mx1)
M3 (Mx2)
M4 (Mx3)
M5 (Mx4)
M6 (Mx5)
M7 (My1)
M8 (My2)
M9 (Mz1)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
2.01
1.55
3.74
Irms (mA)
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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11.3.5.3.5 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMr
process)
Table 11.3.5.3.5.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
Mr1
Mr2
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
0.85
6.51
5.25
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.953 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.422 ) / ( w - 0.02 + 0.0443 ) ]
Table 11.3.5.3.5.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
Mr1
Mr2
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
90.20
24.30
13.65
9.50
7.25
5.90
4.95
4.25
32.55
26.25
x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 1.953 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 2.422 ) / ( w - 0.02 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x2r, then use Mx1 ~ Mx7, and Mr1 ~ Mr2.
If the metal scheme is 1P9M with M1 + 6x2r, then use Mx1 ~ Mx6, and Mr1 ~ Mr2
If the metal scheme is 1P9M with M1 + 7x1r, then use Mx1 ~ Mx7, and Mr1.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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11.3.5.3.6 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMy
process, My/Vy are used as 2X top Metal/Via)
Table 11.3.5.3.6.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1_TM
My2_TM
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
0.85
1.70
1.58
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.853 ) / ( w - 0.02 + 0.0443 ) ]
x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.992 ) / ( w - 0.02 + 0.0443 ) ]
Table 11.3.5.3.6.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1_TM
My2_TM
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
90.20
24.30
13.65
9.50
7.25
5.90
4.95
4.25
8.50
7.8
x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
]
x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 1.853 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.02)2 x ( w - 0.02 + 1.992 ) / ( w - 0.02 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 )
If the metal scheme is 1P10M with M1 + 7x2y, then use Mx1 ~ Mx7, and My1_TM ~ My2_TM.
If the metal scheme is 1P9M with M1 + 6x2y, then use Mx1 ~ Mx6, and My1_TM ~ My2_TM
If the metal scheme is 1P9M with M1 + 7x1y, then use Mx1 ~ Mx7, and My1_TM.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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11.3.5.3.7 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMzMu
process, Mu/Vu are used as top Metal/Via)
Table 11.3.5.3.7.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
Mz1
Mu1
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
0.85
2.01
4.23
14.22
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 1.566 ) / ( w - 0.020 + 0.0443 ) ]
x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 2.043 ) / ( w - 0.020 + 0.0443 ) ]
x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 2.432 ) / ( w - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1z1u, then use Mx1 ~ Mx7, Mz1, and Mu1.
If the metal scheme is 1P9M with M1 + 5x1y1z1u, then use Mx1 ~ Mx5, My1, Mz1, and Mu1.
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My1, and Mu1.
If the metal scheme is 1P6M with M1 + 4x1u, then use Mx1 ~ Mx4, and Mu1.
Table 11.3.5.3.7.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
Mz1
Mu1
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
90.20
24.30
13.65
9.50
7.25
5.90
4.95
4.25
10.05
21.15
71.10
x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.020 )2 x ( w - 0.020 + 1.566 ) / ( w - 0.020 + 0.0443 ) ]
x (w - 0.020 )2 x ( w - 0.020 + 2.043 ) / ( w - 0.020 + 0.0443 ) ]
x (w - 0.020 )2 x ( w - 0.020 + 2.432 ) / ( w - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1y1u, then use Mx1 ~ Mx7, My1, and Mu1.
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My1, and Mu1.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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11.3.5.3.8 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMu
process, My/Vy are 2XTM, Mu/Vu are used as top Metal/Via)
Table 11.3.5.3.8.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My_TM
Mu1
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.04
4.86
2.73
1.9
1.45
1.18
0.99
0.85
1.70
16.40
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 1.853 ) / ( w - 0.020 + 0.0443 ) ]
x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 2.110 ) / ( w - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1y1u, then use Mx1 ~ Mx7, My_TM, and Mu1.
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My_TM, and Mu1.
Table 11.3.5.3.8.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My_TM
Mu1
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
90.20
24.30
13.65
9.50
7.25
5.90
4.95
4.25
8.50
82.00
x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 )
]
x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
x (w - 0.020 )2 x ( w - 0.020 + 1.868 ) / ( w - 0.020 + 0.0443 ) ]
x (w - 0.020 )2 x ( w - 0.020 + 2.110 ) / ( w - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1y1u, then use Mx1 ~ Mx7, My_TM, and Mu1.
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My1_TM, and Mu1.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Peak Current
Ipeak = max ( | I(t) | )
Ipeak is the current at which a metal line undergoes excessive Joule heating and can begin to melt. This current
should be used infrequently.
The limit for the peak current, Ipeak, can be calculated by using the following formula:
I peak
I peak _ DC

r
Note: the above equation is only applicable for frequency larger than 1 MHz and r larger than 0.05.
r is the duty ratio, which is equal to the pulse duration divided by the period,
r

tD

where Ipeak_DC is provided in the following table. In the table, w (in μm) represents the width of the metal line.
Table 11.3.5.4
Metal Level
M1
Mx
My (2nd inter-layer metal)
My (2XTM)
Mz
Mr
Mu
Ipeak_DC (mA)
26.0  (w-0.01)
14.0  (w-0.01)
21.0  (w-0.02)
21.0  (w-0.02)
63.0  (w-0.02)
87.5  (w-0.02)
202.8  (w-0.02)
The Ipeak rule applies to the periodic AC or pulsed DC signals.
For a single event high current pulse or signals which cannot be specified by duty ratio, please follow the ESD
guidelines.
The Ipeak rules provided in this section are applicable to signals with a pulse width (tD) of less than 1sec. No
temperature adjustment factor for the Irms and Ipeak is given.
The Irms and Ipeak of contacts and vias do not include because the heating in contacts and vias is negligible and
is usually determined by metal or substrate. If the metal width is increased to some extent and only one via is
used in that metal, then the heating in the via cannot be considered negligible. However, if the design follows
the SM rules, via heating can be negligible. Please follow the VIAx.R.2~VIAx.R.6, VIAy.R2~VIAy.R6,
VIAz.R.2~VIAz.R.3 and VIAr.R.2~VIAr.R.3 rules to make sure that the via heating is not a problem.
11.3.6
AP RDL AC Operation
The general terminology for AP RDL is the same as Cu interconnects.
The following tables provides the maximum Irms allowed for AP RDL at a junction temperature of 110C. In the
table, w (in μm) represents the width of the RDL line and ∆ T (C) is the temperature rise due to Joule heating.
Table 11.3.6
Metal level
AP RDL (14.5KÅ )
AP RDL (28KÅ )
Irms (mA)
Sqrt [
Sqrt [
2.54  ∆ T  w  ( w + 2.924 ) ]
4.90  ∆ T  w  ( w + 2.924 ) ]
The Ipeak rule for AP RDL (14.5KÅ ) is 58 mA/um.
The Ipeak rule for AP RDL (28KÅ ) is 112 mA/um.
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12 CLN40LP/LPG/45GS(=40G) Reliability
Rules
This chapter provides information about the following:
12.1 Terminology
12.2 Front-end process reliability rules and models
12.3 Back-end process reliability rules
The information in this chapter is to help customers meet their product application needs and their design-in
reliability goals. The following sections include descriptions about gate oxide integrity, hot carrier effect
injection (HCI), PMOS negative bias temperature instability (NBTI), EM, and SM specifications.
12.1
Terminology
This section provides definitions for key terms that are included in this chapter.
Table 12.1.1
Term
Definition
MTTF
The lifetime in which 50% of the population has failed
0.1% cumulative failure
The lifetime in which 0.1% of the population has failed
12.2
Front-End Process Reliability Rules and
Models
This section provides information about overdrive voltage, gate oxide integrity, HCI degradation, and negative
bias temperature instability.
12.2.1
I/O Over Drive Voltage
For 2.5V I/O device, it can be operated at 3.3V with 10% tolerance. The assumptions are:
1. The device concerns Idsat shift only, not Vt shift. The failure criterion is Idsat shift 10%, and an AC lifetime
of 10 years.
2. Device operated at 3.3V only, and 10% Idsat shift is based on 3.3V Idsat value.
3. And, to meet overdrive requirement, poly channel length must be extended to:
(A) NMOS Lg_minimum extend to 0.55um (drawn width) for 3.3V + 10%.
(B) PMOS Lg_minimum extend to 0.44um (drawn width) for 3.3V + 10%
12.2.2
Gate Oxide Integrity
This section provides information to help customers predict gate oxide reliability and prevent a time dependent
dielectric breakdown (TDDB). TDDB is the breakdown of gate oxide induced by a combination of voltage,
junction temperature, and oxide thickness.
Warning: Following the information in this section ensures a reliability performance of a
0.1% cumulative failure rate for reference conditions as a function of transistor type, oxide
thickness and area, junction temperature, and applied gate voltage. Deviations from the
information could result in a potentially unreliable integrated circuit. For specific memory or
analog capacitor applications, please consult with TSMC to ensure the required product
level reliability specification can be met.
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Gate Oxide Lifetime Prediction Model
For core thin gate oxide and I/O thick gate oxide:
Time to failure  (Vcc)-n  exp (Ea/KT)  (Aox)-1/
Time to failure  exp(rVcc)  exp (Ea/KT)  (Aox)-1/ for 3.3V IO only
Where:
Aox is the total gate oxide area on silicon (unit: m2)
T is the absolute junction temperature (unit: K)
Vcc is the gate voltage (unit: volt)
n is the power law exponent for core thin gate oxide
r is the voltage acceleration factor for 3.3V thick gate oxide
Ea is the thermal activation energy
k is the Boltzmann’s constant ((8.617  10-5) cV/K)
 is the Weibull shape factor (distribution spread)
12.2.2.2
Failure Mechanism
When an electron current is passed through gate oxide, defects such as electron traps, interface states,
positively charged donor-like traps, and so on, gradually build up in the gate oxide until a conduction path is
formed, followed by thermal run away.
According to the anode hole injection model, injected electrons generate holes at the anode that can tunnel
back into the oxide. Intrinsic breakdown occurs when a critical hole density is reached.
12.2.2.3
Test Methodology
12.2.2.3.1 Measurement Conditions
1.
2.
3.
Ig is the gate current with Vb=Vs=Vd=GND. T=125C.
Vg is set to 3.6~ 8.6 volts for N40LP/N40LPG/40G (I/O) gate oxide.
Vg is set to 3.4 ~ 3.8 volts for N40LP/N40LPG (LP oxide), or 2.5 ~3.0 volts for N40G/N40LPG (G
oxide) for thin (core) gate oxide.
12.2.2.3.2 Stress Conditions
At least 50 samples constitute a sample size for core.
At least 30 samples constitute a sample size for I/O.
1. To determine the voltage acceleration factor (n), 3 stress voltages are used at each fixed stress
temperature.
2. To determine the thermal activation energy (Ea), 3 stress temperatures are used at each fixed stress
voltage.
12.2.2.3.3 Failure Criteria
The failure criterion for thin (core) gate oxide is an onset of the first soft breakdown when there is a gate
current (Ig) progressively increasing in noise or variance, and progressive breakdown model will be applied to
extend core oxide lifetime after soft breakdown for overdrive purpose if needed. The failure criterion for thick
(I/O) gate oxide is a hard breakdown.
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12.2.2.3.4 DC Lifetime and Vmax
DC Lifetime and Vmax for 40nm LP/LPG/G as shown below:
The following table provides an example of maximum gate voltage (Vccmax) calculations for 40nm LP/LPG/G
gate oxide applications. The reference conditions are a gate oxide area of 0.1 cm² for core, 0.01cm² for IO, a
cumulative failure rate of 0.1%, and a duty factor of 100%.
Table 12.2.1 40nm LP 1.1V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
1.69
1.71
1.72
1.66
1.67
1.69
T=
105C
T=
125C
Lifetime
(Years)
1.63
1.64
1.65
1.6
1.62
1.63
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
1.47
1.49
1.5
1.43
1.45
1.46
1.4
1.41
1.42
1.37
1.38
1.39
Table 12.2.2 40nm LP 1.8V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
2.71
2.73
2.75
2.66
2.68
2.7
T=
105C
T=
125C
Lifetime
(Years)
2.61
2.63
2.65
2.57
2.59
2.61
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
3.05
3.08
3.11
2.93
2.96
2.98
2.83
2.85
2.87
2.73
2.76
2.78
Table 12.2.3 40nm LP 2.5V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
T=
105C
T=
125C
10
7
5
4.4
4.44
4.48
4.29
4.33
4.37
4.19
4.23
4.27
4.11
4.14
4.18
Lifetime
(Years)
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
10
7
5
4.85
4.89
4.94
4.72
4.76
4.81
4.61
4.65
4.69
4.51
4.55
4.59
Table 12.2.4 40nm LPG 0.9V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
T=
105C
T=
125C
Lifetime
(Years)
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
10
7
5
1.18
1.19
1.2
1.15
1.16
1.17
1.13
1.14
1.14
1.1
1.11
1.12
10
7
5
1.34
1.36
1.39
1.26
1.29
1.31
1.2
1.22
1.24
1.15
1.17
1.19
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Table 12.2.5 40nm LPG 1.1V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
T=
105C
T=
125C
10
7
5
1.69
1.7
1.71
1.65
1.67
1.68
1.62
1.64
1.65
1.6
1.61
1.62
Lifetime
(Years)
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
10
7
5
1.48
1.5
1.51
1.44
1.46
1.47
1.41
1.42
1.43
1.38
1.39
1.4
Table 12.2.6 40nm LPG 3.3V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
T=
105C
T=
125C
Lifetime
(Years)
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
10
7
5
4.93
5.01
5.08
4.81
4.89
4.96
4.7
4.78
4.85
4.6
4.68
4.75
10
7
5
5.61
5.69
5.77
5.48
5.56
5.64
5.36
5.44
5.52
5.26
5.34
5.42
Table 12.2.7 40nm G 0.9V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
1.19
1.2
1.21
1.17
1.18
1.19
T=
105C
T=
125C
Lifetime
(Years)
1.14
1.15
1.16
1.12
1.13
1.14
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
1.35
1.37
1.4
1.27
1.3
1.32
1.21
1.23
1.25
1.15
1.17
1.2
Table 12.2.8 40nm G 1.8V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
10
7
5
2.65
2.67
2.69
2.6
2.62
2.64
T=
105C
T=
125C
Lifetime
(Years)
2.55
2.57
2.59
2.51
2.53
2.55
10
7
5
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
2.97
3
3.02
2.85
2.88
2.9
2.75
2.78
2.8
2.66
2.69
2.71
Table 12.2.9 40nm G 2.5V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.01cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
LifeTime
(Years)
T=
65C
NMOS
T=
85C
T=
105C
T=
125C
Lifetime
(Years)
T=
65C
PMOS
T=
85C
T=
105C
T=
125C
10
7
5
4.43
4.47
4.5
4.31
4.35
4.39
4.22
4.25
4.29
4.13
4.17
4.2
10
7
5
4.71
4.76
4.8
4.6
4.64
4.68
4.49
4.54
4.57
4.4
4.44
4.48
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Hot Carrier Injection Effect
Hot carriers are holes or electrons that have been accelerated to a high energy by a local electric field. Hot
carrier degradation can significantly impact circuit performance and functionality. It is important for circuit
designers to carefully check the lifetime degradation of their designs caused by hot carrier injection (HCI).
Cumulative degradation and process variation must be taken into account for burn-in, field operation, and
overdrive applications.
12.2.3.1
Lifetime Prediction Model for Device Degradation
Owing to the importance of hot carrier injection on circuit operation, customers should employ detailed models
to calculate device degradation during circuit operation and to simulate the impact on circuit operation. The
following is a general model for the degradation of device characteristics:
MTTF = A x f (L, W)  (%)1/n  exp [B  (1/Vds)]  exp [Ea/k (1/T)]
Where:
MTTF is the mean time to failure
L is the drawn channel length (unit: μm)
W is the drawn channel width (unit: μm)
egradation of an electrical parameter (for example, 10% Idsat, 10% Gm)
%
Vds is the drain to source bias (unit: volt)
n is the power law factor of time dependent degradation
Ea is the activation energy
k is the Boltzmann constant ((8.617  10-5) cV/K)
T is the absolute junction temperature (unit: K)
A and B are empirical fitting parameters
12.2.3.2
Failure Mechanism
A percentage of the energetic hot carriers will impact the lattice and create electron-hole pairs. The created
electron-hole pairs will create even more pairs later on. If the hot carriers have a kinetic energy larger than the
silicon-insulator barrier height, some of the carriers may surmount the barrier and be propelled toward the
insulator that has a moderate or higher gate bias. These carriers can either be trapped in the oxide region or
at the Si-SiO2 interface. The trapped charges from HCI stress have the following effect on the transistors:
1. Shift in the Vt (threshold voltage) of the device
2. Reduced mobility of the conducting carriers
3. Reduced device drain current
4. Increased effective series resistance, from a charge trapped above the S/D extension region
5. Degraded sub-threshold slope
These transistor changes are dependent on the amount of HCI stress that is incurred. The HCI stress in the
transistor is dependent on several factors: Lgate, Vds, Vgs, Vbs, and temperature.
Negative bias temperature stress under constant voltage (DC) causes the generation of interface trap (N IT)
before the gate oxide and Si substrate, which translate to device Vt shift and Ion loss. The NBTI effect is more
severe for PMOS than NMOS due to the process of holes in the PMOS inversion layer that are known to
interact with oxide state.
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Test Methodology
12.2.3.3.1 Measurement Conditions
1.
2.
3.
4.
Idsat is the forward saturation region drain current with Vd=Vg=Vcc, Vs=Vb=GND.
Idlin is the forward linear region drain current with Vd=0.05V, Vg=Vcc, Vs=Vb=GND.
Gm is the maximum transconductance with Vd=0.1V, Vs=Vb=GND.
Vt is the threshold voltage extrapolated at maximum transconductance.
12.2.3.3.2 Stress Conditions
The core device is stressed at Vd=Vg < 90% device breakdown voltage; Vs=Vb=GND.
The IO device is stressed at a given Vd < 90% device breakdown voltage; Vg is at the maximum substrate
current for a given Vd; Vs=Vb=GND.
12.2.3.3.3 Failure Criteria and Spec
The failure criteria for all devices are 10% degradation
Spec= AC 10 yrs
12.2.3.3.4 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for N40LP
DC Lifetime definition: 0.1% cum
N40LP
1V Core(STD): NMOS=0.212 yrs@1.21V. Vmax of NMOS=1.258V for W/L=10/0.04, 125℃
PMOS=0.21 yrs@1.21V. Vmax of PMOS=1.263V for W/L=10/0.04, 125℃
1.1V Core(LVT): NMOS=0.182 yrs@1.21V. Vmax of NMOS=1.25V for W/L=10/0.04, 125℃
PMOS=0.33 yrs@1.21V. Vmax of PMOS=1.28V for W/L=10/0.04, 125℃
1.1V Core(HVT): NMOS=0.184 yrs@1.21V. Vmax of NMOS=1.25V for W/L=10/0.04, 125℃
PMOS=0.16 yrs@1.21V. Vmax of PMOS=1.25V for W/L=10/0.04, 125℃
1.8V IO: NMOS=0.6yrs@1.98V. Vmax of NMOS= 2.04V for W/L=10/0.15, 25℃
PMOS=23yrs@1.98V. Vmax of PMOS= 2.28V for W/L=10/0.15, 25℃
2.5V IO: NMOS=3.0527yrs@2.75V. Vmax of NMOS= 3V for W/L=10/0.27, 25℃
PMOS=37.1yrs@2.75V. Vmax of PMOS= 3.87V for W/L=10/0.27, 25℃
2.5V OD 3.3V IO: NMOS=0.29yrs@3.63V. Vmax of NMOS=3.68V for W/L=10/0.55, 25℃
PMOS=1yrs@3.63V. Vmax of PMOS=3.98V for W/L=10/0.44, 25℃
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12.2.3.3.5 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for
N40LPG_LP, Vcc = 0.9V+10% and 1.0V +- 5% for N40LPG_G
DC Lifetime definition: 0.1% cum
N40 LPG
0.9 V Core(STD): NMOS=3.03 yrs@0.99V. Vmax of NMOS=1.11V for W/L=10/0.036, 105℃
PMOS=0.431 yrs@0.99V. Vmax of PMOS=1.07V for W/L=10/0.036, 105℃
0.9 V Core(LVT): NMOS=2.84 yrs@0.99V. Vmax of NMOS=1.1V for W/L=10/0.036, 105℃
PMOS=1.01yrs@0.99V. Vmax of PMOS=1.1V for W/L=10/0.036, 105℃
1.1V Core(STD): NMOS=0.3 yrs@1.21V. Vmax of NMOS=1.27V for W/L=10/0.036, 105℃
PMOS=0.37 yrs@1.21V. Vmax of PMOS=1.295V for W/L=10/0.036, 105℃
1.1V Core(HVT): NMOS=0.39yrs@1.21V. Vmax of NMOS=1.28V for W/L=10/0.036, 105℃
PMOS=0.16yrs@1.21V. Vmax of PMOS=1.26V for W/L=10/0.036, 105℃
3.3V IO: NMOS=0.226yrs@3.63V. Vmax of NMOS=3.64V for W/L=10/0.36, 25℃
PMOS=0.5yrs@3.63V. Vmax of PMOS=3.76V for W/L=10/0.36, 25℃
12.2.3.3.6 DC Lifetime and Vmax : Vcc = 0.9V +- 10% and 1.0V+- 5% for N40G
DC Lifetime definition: 0.1% cum
N40G (=N45GS)
0.9 V Core(STD): NMOS=2.29 yrs@0.99V. Vmax of NMOS= 1.1V for W/L=10/0.036, 125℃
PMOS=1.85 yrs@0.99V. Vmax of PMOS= 1.09V for W/L=10/0.036, 125℃
0.9 V Core(HVT): NMOS=1.86 yrs@0.99V. Vmax of NMOS=1.095V for W/L=10/0.036, 125℃
PMOS=0.831 yrs@0.99V. Vmax of PMOS=1.07V for W/L=10/0.036, 125℃
0.9 V Core(LVT): NMOS=3.01 yrs@0.99V. Vmax of NMOS=1.11V for W/L=10/0.036, 125℃
PMOS=2.07 yrs@0.99V. Vmax of PMOS=1.095V for W/L=10/0.036, 125℃
1.8V IO: NMOS=1.053 yrs@1.98V. Vmax of NMOS= 2.08V for W/L=10/0.135, 25℃
PMOS=23.74 yrs@1.98V. Vmax of PMOS= 2.29V for W/L=10/0.135, 25℃
2.5V IO: NMOS=5.6191 yrs@2.75V. Vmax of NMOS= 3.09V for W/L=10/0.243, 25℃
PMOS=19.3 yrs@2.75V. Vmax of PMOS= 3.5V for W/L=10/0.243, 25℃
2.5V OD 3.3V IO: NMOS=0.5219yrs@3.63V. Vmax of NMOS=3.73V for W/L=10/0.5, 25℃
PMOS=1.76yrs@3.63V. Vmax of PMOS=4.05V for W/L=10/0.4, 25℃
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Negative Bias Temperature Instability (NBTI)
Negative Bias Temperature Instability (NBTI) is a key reliability item below 65nm technology that is of newer
aging issue in p-channel MOS devices stressed with negative gate voltages. The high temperature and bias
on Gate terminal will cause significantly NBTI effect, which increase in the threshold voltage and decrease in
drain current. It is significant for circuit designers to consider the lifetime degradation ratio of their designs
caused by negative bias temperature instability (NBTI) and must be taken into account for burn-in, field
operation, and overdrive applications from process variation.
12.2.4.1
Lifetime Prediction Model for Negative Bias
Temperature Instability
The lifetime for the negative bias temperature instability (NBTI) is correlated with voltage, temperature,
parametric failure criteria, device length, and device width.
MTTF = A  f (L, W)  (Idsat%)1/n  exp [- xVg]  exp [Ea/k (1/T)]
Where:
MTTF is the mean time to failure
L is the drawn channel length (unit: μm)
W is the drawn channel width (unit: μm)
Idsat
dsat degradation percentage
n is the power law factor of time dependent degradation
Vg is the operation gate bias (unit: volt)
 is the voltage acceleration factor
Ea is the activation energy
k is the Boltzmann constant ((8.617  10-5) cV/K)
T is the absolute junction temperature (unit:K)
A is a constant
12.2.4.2
Lifetime Prediction Model for AC
For an acceptable specification, the AC lifetime must be considered. Currently, TSMC’s proposed standard
is an AC-to-DC factor of 2, based on the assumption that the off-state operation occupies half the product’s
operation time. The accepted AC lifetime is 10 years, with a DC lifetime of 5 years at temperature 125C.
12.2.4.3
Failure Mechanism
The PMOS device has a lower mobility than the NMOS device. Mobility for a PMOS device is decreased
further, and significantly, by negative bias stress on the transistor gate under a high temperature environment.
A hole injected under negative bias into the oxide-substrate interface increases interface states. The
electrochemical reaction induces device instability that is enhanced by boron implanted in the gate poly
engineering process. Logic circuits could suffer from the driving current decrease, and analog circuits could
suffer from the mismatching or shift of threshold voltage.
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Test Methodology
12.2.4.4.1 Measurement Condition
Idsat is the saturation region of drain current with Vd=Vg=Vcc, Vs=Vb=GND at a stress temperature.
12.2.4.4.2 Stress Conditions
1. Sample size is at least 5 samples for each stress condition.
2. Voltage range is 6~ 10MV/cm for core devices and 6 ~ 10 MV/cm for I/O devices.
3. Temperature range is 75°C ~ 125°C.
12.2.4.4.3 Failure Criteria
The failure criterion for NBTI is Idsat 10% degradation for N40LP/N40LPG/N40G SVT/LVT device, and 15%
for N40LP/N40LPG/N40G HVT device.
Spec=DC 5 years, AC/DC factor=2
12.2.4.4.4 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for N40LP
DC Lifetime definition: 0.1% cum
N40LP
1.1V Core(SVT): PMOS=9.88yrs@1.21V. Vmax of PMOS= 1.24V for W/L=10/0.04, 125℃
1.1V Core(HVT): PMOS=12.7rs@1.21V. Vmax of PMOS=1.259V for W/L=10/0.04, 125℃
1.1V Core(LVT): PMOS=34.7yrs@1.21V. Vmax of PMOS= 1.297V for W/L=10/0.04, 125℃
1.8V IO: PMOS=6.82 yrs@1.98V. Vmax of PMOS=2V for W/L=10/0.15, 125℃
2.5V OD 3.3V IO: PMOS=11.5yrs@2.75V. Vmax of PMOS=3.755V for W/L=10/0.44, 125℃
2.5V IO: PMOS=374yrs@2.75V. Vmax of PMOS= 3.466V for W/L=10/0.27, 125℃
12.2.4.4.5 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for
N40LPG_LP, Vcc = 0.9V+10% and 1.0V +- 5% for N40LPG_G
DC Lifetime definition: 0.1% cum
N40LPG
0.9 V Core(SVT): PMOS=9.09 yrs@0.99V. Vmax of PMOS=1.02V for W/L=10/0.036, 105℃
0.9 V Core(LVT): PMOS=64.3 yrs@0.99V. Vmax of PMOS=1.12V for W/L=10/0.036, 105℃
1.1V Core(SVT): PMOS=11.8yrs@1.21V. Vmax of PMOS=1.257V for W/L=10/0.036, 105℃
1.1V Core(HVT): PMOS=5.48yrs@1.21V. Vmax of PMOS=1.215V for W/L=10/0.036, 105℃
3.3V IO: PMOS=104 yrs@3.63V. Vmax of PMOS=4.235V for W/L=10/0.36, 105℃
12.2.4.4.6 DC Lifetime and Vmax : Vcc = 0.9V +- 10% and 1.0V+- 5% for N40G
DC Lifetime definition: 0.1% cum
N40G(N45GS)
0.9 V Core(STD): PMOS=17 yrs@0.99V. Vmax of PMOS= 1.048V for W/L=10/0.036, 125℃
0.9 V Core(HVT): PMOS=218 yrs@0.99V. Vmax of PMOS=1.152V for W/L=10/0.036, 125℃
0.9 V Core(LVT): PMOS=68.1 yrs@0.99V. Vmax of PMOS=1.105V for W/L=10/0.036, 125℃
1.8V IO: PMOS=13.8 yrs@1.98V. Vmax of PMOS= 2.078V for W/L=10/0.135, 125℃
2.5V IO: PMOS=256 yrs@2.75V. Vmax of PMOS= 3.425V for W/L=10/0.243, 125℃
2.5V OD 3.3V IO: PMOS=14.2 yrs@3.63V. Vmax of PMOS=3.682V for W/L=10/0.4, 125℃
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N40 Poly Current Density
The maximum current density for poly resistor (unsilicided) is 0.50 * (Wp*0.9) mA at a junction temperature of
110C. This density is calculated using 0.1% point of measurement data at a 5% resistance increase after
100K hours of continuous operation. Wp (in μm) represents the drawn width of poly line.
Use the following table to calculate Imax if the junction temperature differs from 110C.
temperature below 105C, use the rule at 105C.
For a junction
Table 12.2.5.1
Junction temperature
Rating factor of Jmax
105C
1.03
110C
1.00
125C
0.927
For example, Imax (at 125C) = 0.927  Imax (at 110C).
This rule is applicable to N+, and P+ unsilicided poly resistors.
For silicided poly, the maximum DC current density is 6 * (Wp*0.9) mA at a junction temperature of 110C.
This density is calculated using 0.1% point of measurement data at a 5% resistance increase after 100K
hours of continuous operation. Wp (in μm) represents the drawn width of poly line.
12.2.6
N40 Poly EM Joule heating
12.2.6.1
Irms current
The following table (Table 12.2.6.1) provides Irms for poly. In this table, Wp (in μm) represents the drawn width
of poly line and ∆ T (C) is the temperature rise due to Joule heating effect.
Table 12.2.6.1, Wp: poly drawn width
poly
unsilicided
silicided
Irms (mA)
Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]
Table 12.2.6.2 Example for the relationships of Irms(mA), poly width(μm), and joule heating effect (∆T)
Poly width (μm)
0.04
0.5
1
3
Irms for unsilicided poly(mA), Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
ΔT=10 ℃
ΔT=20 ℃
ΔT=30 ℃
ΔT=40 ℃
ΔT=50 ℃
0.038
0.054
0.066
0.076
0.085
0.162
0.230
0.281
0.325
0.363
0.266
0.376
0.461
0.532
0.595
0.655
0.927
1.135
1.310
1.465
ΔT=60 ℃
0.093
0.398
0.652
1.605
Poly width (μm)
0.04
0.5
1
3
Irms for silicided poly (mA), Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]
ΔT=10 ℃
ΔT=20 ℃
ΔT=30 ℃
ΔT=40 ℃
ΔT=50 ℃
0.332
0.470
0.576
0.665
0.743
1.329
1.880
2.303
2.659
2.973
2.092
2.958
3.623
4.183
4.677
4.817
6.812
8.343
9.634
10.771
ΔT=60 ℃
0.814
3.256
5.123
11.799
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Ipeak
The following table provides the Ipeak allowed for poly, In the table, Wp (in μm) represents the drawn width of
poly line.
Table 12.2.6.3
poly
Ipeak (mA)
unsilicided
1.5* Wp
silicided
26* Wp
Ipeak is the current at which a poly line undergoes excessive Joule heating and can begin to melt. This
current should be used infrequently.
12.2.7
N40 OD Current Density
For diffusion (OD) unsilicided resistors and/or silicided interconnect, no Imax rule is given. Since diffusion
(OD) is crystalline silicon with implantation, no electromigration or Joule heating problems occur. If the
design follows contact, metal, and via current density rules, there will be no reliability concern for diffusion
(OD).
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12.3
Back-End Process Reliability Rules
12.3.1
Stress Migration (SM)
The Cu vias are frequently subjected to significant stress. The stress frequently causes voids, commonly
referred to stress migration (SM) or stress-induced voids (SIV).
12.3.1.1
Failure Mechanism
The stress result from the different coefficient of thermal expansion (CTE) between Cu and the surrounding
material will drive micro-vacancy in Cu to diffuse and agglomerate through interfacial surface and grain
boundary. Eventually the stress-induced voids may significantly affect the electrical characteristics and may
cause the semiconductor structure to fail.
12.3.1.2
Test Methodology
12.3.1.2.1 Measurement Condition
The measurement is performed under 25 C using wafer-level probing after oven bake. The baking
temperature ranges between 125C and 250C.
12.3.1.2.2 Failure Criteria
A DUT is considered as failed if 10% resistance increase is reached.
12.3.1.3
SM design rule
Please refer to below rule codes of chapter 4.
VIAx.R.2, VIAx.R.3, VIAx.R.4, VIAx.R.5, VIAx.R.6, , VIAxR.8, VIA.x.R.11, VIAy.R.2, VIAy.R.3, VIAy.R.4,
VIAy.R.5, VIAy.R.6, VIAy.R.11, VIAz.R.2, VIAz.R.3, VIAr.R.2, VIAr.R.3
12.3.2
Low-k Dielectric Integrity
This section provides information to help customers predict LK dielectric reliability and prevent a time
dependent dielectric breakdown (TDDB). IMD TDDB is the breakdown of LK dielectric induced by a
combination of operation voltage, temperature, and oxide thickness.
12.3.2.1
Low-k Dielectric Lifetime Prediction Model
TTF = A x exp(-r*E0.5) x exp(Ea/kT)
TTF : Time to Failure
A: a constant
r: field acceleration factor
E: electric field
Ea: activation energy
k: Boltzman’s constant
T: temperature
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Failure Mechanism
While the current passed through LK dielectric and formed a conduction path, it would result in LK dielectric
breakdown.
The possible failure mechanisms after IMD-TDDB test could be as followings.
1. Dielectric interface breakdown (ie: LK dielectric porosity, ESL integration, Cu ions residue…etc.)
2. Dielectric bulk breakdown (ie: trench barrier formation, LK dielectric porosity…etc.)
12.3.2.3
Test Methodology
12.3.2.3.1 Measurement Conditions
1. Ig is the leakage current between metal lines at T=125C under Ed (constant stress field).
2. Ed is set to 2 ~ 4 MV/cm.
12.3.2.3.2 Failure Criteria
A DUT is considered as failed if Ig (Tbd) > 100 * Ig (T0).
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Cu Metal Current Density (EM) Specifications
This section provides information to evaluate the quality of N40 Cu process and to determine the EM lifetime
of metal line, via, stack via, contact under normal operation condition.
12.3.3.1
Electromigration Lifetime Prediction Model
TTF = A x J^(-n) x exp(Ea/kT)
TTF : Time to Failure
A: a constant which contains a factor involving the cross-sectional area of the film
n: exponent of current density ( n =1 )
J: current density flowing in metal
Ea: activation energy ( Ea =0.9eV)
k: Boltzman’s constant
T: temperature
12.3.3.2
Failure Mechanism
When a stress current is applied, Cu ions move from cathode to anode under electromigration, vacancy will
generate at cathode and it will cause resistance increasing.
12.3.3.3
Failure Criteria
A DUT is considered as failed if 10% resistance increase is reached.
12.3.3.4
Rating factor for Maximum DC Current
Imax is the maximum DC current allowed for metal lines, vias, or contacts. Imax is based on 0.1% point of
measurement data at a 10% resistance increase after 100K hours of continuous operation at 110C. Use the
following table to calculate Imax if the junction temperature differs from 110C.
Table 12.3.3.4.1
Temperature
Rating factor of Imax
105C
1.434
110C
1.000
115C
0.704
120C
0.500
125C
0.358
For example, Imax (at 125C) = 0.358  Imax (at 110C).
The rating factor is 2.077 for the case of temperature below 100°C for Joule heating effect consideration.
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Maximum DC Current for Metal Lines, Contacts
and Vias (Tj = 110C)
12.3.3.5.1 General
The table provides the maximum allowed DC current, Imax for each of the metals, contacts, and vias at junction
temperature of 110C. In the table, w (in m) represents the width of the drawn metal line.
Table 12.3.3.5.1
Metal Wiring Level / Interlevel connection
Imax (mA)
M1
1.227  (w x0.9-0.008)
Mx
My (2nd inter-layer metal)
My (2XTM)
Mz
Mr
Mu
1.329  (w x0.9-0.008)
3.040  (w x0.9-0.02)
3.040  (w x0.9-0.02)
9.048  (w x0.9-0.02)
12.631  (w x0.9-0.02)
34.59 X (w x0.9-0.02)
Contact (size: 0.054x0.054 μm2)
0.208 per contact
VIAx (size : 0.063  0.063 μm2)
0.072 per via
VIAy (2nd inter-layer metal) (size : 0.126  0.126 μm2)
0.322 per via
VIAy (2XTM) (size : 0.126  0.126 μm2)
0.322 per via
VIAz (size : 0.324  0.324 μm2)
3.077 per via
VIAr (size : 0.414  0.414 μm2)
5.432 per via
VIAu (size : 0.324  0.324 μm2)
3.077 per via
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12.3.3.5.2 Imax dependence on metal length (length ≤ 10m)
For a metal line with a length ≤ 10 m, the Imax current limit can be further increased by a factor of 1.5 for 10 ≥
L > 5 and a factor of 4 for L ≤ 5. The detailed Imax specs for various metal lines and vias are described in Table
12.3.3.5.2. In this table, w represents the width of the metal line in m, while L represents the length of the
metal line in m. The junction temperature for these specs is 110°C.
Table 12.3.3.5.2
Metal Wiring Level / Interlevel connection
Metal Length, L (m)
L > 10
M1
Mx
My (2nd inter-layer metal)
My (2XTM)
Mz
Mr
Mu
VIAx (size : 0.063  0.063
μm2)
VIAy (2nd inter-layer metal) (size : 0.126 x 0.126 μm2)
VIAy (2XTM) (size : 0.126 x 0.126 μm2)
VIAz (size : 0.324  0.324 μm2)
VIAr (size : 0.414  0.414 μm2)
VIAu (size : 0.324 0.324 μm2)
Imax (mA)
1.227  (w x0.9-0.008)
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
1.5  1.227  (w x0.9-0.008)
4  1.227  (w x0.9-0.008)
1.329  (w x0.9-0.008)
1.5  1.329  (w x0.9-0.008)
4  1.329  (w x0.9-0.008)
3.040  (w x0.9-0.02)
1.5  3.040  (w x0.9-0.02)
4  3.040  (w x0.9-0.02)
3.040  (w x0.9-0.02)
1.5  3.040  (w x0.9-0.02)
4  3.040  (w x0.9-0.02)
9.048  (w x0.9-0.02)
1.5  9.048  (w x0.9-0.02)
4  9.048  (w x0.9-0.02)
12.631  (w x0.9-0.02)
1.5  12.631  (w x0.9-0.02)
4  12.631  (w x0.9-0.02)
34.590  (w x0.9-0.02)
34.590  (w x0.9-0.02)
34.590  (w x0.9-0.02)
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
L > 10
10 ≥ L > 5
L≤5
1.5  0.072 per via
4  0.072 per via
0.322 per via
1.5  0.322 per via
4  0.322 per via
0.322 per via
1.5  0.322 per via
4  0.322 per via
3.077 per via
1.5  3.077 per via
4  3.077 per via
5.432 per via
1.5  5.432 per via
4  5.432 per via
3.077 per via
3.077 per via
3.077 per via
0.072 per via
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Note: The current enhancement factors (the coefficients in the column of “Imax (mA)”) described in Table
12.3.3.5.2 (length dependence) and Table 12.3.3.5.3 (width dependence) should not be multiplied
together because multiplying them together would be too aggressive. Only one enhancement factor from
either Table 12.3.3.5.2 or Table 12.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
(1) Metal Length Definition (L):
The total length of metal wiring level is from one line-end site to another site line-end site of metal.
L
L
L
M x+ 1
M x+ 1
Vx
Vx
M x+ 1
Vx
M x
L
(2) For the Via length rule, use whichever L is larger between upper_metal and lower_metal.
If L1 is larger than L2, Imax of via for short length is based on L1.
If L2 is larger than L1, Imax of via for short length is based on L2.
L2
M x+ 1
Vx
Mx
L1
For example : Via1 connect to 10um-length M1 and 5um-length M2.
Imax of M1 = 1.5 x1.227 x (wx0.9-0.008)
Imax of M2 = 4x 1.329 x (wx0.9-0.008)
Imax of Via1= 1.5 x0.072
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12.3.3.5.3 Imax dependence on metal width (width ≥ 0.5µm)
For a metal line with a width ≥ 0.5 m, the Imax current limit is improved by a factor of 2 compared with a
corresponding narrow metal line (w < 0.5). The detailed Imax specs for various metal lines and vias are
described in Table 12.3.3.5.3. In this table, w represents the width of the metal line in m. The junction
temperature for these specs is 110°C.
Table 12.3.3.5.3
Metal Wiring Level / Interlevel connection
M1
Mx
My (2nd inter-layer metal)
My (2XTM)
Imax (mA)
Metal Length, L (m)
w ≥ 0.5
1.227  (wx0.9-0.008)
2 x 1.227  (wx0.9-0.008)
w < 0.5
w ≥ 0.5
1.329  (wx0.9-0.008)
2 x 1.329  (wx0.9-0.008)
w < 0.5
3.040  (wx0.9-0.02)
2 x 3.040  (wx0.9-0.02)
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
w < 0.5
3.040  (wx0.9-0.02)
2 x 3.040  (wx0.9-0.02)
w ≥ 0.5
9.048  (wx0.9-0.02)
2 x 9.048  (wx0.9-0.02)
Mr
w ≥ 0.5
2 x 12.631  (wx0.9-0.02)
Mu
w ≥ 2.0
1 x 34.590  (wx0.9-0.02)
Contact (size: 0.054x0.054 μm2)
Any metal width
VIAx (size : 0.063  0.063 μm2)
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
0.072 per via
2 x 0.072 per via (Array)
0.322 per via
2 x 0.322 per via (Array)
w < 0.5
w ≥ 0.5
w < 0.5
w ≥ 0.5
3.077 per via
2 x 3.077 per via (Array)
5.432 per via
2 x 5.432 per via (Array)
Mz
VIAy (2nd inter-layer metal) (size : 0.126 x 0.126 μm2)
VIAy (2XTM) (size : 0.126 x 0.126 μm2)
VIAz (size : 0.324  0.324 μm2)
VIAr (size : 0.414  0.414 μm2)
VIAu (size : 0.324  0.324 μm2)
w < 0.5
w ≥ 0.5
0.208 per contact
0.322 per via
2 x 0.322 per via (Array)
3.077 per via
1 x 3.077 per via (Array)
Note: The current enhancement factors (the coefficients in the column of “Imax (mA)”) described in Table
12.3.3.5.2 (length dependence) and Table 12.3.3.5.3 (width dependence) should not be multiplied
together because multiplying them together would be too aggressive. Only one enhancement factor
from either Table 12.3.3.5.2 or Table 12.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
The maximum allowed current for per via can be raised together with this wide metal EM rule (w ≧ 0.5) but
via-array is needed.
Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
current flow) must be maximized to increase reliability by providing redundancy in the case of blocked or
resistive vias. ( increases as much as the line width permits).
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Required vias
Wide Line
Recommended
Wide Line
12.3.3.5.4 Stacked Vias
Stacked via can decompose to single via, and follow single via rule.
12.3.3.5.5 DC Operation, Required Number of Vias
(1) If space permits, it is preferable to have more contacts or vias than the EM rules require.
(2) At a minimum rule, the EM current rules require one via.
(a) Example 1, if M1 is 0.07 μm (drawn width) and the current density is 1.227 mA/μm; that is, the current
is 1.227*(0.07*0.9-0.008) = 0.067 mA, only one VIA1 is necessary to ensure the reliability margin.
(b) Example 2, if M2 is 0.07 μm (drawn width) and the current density is 1.329 mA/μm; that is, the current
is 1.329*(0.07*0.9-0.008) = 0.072 mA, only one VIA1 and one VIA2 are necessary to ensure the
reliability margin.
(3) To determine the required number of vias, please proceed as follow:
(a) From the DC current given in section 12.3.3.5, determine the necessary line width (W-line);
(b) Calculate the Maximum allowed Idc_line for the given line width (W-line).
(c) Calculate the required number of contacts or vias to carry line current Idc_line: Number of vias =
Idc_line/ Idc_via.
(4) Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
current flow) must be maximized to increase reliability by providing redundancy in the case of blocked or
resistive vias. (increases as much as the line width permits).
Narrow Line
Narrow Line
Narrow Line
Narrow Line
Required vias
Wide Line
Recommended
Wide Line
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AP RDL Current Density (EM) Specifications
12.3.4.1
Maximum DC Current
Jmax is maximum DC current allowed per um of AP RDL metal line width or per RV via. The number is based
on 0.1% point of measurement data at 10% resistance increase after 100K hours of continuous operation at
110C. Use the following table to calculate Imax if the junction temperature differs from 110C.
Table 12.3.4.1
Temperature
Rating factor of Imax
85C
1.800
90C
1.623
95C
1.466
100C
1.329
105C
1.151
110C
1.000
115C
0.872
120C
0.764
125C
0.671
For example, Jmax (at 125C) = 0.671  Jmax (at 110C).
If the junction temperature is below 85C, please use the rating factor (1.800) at 85C or contact with TSMC
reliability.
12.3.4.2
Maximum DC Current for AP RDL Metal Lines (Tj =
110C)
The table provides the maximum allowed DC current, Imax for each of the metal wiring levels at junction
temperature of 110C. In the table, w (in μm) represents the drawn width of the metal line.
Table 12.3.4.2
Metal Wiring Level
Imax (mA)
AP RDL (14.5KÅ )
3.0  wx0.9
AP RDL (28KÅ )
5.79  wx0.9
12.3.4.3
Maximum DC Current for AP RDL (RV) Vias (Tj =
110C)
The table provides the maximum allowed DC current, Imax for each of the contact and via at junction
temperature of 110C. In the table, the drawn sizes of contact and via are also noted.
Table 12.3.4.3
Interlevel Connection
Imax (mA)
Size
RV
12.15
per RV
3  3 μm
2
RV
5.4
per RV
2  2 μm
2
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Cu Metal AC Operation
12.3.5.1
Pulsed Signal Terminology
The general terminology for a pulsed DC or AC signal is:
Period ()
Duration (tD)
For your convenience, you could measure the pulse width of Ipeak at half the peak to define the duration (tD).
The definition of Ipeak is:
 max
I peak
 I (t ) 
I (t)
I (t)
Ipeak
Ipeak 
1/2 Ipeak
tD
Time, t
duration
Time, t
tD
duration
, period
12.3.5.2
, period
Average Value of the Current
Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to
Imax rules. Please refer to the DC EM sections. The temperature de-rating table is also applicable to the Iavg
rule for a junction temperature different from 110C.
The definition of Iavg is:
I avg


 

  I ( t ) dt  / 

  0

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Root-Mean-Square Current
Irms is the root-mean-square of the current through a metal line. The definition of Irms is:
I rms
2
 


 
I ( t ) dt  / 

  0


1/2
The following tables provide the Irms allowed for each of the metal wiring levels at a junction temperature of
110C. In the table, w (in μm) represents the drawn width of the metal line and ∆T (C) is the temperature rise
due to Joule heating.
Note to use Irms ∆T limitation:
The EM lifetime is a function of temperature and current density. The higher temperature will cause EM lifetime
degradation. Table 12.3.5.3 is the degradation factor for EM lifetime. The recommend temperature increase,
∆T is below < 5 °C. Because a 5 °C temperature increase is sufficient to degrade the EM lifetime by about
30%.
Table 12.3.5.3
∆T
Temp
TTF
110C
1
5C
115C
0.704
10C
120C
0.500
15C
125C
0.358
20C
130C
0.258
30C
140C
0.138
For M1MxMz combination, please refer to sections 12.3.5.3.1 and 12.3.5.3.2.
For M1MxMyMz, M1MxMr, and M1MxMy combinations, please refer to sections 12.3.5.3.3, 12.3.5.3.4,
12.3.5.3.5, and 12.3.5.3.6.
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12.3.5.3.1 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMz
process, no My)
Table 12.3.5.3.1.1
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.79  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
4.04  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.264 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Table 12.3.5.3.1.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
 (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
92.9
]
25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
23.95  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
20.20  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.264 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
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12.3.5.3.2 Root-Mean-Square Current for LK Dielectrics (other metallization
options, M1MxMz process, no My)
Table 12.3.5.3.2.1 and Table 12.3.5.3.2.2 apply to 1P8M process. For other metallization options, please use
Irms of M9 and M10 as the first and second Mz, respectively.
For example, 1P8M with M2 ~ M7 as Mx, and M8 as Mz, the Irms rules are:
Table 12.3.5.3.2.1
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.79  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Another example, 1P8M with M2 ~ M6 as Mx, M7 and M8 as Mz, the Irms rules are:
Table 12.3.5.3.2.2
Metal level
M1
M2
M3
M4
M5
M6
M7
M8
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.79  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
4.04  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.264 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
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12.3.5.3.3 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMz
process)
Table 12.3.5.3.3.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
My2
Mz1
Mz2
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
1.46  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
3.63  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Table 12.3.5.3.3.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
Irms (mA)
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
My2
Mz1
Mz2
92.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
]
]
13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9- 0.008 + 0.0443 ) ]
9.00  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
7.30  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
21.10  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
18.15  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 )
If the metal scheme is 1P10M with M1 + 5x2y2z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1 ~ Mz2.
If the metal scheme is 1P10M with M1 + 6x1y2z, then use Mx1 ~ Mx6, My1, and Mz1 ~ Mz2
If the metal scheme is 1P9M with M1 + 5x2y1z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1.
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12.3.5.3.4 Root-Mean-Square Current for LK Dielectrics (other metallization
options, M1MxMyMz process)
Table 12.3.5.3.4.1 and Table 12.3.5.3.4.2 apply to 1P10M process. For other metallization options, please use
Irms of M9 and M10 as the first and second Mz, respectively. Please refer to the section 2.5 of Metallization
Options for allowed metal schemes.
For example, 1P10M with M1 + 5x2y2z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 ~ M10 as Mz), the Irms
rules are:
Table 12.3.5.3.4.1
Metal level
M1
M2 (Mx1)
M3 (Mx2)
M4 (Mx3)
M5 (Mx4)
M6 (Mx5)
M7 (My1)
M8 (My2)
M9 (Mz1)
M10 (Mz2)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Irms (mA)
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
1.46  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
3.63  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Another example, 1P10M with M1 + 6x1y2z (M2 ~ M7 as Mx, M8 as My, and M9 ~ M10 as Mz), the Irms rules
are:
Table 12.3.5.3.4.2
Metal level
M1
M2 (Mx1)
M3 (Mx2)
M4 (Mx3)
M5 (Mx4)
M6 (Mx5)
M7 (Mx6)
M8 (My1)
M9 (Mz1)
M10 (Mz2)
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
3.63  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
One more example, 1P9M with M1 + 5x2y1z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 as Mz), the Irms rules
are:
Table 12.3.5.3.4.3
Metal level
M1
M2 (Mx1)
M3 (Mx2)
M4 (Mx3)
M5 (Mx4)
M6 (Mx5)
M7 (My1)
M8 (My2)
M9 (Mz1)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Irms (mA)
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
1.46  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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12.3.5.3.5 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMr
process)
Table 12.3.5.3.5.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
Mr1
Mr2
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
6.54  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.944 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
5.27  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.413 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Table 12.3.5.3.5.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
Irms (mA)
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
Mr1
Mr2
92.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
]
25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
32.70  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.944 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
26.35  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.413 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x2r, then use Mx1 ~ Mx7, and Mr1 ~ Mr2.
If the metal scheme is 1P9M with M1 + 6x2r, then use Mx1 ~ Mx6, and Mr1 ~ Mr2
If the metal scheme is 1P9M with M1 + 7x1r, then use Mx1 ~ Mx7, and Mr1.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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12.3.5.3.6 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMy
process, My/Vy are used as 2X top Metal/Via)
Table 12.3.5.3.6.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1_TM
My2_TM
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.72  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
1.61  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.954 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Table 12.3.5.3.6.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
Irms (mA)
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1_TM
My2_TM
92.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
]
25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
8.60  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
8.05  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.954 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x2y, then use Mx1 ~ Mx7, and My1_TM ~ My2_TM.
If the metal scheme is 1P9M with M1 + 6x2y, then use Mx1 ~ Mx6, and My1_TM ~ My2_TM.
If the metal scheme is 1P9M with M1 + 7x1y, then use Mx1 ~ Mx7, and My1_TM.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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12.3.5.3.7 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMzMu
process, Mu/Vu are used as top Metal/Via)
Table 12.3.5.3.7.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
Mz1
Mu1
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
4.25  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.034 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
14.28  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.423 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Table 12.3.5.3.7.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My1
Mz1
Mu1
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
92.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
9.00  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
21.25  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.034 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
71.40  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.423 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1z1u, then use Mx1 ~ Mx7, Mz1, and Mu1.
If the metal scheme is 1P9M with M1 + 5x1y1z1u, then use Mx1 ~ Mx5, My1, Mz1, and Mu1.
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My1, and Mu1.
If the metal scheme is 1P6M with M1 + 4x1u, then use Mx1 ~ Mx4, and Mu1.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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12.3.5.3.8 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMu
process, My/Vy are 2XTM, Mu/Vu are used as top Metal/Via)
Table 12.3.5.3.8.1
Metal level
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My_TM
Mu1
Irms (mA)
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
1.72  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
16.47  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.100 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Table 12.3.5.3.8.2 Example Root-Mean-Square Current for ∆T = 5C
Metal level
Irms (mA)
M1
Mx1
Mx2
Mx3
Mx4
Mx5
Mx6
Mx7
My_TM
Mu1
92.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
Sqrt [
]
25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
8.60  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
82.35  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.100 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1y1u, then use Mx1 ~ Mx7, My_TM, and Mu1.
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My_TM, and Mu1.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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Document No.
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: 2.6
Peak Current
Ipeak = max ( | I(t) | )
Ipeak is the current at which a metal line undergoes excessive Joule heating and can begin to melt. This current
should be used infrequently.
The limit for the peak current, Ipeak, can be calculated by using the following formula:
I peak

I peak
_ DC
r
Note: the above equation is only applicable for frequency larger than 1 MHz and r larger than 0.05.
r is the duty ratio, which is equal to the pulse duration divided by the period,
r

tD

where Ipeak_DC is provided in the following table. In the table, w (in μm) represents the drawn width of the metal
line.
Table 12.3.5.4
Metal Level
M1
Mx
My (2nd inter-layer metal)
My (2XTM)
Mz
Mr
Mu
Ipeak_DC (mA)
25.0  (w x0.9 -0.008)
14.0  (w x0.9 -0.008)
18.0  (w x0.9 -0.020)
21.0  (w x0.9 -0.020)
63.0  (w x0.9 -0.020)
87.5  (w x0.9 -0.020)
202.8  (w x0.9 -0.020)
The Ipeak rule applies to the periodic AC or pulsed DC signals.
For a single event high current pulse or signals which cannot be specified by duty ratio, please follow the ESD
guidelines.
The Ipeak rules provided in this section are applicable to signals with a pulse width (tD) of less than 1sec. No
temperature adjustment factor for the Irms and Ipeak is given.
The Irms and Ipeak of contacts and vias do not include because the heating in contacts and vias is negligible and
is usually determined by metal or substrate. If the metal width is increased to some extent and only one via is
used in that metal, then the heating in the via cannot be considered negligible. However, if the design follows
the SM rules, via heating can be negligible.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: 2.6
AP RDL AC Operation
The general terminology for AP RDL is the same as Cu interconnects.
The following tables provides the maximum Irms allowed for AP RDL at a junction temperature of 110C. In the
table, w (in μm) represents the drawn width of the RDL line and ∆T (C) is the temperature rise due to Joule
heating.
Table 12.3.6
Metal level
AP RDL (14.5KÅ )
AP RDL (28KÅ )
Irms (mA)
Sqrt [
Sqrt [
2.54
4.90
 ∆ T  w x0.9  ( w x0.9 + 2.924 ) ]
 ∆ T  w x0.9  ( w x0.9 + 2.924 ) ]
The Ipeak rule for AP RDL (14.5KÅ ) is 58 mA/um.
The Ipeak rule for AP RDL (28KÅ ) is 112 mA/um.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
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: T-N45-CL-DR-001
: 2.6
13 Appendix A Revision History
A.1 From Version 0.1 to 0.2
Rule
Sec. No.
1.1
1.2
2.1.1
2.1.1
2.1.2
2.1.2
2.3
2.4
Section Title
Overview
Reference Documentation
Front-End Features
Front-End Features
Front-End Features
Front-End Features
Power Supply and Operation
Temperature Ranges
Cross–section
2.4
Cross–section
2.5
Metallization Options
2.5
Metallization Options
3.1
Mask Information, Key Process
Sequence, and CAD Layout
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
Revision Description
Remove 3.3V device
Add MM/RF rules refere to·
Remove 3.3V device
Add SRAM size of DP and HC
Remove metal thickness
Change AL RDL to AP RDL
Remove 3.3V device
T-N45-CM-DR-001
Modify VIAy W/S to 0.14/0.14 from 0.13/0.15 in Figure 2.4.2 Crosssection for 1P10M_7x2y
Modify VIAy W/S to 0.14/0.14 from 0.13/0.15 in Figure 2.4.3 Crosssection for 1P10M_5x2y2z
Modify Mask layer to “seven” from”six” in Table 2.5.1 Naming for
Different Metal Thicknesses
Modify Mask layer to “seven” from”six” in Table 2.5.2 Naming for
Different Metal Thicknesses
Remove 3.3V device
Modify mask tone of 191, 152, and 118 from clear todark.
Remove 3.3V at Description of mask 193.
Remove 3.3V at Description of mask 194.
Remove 3.3V at Description of mask 152.
Remove 3.3V at Description of mask 116.
Remove 3.3V at Description of mask 115.
Change CAD Layer to 117 from drived at mask 111.
Change 308 mask name to CB2 from CB, change mask ID to 107 from
308, change CAD layer to 86;20 from 76 at option 1.
Change 308 mask name to CB2 from CB, change mask ID to 107 from
308, change CAD layer to 86;0 from 76 at option 2.
3.1
Mask Information, Key Process
Sequence, and CAD Layers
Remove “FW” at Reference Layer in Logical Operation of mask 306,
change CAD layer to 86;20 from 86 at option 3.
3.1
Mask Information, Key Process
Sequence, and CAD Layers
Remove “FW” at Reference Layer in Logical Operation of mask 306,
change CAD layer to 86;0 from 86 at option 4.
3.1
Mask Information, Key Process
Sequence, and CAD Layers
Change VIAy mask type to ASF from DSF in Table 3.1.2 Mask
Name/ID/Grade/Type, OPC, and PSM Information
3.4
Special Recognition CAD Layer
Summary
Add OD25_33 for 2.5V thick oxide (second gate oxide) overdrive to
3.3V
3.4
Special Recognition CAD Layer
Summary
Add OD25_18 for 2.5V thick oxide (second gate oxide) underdrive to
1.8V
3.4
Special Recognition CAD Layer
Summary
Modify Associated With of RH to “OD and PO resistor rules” from
“guideline”.
3.4
Special Recognition CAD Layer
Summary
Modify TSMC Default CAD Layer to 161;0 from 161, and remove “Also
serves as an exclusion layer for dummy feature insertion checks.”
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_1 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_2 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_3 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_4 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
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whole or in part without prior written permission of TSMC.
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Section Title
Revision Description
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_5 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_6 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_7 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_8 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_9 for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add MOMDMY_AP for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add TCDDMY for MOM Dummy layer rule at Table 3.4.1 Special Layer
Summary
3.4
Special Recognition CAD Layer
Summary
Add RFIP_DMY for MOM Dummy layer rule at Table 3.4.1 Special
Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add IP for MOM Dummy layer rule at Table 3.4.1 Special Layer
Summary
3.4
Special Recognition CAD Layer
Summary
Add ROM for ROM device at Table 3.4.1 Special Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add LUPWDMY for waiving latch up rules at Table 3.4.1 Special Layer
Summary
3.4
Special Recognition CAD Layer
Summary
Add ESDIMP for ESD implant. at Table 3.4.1 Special Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add DFMEXCL at Table 3.4.1 Special Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add COROM at Table 3.4.1 Special Layer Summary
3.4
Special Recognition CAD Layer
Summary
Add VIAxEXCL at Table 3.4.1 Special Layer Summary
3.5.1
General Purpose Superb (N45GS):
0.9V Core Design
General Purpose Superb (N45GS):
0.9V Core Design
General Purpose Superb (N45GS):
0.9V Core Design
General Purpose Superb (N45GS):
0.9V Core Design
Design Grid Rules
OPC Recommendations and
Guidelines
Derived Geometries
Minimum Pitches
Minimum Pitches
Minimum Pitches
Gate Oxide and Diffusion (OD) Layout
Rules (120)
Gate Oxide and Diffusion (OD) Layout
Rules (120)
OD Layout Rules
OD Layout Rules
OD Layout Rules
3.5.1
3.5.1
OPC.R.1®
: T-N45-CL-DR-001
: 2.6
Sec. No.
3.5.1
G.5
Document No.
Version
3.7.1
3.7.2
OD.W.1®
4.2.1
4.4
4.4
4.4
4.5.1
OD.W.2
4.5.1
OD.W.2.1
OD.W.2.2
OD.A.1
4.5.1
4.5.1
4.5.1
OD.L.1
OD.L.2
OD.L.2gU
DNW.EN.3
4.5.1
4.5.1
4.5.1
4.5.2
Remove 3.3 device at Table 3.5.2 Device Truth Table for general
purpose superb
Modify 1.1V Varactor to “*” from “0” at Table 3.5.2 Device Truth Table
for general purpose superb
Modify 1.8V Varactor to “*” from “0” at Table 3.5.2 Device Truth Table
for general purpose superb
Modify 2.5V Varactor to “*” from “0” at Table 3.5.2 Device Truth Table
for general purpose superb
Remove the rule
Remove the rule
Remove 3.3 device at OD2
Modify N+/P+ spacing to 0.16 from 0.18
Modify VIAy Pitch to 0.14/0.14 from 0.13/0.15.
VIAy  3 neighboring Pitch to 0.14/0.16 from 0.13/0.17.
Remove the rule
Modify the rule to “>= 0.12” from “=0.12~1.5”
Add new rule for NMOS
Add new rule for PMOS
Modify rule description to (This check doesn't include the patterns
filling 0.12*0.26 rectangular tile) from (This check doesn’t include
rectangle area with length ≧0.26um)
Modify {ACTIVE (source) [width of rule description to 0.12 from 0.15
Modify OD width of rule description to 0.12 from 0.15
Modify rule description to Rs variation from Rs silicidation
Modify rule value to 0.49 from 0.48
OD Layout Rules
OD Layout Rules
OD Layout Rules
Deep N-Well (DNW) Layout Rules
(119) [Optional]
NW.S.5
4.5.3
N-Well (NW) Layout Rules
Modify rule value to 0.08 from 0.09
NW.S.6
4.5.3
N-Well (NW) Layout Rules
Modify rule value to 0.08 from 0.09
NW.EN.1
4.5.3
N-Well (NW) Layout Rules
Modify rule value to 0.08 from 0.09
NW.EN.2
4.5.3
N-Well (NW) Layout Rules
Modify rule value to 0.08 from 0.09
NWROD.S.3®
4.5.4
N-Well Within OD (NWROD) Layout
Modify the rule description to SPICE simulation accuracy from SPICE
Rules
model accuracy.
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NWROD.R.1®
Sec. No.
4.5.4
NWROD.R.2gU
4.5.4
NWROD.R.3g
4.5.4
NWRSTI.EN.2®
4.5.5
NWRSTI.R.1®
4.5.5
NWRSTI.R.2g
4.5.5
NWRSTI.R.3g
4.5.5
NT_N.W.3
OD2.EN.1
OD2.R.1
4.5.6
4.5.7
4.5.7
4.5.8
OD_12.W.1
OD_12.W.3
OD_12.S.1
OD_12.S.2
OD_12.S.3
OD_12.S.4
OD_12.S.6
OD_12.EN.1
OD_12.EN.2
OD_12.EX.3
OD_12.A.1
OD_12.A.2
OD_12.R.2
OD_12.R.3
OD_12.R.4
OD25_33.W.1
OD25_33.W.2
OD25_33.R.1
OD25_18.W.1
OD25_18.R.1
PO.W.1®
PO.W.2
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.8
4.5.9
4.5.9
4.5.9
4.5.10
4.5.10
4.5.8
4.5.11
Section Title
N-Well Within OD (NWROD) Layout
Rules
N-Well Within OD (NWROD) Layout
Rules
N-Well Within OD (NWROD) Layout
Rules
N-Well Under STI (NWRSTI) Layout
Rules
N-Well Under STI (NWRSTI) Layout
Rules
N-Well Under STI (NWRSTI) Layout
Rules
N-Well Under STI (NWRSTI) Layout
Rules
Native Device (NT_N) Layout Rules
Thick Oxide (OD2) Layout Rules
Thick Oxide (OD2) Layout Rules
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
1.2V Core Oxide (OD_12) Layout
Rules (12A)
OD25_33 Layout Rules
OD25_33 Layout Rules
OD25_33 Layout Rules
OD25_18 Layout Rules
OD25_18 Layout Rules
Poly (PO) Layout Rules (130)
Poly (PO) Layout Rules (130)
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Revision Description
Remove the rule
Remove the rule
The rule should be DRC checkable and the body (covered by marker
layer) of NW resistor should be rectangular.
Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
Remove the rule
Remove the rule
Add the rule description of “DRC can flag {NWDMY AND NW} is not a
rectangle”.
Remove 3.3V device)
Remove 3.3V device
Remove 3.3V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Ad the new rule to provide 1.2V device
Add the rule to provide 2.5V overdrive to 3.3V
Add the rule to provide 2.5V overdrive to 3.3V
Add the rule to provide 2.5V overdrive to 3.3V
Add the rule to provide 2.5V underdrive to 1.8V
Add the rule to provide 2.5V underdrive to 1.8V
Remove this rule
Add the rule description of (for 2.5V overdrive to 3.3V, please refer to
section 4.5.9) for overdrive
PO.W.3
4.5.11
Poly (PO) Layout Rules (130)
Remove 3.3V device, remove the rule.
PO.W.4
4.5.11
Poly (PO) Layout Rules (130)
Add the rule description of (for 2.5V underdrive to 1.8V, please refer
to section 4.5.10) for underdrive
PO.S.2
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to “{PO OR SR_DPO}” from poly
PO.S.2.2
4.5.11
Poly (PO) Layout Rules (130)
Remove this rule
PO.S.5
4.5.11
Poly (PO) Layout Rules (130)
Remove this rule
PO.S.5®
4.5.11
Poly (PO) Layout Rules (130)
Modify rule value to 0.06 from 0.07
PO.S.7
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to “{PO OR SR_DPO}” from poly
PO.S.10
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to “{PO OR SR_DPO}” from poly
PO.L.1
4.5.11
Poly (PO) Layout Rules (130)
Modify PO width of rule description to 0.08 from 0.13
PO.DN.1
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to add SR_DPO
PO.DN.2
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to add SR_DPO
PO.DN.3
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to add (except {RFDMY AND RFIP_DMY})
PO.R.7
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to “(50;0 OR 186;0)”
PO.L.1gU
4.5.11
Poly (PO) Layout Rules (130)
Modify rule description to Rs variation from Rs silicidation
SR_DPO.W.1
4.5.12
SR_DPO Layout Rules
Modify rule description to add SR_DPO rule
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SR_DPO.W.2
SR_DPO.W.6
SR_DPO.S.1
SR_DPO.S.2
SR_DPO.S.3
SR_DPO.S.4
SR_DPO.S.9
SR_DPO.S.16
SR_DPO.S.17
SR_DPO.S.18
SR_DPO.S.19
SR_DPO.S.20
SR_DPO.EN.1
SR_DPO.EN.2
SR_DPO.EX.1
SR_DPO.EX.2
SR_DPO.L.2
SR_DPO.A.1
SR_DPO.A.2
SR_DPO.A.3
SR_DPO.A.4
SR_DPO.R.1
SR_DPO.R.2U
SR_DPO.R.4
SR_DPO.R.5
VTH_N.S.2
Sec. No.
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.12
4.5.13
VTH_N.EN.2
4.5.13
VTH_N.L.1
4.5.13
VTH_P.S.2
4.5.14
VTH_P.EN.2
4.5.14
VTH_P.L.1
4.5.14
VTL_N.S.2
4.5.15
VTL_N.EN.2
4.5.15
VTL_N.L.1
4.5.15
VTL_P.S.2
VTL_P.EN.2
VTL_P.L.1
4.5.16
4.5.16
4.5.16
PP.S.2
4.5.17
PP.EX.1
4.5.17
PP.R.1
4.5.17
PP.L.1
4.5.17
NP.S.2
4.5.18
NP.EX.1
4.5.18
NP.R.1
4.5.18
NP.L.1
4.5.18
ESDIMP.W.1
4.5.20
ESDIMP.S.1
4.5.20
ESDIMP.EN.1
4.5.20
Section Title
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
SR_DPO Layout Rules
P+ Source/Drain Ion Implantation (PP)
Layout Rules (197)
P+ Source/Drain Ion Implantation (PP)
Layout Rules (197)
High Vt NMOS (VTH_N) Layout Rules
(11H)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
High Vt PMOS (VTH_P) Layout Rules
(11G)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
Low Vt NMOS (VTL_N) Layout Rules
(118)
Low Vt PMOS (VTL_P) Layout Rules
(117)
Low Vt PMOS (VTL_P) Layout Rules
(117)
Low Vt PMOS (VTL_P) Layout Rules
(117)
P+ Source/Drain Ion Implantation (PP)
Layout Rules (197)
P+ Source/Drain Ion Implantation (PP)
Layout Rules (197)
P+ Source/Drain Ion Implantation (PP)
Layout Rules (197)
P+ Source/Drain Ion Implantation (PP)
Layout Rules (197)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
N+ Source/Drain Ion Implantation (NP)
Rules (198)
ESD Implant (ESDIMP) Layout Rules
(MASK ID: 111)
ESD Implant (ESDIMP) Layout Rules
(MASK ID: 111)
ESD Implant (ESDIMP) Layout Rules
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Revision Description
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Modify rule description to add SR_DPO rule
Add the rule not to allow overlap of SRAM.
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Add the rule
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Add the rule
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Add the rule
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Add the rule
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Add the rule
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Modify rule value to 0.08 from 0.09
Add the rule
Add the rule to provide ESD implant.
Add the rule to provide ESD implant.
Add the rule to provide ESD implant.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
530 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Confidential – Do Not Copy
Rule
Sec. No.
ESDIMP.EN.1®
4.5.20
ESDIMP.A.1
4.5.20
ESDIMP.A.2
4.5.20
ESDIMP.R.1
4.5.20
ESDIMP.R.2® u
4.5.20
RES.R.4
RES.R.5
RES.1gU
RES.3gU
RES.4gU
RES.5g
RES.6gU
RES.7gU
RES.12
RES.13
RES.14g
RES.15g
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
4.5.22
Section Title
(MASK ID: 111)
ESD Implant (ESDIMP) Layout Rules
(MASK ID: 111)
ESD Implant (ESDIMP) Layout Rules
(MASK ID: 111)
ESD Implant (ESDIMP) Layout Rules
(MASK ID: 111)
ESD Implant (ESDIMP) Layout Rules
(MASK ID: 111)
ESD Implant (ESDIMP) Layout Rules
(MASK ID: 111)
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
OD and Poly Resistor Layout Rules
VAR.W.1
4.5.23
MOS Varactor Layout Rules (VAR)
VAR.W.3
VAR.W.4
VAR.S.2®
VAR.S.3®
VAR.A.1®
CO.S.5
CO.EN.0
4.5.23
4.5.23
4.5.23
4.5.23
4.5.23
4.5.24
4.5.24
MOS Varactor Layout Rules (VAR)
MOS Varactor Layout Rules (VAR)
MOS Varactor Layout Rules (VAR)
MOS Varactor Layout Rules (VAR)
MOS Varactor Layout Rules (VAR)
Contact (CO) Layout Rules (156)
Contact (CO) Layout Rules (156)
CO.EN.0®
CO.EN.1®
CO.EN.1.1®
CO.EN.1.3
CO.S.6g
4.5.24
4.5.24
4.5.24
4.5.24
4.5.24
Contact (CO) Layout Rules (156)
Contact (CO) Layout Rules (156)
Contact (CO) Layout Rules (156)
Contact (CO) Layout Rules (156)
Contact (CO) Layout Rules (156)
CO.R.1gU
4.5.24
Contact (CO) Layout Rules (156)
CO.R.5g
4.5.24
Contact (CO) Layout Rules (156)
CO.R.6gU
M1.S.8.1
M1.EN.1®
M1.EN.3
M1.A.1
M1.A.2
M1.DN.1
M1.DN.3
M1.DN.3®
VIAx.EN.0
VIAx.EN.1®
4.5.24
4.5.25
4.5.25
4.5.25
4.5.25
4.5.25
4.5.20
4.5.20
4.5.20
4.5.25
4.5.26
4.5.26
Contact (CO) Layout Rules (156)
M1 Layout Rules
M1 Layout Rules
M1 Layout Rules
M1 Layout Rules
M1 Layout Rules
Metal-1 (M1) Layout Rules (360)
Metal-1 (M1) Layout Rules (360)
Metal-1 (M1) Layout Rules (360)
M1 Layout Rules
VIAx Layout Rules
VIAx Layout Rules
VIAx.EN.2®
VIAx.EN.4
VIAx.EN.4.1
VIAx.R.9gU
Mx.W.4®
Mx.S.5.1
Mx.S.8.1
Mx.EN.0
Mx.EN.1®
4.5.26
4.5.26
4.5.26
4.5.26
4.5.27
4.5.27
4.5.27
4.5.27
4.5.27
VIAx Layout Rules
VIAx Layout Rules
VIAx Layout Rules
VIAx Layout Rules
Mx Layout Rules
Mx Layout Rules
Mx Layout Rules
Mx Layout Rules
Mx Layout Rules
Mx.EN.2®
Mx.EN.3
Mx.EN.3.1
4.5.27
4.5.27
4.5.27
Mx Layout Rules
Mx Layout Rules
Mx Layout Rules
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Revision Description
Add the rule to provide ESD implant.
Add the rule to provide ESD implant.
Add the rule to provide ESD implant.
Add the rule to provide ESD implant.
Add the rule to provide ESD implant.
RES.12 is chaneged the guideline to rule RES.R.4
RES.13 is chaneged the guideline to rule RES.R.5
Remove the rule
Remove the rule
Remove the rule
Remove the rule
Remove the rule
Remove the rule
Chanege the guideline to rule
Chanege the guideline to rule
Remove the rule
Chanege the guideline to checkable, modify the rule description to
SPICE simulation accuracy from SPICE model accuracy.
Remove the rule description of “for the baseband circuit, according to
the SPICE model”
Add this rule for VAR.
Add this rule for VAR.
Remove the rule
Remove the rule
Remove the rule
Remove 3.3V device
Add the rule description of “Enclosure by OD is defined by either
{CO.EN.1 and CO.EN.1.1} or {CO.EN.1.3}”.
Add the new recommendation.
Modify the rule vaue to 0.04 from 0.03
Add the new rule for recommended enclosure by OD
Add the new rule for enclosure by OD
Change the rule to checkable, and add “DRC can flag if the STRAP is
butted on source, one of STRAP and source is without CO.”
Modify the rule description to “unexpected resistance variation.” from
“high Rs”
Change the guideline to “checkable” from uncheckable”. Modify the
rule description.
Remove the rule
Modify to checkabke from unheckable.
Modify the rule value to 0.03 from 0.04
Add the rule description of [four sides]
Modify the rule value to 0.0215 from 0.022
Modify the rule description to 0.17 from 0.21
Modify rule area value.
Modify rule area value.
Modify rule area value.
Add the flow is the DRC implementation of M1.S.8, and M1.S.8.1
Add the new rule
Modify refer section to 4.5.34 from 4.5.31, Modify rule value to 0.03
from 0.04
Modify refer section to 4.5.34 from 4.5.31
Add one option of {VIAx.EN.4 and VIAx.EN.4.1}
Add one option of {VIAx.EN.4 and VIAx.EN.4.1}
Modify refer section to 4.5.34 from 4.5.31
Remove the rule
Add the new rule
Modify to checkabke from unheckable.
Add the new rule
Modify refer section to 4.5.34 from 4.5.31, Modify rule value to 0.03
from 0.04
Modify refer section to 4.5.34 from 4.5.31
Add the new rule
Add the new rule
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
531 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Confidential – Do Not Copy
Rule
Mx.A.2
Mx.DN.1
Mx.DN.3
Mx.DN.3®
Mx.DN.5
Sec. No.
4.5.27
4.5.27
4.5.27
4.5.27
4.5.27
Section Title
Mx Layout Rules
Mx Layout Rules
Mx Layout Rules
Mx Layout Rules
Mx Layout Rules
VIAy.W.1
VIAy.S.1
VIAy.S.2
VIAy.EN.1
VIAy.EN.1®
4.5.27
4.5.28
4.5.28
4.5.28
4.5.28
4.5.28
Mx Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy.EN.2
VIAy.EN.2®
4.5.28
4.5.28
VIAy Layout Rules
VIAy Layout Rules
VIAy.R.8®
VIAy.R.9gU
My.EN.0
My.EN.0®
My.EN.1
My.EN.1®
4.5.28
4.5.28
4.5.29
4.5.29
4.5.29
4.5.29
VIAy Layout Rules
VIAy Layout Rules
My Layout Rules
My Layout Rules
My Layout Rules
My Layout Rules
My.EN.2
My.EN.2®
4.5.29
4.5.29
My Layout Rules
My Layout Rules
AP.R.1
LOGO.O.1
LOGO.R.2
SRAM.R.4U
ROM.W.1
ROM.W.2
ROM.R.1U
ROM.R.2® U
A.R.6
4.5.29
4.5.29
4.5.29
4.5.29
4.5.29
4.5.30
4.5.31
4.5.31
4.5.31
4.5.31
4.5.33
4.5.31
4.5.31
4.5.31
4.5.33
4.5.34
4.5.35
4.5.35
4.5.35
4.5.35
4.3.36
4.3.36
4.3.36
4.3.36
4.3.36
4.3.37
4.3.37
4.3.37
4.3.37
4.3.37
4.3.37
4.3.37
4.3.38
4.3.38
4.5.39
4.5.41
4.5.41
4.5.41
4.5.41
4.5.45
A.R.9
4.5.45
My Layout Rules
My Layout Rules
My Layout Rules
My Layout Rules
My Layout Rules
Top VIAz Layout Rules
Top Mz Layout Rules
Top Mz Layout Rules
Top Mz Layout Rules
Top Mz Layout Rules
Top Mr Layout Rules
Top Mr Layout Rules
Top Mr Layout Rules
Top Mr Layout Rules
Top Mr Layout Rules
Via Layout Recommendations
MOM Layout Rules
MOM Layout Rules
MOM Layout Rules
MOM Layout Rules
RV Layout Rules (CB VIA hole)
RV Layout Rules (CB VIA hole)
RV Layout Rules (CB VIA hole)
RV Layout Rules (CB VIA hole)
RV Layout Rules (CB VIA hole)
AP-MD Layout Rules
AP-MD Layout Rules
AP-MD Layout Rules
AP-MD Layout Rules
AP-MD Layout Rules
AP-MD Layout Rules
AP-MD Layout Rules
Product Labels and Logo Rules
Product Labels and Logo Rules
SRAM Rules
ROM Rules
ROM Rules
ROM Rules
ROM Rules
Antenna Effect Prevention (A) Layout
Rules
Antenna Effect Prevention (A) Layout
My.DN.1
My.DN.2
My.DN.3
DMy.R.1
VIAz.R.5gU
Mz.DN.1
Mz.DN.2
Mz.DN.3
Mr.DN.1
Mr.DN.2
Mr.DN.3
Mr.R.2gU
MOM.S.2
MOM.A.1**
MOM.A.2**
MOM.R.1gU
RV.W.1
RV.S.1
RV.EN.1
RV.R.1
RV.R.2
AP.W.1
AP.W.2
AP.S.1
AP.EN.1
AP.DN.1
U
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Revision Description
Modify the rule description to 0.17 from 0.21
Modify rule area value.
Remove rule
Remove rule
Modify rule value to 85% from 70%,
Modify rule value to “62.5μm x 62.5μm (stepping 31.25)” from “50μm x
50μm (stepping 25)”,
Modify rule value to 85% from 70%,
Add the flow is the DRC implementation of Mx.S.8, and Mx.S.8.1
Modify rule value to 0.14 from 0.13
Modify rule value to 0.14 from 0.15
Modify rule value to 0.16 from 0.17
Modify rule value to 0 from 0.005
Modify rule value to 0.045 from 0.05, modify refer section to 4.5.34
from 4.5.31
Modify rule value to 0.045 from 0.05
Modify rule value to 0.075 from 0.08, modify refer section to 4.5.34
from 4.5.31
Remove the rule
Modify refer section to 4.5.34 from 4.5.31
Add the new rule
Add the new rule
Modify the rule value to 0 from 0.005
Modify refer section to 4.5.34 from 4.5.31. Modify the rule value to
0.05 from 0.045.
Modify the rule value to 0.045 from 0.05
Modify refer section to 4.5.34 from 4.5.31. Modify the rule value to
0.08 from 0.075
Remove rule description of My.DN.2, My.DN.3, and My.DN.5
Modify rule area value.
Remove the rule
Remove the rule
Modify rule No. to DMy.R.1 from Dmy.R.1
Modify refer section to 4.5.34 from 4.5.31
Remove rule description of Mz.DN.2, Mz.DN.3,
Modify rule area value.
Remove rule
Remove rule
Remove rule description of Mr.DN.2, Mr.DN.3
Modify rule area value.
Remove rule
Remove rule
Add the rule for Mr
Re-arrange the section
Add the rule to provide MOM
Add the rule to provide MOM
Add the rule to provide MOM
Add the rule to provide MOM
Add the rule to provide RV Layout
Add the rule to provide RV Layout
Add the rule to provide RV Layout
Add the rule to provide RV Layout
Add the rule to provide RV Layout
Add the rule to provide AP Layout
Add the rule to provide AP Layout
Add the rule to provide AP Layout
Add the rule to provide AP Layout
Add the rule to provide AP Layout
Add the rule to provide AP Layout
Add the rule to provide AP Layout
Remove rule description of AP
Add rule description of OD.W.2.1, OD.W.2.2
Add SRAM size of DP and HC
Add the rule to provide ROM
Add the rule to provide ROM
Add the rule to provide ROM
Add the rule to provide ROM
Modify rule description to 10M from M9.
Modify rule description to VIA9 from VIA8, and modify rule description
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
532 of 600
SECURITY B – TSMC RESTRICTED SECRET
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Confidential – Do Not Copy
Rule
Sec. No.
A.R.10
4.5.45
A.R.11
4.5.45
A.R.7
4.5.45
A.R.8
4.5.45
A.R.12
4.5.45
A.R.13
4.5.45
PO.S.14m®
5.2
PO.EN.1m®
5.2
PO.EN.2m®
5.2
PO.EN.3m®
5.2
AN.R.44mgU
AN.R.34mgU
AN.R.35mgU
PO.EX.1m®
PO.EX.2m gU
AN.R.36mgU
AN.R.37mgU
AN.R.38mU
AN.R.9mgU
AN.R.10mgU
AN.R.39.mgU
AN.R.15mgU
5.4.1
5.4.1
5.4.1
5.4.2
5.4.2
5.4.5
5.4.5
5.5.2
5.5.2
5.5.2
5.5.2
5.5.3
AN.R.17mg
5.5.3
AN.R.40.mgU
5.5.3
AN.R.41mgU
AN.R.42mgU
AN.R.43mgU
DOD.S.7.1
DPO.S.3
DPO.S.6.1
PO.DN.1
PO.DN.2
DTCD.W.1
DTCD.W.2
DTCD.W.3
DTCD.S.1
DTCD.DN.1®
DTCD.R.1
DTCD.R.2
DTCD.R.3
DMx.S.3
DMx.S.5.1
DMx.S.8
DMx.S.10
Mx.DN.1
Mx.DN.3®
Mx.DN.2
Mx.DN.4
Mx.DN.5
Metal
PO.S.5®
PO.S.5®
OPC.R.1®
OD.W.1®
NWROD.S.3®
5.6
5.6
5.6
6.1
6.2
6.2
6.2
6.2
6.3.1
6.3.1
6.3.1
6.3.1
6.3.1
6.3.1
6.3.1
6.3.1
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.5.1
7.2.1
7.2.1
7.2.2
7.2.2
7.2.2
Section Title
Rules
Antenna Effect Prevention (A) Layout
Rules
Antenna Effect Prevention (A) Layout
Rules
Antenna Effect Prevention (A) Layout
Rules
Antenna Effect Prevention (A) Layout
Rules
Antenna Effect Prevention (A) Layout
Rules
Antenna Effect Prevention (A) Layout
Rules
Layout Rules for the WPE (Well
Proximity Effect)
Layout Rules for the WPE (Well
Proximity Effect)
Layout Rules for the WPE (Well
Proximity Effect)
Layout Rules for the WPE (Well
Proximity Effect)
General Guidelines
General Guidelines
General Guidelines
MOS Recommendations
MOS Recommendations
Capacitor Guidelines
Capacitor Guidelines
Matching Rules and Guidelines
Matching Rules and Guidelines
Matching Rules and Guidelines
Matching Rules and Guidelines
Electrical Performance Rules and
Guidelines
Electrical Performance Rules and
Guidelines
Electrical Performance Rules and
Guidelines
Burn-in Guidelines for Analog Circuits
Burn-in Guidelines for Analog Circuits
Burn-in Guidelines for Analog Circuits
Dummy OD (DOD) Rules
Dummy Poly (DPO) Rules
Dummy Poly (DPO) Rules
Dummy Poly (DPO) Rules
Dummy Poly (DPO) Rules
Dummy TCD Rules
Dummy TCD Rules
Dummy TCD Rules
Dummy TCD Rules
Dummy TCD Rules
Dummy TCD Rules
Dummy TCD Rules
Dummy TCD Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Metal (DM) Rules
Dummy Pattern Filling Requirements
Action-Required Rules
Action-Required Rules
Recommendations
Recommendations
Recommendations
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Revision Description
to VIA from Via.
Modify rule value
Modify rule value
Remove rule description of diode area. Modify rule description to VIA9
from VIA8, and modify rule description to VIA from Via.
Remove rule description of diode area
Remove rule description of diode area
Modify rule value
Remove rule description of diode area
Modify rule value
Add this rule for WPE
Add this rule for WPE
Add this rule for WPE
Add this rule for WPE
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Modify rule description of “refer to the CO.R.5g”
Modify rule description
Add this rule for analog circuit
Modify rule description
Modify rule description
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Add this rule for analog circuit
Remove the rule
Add rule description “OR SR_DPO”
Remove the rule
Modify rule description to add SR_DPO
Modify rule description to add SR_DPO
Add this rule to provide Dummy TCD
Add this rule to provide Dummy TCD
Add this rule to provide Dummy TCD
Add this rule to provide Dummy TCD
Add this rule to provide Dummy TCD
Add this rule to provide Dummy TCD
Add this rule to provide Dummy TCD
Add this rule to provide Dummy TCD
Remove rule description of (This check doesn't include Mx.)
Remove the rule
Modify rule value to 0 from 18
Remove the rule
Modify rule area value.
Remove the rule
Remove the rule
Modify this rule to provide Mr
Modify rule value to 85% from 70%
Modify rule value to 85% from 70%,
Modify rule value to PO.S.4 from PO.S.5.
Modify rule value to 0.06 from 0.07
Remove the rule
Remove the rule
Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
533 of 600
SECURITY B – TSMC RESTRICTED SECRET
tsmc
Confidential – Do Not Copy
Rule
NWROD.R.1®
NWRSTI.EN.2®
Sec. No.
7.2.2
7.2.2
Section Title
Recommendations
Recommendations
NWRSTI.R.1®
PO.W.1®
ESDIMP.EN.1®
VAR.S.2®
VAR.S.3®
VAR.A.1®
CO.EN.1®
CO.EN.1.1®
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
M1.EN.1®
M1.DN.3®
VIAx.EN.1®
VIAx.EN.2®
Mx.W.4®
Mx.EN.1®
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Mx.EN.2®
Mx.DN.3®
VIAy.EN.1®
VIAy.EN.2®
VIAy.R.8®
My.EN.1®
My.EN.2®
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
7.2.2
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Recommendations
Mr.W.3®
G.6gU
OD.L.2gU
DNW.R.6gU
NWROD.R.2g
NWROD.R.3g
7.2.2
7.2.2.1
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
Recommendations
Grouping Table of Recommendations
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
NWRSTI.R.2gu
NWRSTI.R.3g
7.2.3
7.2.3
Guidelines
Guidelines
PO.L.1gU
RES.1gU
RES.3gU
RES.4gU
RES.5g
RES.6g
RES.7g
RES.11g
RES.12g
RES.14g
RES.15g
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
7.2.3
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
CO.S.6g
7.2.3
Guidelines
CO.R.1gU
7.2.3
Guidelines
CO.R.5g
7.2.3
Guidelines
CO.R.6gU
VIAr.R.5gU
Mz.R.2gU
MOM.R.1gU
7.2.3
7.2.3
7.2.3
7.2.3
7.3
Guidelines
Guidelines
Guidelines
Guidelines
Mechanical and Thermal Guidelines
for FCBGA
DFM Service
GDA die size optimization kit
Layout Guidelines for Latch-Up
Prevention
Layout Guidelines for Latch-Up
Prevention
Layout Guidelines for Latch-Up
Prevention
LUP.1
7.3
7.4
8.1
LUP.2
8.1
LUP.3.1
8.1
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Revision Description
Remove the rule.
Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
Remove the rule
Remove this rule
Add the new rule
Remove the rule
Remove the rule
Remove the rule
Modify rule value to 0.03 from 0.04.
Adfd the rule for recommended enclosure by OD [at least two opposite
sides]
Modify rule value to 0.03 from 0.04.
Remove the rule
Modify rule value to 0.03 from 0.04.
Modify rule description to 4.5.34 from 4.5.29
Remove the rule
Modify rule value to 0.03 from 0.04. Modify rule description to 4.5.34
from 4.5.29
Modify rule description to 4.5.34 from 4.5.29
Remove the rule
Modify rule value to 0.045 from 0.05.
Modify rule value to 0.075 from 0.08.
Remove the rule
Modify rule description to 4.5.34 from 4.5.29
Modify rule value to 0.075 from 0.08. Modify rule description to 4.5.34
from 4.5.29
Add the rule
Modify rulw table.
Add the rule
Modify rule description to Rs variation from Rs silicidation
Add the rule
Remove the Guidelines
Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
Remove the Guidelines
Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
Modify rule description to Rs variation from Rs silicidation
Remove the Guidelines
Remove the Guidelines
Remove the Guidelines
Remove the Guidelines
Remove the Guidelines
Remove the Guidelines
Change the Guidelines to rule
Change the Guidelines to rule
Remove the Guidelines
Chanege the guideline to checkable, modify the rule description to
SPICE simulation accuracy from SPICE model accuracy.
Change the rule to checkable, and add “DRC can flag if the STRAP is
butted on source, one of STRAP and source is without CO.”
Modify the rule description to “unexpected resistance variation.” from
“high Rs”
Change the guideline to “checkable” from uncheckable”. Modify the
rule description.
Remove the rule
Add the rule
Add the rule
Add the rule
Remove the section
Add new section to provide DFM service
Add new section to provide GDA die size optimization kit
Add new rule for Latch-Up
Add new rule for Latch-Up
Add new rule for Latch-Up
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
534 of 600
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Rule
LUP.3.2
Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Sec. No.
8.1
Section Title
Revision Description
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
LUP.3.3
8.1
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
LUP. 4
8.1
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
LUP.5.1
8.1
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
LUP.5.2
8.1
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
LUP.5.3
8.1
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
LUP.6
8.1
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
LUP.7U
8.1
Layout Guidelines for Latch-Up
Add new rule for Latch-Up
Prevention
ESD.warn.1
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.1gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.2gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.3g
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.4gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.5gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.6gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.7gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.8gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.9gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.10gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.11gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.12gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.13gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.14gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.15gU
8.2.4.1
General Guideline for ESD Protection
Add new rule for Latch-Up
ESD.16GU
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.17GU
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.18G
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.19GU
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.20G
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.21G
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.22G
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.23G
8.2.4.2
Regular I/O (2.5V/1.8V/1.1V/0.9V
Add new rule for Latch-Up
RPO Device)
ESD.24gU
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.25gU
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.26g
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.27gU
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.28g
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.29g
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.30g
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.31g
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.32g
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.33g
8.2.4.3
HV Tolerant I/O (2.5V/1.8V RPO
Add new rule for Latch-Up
device)
ESD.34gU
8.2.4.4
Power Clamp (0.9V, 1.1V, 1.8V and
Add new rule for Latch-Up
2.5V Salicide Device)
ESD.35gU
8.2.4.4
Power Clamp (0.9V, 1.1V, 1.8V and
Add new rule for Latch-Up
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
535 of 600
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Confidential – Do Not Copy
Rule
Sec. No.
ESD.36g
8.2.4.4
ESD.37g
8.2.4.4
9.1
9.2
9.3
9.4
Section Title
2.5V Salicide Device)
Power Clamp (0.9V, 1.1V, 1.8V and
2.5V Salicide Device)
Power Clamp (0.9V, 1.1V, 1.8V and
2.5V Salicide Device)
Terminology
Front-End Process Reliability Rules
and Models
Back-End Process Reliability Rules
Cu Metal Current Density (EM)
Specifications
Document No.
Version
: T-N45-CL-DR-001
: 2.6
Revision Description
Add new rule for Latch-Up
Add new rule for Latch-Up
Add the section contents
Add the section contents
Add the section contents
Add the section contents
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.
536 of 600
SECURITY B – TSMC RESTRICTED SECRET
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Confidential – Do Not Copy
Document No.
Version
: T-N45-CL-DR-001
: 2.6
A.2 From Version 0.2 to 1.0
1.
Rule
Sec. No.
2.1.1
Section Title
Front-End Features
1.
3.1
Mask Information, Key Process
Sequence, and CAD Layers
2.
3.1
3.
3.1
4.
3.4
5.
3.4
6.
3.4
7.
3.4
8.
3.4
9.
3.4
10.
3.4
11.
3.4
Mask Information, Key Process
Sequence, and CAD Layers
Mask Information, Key Process
Sequence, and CAD Layers
Special Recognition CAD Layer
Summary
Special Recognition CAD Layer
Summary
Special Recognition CAD Layer
Summary
Special Recognition CAD Layer
Summary
Special Recognition CAD Layer
Summary
Special Recognition CAD Layer
Summary
Special Recognition CAD Layer
Summary
Special Recognition CAD Layer
Summary
Gate Oxide and Diffusion (OD)
Layout Rules (120)
Deep N-Well (DNW) Layout Rules
(119) [Optional]
Deep N-Well (DNW) Layout Rules
(119) [Optional]
1.2V Core Oxide (OD_12) Layout
Rules (12A)
12.
OD.A.1
4.5.1
13.
DNW.S.4
4.5.2
14.
DNW.S.5
4.5.2
15.
OD_12.W.3
4.5.8
16.
PO.R.7
4.5.11
Poly (PO) Layout Rules (130)
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
PO.R.8
SR_DPO.R.6
RES.R.15g
VAR.W.4
CO.W.2
CO.EN.5
CO.EN.6
M1.W.3
VIAx.W.2
VIAx.W.3
Mx.W.3
VIAy.W.2
VIAy.W.3
VIAy.W.4
VIAy.W.5
VIAy.R.2
VIAy.R.3
VIAy.R.4
VIAy.R.5
VIAy.R.6
VIAz.W.2
VIAz.W.3
VIAz.EN.1
VIAz.R.2
VIAz.R.3
Mz.EN.1
VIAr.W.2
4.5.11
4.5.12
4.5.22
4.5.23
4.5.24
4.5.24
4.5.24
4.5.25
4.5.26
4.5.26
4.5.27
4.5.28
4.5.28
4.5.28
4.5.28
4.5.28
4.5.28
4.5.28
4.5.28
4.5.28
4.5.30
4.5.30
4.5.30
4.5.30
4.5.30
4.5.31
4.5.32
Poly (PO) Layout Rules (130)
SR_DPO Layout Rules
OD and Poly Resistor Layout Rules
MOS Varactor Layout Rules (VAR)
Contact (CO) Layout Rules (156)
Contact (CO) Layout Rules (156)
Contact (CO) Layout Rules (156)
Metal-1 (M1) Layout Rules (360)
VIAx Layout Rules
VIAx Layout Rules
Mx Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
VIAy Layout Rules
Top VIAz Layout Rules
Top VIAz Layout Rules
Top VIAz Layout Rules
Top VIAz Layout Rules
Top VIAz Layout Rules
Top Mz Layout Rules
Top VIAr Layout Rules
Revision Description
Change SRAM cell name to HCDP from HC.
Add two warnings:
1. Need to re-tapeout 12E, 12F, and 123 masks if OD GDS is
changed.
2. Need to re-tapeout 12E, 12F, 123, and 14D masks if Poly
GDS is changed.
Change OD_12 mask tone to C from D.
Change mask name to CB2_WB and CB2_FC from CB2.
Add new layer SRAM_HS for SRAM.
Change description to HCDP from HC_DP at SRM_HCDP.
Add new layer RRuleRequire (182;1) for DFM ActionRequired recommendation.
Add new layer RRuleRequire (182;2) for DFM Recommended
recommendation.
Add new layer RRuleRequire (182;3) for DFM Recommended
Dimension for Analog Designs.
Add new layer RRuleRequire (182;11) for excluding DFM
action-required recommnedation check.
Add new layer RRuleRequire (182;12) for excluding DFM
recommendaed recommendation check.
Add new layer RRuleRequire (182;13) for excluding Rules and
Recommendations check for Analog Designs.
Change rule description to 0.06*0.26 from 0.12*0.26.
Change rule value to 0.8 from 1.0
Change rule value to 1.0 from 1.2, and change rule
description to {RW OR PW} from RW.
Change rule value to 0.07 from 0.06.
Remove rule description “Poly gates of all core devices can be
uni-directional in a chip with tighter SPICE corners. The
SPICE corners of the other poly gates perpendicular to the
uni-directional gates are 2 sigma wider”
Add new rule for Floating Gate.
Add new rule for SR_DPO insertion.
Change rule number to RES.R.15g from RES.15g.
Add label G in rule picture.
Add the new rule for sealring.
Add rule picture
Add rule picture
Add rule description not to include the rule check in sealring.
Add the new rule for sealring.
Add the new rule for sealring.
Add rule description not to include the rule check in sealring.