1. Test list:
Source 1:
1. Design for Testability (DFT) is a set of techniques
employed during the design phase of integrated
circuits (ICs) to facilitate the testing and debugging of
the final product. In the context of boundary scan
testing, DFT plays a crucial role in ensuring that the
design of the IC includes features that make it easier
to test using the JTAG (Joint Test Action Group)
boundary scan architecture. Here's a detailed
explanation of DFT in design for boundary scan test:
a. Boundary Scan Architecture:
 The boundary scan architecture,
standardized as IEEE 1149.1, provides a
standardized method for testing the
interconnections between ICs on a PCB
without requiring physical access to each
pin. It comprises:
 Test Access Port (TAP) Controller:
Manages the shift of test data in and out of
the IC.
 Boundary Scan Register (BSR): Contains
cells connected to each I/O pin, allowing
test patterns to be shifted in and out.
 Instruction Register (IR): Determines the
operation to be performed (e.g., Extest,
Sample/Preload).
b. DFT Techniques for Boundary Scan:
 Insertion of Boundary Scan Cells: DFT
involves integrating boundary scan cells
into the design of the IC. These cells allow
for the capture and driving of test data to
and from the IC's I/O pins, enabling
thorough testing of the interconnections.
 Structural Testing: DFT techniques ensure
that the design of the IC is structured in a
way that facilitates thorough structural
testing. This involves verifying the
connectivity of the internal logic elements
and ensuring that the boundary scan cells
effectively cover the entire device.
 Testability Features: Designers incorporate
features into the IC design to enhance
testability. This includes the insertion of
additional test points, scan chains, or other
circuitry to facilitate testing and diagnosis.
 Boundary Scan Register Optimization: DFT
techniques aim to optimize the design of
the boundary scan register to minimize its
size and complexity while maximizing its
effectiveness in testing the device.
 DFT Rules and Guidelines: Designers
follow specific rules and guidelines to
ensure that the IC design is testable using
boundary scan. This includes adhering to
standards such as IEEE 1149.1 and
considering factors like scan chain length,
signal integrity, and test coverage.
c. Benefits of DFT in Boundary Scan Testing:
 Improved Test Coverage: DFT techniques
ensure that the design of the IC is
optimized for boundary scan testing,
resulting in improved test coverage and
detection of faults.
 Reduced Test Time: By integrating
boundary scan cells and optimizing the
design for testability, DFT helps reduce the
time and resources required for testing the
IC.
 Enhanced Diagnosis: DFT techniques
enable easier diagnosis of faults by
providing detailed information about the
connectivity and behaviour of the IC during
testing.
 Faster Time-to-Market: By facilitating faster
and more efficient testing, DFT contributes
to reducing the time-to-market for the final
product, leading to cost savings and
improved competitiveness.
d. Summary
 DFT in design for boundary scan testing
involves incorporating features into the IC
design to optimize its testability using the
JTAG boundary scan architecture. By
following specific techniques and
guidelines, designers can ensure that the
IC is easier to test, diagnose, and debug,
ultimately leading to improved product
quality and faster time-to-market.
Source 2:
1. Design for Testability (DFT) in the context of
boundary scan testing refers to the integration of
features and techniques during the design phase of
an integrated circuit (IC) to enhance its testability
using the boundary scan (JTAG) architecture. DFT in
boundary scan aims to ensure that the IC can be
thoroughly tested for faults and defects in its
interconnections and internal logic using the
standardized JTAG interface. Here's a detailed
explanation
a. Insertion of Boundary Scan Cells:
DFT in boundary scan involves inserting
boundary scan cells into the design of the
IC. These cells are connected to each I/O
pin of the IC and enable the capture and
driving of test patterns to and from the
pins. The boundary scan cells provide a
means to access and test the internal
nodes of the IC that are not directly
observable from its external pins.
b. Structural Testing:
 DFT techniques ensure that the design of
the IC facilitates thorough structural
testing. This involves verifying the
connectivity of the internal logic elements
and ensuring that the boundary scan cells
effectively cover the entire device.
Structural testing using boundary scan
helps detect faults such as open circuits,
short circuits, and stuck-at faults within the
IC.
c. Testability Features:
 Designers incorporate testability features
into the IC design to enhance its testability
using boundary scan. These features may
include the insertion of additional test
points, scan chains, or other circuitry to
facilitate testing and diagnosis. Testability
features help improve the efficiency and
effectiveness of boundary scan testing by
providing additional access points and
diagnostic capabilities.
d. Boundary Scan Register Optimization:
 DFT in boundary scan includes optimizing
the design of the boundary scan register
(BSR) to maximize its effectiveness in
testing the device. This may involve
minimizing the size and complexity of the

BSR while ensuring that it provides
sufficient coverage for testing the IC's
interconnections and internal logic. BSR
optimization helps reduce test time and
resource usage while maintaining high test
coverage.
e. Compliance with Standards:
 Designers follow specific rules and
guidelines to ensure that the IC design is
compliant with standards such as IEEE
1149.1, which defines the boundary scan
architecture. Adhering to standards
ensures interoperability and compatibility
with boundary scan testing equipment and
software tools. Compliance with standards
also facilitates the integration of the IC into
larger systems and simplifies the testing
and debugging process.
f. Benefits of DFT in Boundary Scan Testing:
 Improved test coverage for
interconnections and internal logic.
 Reduced test time and resource usage.
 Enhanced diagnosis of faults and defects.
 Faster time-to-market for the final product.
 Compatibility and interoperability with
boundary scan testing equipment and
software tools.
 In summary, DFT in boundary scan testing
involves integrating features and
techniques into the design of an IC to
optimize its testability using the
standardized JTAG interface. By following
specific guidelines and best practices,
designers can ensure that the IC is easier
to test, diagnose, and debug, leading to
improved product quality and faster timeto-market.
2.