ECE411s ICT Midterm Exam – April 2024 – 90 min
Consider the shown layout for a 3.3 V NMOS 0.35 m technology DRAM cell. All dimensions are in m.
1) Draw a cross-section in silicon at a horizontal line in the middle of the layout.
2) Select the appropriate process name. How many masks are needed? What is (are) the additional
mask(s) w.r.t. the core module (if any)?
3) Extract the schematic diagram of this DRAM cell (1T1C design) indicating W/L for the pass
transistor (PT).
4) Assume that the “Bit In” is logic 1 and the PIP cap initially discharged, when the PT “SEL” becomes
High, the cap will store “1” after a certain delay time related to the charging time constant .
4.1)
How much is the stored logic “1” in volts if the input logic “1” = 3V.
4.2)
Estimate  as accurate as possible. (neglect M1 cap).
5) When the “SEL” becomes Low, the voltage stored will drop due to the PT subthreshold
channel leakage current and junction leakage current. The stored data retention time is
defined as the time tr at which the stored voltage drops down to 80% of its maximum
value.
5.1) Verify that the junction leakage is negligible compared to the channel leakage.
5.2) Estimate tr assuming that the leakage behaves as a constant current sink.
Data for the 350 nm Process from AMS
Parameter
threshold voltage
CPOLY area capacitance
CPOLY perimeter capacitance
area junction capacitance
sidewall junction capacitance
area junction leakage current
sidewall junction leakage current
on-resistance
subthreshold leakage current.
Typical
0.5
0.8
0.08
0.9
0.3
0.02
0.1
12
1
Units
V
fF/m2
fF/m
fF/m2
fF/m
fA/m2
fA/m
k.m
pA/m