8
7
6
5
4
3
2
1
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.
For DB build
SOUTH BRIDGE
HM75 QPEG Q0
BD82PPSM
P/N : 6019B0919101
HSF Property:ROHS or Halogen-Free(5L3?)
F
DB BUILD QUANTITY LIST :
1310A2493104
1310A2493105
1310A2493106
1310A2493201
1310A2493601
1310A2493701
10 PCS
72 PCS
55 PCS
137 PCS
137 PCS
137 PCS
F
CR-SG + H-VRAM + GIGA LAN
CR-SG + S-VRAM + 10/100 LAN
CR-UMA + GIGA LAN
POWER /B
PICK BTN /B
USB /B
E
E
PAD402
PAD4500
PAD2
PAD4
PAD400
PAD4700
PAD500
PAD508
PAD6015
PAD6100
PAD6103
PAD6105
PAD6110
PAD6150
PAD6200
PAD6210
PAD6220
PAD6300
PAD6301
PAD6310
PAD6510
PAD6500
PAD6610
PAD6710
PAD6750
PAD6970
PAD9000
PAD9001
PAD9200
MOTHER BOARD PCB
P/N：6050A2493101
HARVEY 14
POWER BOARD PCB
P/N：6050A2493201
USB BOARD PCB
P/N：6050A2493601
D
TOUCHPAD BOARD PCB
P/N：6050A2493701
HARVEY 14 ID LIST
HURON RIVER UMA : 0X1854
HURON RIVER DIS : 0X1855
CHIEF RIVER UMA : 0X1856
CHIEF RIVER DIS :
0X1857
SUB SYSTEM ID :
HP : 0X103C
CR / HR
UMA / DIS
2011.09.27
BASE SCHEMATIC :
CR-SG + SAMSUNG VRAM + 10/100 LAN + 90W ADAPTER + SUPPORT 27MHZ GREEN CLK + USB2.0 CONN
C
DIS GREEN CLK SUPPORT 27MHZ
BOARD ID
CR-UMA
HR-UMA
INTEL
U5 , U6 , U7 , U8
U9
C188
R126
D4400
ID0-HI R960
0
1
ID1-HI R905
0
0
1
ID2-HI R902
0
0
0
ID3-HI R967
0
0
0
ID4-HI R899
0
0
0
ID5-HI R914
1
1
1
ID0-LO R961
1
0
1
0
SAMSUNG 1GB C-DIE
PN : 6019B0818601
U9
C188
R126
D4400
HYNIX 1GB D-DIE
PN : 6019B0938301
R2 : MOUNT
R3 : NA
R33 : NA
R61 : NA
SLG3NB300V P/N : 6019B0941101
MOUNT
0.1UF : 6010A0036403
10R : 60130B10000X
MOUNT
NA
P/N : 6011A0026803
UMA GREEN CLK
R2 : NA
R3 : NA
R33 : NA
R61 : NA
B
CR-SG
HR-SG
SEYMOUR
GPU VRAM TYPE:
SLG3NB250V
NA
NA
NA
6019B0934701
DIS ADAPTER 90W
0R : 60130B0000ZT
R802
R769
MOUNT 100K : 60130B1040ZT
NA
UMA ADAPTER 65W
R802
R769
SAMSUNG 512KB
R2 : NA
R3 : MOUNT
R33 : NA
R61 : NA
NA
MOUNT 100K : 60130B1040ZT
CN518
C2405
C2406
D2400
L470
L471
R2 : MOUNT
R3 : MOUNT
R33 : NA
R61 : NA
6012B0370301
MOUNT 0.1UF : 6010A0036403
MOUNT 0.1UF : 6010A0036403
NA >> ESD
MOUNT
P/N : 6014B0177901
MOUNT
P/N : 6014B0177901
USB 2.0 CONN
A
AUGUST
30, 2010
21-OCT-2002
X01
1
1
1
ID4-LO R900
1
1
1
ID5-LO R920
0
0
0
ID0 = GPIO40
ID1 = GPIO41
ID2 = GPIO42
ID3 = GPIO43
ID4 = GPIO9
ID5 = GPIO10
RXXX = 10K : 60130B1030ZT
0 : RXXX NA
1 : RXXX MOUNT
CN518
C2405
C2406
D2400
L470
L471
6012B0370102
NA
NA
NA >> ESD
NA
NA
7
開
開
開
開
開
開
開
開
開
開
開
M/B ID
R844
R824
R845
R828
DB
MOUNT
MOUNT
NA
NA
R408 : NA
R407 : MOUNT
R413 : MOUNT
C404 : MOUNT
C405 : MOUNT
C406 : MOUNT
C409 : MOUNT
C411 : MOUNT
C415 : MOUNT
C417 : MOUNT
C420 : MOUNT
L400 : MOUNT
U470 : MOUNT
U502 : NA
U400 : MOUNT
BOARD_ID5 ONLY FOR WEBCAN USE
FOR HD WEB CAM BOARD_ID5 PULL P3V3A
FOR VGA WEB CAM BOARD_ID5 PULL GND
開
開
D
開
開
開
開
開
開
開
SI
NA
MOUNT
MOUNT
NA
PV
MOUNT
NA
NA
MOUNT
NOV
JAN
4
B
MV
NA
NA
MOUNT
MOUNT
EE
DATE
0R_0603 : 60130B00000Z
4.7UF : 6010B0009904
0.1UF : 6010A0036403
0.1UF : 6010A0036403
0.1UF : 6010A0036403
0.1UF : 6010A0036403
0.1UF : 6010A0036403
4.7UF : 6010B0009904
0.1UF : 6010A0036403
P/N : 6014B0200401
6016B0010401
6019B0928101 ( GIGALAN )
POWER
MAR
DESIGN
3
A
INVENTEC
DATE
CHECK
TITLE
MODEL,PROJECT,FUNCTION
HARVEY 14
SIZE=
FILE NAME:
6050A2493101
P/N
XXX
5
開
----> CHOOSE LDO MODE
----> CHOOSE SWITCHING MODE 0R : 60130B1030ZT
RESPONSIBLE
6
開
C
DRAWER
RXXX = 10K : 60130B1030ZT
開
RTL8161FH(GIGA-LAN) SWITCHING MODE
REV
CHANGE NO.
8
1
1
1
開
開
R408 : MOUNT ----> CHOOSE LDO MODE 0R : 60130B0000ZT
R407 : NA
----> CHOOSE SWITCHING MODE
R413 : NA
C404 : NA
C405 : NA
C406 : NA
C409 : NA
C411 : NA
C415 : NA
C417 : NA
C420 : NA
L400 : NA
U470 : NA
U502 : MOUNT 6016B0008101
U400 : MOUNT
6019B0928301 ( 10/100 LAN )
USB 3.0 CONN
HYNIX 512MB
DATE
1
1
ID3-LO R968
開
RTL8165EH(10/100) LDO MODE
0
ID2-LO R904
開
RTL8161FH = 6019B0928101(10/100/1000)
RTL8165EH = 6019B0928301(10/100)
CR-SG
HR-SG
THAMES
ID1-LO R903
不開不不 RTC Rest
不開不不 SM_Vrer
VER:
SIZE
C
CODE
CS
DOC.NUMBER
2
REV
1310xxxxx-0-0
SHEET
1
1
X01
of
57
8
7
6
5
4
3
2
1
Index
D
C
B
D
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Project Name
Page Index
Block Diagram
Power Procedure
Charger
Battery Connecter
P3V3A, P5V0A
P1V5
P1V05S
P1V8S
PVSA
PVCORE-1
PVCORE-2
PORT & EMI PART
P3V3S, P5V0S
GREEN CLK
CPU -1
CPU-2
CPU-3
CPU-4
CPU-5
CPU-6
Thermal & Fan
DDR3-1
DDR3-2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PCH-1
PCH-2
PCH-3
PCH-4
PCH-5
PCH-6
PCH-7
PCH-8
PCH-9
EC ITE8517E
KB & LED
CRT
LCD & WEBCAN
HDMI
SATA HDD& ODD
LAN
RJ-45 CONN
CARD READER
AUDIO CODEC
HP & MIC JACK
WLAN
USB 3.0 CONN
SEYMOUR PCI-E INTERFACE
SEYMOUR CRT CLK THERMAL
SEYMOUR THERMAL SENSOR
51
52
53
54
55
56
57
SEYMOUR POWER
SEYMOUR DP-POWER & LVDS
SEYMOUR MEMORY INTERFACE
VRAM DDR3
DGPU POWER EE
DGPU POWER
USB, POWERBUTTON ,TP DB
C
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
INDEX
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
2
57
of
1
X01
X01
8
7
CRT
6
VGA
V-RAM
AMD SEYMOUR 64BIT
128M X 16
P37
(2GB)
5
PCIE-8X
1333/1600
FDI
1
MAX 8GB
P24
DDR3 SO-DIMM2
DDR3
1333/1600
P17~P22
P39
2
DDR3 SO-DIMM1
DDR3
(SOCKET RPGA 989)
37.5MM X 37.5MM
P48~P53
HDMI
3
IVY BRIDGE
S3 PACKAGE
P54
4
MAX 8GB
P25
DMI
D
D
LCM
USB
P38
CARD READER
RTL 5239-GR
PANTHER
POINT
PCIE
WEBCAM
P38
USB 2.0
P43
USB
RTL 8165EH-CG
RJ-45
10/100 LAN
P42
P41
P57
PCIE
C
MINI CARD
RTL 8161FH-CG
USBCONN2
P57
USB 3.0
WLAN + BT
C
USB
USB CONN1
PCIE
P46
GIGA LAN
USB CONN3
25MM X 25MM
SATA
P47
P41
SATA
P26~P34
HDA
SPI ROM
LPC
4MB
SATA HDD
P26
SATA ODD
P40
P40
HSPI
B
SPEAKER
ALC 3201-GR
P44
P44
P45
1MB
P35
P35
DMIC
COMBO JACK
THERMAL METER
TI TMP431A
SPI ROM
ITE IT8517E
AUDIO CODEC
HP JACK
B
KBC
P44
KEYBOARD
P6
P47
P36
P45
MAIN BATT
TOUCHPAD
SYSTEM CHARGER
A
DC/DC SYSTEM POWER
P23
P4
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
3
57
of
1
X01
A
8
7
AC
PVADPTR
DC
PVPACK
MOS
VADPBL
6
5
4
3
2
1
MOS
MOS
VRP5V0A
D
CHARGER
BQ24728
MOS
PAD
P5V0A
PAD
PVBAT
5V / 3.3V
MOS
TPS51123RGER
MOS
VRP3V3A
PAD
PAD
PAD
1.5V
TPS51216RUKR
VRP1V5
PAD
VCCSA
TPS51461RGER
1.8V
AT1530F11U
P1V5
MOS
VRPVSA
PAD
PVSA
D
P5V0S
P3V3A
MOS
C
VRPVCCSA_IN
P3V3S
P1V5S
MOS
MOS
VRP1V8S
PAD
P1V8S
MOS
P1V8S_DGPU
P3VSS_DGPU
P1V5S_DGPU
C
1.05V
TPS51219RTER
VRP1V05S_VCCP
PAD
MOS
P1V05S_CPU
PAD
P1V05S_PCH
P1V0S_DGPU
B
B
PAD
VCORE
TPS51650RSLR
PVCORE
PAD
AXG
TPS51601DRBR
PVAXG
VCORE_DGPU
RT8208BGQW
VRPVCORE_DGPU
A
A
PAD
PVCORE_DGPU
DGPU_PG
EN_DGPU
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER PROCEDURE
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
4
57
of
1
X01
8
7
5
2
R6023
100K_1%_2
2
1
1
2
2
1
1
2
C6001
10UF_25V_5
1
C6002
4.7UF_25V_5
6
1
A
VRPVPACK_CSN
2
R6020
SHORT_0402
1
2
OUT
INVENTEC
BATDRV 5
R6043
4.3K_5%_2
TITLE
MODEL,PROJECT,FUNCTION
CHANGE by
7
D6019
B0530W_7
2
1
C6021
0.1UF_25V_2
C6023
0.1UF_16V_2
Block
8
1
1
2
2
C6011
10UF_25V_5
1
2
1
C6010
10UF_25V_5
2
4
2
R6025
SHORT_0402
36.5K_1%_2
2
R6046
1
3
VRPVPACK_CSP
1
1
1
B
R6001
0.01_1%_6
2
P3V3A
C6047
CSC0402_DY
2
1
2
1
1
2
VRPVPACK_LG
2
R7600
RSC_0603_DY
2
1
1
D6016
BAT54WS
4
3
2
1
C6046
100PF_50V_2
2
1
C6000
CSC0805_DY
4
3
2
1
5
6
7
8
2
PVBAT_CHG
C6012
CSC0805_DY
1
2
2
R6027
20_5%_5
1
2
5
4
3
2
1
11
12
13
14
15
C6025
1UF_10V_2
2
1
1
R6024
10K_5%_2
2
PAD6015
7
IN
VRP5V0A_VIN
1
C6030
CSC0402_DY
2
VRPVADPTR_CSN
VRPVADPTR_CSP
C6029
1UF_25V_3
1
2
2
1
R6018
4.3K_5%_2
2
1
R6028
4.3K_5%_2
1
2
1
R6049
47K_1%_2
2
1
C6022
CSC0402_DY
2
RSC_0402_DY
R6021
300K_1%_2
RSC_0402_DY
1
R6029
2
1
R6030
2
S
2
1
C6026
0.047UF_16V_2
D
ACDET>3.15V = AC_OVP
2
R6026
2.2_5%_2
Q6001
BI
ACDET>2.4V = AC_OK TO CHARGE
1
G
BI
6
BATT_CLK
REGN
1
NMOS_4D3S
6
BATT_DAT
35
L6000
ETQP3W4R7WFN
VRPVPACK_PH
AON7410
35
ACDET>1.8V = ADP_PRES HI
35
S
LODRV
GND
SRP
SRN
BATDRV
OUT
D
BTST
ILIM
1
ACDET>0.6V = SMBUS OK
ADP_ID
PVPACK
1
VRPVPACK_HG
HIDRV
SCL
1SS355VMTE_17
I_ADP
20
19
18
17
16
PHASE
SDA
35
OUT
ADP_PRES
35
VCC
2
Q6000
U6000
IOUT
21
G
ACDET
D6018
AC_OK 35
AC_LED# 35
C
NMOS_4D3S
ACN
ACP
CMSRC
ACDRV
ACPRES
A
6
7
8
9
10
C6027
0.047UF_25V_3
TML
AON7410
TI_BQ24728_QFN_20P
OUT
IN
D
IN
P3V3AL
1
8
2
2
1
1
C6028
0.1UF_16V_2
PVADPTR
0.0015UF_50V_2
1
NMOS_4D3S
Q6011
AON7410
B
7
2
4
6
8
2
4
R6000
0.01_1%_6
C
PVADPTR
6
1
3
C7600
CSC0402_DY
G
8
7
6
5
4
POWERPAD_2_0610
OUT
D
2
5 ACDRV
PVBAT
S
2
5
R6048
1K_1%_2
2
8
7
6
5
NMOS_4D3S
1
2
3
4
1
3
ACES_59012_0080N_002_8P
C6024
CSC0402_DY
2
1
G
JACK6015
OUT
C6048
D
1
3
5
7
2
2
2
S
1
1SS355VMTE_17
1
C6032
0.01UF_50V_2
2
1
R6047
12K_1%_2
1
1
3
2
1
C6015
1000PF_50V_2
1
CSC0402_DY
2
C6016
3
1
C6017
1000PF_50V_2
2
1
IN
1
5
6
7
8
R6017
1M_5%_2
2
1
2
3
4
2
P1V5S
D6015
Q6012
AON7410
PVPACK
5BATDRV
P3V3AL
D6017
SEM_SM24_SOT23_3P_DY
1
C6019
0.1UF_25V_2
2
1
C6031
2200PF_50V_2
2
2
35
IN
CHG_LED#
3
1
2
2
CSC0402_DY
2
1
D
C6018
NMOS_4D3S
AON7410
2
G
8
7
6
5
1
D
R6015
2_5%_6
S
C6033
1UF_25V_3
1
2
3
4
IN
3
L6015
NFE31PT222Z1E9L
1
2
Q6010
5 ACDRV
4
PVADPTR
VADPBL
4
OUT
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
5
57
of
1
X01
8
7
6
5
4
3
2
1
D
D
5
35
BATT_CLK
1
BI
BI
D7506
PHP_PESD5V0S1BB_SOD523_2P
1
1
2
2
1
2
C7502
100PF_50V_2
D7505
1
1
2
2
1
2
C7501
100PF_50V_2
PHP_PESD5V0S1BB_SOD523_2P
R6051
100_5%_2
5
35
BATT_DAT
PHP_PESD5V0S1BB_SOD523_2P
1
1
D7504
2
2
1
2
C
C7500
100PF_50V_2
1
2
PVPACK
R6050
2.2K_5%_2
1
2
R6052
2.2K_5%_2
P3V3AL
C
1
2
3
4
5
6
7
8
2
1
2
R6053
1
100_5%_2
2
R6057
100_5%_2
P3V3AL
CN6050
1
2
3
4
5
6
G1
7
G2
G1
G2
8
FOX_BP02083_B82B5_9HV_8P
2
D7502
BAV99W_7_F
2
1
R6058
100K_5%_2
3
1
3
1
3
D7501
BAV99W_7_F
1
B
D7500
BAV99W_7_F
1
2
2
2
P3V3AL
C6050
0.1UF_25V_2
6012B0387101-002
B
BATT_IN# 35
OUT
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SELETOR
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
6
57
of
1
X01
8
7
6
5
4
3
2
D6999
OCP=7AMP
PVADPTR
OCP=7AMP
1
IN
1
2
IN
P5V0A
PVBAT
P3V3A
2
1
2
3
PAD6100
2
PAD6150
BAV70W_7_F
1
7 VRP3V3A
IN
OUT
75VRP5V0A_VIN
IN
EN_5V
2
1
1
VRP5V0A 7
IN
14
POWERPAD_2_0610
POWERPAD_2_0610
PVBAT
1
2
R6160
61.9K_1%_2
R6110
73.2K_1%_2
2
1
1
1
2
PAD6110
2
D
OUT
IN
VBATP
7
IN
POWERPAD_2_0610
EN_3V
D
2VREF
TON=3.3V:300KHZ/375KHZ
5V_PG OUT
VRP5V0A_PH
14
OUT
7
VBATP 7
1
2
C6161
10UF_25V_5
1
C6160
4.7UF_25V_5
2
5
6
7
8
4
3
2
1
1
2
1
R6150
15.4K_1%_2
2
1
B
R6151
10K_1%_2
2
2
1
2
1
C6120
10UF_6.3V_3
2
1UF_25V_3
C6122
1
2
R6113
330K_5%_2_DY
2
1
C6121
1UF_6.3V_2
2
1
VO=((6.8K/10K)+1)*2
7VRP5V0A_LDO
C7615
CSC0402_DY
+
1
13
14
15
16
17
18
G
1
2
3
4
OUT
C6150
330UF_6.3V
1
U6100
TI_TPS51123RGER_QFN_24P
7
OUT
VRP3V3A_LDO
VRP5V0A 714
OUT
ETQP3W3R3WFN
R7615
RSC_0603_DY
8
7
6
5
D
S
1
R7610
RSC_0603_DY
2
1
C7610
CSC0402_DY
2
1
+
VRP5V0A_HG
VRP5V0A_PH
1
2
3
4
2
L6150
S
C6100
220UF_6.3V
1
2
OCP=8AMP
2
Q6151
R6100
6.8K_1%_2
LL1
DRVL1
1
D
1
LL2
DRVL2
2
G
2
DRVH1
C6155
0.1UF_16V_2
2.2_5%_3
1
AON7702A
R6101
10K_1%_2
DRVH2
R6155
24
23
22
21
20
19
8
7
6
5
Q6101
AON7702A
B
VBST1
ENC
VREG5
VIN
GND
SKIPSEL
EN0
VRP3V3A_HG
VRP3V3A_PH
VRP3V3A_LG
2
ETQP3W3R3WFN
PGOOD
VBST2
2
1
OUT
C6123
0.22UF_6.3V_2
2
1
25
NMOS_4D3S
G
S
1
2
3
4
VRP3V3A
6
5
4
3
2
1
8
7
6
5
D
1
C6111
10UF_25V_5
2
1
2
7
VO1
VREG3
Q6150
L6100
VO2
C
S
7
8
9
10
11
12
2
D
R6114
2.2_5%_3
1
G
2
NMOS_4D3S
1
AON7410
C6115
0.1UF_16V_2
TRIP1
VFB1
VREF
TONSEL
VFB2
TRIP2
TML
OCP=8AMP
Q6100
AON7410
C6110
4.7UF_25V_5
IN
C
VO=((15.4K/10K)+1)*2
14VRP5V0A_LG
IN
A
A
SKIP:OOA=3.3V; PWM=2VREF; AUTO=GND
14
SKIP_3V_5V
IN
EN_3V_5V
IN
75
VRP5V0A_VIN
IN
14
P3V3AL
INVENTEC
P5V0AL
PAD6103
2
2
1
1
IN
2
POWERPAD1X1M
2
1
1
IN
7
6
5
4
XXX
3
MODEL,PROJECT,FUNCTION
7 VRP5V0A_LDO
POWERPAD1X1M
CHANGE by
8
TITLE
PAD6105
7 VRP3V3A_LDO
DATE
21-OCT-2002
2
P3V3A
SIZE
CODE
A3
CS
& P5V0A
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
7
57
of
1
X01
8
7
6
5
4
3
2
1
OCP=16AMP
P1V5
PVBAT
PAD6200
2
P5V0A
1
1
D
2
MODE
VTTGND
18
TRIP
VTTREF
1
2
C6210
10UF_25V_5
4.7UF_25V_5
1
C6211
2
VRP1V5
8
1
C
5
1
OUT
C6221
0.22UF_6.3V_2
2
1
C6220
TI_TPS51216RUKR_QFN_20P
10UF_6.3V_3
21
2
R6202
75K_1%_2
1
2
OUT
P0V75M_VREF
TML
R6203
100K_5%_2
2
1
1
0.1UF_16V_2
C6218
2
1
C6217
2
0.01UF_50V_2
2
R6201
19
2
4
+
4
GND
4
C6200
330UF_2V_9MR_PANA_-35%
1
7
2
2
3
VTTSNS
1
2
VTT
1
9
VLDOIN
S
VDDQSNS
1
2
3
4
10
20
G
REFIN
PGND
PGOOD
D
VREF
1
3
PAD6220
POWERPAD1X1M
1
2
1
2
VRP1V5_LG
11
Q6201
6
2
2
ETQP3W1R0WFN
1
3
FDMS0310AS
1
8
L6200
VRP1V5_HG
8
7
6
5
2
8
52.3K_1%_2
VRP1V5
OCP=16AMP
S5
10K_1%_2
B
IN
D
VRP1V5_PH
R6200
1
IN
1
S
1
D
13
C6215
0.1UF_16V_2
2
Q6200
SW
DRVL
DDR3L_SEL
1
1
2
3
4
DRVH
14
R6215
2.2_5%_3
1
G
15
NMOS_4D3S
16
IN
S3
VBST
FDMC8884
15 EN_P1V5
17
IN
V5IN
R7620
C7620
CSC0402_DY RSC_0603_DY
C6216
2.2UF_6.3V_3
2
1
8
7
6
5
U6200
C
2
P0V75S
12
15 EN_P0V75
PAD6210
POWERPAD_2_0610
2
2
POWERPAD_2_0610
P1V5_PG
B
15
VOUT=REFIN=1.8*(52.3K/(10K+52.3K))
MODE=100KOHM:TRACKING DISCHARGE
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P1V5
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
8
57
of
1
X01
8
7
6
5
4
3
2
1
OCP=17AMP
P1V05S_CPU
PAD6300
2
2
1
1
IN
955
12
VRP1V05S_VCCP
POWERPAD_2_0610
D
D
2
2
1
1
1
R6303
100K_5%_2
2
14
13
EN
BST
VRP1V05S_VCCP_PH
11
VRP1V05S_VCCP_HG
1
1
2
15
MODE
12
DH
C6311
4.7UF_25V_5
16
SW
2
17
PWPD
REFIN
S
VREF
2
D
1
Q6300
R6307 2
C
OCP=17AMP
1
3
1
2
3
4
2
4
OUT
9VRP1V05S_VCCP
55
12
1
+
C6301
560UF_2.5V
2
1
CYN_PCMB063T_R68MS_4P
C6300
22UF_6.3V_5
1
1
1
5
6
7
8
2
7
6
5
8
2
S
R6302
60.4K_1%_2
1
2
D
VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND
G
B
Q6301
1
C6319
0.01UF_50V_2
L6300
P5V0A
TI_TPS51219RTER_QFN_16P
2
VRP1V05S_VCCP_LG
2
9
2
10
V5
R7630
RSC_0603_DY
DL
VSNS
C7630
CSC0402_DY
GSNS
4
4
3
2
1
IN
3
C6316
2.2UF_6.3V_3
0_5%_2
GND
IN
20
VCC_SENSE_VCCIO
CHOKE_4PIN_2PIN
PGND
20
VSS_SENSE_VCCIO
TRIP
IN
COMP
1
C6308
2
21
VCCIO_SEL
FDMS0310AS
2.2UF_10V_3
1
2
3
4
1
U6300
G
R6306
10K_5%_2
2
NMOS_4D3S
1
C6315
0.1UF_16V_2
1
2
FDMC8884
C
R6315
2.2_5%_3
2
8
7
6
5
1
P3V3A
2
1
OUT
PGOOD
15 VCCIO_PG
C6310
10UF_25V_5
MODE=100KOHM/300KHZ
C6312
CSC0805_DY
IN
PAD6310
POWERPAD_2_0610
PVBAT
15
EN_P1V0_VCCP
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P1V05S_CPU
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
9
57
of
1
X01
8
7
6
5
4
3
2
1
OCP=4.5AMP
P1V8S
PAD6970
2
2
1
1
10
VRP1V8S
IN
POWERPAD_2_0610
D
D
U6970
GMT_AT1530F11U_SOP8_8P
TML
OCP=4.5AMP
C
9
L6970
7
1
VRP1V8S_PH
2
OUT
5
EN
REF
2
1
1
1
2
C6973
0.1UF_16V_2
2
GND
3
IN
PGND
EN_P1V8
6
1
2
C6972
0.1UF_16V_2
15
C6970
22UF_6.3V_5
4
2
FB
1
1
VCC
2
1
VRP1V8S
10
PAN_ELL5PR2R2N
C6974
CSC0402_DY
LX
2
VIN
R6973
13K_1%_2
8
R6972
10K_1%_2
1
2
C6971
10UF_6.3V_3
2
C
P3V3S
R6970
10_5%_2
1
P3V3S
VOUT=((13K+10K)+1)*0.8
B
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P1V8S
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
10
57
of
1
X01
8
7
6
5
4
3
2
1
OCP=7AMP
PVSA
P5V0A
PAD6500
PAD6510
1
1
2
2
OUT
2
11
VRPVCCSA_IN
2
1
1
IN
VRPVSA
21
11
POWERPAD_2_0610
POWERPAD1X1M
D
1
C6522
0.01UF_50V_2
2
1
R6520
5.11K_1%_2
2
1
2
C6521
0.22UF_6.3V_2
2
1
C6520
3300PF_50V_2
D
IN
1
21
VCCSA_SENSE
2
OCP=7AMP
GND
VREF
COMP
SLEW
VOUT
MODE
1
2
3
4
5
6
R6521
RSC_0402_DY
18
17
16
15
14
13
11
VRPVCCSA_IN
2
4
11
VRPVSA 21
OUT
2
C6515
0.1UF_16V_2
TI_TPS51461RGER_QFN_24P
1
R6502
0_5%_22
1
R6524
0_5%_2
2
1
R6525
0_5%_2
2
C6500
C6501
C6502
C6503
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5_DY
15
IN
EN_PVCCSA
IN
VCCSA_VID0 21
IN
VCCSA_VID1 21
B
R6523
10K_5%_2
2
1
R6522
10K_5%_2
2
1
B
C6524
1UF_6.3V_2
2
1
4
CYN_PCMB063T_R33MS_4P
1
IN
C6523
1UF_6.3V_2
2
1
2
1
BST
1
3
2
SW
PGND
1
3
1
SW
PGND
C
L6500
VRPVSA_PH
7
8
9
10
11
12
2
U6500
PGND
SW
1
SW
VIN
2
SW
VIN
V5DRV
V5FILT
PGOOD
VID1
VID0
EN
C6510
22UF_6.3V_5
2
1
TML
VIN
1
25
24
23
22
21
20
19
IN
C6511
0.1UF_16V_2
2
1
11
VRPVCCSA_IN
2
C
OUT PVCCSA_PG 15
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PVSA
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
11
57
of
1
X01
3
28
14
OUT
PVCORE_PG
17
CPGOOD
20
12
IN
VR_SVID_CLK
18
VCLK
OUT
VR_SVID_ALERT#
19
ALERT#
BI
VR_SVID_DATA
20
VDIO
1
2
39
1
23
GPGOOD
CDH2
38
2.2_5%_3
24
GF_IMAX
VBAT
37 1
1
0.1UF_16V_2
R6616
10K_5%_3
R6723
0_5%_2_DY
IN
6
2
1
C6615
CSC0805_DY
1
C6614
CSC0805_DY
2
1
1
+
C6603
470UF_2V
1
+
2
3
+
1
C6602
470UF_2V
1
2
1
VREF_CPU
2
IN
12
1
C6727
0.1UF_16V_2_DY
R6729
100K_1%_NTC
20
12
IN
VR_SVID_CLK
C6635
0.1UF_16V_2
R6728
15.4K_1%_2
A
55
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PVCORE
BI
VR_SVID_DATA
13
13
7
9VRP1V05S_VCCP
IN
CHANGE by
8
3
36
CPWM3
9/21 EE CHANGE TO VRP1V05S FROM P1V05S_CPU
20
12
R6638
2
35
GPWM2
5
6
7
8
4
3
2
1
13
R6730
100K_5%_2
2
IN
IN
IN
2
R6631
8.66K_1%_2
OUT
1
12
GSKIP#
2
OUT
1
VR_ON
CSC0402_DY
R6633
130_1%_2
2
GPU_CSN1 2
R6724
GPU_CSP1 2
R6720
GPU_CSP2 2
R6722
GPU_CSN2 2
R6726
1
R6630
20K_5%_2
12
1
1
A
B
RSC_0402_DY
2
R6725
0_5%_2
R6718
4.12K_1%_2
IN
1
EN_PVCORE
VREF_CPU
2
IN
2
1
1
2
2
C6726
100PF_50V_2
1
R6731
1
2
2
PVCORE
4
2
C7662
R6632
54.9_1%_2
1
13
2
2
L6620
PAN_ETQP4LR36ZFC_4P
R7662
RSC_0603_DY
1
1
1
R6609
28.7K_1%_2
2
VREF_CPU
1
0_5%_2
1
0_5%_2
1
0_5%_2_DY
1
0_5%_2_DY
IN
2
S
12
G
2
1
R6608
100K_5%_NTC
2
R6721
0_5%_2
1
2
4
3
2
1
34
33
GPWM1
32
31
30
29
28
27
R6719
0_5%_2_DY
1
2
OUT
1
OUT
2
2
OUT
1
2
3
1
Q6621
GFX_VSS_SENSE
D
IN
R6716
0_5%_2_DY
15
1
R6607
17.8K_1%_2
2
25
PVBAT
FDMS0306AS
21
2
R6610
162K_1%_2
S
P3V3A
R6715
0_5%_2
1
1
Q6620
2
D
R6714
0_5%_2_DY
OUT CPU_CSP2
C6625
0.033UF_16V_2
G
1
OUT CPU_CSN2
12
12
2
NMOS_4D3S
2
2
IN
12
C6624
2
FDMS7692
CPWM3
GPWM2
GSKIP#
GPWM1
GTHERM
GCSP2
GCSN2
1
1
2
40
R6713
0_5%_2
GFX_VCC_SENSE
C
2
CSW2
CBST2
R6606
PVAXG_PG
4
3
2
1
PVBAT_CPU
VR_HOT#
GCSP1
1
41
SLEW
GCSN1
2
42
CDL2
22
GVFB
IN
PGND
2
C7661
CSC0402_DY
P5V0A
21
GCOMP
R6629
20K_1%_2
21
OUT
CPU_PROCHOT#
GGFB
1
R6712
30K_1%_2
14
OUT
43
0.1UF_16V_2
5
6
7
8
2
C6633
2.2UF_6.3V_3
35
17
44
TI_TPS51650RSLR_QFN_48P
26
2
1
R6628
0_5%_2_DY
2
1
R6711
200K_1%_2
20
20
12
CDL1
V5DRV
U6600
C6613
10UF_25V_5
1
2
1
L6610
PAN_ETQP4LR36ZFC_4P
R7661
RSC_0603_DY
1
2
PVCORE
4
2
+
IN
2.2_5%_3
3
1
2
C6601
470UF_2V
1
45
1
R6604
28.7K_1%_2
3
46
CSW1
2
2
CBST1
VR_ON
1
R6603
100K_5%_NTC
C6600
470UF_2V
V3R3
16
12
2
R6602
17.8K_1%_2
S
15
VR_ON
1
G
C6622
2
3
12
IN
C6612
10UF_25V_5
1
C6611
10UF_25V_5
2
1
2
V5_CPU
1
R6605
162K_1%_2
2
47
C6630
4.7UF_10V_3
1
2
C6629
2.2UF_10V_3
3
1
4
2
5
48
D
1
1
IN
CPU_CSP1
6
V5
CDH1
2
+
2
2
C6631
0.1UF_16V_2_DY
12
IN
IN
7
CPU_CSN1
CPU_CSN2
IN
8
CPU_CSP2
9
CPU_CSP3
10
CPU_CSN3
2
1
R6618
100K_1%_NTC
12
12
IN
12
IN
20
20
IN
IN
11 VCCSENSE
2
49
2
C6623
0.033UF_16V_2
Q6611
CF-IMAX
GND
2
R6617
10_5%_3
IN
D
CCSP1
C6634
2.2UF_6.3V_3
1
1
12
FDMS0306AS
CCSN1
COCP-R
CCSN2
CTHERM
CCSP2
VREF
CCSP3
GOCP-R
14
V5_CPU
OUT
R6601
C
B
13
CCSN3
IN
12
12
CCOMP
P3V3A
VREF_CPU
12 VSSSENSE
VREF_CPU
P5V0A
CPU_CSP1
OUT
Q6610
OUT
VREF_CPU
12
IN
S
0
DNP 12 0
R6619
15.4K_1%_2
1
2
12
OUT
OUT CPU_CSN1
12
PVBAT_CPU
12
D
DNP
R6723
1
R6636
0_5%_2
2
9/21 EE CHANGE
MOVE C6699.1 TO PAD6610.1
FROM PAD6610.2
G
R6719
R6635
0_5%_2
2
C6699
68UF_25V
NMOS_4D3S
0
1
PVBAT_CPU
2
2
FDMS7692
0
DNP
CVFB
DNP
R6716
2
P3V3A
1
POWERPAD_2_0610
1
R6623
24K_1%_2
1
2
R6625
8.45K_1%_2
CGFB
R6714
1
1
30K DNP
R6626
3.3K_1%_2
200K DNP
R6712
2
C6632
100PF_50V_2
2
R6711
1
1
56K DNP
VREF_CPU
IN
R6627
56K_1%_2
R6627
12
1
D
2+0
3.3K DNP
2
2+1
R6626
1
PAD6610
1
R6621
90.9K_1%_2
1
2
2
PVBAT
1
VREF_CPU
IN
4
R6622
39K_1%_2
1
2
5
6
7
8
12
5
R6620
43K_1%_2
1
2
C6610
10UF_25V_5
6
4
3
2
1
7
5
6
7
8
8
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
1
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
12
57
of
1
X01
8
7
6
5
4
3
2
1
D
D
12
PVBAT_AXG
12
IN
OUT
GPU_CSN1
13OUT
GPU_CSP1
1
5
6
7
8
1
1
PVBAT_AXG
2
2
C7671
CSC0402_DY
1
2
1
1
C6700
470UF_2V
OUT
13
C6711
10UF_25V_5
2
PAN_ETQP4LR24AFM_4P
+
R7671
RSC_0603_DY
PAD6710
POWERPAD_2_0610
2
1
4
2
3
1
4
S
C6721
D
2
3
L6710
Q6711
P5V0A
G
FDMS0306AS
TI_TPS51601DRBR_SON_8P
3
1
2
DRVL
8
7
6
5
C
PVAXG
2
R6704
28.7K_1%_2
9
1
VDD
GND
PVBAT
1
C6710
10UF_25V_5
4
3
2
1
SW
PWM
2
R6703
100K_5%_NTC
1 2
SKIP#
DRVH
1
2
BST
2
R6702
17.8K_1%_2
5
6
7
8
GPWM1
1
2
3
4
1
4
3
2
1
IN
PAD
GSKIP#
1UF_6.3V_2
12
IN
2
R6705
162K_1%_2
S
U6710
12
D
2
0.1UF_16V_2
G
2.2_5%_3
1
1
Q6710
C6720
2
NMOS_4D3S
1
FDMS7692
R6701
C
2
C6722
0.033UF_16V_2
B
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PVCORE
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
2
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
13
57
of
1
X01
8
7
6
5
4
3
2
1
P3V3A
IN
1
OUT PVAXG_PG
P15V0A
D
2
DGPU_PWROK
1
2
P3V3AL
1
DGPU_PG
2
2
IN
56
VRP5V0A 7
IN
1
D6997
BAV99W_7_F
2
2
PAD2
OUT
1
C6995
0.1UF_25V_2
1
R123
10K_5%_2
31
2
D6998
BAV99W_7_F
P3V3S
1
1
1
12
1
C6994
0.1UF_25V_2
OUT PVCORE_PG
2
C6997
0.1UF_25V_2
2
12
1
3
28
POWERPAD_2_0610
2
C6998
0.1UF_25V_2
C6996
0.1UF_25V_2
1
2
2
D
35
7
3
PAD6301
2
1
R6732
2K_5%_2
P1V05S_CPU
2
P1V05S_PCH
52
VRP5V0A_LG
OCP=8AMP
1
R6634
2K_5%_2
OCP=12AMP
R6999
7
POWERPAD1X1M
5V_PG
1
IN
2
2
100K_5%_2_DY
60110GA0367T_DY
NC
D504
56
P1V5
P5V0A
PVCORE
1
2
0.1UF_25V_2_DY
P1V5S_DGPU
C977
0.1UF_25V_2_DY
1
C976
2
0.1UF_25V_2_DY
1
C975
2
1
C981
P1V5S_DGPU
0.1UF_25V_2_DY
2
P1V05S_CPU
2
1
0.1UF_25V_2_DY
C980
1
0.1UF_25V_2_DY
C989
2
1
0.1UF_25V_2_DY
C988
1
P3V3S
2
C984
2
2
B
C987
1
0.1UF_25V_2_DY
1
C111
0.01UF_50V_2
P3V3S
0.1UF_25V_2_DY
P3V3S
2
OUT
1
EN_DGPU
2
0_5%_2
0.1UF_25V_2_DY
1
C986
PX_MODE
2
IN
EMI Part
1
52
1
2
55
R6781
C
DIODE-BAT54-TAP-PHP_DY
0.1UF_25V_2_DY
3
C985
C
B
PVCORE_DGPU
R6996
35
21
15
1
CORE_PWEN IN
2
OUT
SKIP_3V_5V
7
SHORT_0402
OUT
ALWAYS_PW_EN 35
PVBAT
0.1UF_25V_2_DY
1
C983
2
0.1UF_25V_2_DY
1
2
C982
0.1UF_25V_2_DY
1
2
C990
0.1UF_25V_2_DY
1
C995
2
0.1UF_25V_2_DY
1
2
C994
1
2
0.1UF_25V_2_DY
C993
1
C992
0.1UF_25V_2_DY
2
C991
1
A
2
1
2
R6998
200K_5%_2
2
A
2
R6997
1K_5%_2
0.1UF_25V_2_DY
1
IN
1
EN_3V_5V
C6999
0.1UF_25V_2
7
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER TO EE PORT & EMI PART
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
14
57
of
1
X01
8
7
6
5
4
3
2
1
P3V3S
P3V3S
R1067
2
8
R1070
P1V5_PG
IN
1
2
100_5%_2
2
11
0_5%_2
PVCCSA_PG
1
IN
R1068
ALL_PWGD_IN
2
P5V0S
15
9
VCCIO_PG 1
IN
3.135A
R1069
2
100_5%_2
2
P5V0A
C1013
1
100_5%_2
3
RSC_0603_DY
C1012
1
1
2
2
35
IN
R703
2
100K_5%_2
RESUME_PWEN
1
EN_P1V5
0_5%_2
2
Q559
OUT
C
R950
D
5.647A
IN
CORE_PWEN 1
EN_P1V8
2
0.01uF_50V_2
2
1
DIODE-BAT54-TAP-PHP
21
15
14
IN
R842
1
EN_P0V75
2
100K_5%_2
C843
2
8
9
IN
P3V3S
15
VCCIO_PG
R7016
1
B
2
EN_PVCCSA
OUT
11
2
EN_PVCORE
OUT
12
D
Q566
OUT
1
35
CORE_PWEN
1
0_5%_2
3
10
OUT
10K_5%_2
1
2
2
C868
2
D7000
C998
R7006
1
RSC_0603_DY
1
14
R7017
G
1
2
3
4
NC
S
0.1uF_16V_2
2
D
10uF_6.3V_3
8
7
6
5
P5V0S
R1066
15
10K_5%_2
NMOS_4D3S
32
21
Q560
AON7410
B
35
1
G
SSM3K7002FU_DY
D
35
P1V5S
P1V5
S
1
17
8
2
1
R1071
32
C
R7005
1
G
NMOS_4D1S
FDC655BN
P3V3S
CSC0402_DY
4
C681
S
D
10uF_6.3V_3
Q558
1
2
5
6
OUT
1000PF_50V_2
1
2
1
2
2
SSM3K7002FU
2200pF_50V_2
C999
G
10uF_6.3V_3
C1014
1M_5%_2
1
CORE_PWEN# 1
IN
3
R7004
1
3
15
S
35
G
D
NMOS_4D1S
D
Q561
S
4
FDC655BN
2
R1053
Q567
1
2
5
6
P15V0A_RC
D
1
2.665A
P15V0A
10K_5%_2
P3V3A
0_5%_2
G
S
1
EN_P1V0_VCCP => 1.05V
35
21
15
14
IN
CORE_PWEN 1
R657
EN_P1V0_VCCP
2
2
2
R841
31
9
35
IN
CPU_PWEN
R7021
1
0_5%_2
D
Q545
35
15
IN
CORE_PWEN#1
A
G
S
G
S
1
OUT
D
Q568
A
22_5%_2_DY
P0V75S
220_5%_2_DY
31
R1073
2
P1V5S
C662
1
10K_5%_2
0.01uF_50V_2
2
SSM3K7002FU_DY
2
SSM3K7002FU_DY
2
SSM3K7002FU_DY
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P5V0S
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
& P3V3S
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
15
57
of
1
X01
8
7
6
5
4
Green CLK
3
2
1
P3V3AL
1
L1
2
FBM_11_160808_121T
200MA_0603
60140EA0319T
0.1UF_16V_2
C185
2
P3V3AL
D
1
P3V3_RTC
C186
C182
2
16
1
0.1UF_16V_2
R125
33_5%_2
P3V3A_LAN
V3.3A
VDDIO_25M_B
GND
XTAL_IN
VDD
GND
17
GND
NC
25M_B
NC
25M_A
GND
VBAT
R126
10_5%_2
1
C188
1
VBAT
IN
2
RTC_32K_IN
2
1
VS_SLG3NB250V_TQFN_16P
0.1UF_16V_2
26
OUT
49
PCH_25M_IN
OUT
27
LAN_25M_IN
OUT
41
1
6019B0934701
C
D
0.1UF_16V_2
2
GPU_27M_IN_1V8
8
C184
2
32k
15
14
13
12
11
10
9
VOUT
VDDIO_25M_A
GREEN_CLK_25M_IN 1
2
3
4
R127
SHORT_0402
1
2
5
PCH_25M_IN
1
2
6
LAN_25M_IN
7
C183
OUT
GPU_27M_IN_1V8
P1V8S
U9
XTAL_OUT
P1V05S_PCH
26
TYPICAL RTC_32K_IN TRACE <= 6
MAX. LENGTH <= 24
TYPICAL GPU_27M_IN TRACE <= 8
MAX. LENGTH <= 12
22UF_6.3V_5
0.1UF_16V_2
2
1
GREEN_CLK_25M_OUT
1
C187
2
2.2UF_6.3V_2
RTC_32K_IN
TYPICAL LAN_25M_IN TRACE <= 8
MAX. LENGTH <= 12
C
TYPICAL LAN_25M_IN TRACE <= 8
MAX. LENGTH <= 12
FOR SG USE
SLG3NB300V SUPPORT 27MHZ
P/N : 6019B0941101
FOR UMA USE
SLG3NB250V
P/N : 6019B0934701
FOR UMA
U9 : 6019B0934701
R126 : NA
C188 : NA
X2
25MHz
6018B0044501
27pF_50V_2
2
1
4
GREEN_CLK_25M_OUT
1
3
C181
C180
1
2
27pF_50V_2
GREEN_CLK_25M_IN
2
B
FOR SG
U9 : SLG3NB300V P/N APPLY
R126 : MOUNT
C188 : MOUNT
IF USE U9 ( SLG3NB250V )
MOUNT
X2
R1
L1
C180
C181
C182
C183
C184
C185
C186
C187
R906 (PAGE26)
R912 (PAGE27)
R414 (PAGE41)
R120 (PAGE49)
OPEN (PAGE26)
D4400
X501
R958
C874
C875
OPEN (PAGE41)
X400
C402
C403
OPEN (PAGE27)
X503
R1041
C962
C965
OPEN (PAGE49)
X1
R29
C35
C36
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
GREEN CLK SLG3NB250
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
16
57
of
1
X01
8
7
6
5
4
3
2
1
P1V8S
1
C26
H_SNB_IVB#
PROC_SELECT#
CLOCKS
R683
2
2.2K_5%_2
R684
1
CN510
MISC
NV_CLE
OUT
2
R4500
2
31
1K_5%_2_DY
1
6026B0154901_CHIEFRIVER
1 AN34
A16
A15
DPLL_REF_CLK
R750
31
AN33
PECI
AL32
PROCHOT#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_THRMTRIP#
OUT
AN32
2
H_PM_SYNC
BI
31
IN
17
IN
AM34
H_CPUPWRGD
PM_SYNC
AP33
PM_DRAM_PWRGD_CPU
1
46
35
30
BUF_PLT_RST#1
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
R693
R737
140_1%_2
2
2 25.5_1%_2
2
R694
200_1%_2
1
1
1
TP30
TP30
TP4504 1
TP4505 1
TP4506 1
TP30
TP30
TP30
TDO
AR28
AP26
XDP_TDI_R
XDP_TDO
TP4507 1
TP4508 1
TP30
TP30
DBR#
AL35
XDP_DBRESET#
TP4509 1
TP30
TCK
TDI
17
IN
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
BPM#[0]
BPM#[2]
AR33
2 BUF_PLT_RST#_CPU
RESET#
BPM#[3]
1
2
750_1%_2
R789
C
SM_DRAMPWROK
R790
200_5%_2
1
0.1uF_16V_2
R800
2
1
C4502
2
BPM#[5]
BPM#[6]
BPM#[7]
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
B
U500
P1V5
VCC
A
Y
3
GND
5
4
PM_DRAM_PWRGD_CPU
OUT
17
1
B
R807
1
2
NXP_74AHC1G09GV_SOT753_5P
6019B0773901
XDP_DBRESET# R788
R801
2
(OD AND GATE)
P3V3S
1K_1%_2
1
200_5%_2
AK1
A5
A4
OUT
TP4502 1
TP4503 1
BPM#[4]
R14115
2
P1V05S_CPU
UNCOREPWRGOOD
V8
2 PM_DRAM_PWRGD_CPU_R
1.5K_1%_1/16W
PM_DRAM_PWRGD
ALL_PWGD_IN
CPU_DRAMRST#
XDP_TCLK
XDP_TMS
XDP_TRST#
BPM#[1]
IN
IN
R8
XDP_PREQ#
TMS
130_1%_2
28
15
1K_5%_2
AR26
AR27
AP30
TRST#
R799
35
1K_5%_2
AP29
AP27
PRDY#
PREQ#
JTAG & BPM
28
B
27
27
IN
IN
R749
1
C
P1V5S
2
2
THERMTRIP#
10K_5%_2
P3V3A
CLK_DP_PCH_R_DN
CLK_DMI_PCH_DP
CLK_DMI_PCH_DN
D
MISC
DDR3
CATERR#
56_5%_2
47pF_50V_2
1
C805
CPU_PROCHOT#_R
2
AL33
THERMAL
H_PECI
OUT
1
2
1
PWR MANAGEMENT
1
62_5%_2
R748
2
TP4501
TP30
CPU_PROCHOT#
IN
R689
1
1
CLK_DP_PCH_R_DP
R690
P1V05S_CPU
35 12
CLK_DMI_PCH_R_DN
SKTOCC#
DPLL_REF_CLK#
35
1
1
CLK_DMI_PCH_R_DP
R638
1K_5%_2TP4500
TP30
D
0_5%_2
2
2
0_5%_2
R639
A28
A27
BCLK
BCLK#
2
DIMM_DRAMRST# OUT
24
1
2
1K_5%_2
25
P1V05S_CPU
3
1
1K_5%_2
21
IN
PCH_DDR_RST
1
G
S
27
D
Q539
BSS138LT1
R805
2
2
C809
1
A
1
2
CPU_DRAMRST#
4.99K_1%_2
IN
0.047uF_16V_2
17
XDP_TDO
R792
1
XDP_TMS
R1076
1
2 51_5%_2
2 51_5%_2
XDP_TDI_R
R1074
1
2 51_5%_2
XDP_PREQ#
R1075
1
2 51_5%_2_DY
XDP_TRST#
R791
1
XDP_TCLK
R1077
1
2 51_5%_2
2 51_5%_2
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
1
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
17
57
of
1
X01
8
7
6
CN510
5
R736
WITHIN 500 MILS
OF THE CPU
6026B0154901_CHIEFRIVER
PEG_ICOMPI
PEG_ICOMPO
IN
IN
IN
IN
28
28
28
28
IN
IN
IN
IN
DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP
B28
B26
A24
B23
28
28
28
28
OUT
OUT
OUT
OUT
DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN
G21
E22
F21
D21
28
28
28
28
OUT
OUT
OUT
OUT
DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP
G22
D22
F20
C21
D
B27
B25
A25
B24
DMI_RX#[0]
PEG_RCOMPO
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
DMI_RX[2]
PEG_RX#[4]
DMI_RX[3]
PEG_RX#[5]
28
28
28
28
28
28
28
28
P1V05S_CPU
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
A21
H19
E19
F18
B21
C20
D18
E17
FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP
A22
G19
E20
G18
B20
C19
D19
F17
PCI EXPRESS* - GRAPHICS
C
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
Intel(R) FDI
28
28
28
28
28
28
28
28
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
28
28
IN
IN
FDI_FSYNC0
FDI_FSYNC1
J18
J17
FDI0_FSYNC
28
IN
FDI_INT
H20
FDI_INT
PEG_TX#[8]
28
28
IN
IN
FDI_LSYNC0
FDI_LSYNC1
FDI0_LSYNC
PEG_TX#[10]
FDI1_LSYNC
PEG_TX#[11]
FDI1_FSYNC
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[9]
J19
H17
PEG_TX#[12]
PEG_TX#[13]
R686
1
PEG_TX#[14]
2
CPU_EDP_COMPIO
A18
A17
B16
24.9_1%_2
eDP_COMPIO
PEG_TX#[15]
PEG_TX[0]
eDP_HDP#
PEG_TX[1]
eDP_AUX
eDP_AUX#
PEG_TX[2]
eDP
R686
WITHIN 500 MILS
OF THE CPU
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
C17
F16
C16
G15
PEG_TX[7]
eDP_TX[0]
eDP_TX[1]
PEG_TX[8]
eDP_TX[2]
PEG_TX[9]
eDP_TX[3]
PEG_TX[10]
PEG_TX[11]
C18
E16
D16
F15
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RX0_C_DN
PEG_RX1_C_DN
PEG_RX2_C_DN
PEG_RX3_C_DN
PEG_RX4_C_DN
PEG_RX5_C_DN
PEG_RX6_C_DN
PEG_RX7_C_DN
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_RX0_C_DP
PEG_RX1_C_DP
PEG_RX2_C_DP
PEG_RX3_C_DP
PEG_RX4_C_DP
PEG_RX5_C_DP
PEG_RX6_C_DP
PEG_RX7_C_DP
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_TX0_DN
PEG_TX1_DN
PEG_TX2_DN
PEG_TX3_DN
PEG_TX4_DN
PEG_TX5_DN
PEG_TX6_DN
PEG_TX7_DN
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_TX0_DP
PEG_TX1_DP
PEG_TX2_DP
PEG_TX3_DP
PEG_TX4_DP
PEG_TX5_DP
PEG_TX6_DP
PEG_TX7_DP
1
R736
1
2
24.9_1%_2
IN
IN
IN
IN
IN
IN
IN
IN
CLOSE TO CPU
IN
IN
IN
IN
IN
IN
IN
IN
48
48
48
48
48
48
48
48
18
48
48
48
48
48
48
48
48
18
18
18
18
18
18
18
18
PEG_TX0_DN
C628
1
2
0.1UF_16V_2
PEG_TX0_C_DN
OUT
48
C622
1
2
0.1UF_16V_2
PEG_TX1_C_DN
IN
OUT
48
18
IN
PEG_TX2_DN
C629
1
2
0.1UF_16V_2
PEG_TX2_C_DN
OUT
48
18
IN
PEG_TX3_DN
C623
1
2
0.1UF_16V_2
PEG_TX3_C_DN
OUT
48
18
IN
PEG_TX4_DN
C626
1
2
0.1UF_16V_2
PEG_TX4_C_DN
OUT
48
18
IN
PEG_TX5_DN
C624
1
2
0.1UF_16V_2
PEG_TX5_C_DN
OUT
48
18
IN
PEG_TX6_DN
C601
1
2
0.1UF_16V_2
PEG_TX6_C_DN
OUT
48
18
IN
PEG_TX7_DN
C620
1
2
0.1UF_16V_2
PEG_TX7_C_DN
OUT
48
18
IN
PEG_TX0_DP
C631
1
2
0.1UF_16V_2
PEG_TX0_C_DP
OUT
48
C619
1
2
0.1UF_16V_2
PEG_TX1_C_DP
IN
PEG_TX1_DP
OUT
48
18
IN
PEG_TX2_DP
C630
1
2
0.1UF_16V_2
PEG_TX2_C_DP
OUT
48
18
IN
PEG_TX3_DP
C618
1
2
0.1UF_16V_2
PEG_TX3_C_DP
OUT
48
18
IN
PEG_TX4_DP
C627
1
2
0.1UF_16V_2
PEG_TX4_C_DP
OUT
48
18
IN
PEG_TX5_DP
C621
1
2
0.1UF_16V_2
PEG_TX5_C_DP
OUT
48
18
IN
PEG_TX6_DP
C625
1
2
0.1UF_16V_2
PEG_TX6_C_DP
OUT
48
18
IN
PEG_TX7_DP
C600
1
2
0.1UF_16V_2
PEG_TX7_C_DP
OUT
48
18
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
PEG_TX1_DN
18
D
C
eDP_ICOMPO
B
C15
D15
CPU_PEG_ICOMPI
2
P1V05S_CPU
DMI_RX#[2]
PEG_RX#[6]
FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN
J22
J21
H22
3
DMI_RX#[1]
DMI
28
28
28
28
DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN
4
eDP_TX#[0]
PEG_TX[12]
eDP_TX#[1]
PEG_TX[13]
eDP_TX#[2]
PEG_TX[14]
eDP_TX#[3]
PEG_TX[15]
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
18
18
18
18
18
18
18
18
B
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
2
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
18
57
of
1
X01
8
7
6
5
4
3
2
1
CN510
CN510
6026B0154901_CHIEFRIVER
SA_CLK[0]
SA_CLK#[0]
C
B
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
M_A_DQ<0>
M_A_DQ<1>
M_A_DQ<2>
M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<38>
M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ[0]
SA_CKE[0]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQ[38]
SA_DQS#[1]
SA_DQ[39]
SA_DQS#[2]
SA_DQ[40]
SA_DQS#[3]
SA_DQ[41]
SA_DQS#[4]
SA_DQ[42]
SA_DQS#[5]
SA_DQ[43]
SA_DQS#[6]
SA_DQ[44]
SA_DQS#[7]
M_A_BS0
M_A_BS1
M_A_BS2
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
M_CS#0
M_CS#1
M_ODT0
M_ODT1
M_A_DQS0_DN
M_A_DQS1_DN
M_A_DQS2_DN
M_A_DQS3_DN
M_A_DQS4_DN
M_A_DQS5_DN
M_A_DQS6_DN
M_A_DQS7_DN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
24
24
24
24
24
24
24
24
24
24
24
24
SA_DQ[48]
SA_DQ[49]
SA_DQS[0]
SA_DQ[50]
SA_DQS[1]
SA_DQ[51]
SA_DQS[2]
SA_DQ[52]
SA_DQS[3]
SA_DQ[53]
SA_DQS[4]
SA_DQ[54]
SA_DQS[5]
SA_DQ[55]
SA_DQS[6]
SA_DQ[56]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
M_A_DQS0_DP
M_A_DQS1_DP
M_A_DQS2_DP
M_A_DQS3_DP
M_A_DQS4_DP
M_A_DQS5_DP
M_A_DQS6_DP
M_A_DQS7_DP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
24
24
24
24
24
24
24
24
SA_DQ[57]
SA_DQ[58]
24
24
24
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
M_B_DQ<0>
M_B_DQ<1>
M_B_DQ<2>
M_B_DQ<3>
M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<7>
M_B_DQ<8>
M_B_DQ<9>
M_B_DQ<10>
M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>
M_B_DQ<14>
M_B_DQ<15>
M_B_DQ<16>
M_B_DQ<17>
M_B_DQ<18>
M_B_DQ<19>
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
M_B_DQ<24>
M_B_DQ<25>
M_B_DQ<26>
M_B_DQ<27>
M_B_DQ<28>
M_B_DQ<29>
M_B_DQ<30>
M_B_DQ<31>
M_B_DQ<32>
M_B_DQ<33>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<36>
M_B_DQ<37>
M_B_DQ<38>
M_B_DQ<39>
M_B_DQ<40>
M_B_DQ<41>
M_B_DQ<42>
M_B_DQ<43>
M_B_DQ<44>
M_B_DQ<45>
M_B_DQ<46>
M_B_DQ<47>
M_B_DQ<48>
M_B_DQ<49>
M_B_DQ<50>
M_B_DQ<51>
M_B_DQ<52>
M_B_DQ<53>
M_B_DQ<54>
M_B_DQ<55>
M_B_DQ<56>
M_B_DQ<57>
M_B_DQ<58>
M_B_DQ<59>
M_B_DQ<60>
M_B_DQ<61>
M_B_DQ<62>
M_B_DQ<63>
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_DQ[0]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQ[37]
SB_DQS#[0]
SB_DQ[38]
SB_DQS#[1]
SB_DQ[39]
SB_DQS#[2]
SB_DQ[40]
SB_DQS#[3]
SB_DQ[41]
SB_DQS#[4]
SB_DQ[42]
SB_DQS#[5]
SB_DQ[43]
SB_DQS#[6]
SB_DQ[44]
SA_MA[1]
SA_DQ[63]
SA_MA[2]
SA_MA[6]
AE10
AF10
V6
SA_BS[0]
SA_MA[7]
SA_BS[1]
SA_MA[8]
SA_BS[2]
SA_MA[9]
AE8
AD9
AF9
SA_CAS#
SA_MA[13]
SA_RAS#
SA_MA[14]
SA_WE#
SA_MA[15]
M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>
M_A_A<6>
M_A_A<7>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>
M_A_A<14>
M_A_A<15>
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
M_B_BS0
M_B_BS1
M_B_BS2
AA9
AA7
R6
SB_DQS#[7]
SB_DQ[49]
SB_DQS[0]
SB_DQ[50]
SB_DQS[1]
SB_DQ[51]
SB_DQS[2]
SB_DQ[52]
SB_DQS[3]
SB_DQ[53]
SB_DQS[4]
SB_DQ[54]
SB_DQS[5]
SB_DQ[55]
SB_DQS[6]
SB_DQ[56]
M_B_CAS#
M_B_RAS#
M_B_WE#
D
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
M_CS#2
M_CS#3
OUT
OUT
25
25
AE4
AD4
AD5
AE5
M_ODT2
M_ODT3
OUT
OUT
25
25
D7
F3
K6
N3
AN5
AP9
AK12
AP15
M_B_DQS0_DN
M_B_DQS1_DN
M_B_DQS2_DN
M_B_DQS3_DN
M_B_DQS4_DN
M_B_DQS5_DN
M_B_DQS6_DN
M_B_DQS7_DN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
25
25
25
25
25
25
25
25
C7
G3
J6
M3
AN6
AP8
AK11
AP14
M_B_DQS0_DP
M_B_DQS1_DP
M_B_DQS2_DP
M_B_DQS3_DP
M_B_DQS4_DP
M_B_DQS5_DP
M_B_DQS6_DP
M_B_DQS7_DP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
25
25
25
25
25
25
25
25
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
C
SB_DQS[7]
B
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_MA[0]
SB_DQ[62]
SB_MA[1]
SB_DQ[63]
SB_MA[2]
SB_BS[0]
SB_MA[7]
SB_BS[1]
SB_MA[8]
SB_BS[2]
SB_MA[9]
SB_MA[12]
AA10
AB8
AB9
25
25
25
SB_DQ[57]
SB_MA[11]
OUT
OUT
OUT
OUT
OUT
OUT
SB_DQ[48]
SB_MA[10]
25
25
25
M_CLK_DDR3_DP
M_CLK_DDR3_DN
M_CKE3
SB_DQ[47]
SB_MA[6]
OUT
OUT
OUT
AE1
AD1
R10
SB_DQ[46]
SB_MA[5]
25
25
25
25
25
25
SB_DQ[45]
SB_MA[4]
SA_DQ[62]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
OUT
OUT
OUT
SB_DQ[3]
SB_MA[3]
SA_MA[0]
M_CLK_DDR2_DP
M_CLK_DDR2_DN
M_CKE2
SB_DQ[2]
SA_DQ[60]
SA_DQ[61]
AE2
AD2
R9
SB_DQ[1]
SA_DQ[59]
SA_MA[12]
M_A_CAS#
M_A_RAS#
M_A_WE#
OUT
OUT
OUT
SA_DQ[47]
SA_MA[11]
OUT
OUT
OUT
M_CLK_DDR1_DP
M_CLK_DDR1_DN
M_CKE1
SA_DQ[46]
SA_MA[10]
24
24
24
AA5
AB5
V10
SA_DQ[45]
SA_MA[5]
OUT
OUT
OUT
24
24
24
SA_DQ[3]
SA_MA[4]
24
24
24
OUT
OUT
OUT
SA_DQ[2]
SA_MA[3]
A
M_CLK_DDR0_DP
M_CLK_DDR0_DN
M_CKE0
SA_DQ[1]
DDR SYSTEM MEMORY A
D
AB6
AA6
V9
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
DDR SYSTEM MEMORY B
6026B0154901_CHIEFRIVER
SB_CAS#
SB_MA[13]
SB_RAS#
SB_MA[14]
SB_WE#
SB_MA[15]
A
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
INVENTEC
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
TITLE
MODEL,PROJECT,FUNCTION
CPU -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
3
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
19
57
of
1
X01
6
2
1
P1V05S_CPU
CN510
6026B0154901_CHIEFRIVER
VCC20
VCC21
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCC22
VCCIO21
VCC23
VCCIO22
VCC24
VCCIO23
VCC25
VCCIO24
1
22uF_6.3V_5
C754
2
1
22uF_6.3V_5
C756
2
1
22uF_6.3V_5
C752
2
1
C706
2
22uF_6.3V_5
1
C758
2
1
1
C760
2
1
C761
2
22uF_6.3V_5
D
22uF_6.3V_5
VCC19
VCCIO15
C757
VCC18
2
VCC17
22uF_6.3V_5
VCCIO14
VCC16
22uF_6.3V_5
VCCIO13
VCC15
1
VCCIO12
VCC14
C759
VCC13
2
VCCIO11
22uF_6.3V_5
VCC12
22uF_6.3V_5
VCCIO10
1
VCCIO9
VCC11
C707
VCCIO8
VCC10
2
VCCIO7
VCC9
1
VCCIO6
VCC8
22uF_6.3V_5
VCCIO5
VCC7
C755
VCCIO4
VCC6
2
VCCIO3
VCC5
1
VCCIO2
VCC4
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
C753
VCC3
VCCIO1
2
POWER
VCC2
22uF_6.3V_5
VTT
VCC1
VCC26
VCC32
VCCIO30
VCC33
VCCIO31
VCC34
VCCIO32
VCC35
VCCIO33
VCC36
VCCIO34
VCC37
VCCIO35
VCC38
VCCIO36
VCC39
VCCIO37
VCC40
VCCIO38
VCC41
VCCIO39
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
VCCIO40
J23
VCC27
VCCIO25
VCC28
VCCIO26
VCC29
VCCIO27
VCCIO28
VCC30
VCCIO29
VCC31
VCCIO
IMAX
= 8.5A
C
VCC42
VCC43
VCC44
VCC45
VCC46
VCC53
P1V05S_CPU
VCC54
VCC55
VCC56
VCC57
2
VCC58
VCC59
VCC60
VCC61
VIDALERT#
VCC62
VIDSCLK
VCC63
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
1
VCC52
R751
R4538
R4539
1
1
1
2 43_5%_2
2 0_5%_2
2 0_5%_2
75_1%_2
VCC51
2
VCC50
R753
VCC49
130_1%_2
VCC48
1
VCC47
VR_SVID_ALERT#
VR_SVID_CLK
VR_SVID_DATA
VCC64
VCC65
PVCORE
VCC66
VCC67
1
VCC69
R734
VCC70
VCC71
VCC72
2
VCC73
VCC74
100_1%_2
VCC68
VCCSENSE
VSSSENSE
1
VCC76
VCC77
R735
VCC78
VCC79
VCC80
2
VCC81
VCC82
100_1%_2
VCC75
OUT
OUT
12
12
VCC83
VCC84
VCC88
VCC89
VCC90
VCC_SENSE
VSS_SENSE
1
AJ35
AJ34
VCC91
VCCIO_SENSE
VCC94
VSS_SENSE_VCCIO
B10
A10
1
VCC93
2
VCC92
10_1%_2
VCC87
A
P1V05S_CPU
VCC95
R692
VCC96
VCC97
VCC98
VCC99
VCC_SENSE_VCCIO
VSS_SENSE_VCCIO
10_1%_2
VCC86
R691
VCC85
OUT
OUT
9
9
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU -
VCC100
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
CHANGE by
8
7
6
B
12
12
12
OUT
OUT
OUT
2
A
3
R755
22uF_6.3V_5
10uF_6.3V_5
10uF_6.3V_5
1
C736
2
1
C727
2
1
C726
2
22uF_6.3V_5
10uF_6.3V_5
10uF_6.3V_5
1
C742
2
1
C724
2
10uF_6.3V_5
10uF_6.3V_5
1
C723
2
1
C729
2
10uF_6.3V_5
10uF_6.3V_5
1
C738
2
1
C748
2
10uF_6.3V_5
1
C725
2
1
C722
2
B
10uF_6.3V_5
2
C730
1
D
4
PEG AND DDR
1
22uF_6.3V_5
C728
2
1
22uF_6.3V_5
C749
2
1
22uF_6.3V_5
C731
2
1
22uF_6.3V_5
C739
2
1
22uF_6.3V_5
C744
2
1
C743
2
22uF_6.3V_5
1
22uF_6.3V_5
C737
2
1
22uF_6.3V_5
C745
2
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
SVID
PVCORE
IMAX = 53A
C
5
SENSE LINES
7
CORE SUPPLY
8
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
4
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
20
57
of
1
X01
4
3
2
SANDY BRIDGE + IVY BRIDGE COMPTIBILITY DG 2.5.17.1
P0V75M_VREF
27
35
14
CORE_PWEN
IN
1
15
VAXG9
VAXG10
SM_VREF
AL1
VAXG16
SA_DIMM_VREFDQ
VAXG17
SB_DIMM_VREFDQ
B4
D1
VAXG13
VAXG15
1
C787
VAXG20
VAXG32
VAXG33
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VAXG34
VDDQ10
VAXG35
VDDQ11
VAXG36
VDDQ12
VAXG37
VDDQ13
VAXG38
VDDQ14
VAXG39
VDDQ15
22uF_6.3V_5
10uF_6.3V_5
C708
2
1
1
21
21
C
P1V5S
5A
10uF_6.3V_5
VAXG31
VDDQ4
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
10uF_6.3V_5
C768
2
1
VAXG30
VDDQ3
10uF_6.3V_5
C766
2
1
VAXG29
VDDQ2
10uF_6.3V_5
C767
2
1
VAXG28
VDDQ1
10uF_6.3V_5
C762
2
1
VAXG27
1
VAXG26
C765
VAXG25
2
VAXG24
10uF_6.3V_5
C763
2
1
VAXG23
DDR3 -1.5V RAILS
VAXG22
2
VAXG21
OUT
OUT
0.1uF_16V_2
VAXG19
B
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
PVSA
VAXG47
VCCSA1
VAXG52
VCCSA2
VAXG53
VCCSA3
VAXG54
VCCSA4
M27
M26
L26
J26
J25
J24
H26
H25
R4567
2
VRPVSA
11
IN
100_5%_2
MISC
VCCPLL2
1.8V RAIL
VCCPLL1
IMAX = 6A
10uF_6.3V_5
VAXG51
SYSTEM AGENT
1
VAXG50
C7051
VAXG49
2
VAXG48
1
1uF_6.3V_2
C709
2
1
1
C710
2
DDR_WR_VREF01
DDR_WR_VREF02
VAXG18
A
1uF_6.3V_2
C808
VAXG14
VCCSA8
1
P0V75M_VREF_H
VAXG12
IMAX = 1.2A
C711
12
12
OUT
OUT
VAXG11
VCCSA7
B6
A6
A2
GFX_VCC_SENSE
GFX_VSS_SENSE
D
VREF
VAXG8
2
2
1
VAXG7
VCCSA6
2
1
2
VAXG6
VCCSA5
P1V8S
AK35
AK34
100_1%_2
VAXG5
VAXG_SENSE
VSSAXG_SENSE
R757
VAXG4
SENSE
LINES
VAXG3
SA RAIL
+ 1
2
330UF_2V_9MR_PANA_-35%
C807
VAXG2
GRAPHICS
1
22uF_6.3V_5
C741
2
1
22uF_6.3V_5
C733
2
1
22uF_6.3V_5
C740
2
22uF_6.3V_5
1
C750
2
1
2
22uF_6.3V_5
C746
1
22uF_6.3V_5
C732
2
1
22uF_6.3V_5
C735
2
1
22uF_6.3V_5
C747
2
B
POWER
VAXG1
100_1%_2
R756
6026B0154901_CHIEFRIVER
CN510
IMAX = 33A
R4566
21
2
17
1
IN
PVAXG
PVAXG
C
R4565
1
PMV56XN
PCH_DDR_RST
D
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
2
G
Q538
PMV56XN
2
3
Q4504
1
27
POWERPAD1X1M_DY
3
10uF_6.3V_5
C721
2
1
21
2
2
C7041
17
IN
1
2
2
R4563
PMV56XN
2
G
1
Q4503
PCH_DDR_RST
1
1
DDR_WR_VREF02
IN
1K_5%_2_DY
21
1 G
1
R4561
2
S
1K_5%_2_DY
3
D
2
S
DDR_WR_VREF01
IN
P0V75M_VREF_H P1V5S
PAD4500
CPUDDR_WR_VREF2_M
2
0_5%_2_DY
0_5%_2_DY
21
R4564
470pF_50V_2_DY
1
CPUDDR_WR_VREF1_M
D
2
D
R4562
1
1
1K_1%_2_DY
5
1K_1%_2_DY
6
10uF_6.3V_5
7
S
8
VCCSA_SENSE
A
H23
VCCSA_SENSE
OUT
11
C22
C24
A19
VCCSA_VID0
VCCSA_VID1
VCCIO_SEL
OUT
OUT
OUT
11
11
9
VCCPLL3
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
INVENTEC
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
TITLE
MODEL,PROJECT,FUNCTION
CPU -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
5
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
21
57
of
1
X01
8
7
CN510
6
TP4522
TP4523
TP4524
TP4525
D
1
1
1
1
1
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
AJ31
AH31
AJ33
AH33
AJ26
CFG[0]
RSVD30
CFG[1]
RSVD31
CFG[2]
RSVD32
CFG[4]
CFG[5]
RSVD33
CFG[6]
RSVD34
CFG[7]
RSVD35
CFG[9]
VCC_DIE_SENSE
CFG[10]
VSS_DIE_SENSE
CFG[12]
CFG[13]
RSVD37
CFG[14]
RSVD38
CFG[15]
RSVD39
CFG[16]
RSVD40
CFG[17]
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
RSVD5
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF9
RSVD_NCTF10
J20
B18
AH27
AH26
CFG[11]
RSVD_NCTF8
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
AT26
AM33
AJ27
CFG[8]
RSVD_NCTF7
C
CN510
L7
AG7
AE7
AK2
W8
CFG[3]
RESERVED
TP4521
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
RSVD8
RSVD9
RSVD10
RSVD11
RSVD51
RSVD12
RSVD52
AJ32
AK32
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
BCLK_ITP
RSVD21
BCLK_ITP#
AN35 XDP_BCLK_ITP_DP TP4518
AM35XDP_BCLK_ITP_DNTP4519
1
1
TP30
TP30
RSVD22
RSVD23
RSVD24
RSVD25
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
AT2
AT1
AR1
B
J15
RSVD27
KEY
B1
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
CFG0
1
R796
2
1K_1%_2
CFG2
2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS234
VSS162
VSS235
VSS163
VSS236
VSS164
VSS237
VSS165
VSS238
VSS166
VSS239
VSS167
VSS240
VSS168
VSS241
VSS169
VSS242
VSS170
VSS243
VSS171
VSS244
VSS172
VSS245
VSS173
VSS246
VSS174
VSS247
VSS175
VSS248
VSS176
VSS249
VSS177
VSS250
VSS178
VSS251
VSS179
VSS252
VSS180
VSS253
VSS181
VSS254
VSS182
VSS255
VSS183
VSS256
VSS184
VSS257
VSS185
VSS258
VSS186
VSS259
VSS187
VSS260
VSS188
VSS261
VSS189
VSS262
VSS190
VSS263
VSS191
VSS264
VSS192
VSS265
VSS
VSS193
VSS194
VSS266
VSS267
VSS195
VSS268
VSS196
VSS269
VSS197
VSS270
VSS198
VSS271
VSS199
VSS272
VSS200
VSS273
VSS201
VSS274
VSS202
VSS275
VSS203
VSS276
VSS204
VSS277
VSS205
VSS278
VSS206
VSS279
VSS207
VSS280
VSS208
VSS281
VSS209
VSS282
VSS210
VSS283
VSS211
VSS284
VSS212
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
R797
1
2
CFG[2] : PCI Express* Static x16 Lane Numbering Reversal.
1 = Normal operation
0 = Lane numbers reversed
R798
1
2
1
6026B0154901_CHIEFRIVER
6026B0154901_CHIEFRIVER
VSS161
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
1K_1%_2_DY
CFG4
3
CN510
RSVD29
1
4
6026B0154901_CHIEFRIVER
RSVD28
TP4520
5
VSS1
VSS81
VSS2
VSS82
VSS3
VSS83
VSS4
VSS84
VSS5
VSS85
VSS6
VSS86
VSS7
VSS87
VSS8
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
VSS88
VSS9
VSS89
VSS10
VSS90
VSS11
VSS91
VSS12
VSS92
VSS13
VSS93
VSS14
VSS94
VSS15
VSS95
VSS16
VSS96
D
VSS17
VSS18
VSS98
VSS19
VSS99
VSS20
VSS100
VSS21
VSS101
VSS22
VSS102
VSS23
VSS103
VSS24
VSS104
VSS25
VSS105
VSS26
VSS106
VSS27
VSS107
VSS28
VSS108
VSS29
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
VSS109
VSS30
VSS110
VSS31
VSS111
VSS32
VSS112
VSS33
VSS113
VSS34
VSS114
VSS
VSS35
VSS36
VSS115
VSS116
VSS37
VSS117
VSS38
VSS118
VSS39
VSS119
VSS40
VSS120
VSS41
VSS121
VSS42
VSS122
VSS43
VSS123
VSS44
VSS124
VSS45
VSS125
VSS46
VSS126
VSS47
VSS127
VSS48
VSS128
VSS49
VSS129
VSS50
VSS130
VSS51
VSS131
VSS52
VSS132
VSS53
VSS133
VSS54
VSS134
VSS55
VSS135
VSS56
VSS136
VSS57
VSS137
VSS58
VSS138
VSS59
VSS139
VSS60
VSS140
VSS61
VSS141
VSS62
VSS142
VSS63
VSS143
VSS64
VSS144
VSS65
VSS145
VSS66
VSS146
VSS67
VSS147
VSS68
VSS148
VSS69
VSS149
VSS70
VSS150
VSS71
VSS151
VSS72
VSS152
VSS73
VSS153
VSS74
VSS154
VSS75
VSS155
VSS76
VSS156
VSS77
VSS157
VSS78
VSS158
VSS79
VSS159
VSS80
VSS160
C
B
1K_1%_2_DY
A
CFG5
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
R794
1
A
2
CFG[4] : eDP enable
1 = Disabled
0 = Enabled
CFG[6:5] : PCI Express Bifurcation:
00 = 1 x8, 2 x4 PCI Expres
01 = reserved
10 = 2 x8 PCI Express
11 = 1 x16 PCI Express
CFG[7] :PEG DEFER TRAINING
1: (Default) PEG Train immediately following RESETB deassertion
0: PEG Wait for BIOS for training
1K_1%_2
CFG6
R795
1
2
1K_1%_2
CFG7
R793
1
2
1K_1%_2_DY
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
6
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
22
57
of
1
X01
8
7
6
5
4
3
2
1
FAN CONN
P5V0S
C602
1
THERMAL SENSOR(LOCAL)
NCT7717U I2C / SMBus address is 1001000xb (x is R/W bit).
3
G
4
G
G1
G2
ACES_50273_0047N_001_4P
6012A0081607
50
35
BI
THM_CLK
1
2
49
35
P3V3S
OUT
THERMTRIP# 3
U510
SCL
SDA
THM_DAT
5
ALERT#
VDD
1
4
NUVO_NCT7717U_SOT23_5P
700UA
2
2
C679
7.5K_1%_2
C
2
1
1
2
1
P3V3S
R115
10K_5%_2_DY
50
P3V3S
2
R1018
R116
22_5%_2
6019B0914301
1
35
BI
GND
CO- LAY U2 (OPEN)
1
2
C4412
1
R631
2
CN500
2
C530
2
D
0.1uF_16V_2
4.7uF_6.3V_3
FAN_TACH1
CPUFAN1_ON#
1
OUT
IN
1
4.7uF_6.3V_3
C574
2
1
1
2
3
4
CSC0402_DY
35
35
4.7K_5%_2
2
R598
1
D
4.7K_5%_2
2
0.1uF_16V_2
P3V3S
C
U2
1
2
3
R114
TRIPSET0
6
5
4
TRIPSET1
GND
VS
OUT#
HYSTSET
10K_5%_2_DY
TI_TMP302BDRLR_SOT_6P_DY
6019B0843501_DY
B
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
THERMAL
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
& FAN
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
23
57
of
1
X01
8
7
6
5
4
DDR3 (8mm) P/N : 6026B0221101
3
2
1
P1V5
P1V5
CKE0
DQ26
CKE1
DQ27
CAS#
DQ28
RAS#
DQ29
WE#
DQ30
SA0
DQ31
SA1
DQ32
SCL
DQ33
SDA
DQ34
DQ35
116
120
ODT0
DQ36
ODT1
DQ37
11
28
46
63
136
153
170
187
DM0
DQ39
DM1
DQ40
DM2
DQ41
DM3
DQ42
DM4
DQ43
DM5
DQ44
DM6
DQ45
DM7
DQ46
DQ38
DQ47
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
B
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
M_A_DQS0_DP 12
M_A_DQS1_DP 29
M_A_DQS2_DP 47
M_A_DQS3_DP 64
M_A_DQS4_DP137
M_A_DQS5_DP154
M_A_DQS6_DP171
M_A_DQS7_DP188
M_A_DQS0_DN 10
M_A_DQS1_DN 27
M_A_DQS2_DN 45
M_A_DQS3_DN 62
M_A_DQS4_DN135
M_A_DQS5_DN152
M_A_DQS6_DN169
M_A_DQS7_DN186
DQS0
DQS1
DQ48
DQ49
DQS2
DQ50
DQS3
DQ51
DQS4
DQ52
DQS5
DQ53
DQS6
DQ54
DQS7
DQ55
DQS#0
DQ56
DQS#1
DQ57
DQS#2
DQ58
DQS#3
DQ59
DQS#4
DQ60
DQS#5
DQ61
DQS#6
DQ62
DQS#7
DQ63
1
22uF_6.3V_5
C775
2
1
22uF_6.3V_5
C774
2
2
C776
1
22uF_6.3V_5
1uF_6.3V_2
1
C770
2
1
C772
2
VSS20
VDD6
VSS21
VDD7
VSS22
VDD8
VSS23
VDD9
VSS24
VDD10
VSS25
VDD11
VSS26
VDD12
VSS27
VDD13
VSS28
VSS29
VDD14
VDD15
VSS30
VDD16
VSS31
VDD17
VSS32
VDD18
VSS33
199
VDDSPD
77
122
125
NC1
VSS37
NC2
VSS38
NCTEST
VSS39
198
30
EVENT#
VSS41
RESET#
VSS42
VSS35
VSS36
VSS40
25
17
DIMM_DRAMRST#
IN
VSS43
VSS44
1
126
VREF_DQ
VSS45
VREF_CA
VSS46
VSS47
VSS48
P0V75S_DIMM0_VREF_DQ
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
P0V75S_DIMM0_VREF_CA
0.5A
0.5A
VSS1
VSS49
VSS2
VSS50
VSS3
VSS51
VSS4
VSS52
D
C
VSS5
VSS6
P0V75S
VSS7
VSS8
VSS9
VSS10
VTT1
VSS11
VTT2
1A
203
204
VSS12
VSS13
G1
VSS14
G2
G1
G2
VSS15
FOX_AS0A626_J8R6_7H_204P
B
P1V5
1uF_6.3V_2
DQ25
VDD5
1
DQ24
CK1#
VSS19
VDD4
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
1uF_6.3V_2
C832
2
1
CK1
VSS18
C831
DQ23
VSS17
VDD3
2
CK0#
VSS16
VDD2
1uF_6.3V_2
DQ22
1
CK0
VDD1
VSS34
C833
DQ21
2
DQ20
S1#
CN511
1uF_6.3V_2
C830
2
1
S0#
0.1uF_16V_2
DQ19
1
DQ18
BA2
C773
BA1
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
P3V3S
2
DQ17
1
BA0
2.2uF_16V_3
DQ16
C788
DQ15
2
A15
1uF_6.3V_2
C771
2
1
DQ14
0.1uF_16V_2
DQ13
A14
0.1uF_16V_2
DQ12
A13
0.1uF_16V_2
C769
2
1
DQ11
A12
0.1uF_16V_2
A11
1
DQ10
C810
DQ9
A10_AP
2
DQ8
A9
1
A8
C665
DQ7
2
A7
1
DQ6
1
DQ5
A6
+
DQ4
A5
100uF_6.3V_DY
A4
2
M_ODT0
M_ODT1
DQ3
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
2.2uF_16V_3
IN
IN
A3
M_A_DQ<0>
M_A_DQ<1>
M_A_DQ<2>
M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<23>
M_A_DQ<22>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<39>
M_A_DQ<38>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<37>
M_A_DQ<36>
M_A_DQ<43>
M_A_DQ<42>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<41>
M_A_DQ<40>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<55>
M_A_DQ<54>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<61>
M_A_DQ<60>
M_A_DQ<62>
M_A_DQ<63>
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
1
19
19
DQ2
2.2uF_16V_3
M_A_BS0
109
M_A_BS1
108
M_A_BS2
79
M_CS#0
114
M_CS#1
121
M_CLK_DDR0_DP
101
M_CLK_DDR0_DN
103
M_CLK_DDR1_DP
102
M_CLK_DDR1_DN
104
M_CKE0
73
M_CKE1
74
M_A_CAS#
115
M_A_RAS#
110
M_A_WE#
113
SA0_DIM0
197
SA1_DIM0
201
PCH_3S_SMCLK
202
PCH_3S_SMDAT
200
DQ1
A2
C4109
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ0
A1
C664
27
27
19
19
19
19
19
19
19
19
19
19
19
19
19
19
24
24
25
25
A0
2
C
M_A_A<0> 98
M_A_A<1> 97
M_A_A<2> 96
M_A_A<3> 95
M_A_A<4> 92
M_A_A<5> 91
M_A_A<6> 90
M_A_A<7> 86
M_A_A<8> 89
M_A_A<9> 85
M_A_A<10>
107
M_A_A<11>84
M_A_A<12>83
M_A_A<13>
119
M_A_A<14>80
M_A_A<15>78
C712
D
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
2
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
4.32A
CN511
P1V5
FOX_AS0A626_J8R6_7H_204P
P0V75S_DIMM0_VREF_CA
P0V75M_VREF
2
1K_1%_2
1
R759
1K_1%_2
P0V75M_VREF
2
R4104
1
P0V75S_DIMM0_VREF_DQ
R662
1
2
2
A
1K_1%_2
R663
R760
1
0_5%_2_DY
CPUDDR_WR_VREF1_M
1
R761
2
24
1K_1%_2
R660
24
2
1
IN
IN
10K_5%_2
R838
2
2
R839
1
SA1_DIM0
1
0_5%_2_DY
SA0_DIM0
10K_5%_2
Note :
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
A
1
2
0_5%_2
INVENTEC
SANDY BRIDGE + IVY BRIDGE DG4.14
TITLE
MODEL,PROJECT,FUNCTION
DDR3 -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
1
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
24
57
of
1
X01
8
7
6
5
4
3
2
1
DDR3 (4mm) P/N : 6026B0221601
P1V5
CN512
DQ26
CKE1
DQ27
CAS#
DQ28
RAS#
DQ29
WE#
DQ30
SA0
DQ31
SA1
DQ32
SCL
DQ33
SDA
DQ34
DQ35
116
120
ODT0
DQ36
ODT1
DQ37
11
28
46
63
136
153
170
187
DM0
DQ39
DM1
DQ40
DM2
DQ41
DM3
DQ42
DM4
DQ43
DM5
DQ44
DM6
DQ45
DM7
DQ46
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQ48
DQS1
DQ49
DQ38
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
B
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ47
M_B_DQS0_DP
M_B_DQS1_DP
M_B_DQS2_DP
M_B_DQS3_DP
M_B_DQS4_DP
M_B_DQS5_DP
M_B_DQS6_DP
M_B_DQS7_DP
M_B_DQS0_DN
M_B_DQS1_DN
M_B_DQS2_DN
M_B_DQS3_DN
M_B_DQS4_DN
M_B_DQS5_DN
M_B_DQS6_DN
M_B_DQS7_DN
DQS2
DQ50
DQS3
DQ51
DQS4
DQ52
DQS5
DQ53
DQS6
DQ54
DQS7
DQ55
DQS#0
DQ56
DQS#1
DQ57
DQS#2
DQ58
DQS#3
DQ59
DQS#4
DQ60
DQS#5
DQ61
DQS#6
DQ62
DQS#7
DQ63
1
22uF_6.3V_5
C782
2
1
22uF_6.3V_5
C780
2
1
C781
2
EVENT#
VSS41
RESET#
VSS42
VSS24
VDD10
VSS25
VDD11
VSS26
VDD12
VSS27
VDD13
VSS28
VSS29
VDD14
VDD15
VSS30
VDD16
VSS31
VDD17
VSS32
VDD18
VSS33
VSS35
VSS40
24
17
DIMM_DRAMRST#
IN
VSS43
1
126
VREF_DQ
VSS45
VREF_CA
VSS46
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
VSS1
VSS48
P0V75S_DIMM1_VREF_DQ
P0V75S_DIMM1_VREF_CA
0.5A
0.5A
VSS49
VSS2
VSS50
VSS3
VSS51
VSS4
VSS52
D
C
VSS5
VSS6
P0V75S
VSS7
VSS8
VSS9
VSS10
VTT1
VSS11
VTT2
1A
203
204
VSS12
VSS13
G1
VSS14
G2
G1
G2
VSS15
FOX_AS0A626_U4RG_7H_204P
P1V5
1
1K_1%_2
R642
2
P0V75M_VREF
P0V75S_DIMM1_VREF_CA
P0V75M_VREF
1
2
25
1
2
1K_1%_2
IN
R738
SA0_DIM1
CPUDDR_WR_VREF2_M
R666
1
2
A
2
25
R739
0_5%_2_DY
2
IN
1K_1%_2
1
0_5%_2_DY
SA1_DIM1
B
P1V5
P0V75S_DIMM1_VREF_DQ
1
R643
1
VSS39
198
30
VSS23
VDD9
VSS47
10K_5%_2
R809
2
0_5%_2
10K_5%_2
1
R808
VSS38
NCTEST
VSS22
VDD8
VSS36
R665
2
VSS37
NC2
VDD7
VSS44
P3V3S
Note :
SO-DIMMA SPD Address is 0xA4
SO-DIMMA TS Address is 0x34
NC1
VSS21
VSS34
FOX_AS0A626_U4RG_7H_204P
A
77
122
125
VSS20
VDD6
1uF_6.3V_2
CKE0
VDDSPD
VDD5
1uF_6.3V_2
C837
2
1
DQ25
199
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
VSS19
VDD4
1uF_6.3V_2
C834
2
1
CK1#
VSS18
1
DQ24
VSS17
VDD3
1uF_6.3V_2
C835
2
1
CK1
VSS16
VDD2
C836
DQ23
VDD1
2
CK0#
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
0.1uF_16V_2
DQ22
1
CK0
22uF_6.3V_5
M_ODT2
M_ODT3
DQ21
2
C
DQ20
S1#
P3V3S
C789
27
27
S0#
1uF_6.3V_2
IN
IN
DQ16
1
19
19
DQ15
2.2uF_16V_3
DQ19
DQ14
A15
C777
BA2
A14
2
DQ18
DQ13
1
BA1
DQ12
A13
C778
DQ17
A12
2
BA0
DQ11
1uF_6.3V_2
C779
2
1
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
A11
1K_1%_2
M_B_BS0
M_B_BS1
M_B_BS2
M_CS#2
M_CS#3
M_CLK_DDR2_DP
M_CLK_DDR2_DN
M_CLK_DDR3_DP
M_CLK_DDR3_DN
M_CKE2
M_CKE3
M_B_CAS#
M_B_RAS#
M_B_WE#
SA0_DIM1
SA1_DIM1
PCH_3S_SMCLK
PCH_3S_SMDAT
DQ10
0.1uF_16V_2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ9
A10_AP
1
19
19
19
19
19
19
19
19
19
19
19
19
19
19
25
25
24
24
A9
R740
DQ8
CN512
2
A8
1
DQ7
2
DQ6
A7
0.1uF_16V_2
DQ5
A6
1
A5
C784
DQ4
2
A4
0.1uF_16V_2
C783
2
1
DQ3
1
DQ2
A3
0.1uF_16V_2
DQ1
A2
4.32A
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
C668
A1
M_B_DQ<0>
M_B_DQ<1>
M_B_DQ<7>
M_B_DQ<3>
M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<2>
M_B_DQ<8>
M_B_DQ<9>
M_B_DQ<10>
M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>
M_B_DQ<14>
M_B_DQ<15>
M_B_DQ<16>
M_B_DQ<17>
M_B_DQ<18>
M_B_DQ<19>
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
M_B_DQ<24>
M_B_DQ<25>
M_B_DQ<26>
M_B_DQ<27>
M_B_DQ<28>
M_B_DQ<29>
M_B_DQ<31>
M_B_DQ<30>
M_B_DQ<36>
M_B_DQ<37>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<32>
M_B_DQ<33>
M_B_DQ<39>
M_B_DQ<38>
M_B_DQ<41>
M_B_DQ<45>
M_B_DQ<46>
M_B_DQ<42>
M_B_DQ<44>
M_B_DQ<40>
M_B_DQ<43>
M_B_DQ<47>
M_B_DQ<48>
M_B_DQ<53>
M_B_DQ<54>
M_B_DQ<55>
M_B_DQ<49>
M_B_DQ<52>
M_B_DQ<51>
M_B_DQ<50>
M_B_DQ<58>
M_B_DQ<61>
M_B_DQ<62>
M_B_DQ<63>
M_B_DQ<57>
M_B_DQ<56>
M_B_DQ<59>
M_B_DQ<60>
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
C811
DQ0
2
A0
1
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
2.2uF_16V_3
M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>
C667
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
2
D
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
SANDY BRIDGE + IVY BRIDGE DG4.14
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
DDR3 -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
2
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
25
57
of
1
X01
8
7
6
5
4
3
2
1
C874
1
2
4
3
R906
1
2
RTC_32K_IN
2
HDA_SYNC_Q
A20
RTCX1
XTAL32RTC_OUT C20
RTCX2
S
D
1M_5%_2
1
R4705
44
AMC_AZ2015_01H_SOD523_2P_DY
R898
P3V3S
1
35
35
35
35
46
46
46
46
FWH4/LFRAME#
D36
LPC_FRAME#
OUT
35
46
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
LDRQ1#/GPIO23
PCH_INTVRMEN
C17
INTVRMEN
SERIRQ
2 HDA_BITCLK_PCH
N34
HDA_BCLK
LPC
P3V3_RTC_RTCRST#
HDA_SYNC_PCH
PCSPKR
44
OUT
44
OUT
HDA_RST#
IN
HDA_SDIN0
44
2
1
R975
2
L34
HDA_SYNC
T10
SPKR
HDA_RST#_PCH K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
P5V0S
C34
HDA_SDIN2
A34
HDA_SDIN3
SATA0TXN
SATA0TXP
G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXP
SATA2TXN
SATA2TXP
D510
SATA3TXP
A36
SATA
R952 2
HDA_SDO_PCH
1
33_5%_2
R953
GPIO33
1
2
1K_5%_2_DY
GPIO13
1
2
P3V3A
10K_5%_2
R976
HDA_SDO_R
1
2
SATA3TXN
HDA_SDO
C36
HDA_DOCK_EN#/GPIO33
N32
HDA_DOCK_RST#/GPIO13
SATA4RXP
SATA4TXN
SATA4TXP
EMI
SATA5TXP
SATAICOMPO
Y11
SATAICOMPI
Y10
SATA5TXN
1
2
51_5%_2
PCH_TCK
J3
JTAG_TCK
OUT
PCH_TMS
H7
JTAG_TMS
26
OUT
PCH_TDI
K5
JTAG_TDI
26
OUT
PCH_TDO
H1
JTAG_TDO
26
IN
IN
OUT
OUT
40
40
40
40
SATA_ODD_RX_DN
SATA_ODD_RX_DP
SATA_ODD_TX_DN
SATA_ODD_TX_DP
IN
IN
OUT
OUT
40
40
40
40
1
U520
26
26
PCH_SPI_CS0#
PCH_SPI_SO
IN
OUT
1
2
3
4
CE#
VDD
SO
HOLD#
WP#
SCK
VSS
SI
P1V05S_PCH
2
AMC_AZ2015_01H_SOD523_2P_DY
SATAICOMPO
1
AB13
SATA3RBIAS
AH1
R934
6011B0082901_DY
2
37.4_1%_2
AB12 SATA3RCOMPO 1
SATA3COMPI
26
OUT
PCH_SPI_CLK
T3
SPI_CLK
R935
R934,R935
WITHIN 500 MILS
OF THE PCH
2
OUT
PCH_SPI_CS0#
Y14
T1
SPI_CS1#
SPI_CS0#
P3
LED_SATA#
OUT
PCH_SPI_SI
V4
SPI_MOSI
SATA0GP/GPIO21
V14
2nd_WLAN_RF_OFF#
26
IN
PCH_SPI_SO
U3
SPI_MISO
SATA1GP/GPIO19
P1
26
MXIC_MX25L3206EM2I-12G P/N : 6019B0794701
26
WINBOND_W25Q32BVSSIG P/N : 6019B0704901
BI
PCH_SPI_CLK
1
R947
2
HSPI_CLK
BI
35
2
HSPI_CS0#
BI
35
2
HSPI_SI
BI
35
2
HSPI_SO
BI
35
0_5%_2
BI
PCH_SPI_CS1#
BI
PCH_SPI_SI
1
BI
PCH_SPI_SO
1
1
R946
0_5%_2
R948
26
26
26
IN
IN
IN
PCH_TMS
PCH_TDI
PCH_TDO
R881 1
2
10K_5%_2
R989
0_5%_2
1
R851
2
210_1%_2
R927
2
OUT
36
OUT
46
IN
30
1
210_1%_2
R863
2
7
6
5
4
3
6011B0082901_DY
210_1%_2
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH -
100_1%_2
XXX
2
AMC_AZ2015_01H_SOD523_2P_DY
A
100_1%_2
R853 1
2
CHANGE by
EMI
1 R933
2
10K_5%_2
R864 1
2
100_1%_2
R928 1
2
0_5%_2
26
1
BBSTRAP0
1
D507
2
P3V3A
26
26
26
R890
OUT
ITL_PANTHERPOINT_FCBGA_989P
IN
IN
1
26
SATALED#
8
R879
7
0_5%_2
6 PCH_SPI_CLK_ROM 1
2
PCH_SPI_CLK
5
PCH_SPI_SI
SATA3RBIAS
PCH_SPI_CS1#
26
BIOS ROM 4MB ( BIOS & EC ROM VENDOR MUST SAME )
8
B
49.9_1%_2
750_1%_2
ACES_91960_0084L_8P
6026B0150101
A
EMI
1
SPI
C923
0.1UF_16V_2
2
R945
3.3K_5%_2
2
1
P3V3A
2
C
P3V3S
26
R991
EMI
D506
Y3
Y1
AB3
AB1
SATA5RXN
SATA5RXP
R857
SATA_HDD_RX_DN
SATA_HDD_RX_DP
SATA_HDD_TX_DN
SATA_HDD_TX_DP
P3V3A
1
1
10K_5%_2
35
BI
Y7
Y5
AD3
AD1
SATA4RXN
SATA3RCOMPO
3.3K_5%_2
P3V3S
AB8
AB10
AF3
AF1
SATA3RXP
JTAG
3
D
AMC_AZ2015_01H_SOD523_2P_DY
B
S
6011B0082901_DY
HDA_SDO_PCH :
High : Enable
Low : Disable
22pF_50V_2
Flash Descriptor Security Overide
HDA_SDO_PCH
2
AD7
AD5
AH5
AH4
SATA2RXN
SSM3K7002FU
1
C928
35
IN
2
1K_5%_2
1 R14086 2
ME_FLASH_EN
HDA_SDO
R876
2
D
AM10
AM8
AP11
AP10
SATA1RXN
SATA3RXN
Q553
OUT
AM3
AM1
AP7
AP5
SATA0RXP
1
1K_5%_2_DY
44
E36
K36
1
TP30
TP4700
SERIRQ
V5
LDRQ0#
SATA0RXN
R1086
33_5%_2
33_5%_2
R873
BI
BI
BI
BI
P3V3_RTC_SRTCRST#
2
HDA_BITCLK 1
OUT
6011B0082901_DY
2
C
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
FWH2/LAD2
D505
EMI
3
FWH3/LAD3
C38
A38
B37
C37
FWH0/LAD0
FWH1/LAD1
1
U519
XTAL32RTC_IN
330K_5%_2
2
SSM3K7002FU
16
6011B0082901_DY
2
33_5%_2
IN
0_5%_2
2
1
1
AMC_AZ2015_01H_SOD523_2P_DY
2
2
1
2
IHDA
HDA_SYNC
BI
2
G
44
1K_5%_2
R4706
1
1
Q565
R4704
1
32.768KHZ_DY
6018A0001401_DY
C875
18PF_50V_2_DY
P3V3A
1
For DB build
HM75 QPEG Q0
BD82PPSM
P/N : 6019B0919101
X501
2
10M_5%_2_DY
P5V0S
D509
1
18PF_50V_2_DY
SATA 6G
6026B0219701
R958
RTC
1
2
1
1
LOTES_AAA_BAT_063_P02_A_2P
1
D508
2
330_5%_2
POWERPAD2X2M_DY
PAD402
1
1uF_6.3V_2
C860
2
1
6011B0082901_DY
16
C878
OUT
AMC_AZ2015_01H_SOD523_2P_DY
A2
A1
VBAT
2
2
20K_5%_2
1uF_6.3V_2
R4400
2
R969
1M_5%_2
1
R964
1
1uF_6.3V_2
1
1
EMI
C859
+
P3V3_RTC
2
2
-
3
IF USE U9
D4400 OPEN
1
CN4400
2
BAT54C_30V_0.2A
D4400
D
2
2
20K_5%_2
P3V3_RTC
C
P3V3AL_RTC_BAT
R910
1
P3V3AL
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
1
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
26
57
of
1
X01
8
7
6
5
4
3
2
1
P3V3A
2
2
C940
1
DGPU_PRSNT#
2
BF36
BE36
AY34
BB34
0.1uF_16V_2
R14067
10K_5%_2_DY
41
41
41
41
P3V3A
1
R4742
CLKREQ_LAN#
2
27
IN
C917
PCIE_LAN_RX_C_DN
PCIE_LAN_RX_C_DP
PCIE_LAN_TX_C_DN
PCIE_LAN_TX_C_DP
IN
IN
OUT
OUT
0.1uF_16V_2
1
1
C916
41
2
2
1
R4880
PCH_DDR_RST
2
17
IN
1K_5%_2
21
PETN4
PETP4
PCIE_LAN_TX_DP
BB36
PETP5
BJ38
BG38
AU36
AV36
BE38
BC38
AW38
AY38
C
P3V3A
GPIO73
2
PERP4
PETN5
BG40
BJ40
AY40
BB40
R856
PERN4
PERN5
27
1
SML0DATA
G12
TP_SMBUS_DAT
BI
47
1 R1048
2
1
2
0_5%_2
R1050
46
27
IN
CLK_PCIE_WLAN_R_DN
CLK_PCIE_WLAN_R_DP
PERP5
C13
GPIO74
SML1CLK/GPIO58
E14
PCH_THM_SMCLK
BI
35
SML1DATA/GPIO75
M16
PCH_THM_SMDAT
BI
35
CL_CLK1
M7
CL_DATA1
T11
CL_RST1#
P10
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
P3V3A
J2
PCIECLKRQ0#/GPIO73
PEG_A_CLKRQ#/GPIO47
M10
CLKOUT_PEG_A_N
AB37
AB38
B
41
41
CLK_PCIE_LAN_DN
CLK_PCIE_LAN_DP
OUT
OUT
27
IN
CLKOUT_PEG_A_P
CLKOUT_PCIE1N
CLKOUT_DMI_N
CLKOUT_PCIE1P
CLKOUT_DMI_P
41
P3V3A
P3V3S
27
IN
CLK_PCIE_CR_R_DP
CLKREQ_CR#
V10
PCIECLKRQ2#/GPIO20
CLK_PCIE_LAN_R_DN
Y37
Y36
CLKOUT_PCIE3N
CLKREQ_GPU#
CLK_PEG_DN
CLK_PEG_DP
OUT
OUT
48
48
AV22 CLK_DMI_PCH_DN
AU22 CLK_DMI_PCH_DP
OUT
OUT
17
17
R4755
2
1
210K_5%_2
GPIO44
BJ30 CLKIN_BUF_CPYCLK_DN R984 1
BG30 CLKIN_BUF_CPYCLK_DP R1004 1
2 10K_5%_2
2 10K_5%_2
BI
PCH_3A_SMCLK
BI
PCH_3S_SMDAT
2
G24
E24
R973 1
R972 1
2 10K_5%_2
2 10K_5%_2
R937 1
R936 1
2 10K_5%_2
2 10K_5%_2
1
2 10K_5%_2
CLKIN_DMI_PCH_DP
B
PCIECLKRQ3#/GPIO25
Y43
Y45
CLKOUT_PCIE4N
L12
PCIECLKRQ4#/GPIO26
CLKIN_SATA_P
AK7
AK5
V45
V46
CLKOUT_PCIE5N
REFCLK14IN
K45
CLKIN_PCILOOPBACK
H45
L14
AB42
AB40
1
R858
1
Q547
210K_5%_2
GPIO56
23
24
2 10K_5%_2
2 10K_5%_2
CLKIN_BUF_DOT96_DN
CLKIN_BUF_DOT96_DP
CLKOUT_PCIE4P
CLKIN_SATA_DN
CLKIN_SATA_DP
E6
XTAL25PCH_OUT
PCIECLKRQ5#/GPIO44
CLKOUT_PEG_B_N
XTAL25_IN
CLKOUT_PEG_B_P
XTAL25_OUT
V47
V49
S
1
CLKIN_PCI_FB
R912
2
PCH_25M_IN
0_5%_2
XTAL25PCH_IN
XTAL25PCH_OUT
R932
1
210K_5%_2
GPIO45
IN
IN
30
XTAL25PCH_IN
V40
V42
CLKOUT_PCIE6N
Y47
T13
PCIECLKRQ6#/GPIO45
V38
V37
CLKOUT_PCIE7N
PCH_XCLK_RCOMP
1
1
2
90.9_1%_2
CLKOUT_PCIE6P
G
PCH_3A_SMDAT
Q548
3
BI
R921
1
210K_5%_2
GPIO46 K12
AK14
AK13
FLEX CLOCKS
D
27
CLKOUT_PCIE7P
PCIECLKRQ7#/GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUTFLEX0/GPIO64
K43
CLKOUTFLEX1/GPIO65
F47
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
EDID_SELECT#
IN
27
DGPU_PRSNT#
OUT
27
H47
K49
2
1M_5%_2_DY
P1V05S_PCH
R1043
R1041
1
16
PEG_B_CLKRQ#/GPIO56
XCLK_RCOMP
SSM3K7002FU
R1036
CLKIN_BUF_REF14
CLKOUT_PCIE5P
SSM3K7002FU
G
25
CLKIN_GND1_P
R980 1
R981 1
CLKIN_DMI_PCH_DN
1
D
A
CLKIN_GND1_N
CLKIN_SATA_N
GPIO26
S
27
CLKIN_DMI_P
CLKIN_DOT_96P
2
3
10K_5%_2
2
2
PCH_3S_SMCLK
1 R908
1 R909
2
2.2K_5%_2
1 R915
2
2.2K_5%_2
1 R916
BI
2.2K_5%_2
2.2K_5%_2
24
CLKOUT_PCIE3P
BF18
BE18
CLKIN_DMI_N
CLKIN_DOT_96N
R911
25
CLKOUT_PCIE2P
P3V3S P3V3A
1
C
Q554
SSM3K7002FU
AM12
AM13
CLKOUT_DP_P
CLKREQ_LAN# A8
55
PCIECLKRQ1#/GPIO18
CLKOUT_PCIE2N
CLK_PCIE_LAN_R_DP
52
CLKOUT_PCIE0P
0_5%_2
1 R1049
2
1
2
0_5%_2
R1047
30
IN
1
PETP8
CLOCKS
43
DGPU_PWR_EN
R996
10K_5%_2
PETN8
AA48
AA47
CLK_PCIE_CR_R_DN
1
PCH_THM_SMDAT
PETP6
0_5%_2
1 R1044
2
1
2
0_5%_2
R1046
CLK_PCIE_CR_DN
CLK_PCIE_CR_DP
OUT
OUT
P3V3A
PCH_THM_SMCLK
PETN6
CLKOUT_DP_N
43
43
D
PERP6
CLKOUT_PCIE0N
CLKREQ_WLAN# M1
TP_SMBUS_DAT
P3V3A
PERN6
Y40
Y39
AB49
AB47
TP_SMBUS_CLK
10K_5%_2
1
2
SML1ALERT#/PCHHOT#/GPIO74
0_5%_2
CLK_PCIE_WLAN_DN
CLK_PCIE_WLAN_DP
OUT
OUT
27
TP SMB(I2C) ADDRESS IS 0X2CR917
10K_5%_2
46
46
21
2.2K_5%_2
47
2 R922
17
BI
2 R854
OUT
TP_SMBUS_CLK
2.2K_5%_2
1
PETP3
BG37
BH37
0.1uF_16V_2
PCH_DDR_RST
C8
PETN3
PCIE_LAN_TX_DN
AY36
10K_5%_2
A12
SML0CLK
3
4
2
X503
27PF_50V_2_DY
IN
27
1
1
PERP3
R977 2
27
SML0ALERT#/GPIO60
PERN3
1
IN
27
2.2K_5%_2
DGPU_PRSNT#
2
27
BI
1
R1030
10K_5%_2
BG36
BJ36
PCIE_CR_TX_DNAV34
PCIE_CR_TX_DPAU34
BI
PCH_3A_SMDAT
C965
1
0.1uF_16V_2
PETP2
PCH_3A_SMCLK
C9
25MHZ_DY
6018B0044501_DY
2
D
C939
PCIE_CR_RX_C_DN
PCIE_CR_RX_C_DP
PCIE_CR_TX_C_DN
PCIE_CR_TX_C_DP
IN
IN
OUT
OUT
PETN2
H14
1
43
43
43
43
PERP2
SMBCLK
SMBDATA
1
27
IN
PERN2
2
EDID_SELECT#
2
PETP1
27PF_50V_2_DY
R4739
10K_5%_2
PETN1
C962
1
P3V3A
R965 2
43
10K_5%_2_DY
2
2.2K_5%_2
BE34
BF34
BB32
AY32
GPIO11
G
2
2
0.1uF_16V_2
E12
2
27
IN
1
1
C914
SMBALERT#/GPIO11
1
CLKREQ_CR#
2
46
PERP1
SMBUS
R887
1
27
IN
R918
10K_5%_2
1
PERN1
Controller
Link
CLKREQ_WLAN#
2
10K_5%_2
U519
BG34
BJ34
PCIE_WLAN_TX_DN
AV32
PCIE_WLAN_TX_DP
AU32
PCI-E*
R878
1
IN
IN
OUT
OUT
0.1uF_16V_2
D
P3V3S
C915
PCIE_WLAN_RX_C_DN
PCIE_WLAN_RX_C_DP
PCIE_WLAN_TX_C_DN
PCIE_WLAN_TX_C_DP
S
46
46
46
46
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
ITL_PANTHERPOINT_FCBGA_989P
PCH -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
2
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
27
57
of
1
X01
A
8
7
6
5
4
3
2
1
U519
DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN
BC24
BE20
BG18
BG20
18
18
18
18
IN
IN
IN
IN
DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP
BE24
BC20
BJ18
BJ20
18
18
18
18
OUT
OUT
OUT
OUT
DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN
AW24
AW20
BB18
AV18
OUT
OUT
OUT
OUT
DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP
AY24
AY20
AY18
AU18
DMI0RXN
FDI_RXN0
DMI1RXN
FDI_RXN1
DMI2RXN
FDI_RXN2
DMI3RXN
FDI_RXN3
FDI_RXN4
DMI0RXP
FDI_RXN5
DMI1RXP
FDI_RXN6
DMI2RXP
FDI_RXN7
R983
WITHIN 500 MILS
OF THE PCH
2
1
IN
IN
IN
IN
IN
IN
IN
IN
18
18
18
18
18
18
18
18
FDI_RXP6
DMI1TXP
FDI_RXP7
FDI
DMI3TXN
DMI
DMI2TXN
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
D
DMI2TXP
DMI3TXP
FDI_INT
AW16
FDI_INT
OUT
18
DMI_ZCOMP
FDI_FSYNC0
AV12
FDI_FSYNC0
OUT
18
BG25
DMI_IRCOMP
FDI_FSYNC1
BC10
FDI_FSYNC1
OUT
18
BH21
DMI2RBIAS
PCH_DMI2RBIAS
2
FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP
DMI0TXP
DMI1TXN
PCH_DMI_ZCOMP BJ24
49.9_1%_2
R982
18
18
18
18
18
18
18
18
FDI_LSYNC0
AV14
FDI_LSYNC0
OUT
18
FDI_LSYNC1
BB10
FDI_LSYNC1
OUT
18
DSWVRMEN
A18
PCH_DSWVRMEN
DPWROK
E22
WAKE#
2
750_1%_2
P3V3_RTC
1
R983
1
IN
IN
IN
IN
IN
IN
IN
IN
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
DMI0TXN
FDI_RXP5
P1V05S_PCH
FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN
DMI3RXP
FDI_RXP0
18
18
18
18
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
P3V3S
SUS_PWR_DN_ACK
IN
1 R907
2 PCH_SUSACK# C12
0_5%_2_DY
1
14 12
35
IN
PVCORE_PG
IN
SB_PWRGD
1
R868
2 PCH_SYSRESET#K3
10K_5%_2
R930
SUSACK#
R4782
2
P12
SYS_PWROK
2
L22
PWROK
2
L10
APWROK
0_5%_2
1
R926
0_5%_2
17
35
28
OUT
PM_DRAM_PWRGD
B13
DRAMPWROK
IN
RSMRST#
C21
RSMRST#
OUT
SUS_PWR_DN_ACK
K16
SUSWARN#/SUSPWRDNACK/GPIO30
IN
SB_PWRBTN#
B
35
28
P3V3A
35
C877
B9
PCIE_WAKE#
CLKRUN#/GPIO32
N3
R867
SUS_STAT#/GPIO61
G8
PCI_CLKRUN#
IN
28
35
IN
28
41
P3V3S
TP4702
TP30
N14
SLP_S5#/GPIO63
D10
R861
1
2 0_5%_2_DY
SLP_S4#
H4
R862
1
2 0_5%_2
SLP_S4#
OUT
35
SLP_S3#
F4
R860
1
2 0_5%_2
SLP_S3#
OUT
35
SLP_A#
G10
H_PM_SYNC
OUT
17
1
C
1
2
8.2K_5%_2
SUSCLK/GPIO62
B
E20
PWRBTN#
1
10K_5%_2
GPIO31
H20
ACPRESENT/GPIO31
SLP_SUS#
G16
R913 1
2
10K_5%_2
GPIO72
E10
BATLOW#/GPIO72
PMSYNCH
AP14
R849 1
2
10K_5%_2
PM_RI#
A10
1 0.1uF_16V_2_DY
R966
2
2
RSMRST#
2
0_5%_2
SYS_RESET#
0_5%_2
1
R971
1
2
28
System Power Management
35
R957
1
C
330K_5%_2_DY 330K_5%_2
IN
IN
IN
IN
R956
D
18
18
18
18
RI#
SLP_LAN#/GPIO29
K14
GPIO29
1
R4795
P3V3A
2
10K_5%_2
ITL_PANTHERPOINT_FCBGA_989P
P3V3A
R959
35
28
IN
SUS_PWR_DN_ACK
1
41
28
IN
PCIE_WAKE#
1
2
10K_5%_2
A
A
2
R850
1K_5%_2
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
3
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
28
57
of
1
X01
8
7
6
5
4
3
2
1
U519
38
38
OUT
OUT
PCH_LCD_BKEN
PCH_LCDVDD_EN
J47
M45
L_BKLTEN
SDVO_TVCLKINN
L_VDD_EN
SDVO_TVCLKINP
38
OUT
PCH_LCD_PWM
P45
L_BKLTCTL
SDVO_STALLN
BI
BI
PCH_LCD_CLK
PCH_LCD_DAT
T40
K47
L_DDC_CLK
SDVO_STALLP
SDVO_INTN
L_DDC_DATA
SDVO_INTP
AE48
AE47
LVD_VREFH
AK39
AK40
OUT
OUT
OUT
PCH_LCD_TXA0_DN
PCH_LCD_TXA1_DN
PCH_LCD_TXA2_DN
AN48
AM47
AK47
AJ48
LVDSA_CLK#
DDPB_AUXP
DDPB_HPD
LVDSA_CLK
DDPB_0N
LVDSA_DATA#0
DDPB_1N
DDPB_0P
C
38
38
38
OUT
OUT
OUT
PCH_LCD_TXA0_DP
PCH_LCD_TXA1_DP
PCH_LCD_TXA2_DP
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
LVDSA_DATA#1
DDPB_1P
LVDSA_DATA#2
DDPB_2N
Digital Display Interface
38
38
38
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
LVDSB_DATA2
DDPC_2P
LVDSB_DATA3
DDPC_3N
DDPC_3P
B
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
OUT
OUT
OUT
R1035
1
2 150_1%_2
R1037
1
2 150_1%_2
R1039
1
N48
P49
T49
37
37
2 150_1%_2
37
37
OUT
OUT
PCH_CRT_HSYNC
PCH_CRT_VSYNC
OUT
OUT
1
1
PCH_CRT_CLK
PCH_CRT_DAT
0_5%_2
R4804
2 PCH_CRT_HSYNC_PCH
2 PCH_CRT_VSYNC_PCH
R4805
0_5%_2
T39
M40
CRT_BLUE
CRT_GREEN
CRT_RED
DDPD_CTRLCLK
CRT
37
37
37
DDPD_CTRLDATA
DDPD_AUXN
CRT_DDC_CLK
DDPD_AUXP
CRT_DDC_DATA
DDPD_HPD
DDPD_0N
M47
M49
CRT_HSYNC
DDPD_0P
CRT_VSYNC
DDPD_1N
DDPD_1P
DDPD_2N
PCH_DAC_IREF
T43
T42
DAC_IREF
DDPD_2P
CRT_IRTN
DDPD_3N
R1002
MINIMUM SPACING
OF 30 MILS
A
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
29
OUT PCH_HDMI_HPD
2
S
P46
P42
HDMI_HPD
3
D
IN
39
C
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
PCH_HDMI_CLK
PCH_HDMI_DAT
BI
BI
AT45
AT43
BH41
PCH_HDMI_HPD
IN
29
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
PCH_HDMI_TX2_DN
OUT
PCH_HDMI_TX2_DP
OUT
PCH_HDMI_TX1_DN
OUT
PCH_HDMI_TX1_DP
OUT
PCH_HDMI_TX0_DN
OUT
PCH_HDMI_TX0_DP
OUT
PCH_HDMI_TXCL_DN
OUT
PCH_HDMI_TXCL_DP
39
39
39
39
39
39
39
39
OUT
39
39
B
ITL_PANTHERPOINT_FCBGA_989P
2
CLOSE TO PCH
R1002 1
1K_1%_2
DDPD_3P
AT49
AT47
AT40
G
PCH_LCD_TXACL_DN
PCH_LCD_TXACL_DP
DDPB_AUXN
P3V3S
Q543
OUT
OUT
LVD_VREFL
P38
M39
2
SDVO_CTRLDATA
R831
SDVO_CTRLCLK
LVD_VBG
SSM3K7002FU
38
38
LVD_IBG
20K_5%_2
2.37K_1%_2
L_CTRL_DATA
AF37
AF36
1
PCH_LVD_IBG
1
1
1
R979
LVDS
2
AP39
AP40
L_CTRL_CLK
R834
T45
P39
D
AM42
AM40
1M_5%_2
38
38
AP43
AP45
2
R1045 1
2
2.2K_5%_2
R1001 1
2
D
2.2K_5%_2
P3V3S
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
4
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
29
57
of
1
X01
8
30
7
5
4
3
2
30
30
GPIO55 : TOP-BLOCK SWAP OVERRIDE
LOW=A16 SWAP OVERRIDE
HIGH=DEFAULT
30
RSVD2
1
2
1K_5%_2_DY
1 R1029
2
1K_5%_2_DY
BBSTRAP1
IN
RSVD1
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
D
30
DGPU_PWM_SELECT# 1
R999
2
1K_5%_2_DY
IN
BBSTRAP1
0
0
1
1
BBSTRAP0
0
1
0
1
BOOT BIOS
LPC
Reserved (NAND)
-SPI
TP1
RSVD3
TP2
RSVD4
R1027
1
2
DGPU_HOLD_RST#
IN
10K_5%_2
R1025
1
2
10K_5%_2
C
R1020
1
2
10K_5%_2
R14066
1
2
10K_5%_2
DGPU_SELECT#
IN
DGPU_PWR_EN#
30
B21
M20
AY16
BG46
48
30
47
IN
30
USB30_SMI#
IN
30
ACCEL_INT#
IN
30
55
47
R14065
R14064
RSVD5
TP5
RSVD6
USB3_P1_TX_DP
OUT
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
2
55
D
3
OUT
30
IN
52
55
OUT
OUT
OUT
DGPU_HOLD_RST#
DGPU_SELECT#
DGPU_PWR_EN#
C46
C44
E40
30
30
30
IN
OUT
IN
BBSTRAP1
DGPU_PWM_SELECT#
GPIO55
D47
E42
F46
Q555
P3V3A
R923
48
43
41
30
OUT
PLT_RST#
30
IN
30
IN
USB30_SMI#
GPIO3
GPIO4
ACCEL_INT#
1
2
10K_5%_2_DY
PCH_PME#
A
35
27
P3V3A
CLK_LPC_EC
CLKIN_PCI_FB
OUT
OUT
1
1
R1033
C1005
0.1uF_16V_2
1
46
2
CLK_LPC_DEBUG
OUT
1
R997
22_5%_2
CLK_LPC_EC_R
2
CLKIN_PCI_FB_R
2
22_5%_2
2
CLK_LPC_DEBUG_R
5
22_5%_2
210K_5%_2_DY
1
210K_5%_2_DY
R902
1
210K_5%_2_DY
210K_5%_2_DY
210K_5%_2_DY
OUT
OUT
OUT
OUT
OUT
OUT
BOARD_ID3
R967
1
BOARD_ID4
R899
1
BOARD_ID5
R914
1
2 10K_5%_2
BOARD_ID0
R961
1
2 10K_5%_2
BOARD_ID1
R903
1
2 10K_5%_2
BOARD_ID2
R904
BOARD_ID3
1
0
0
0
0
USB3RN1
RSVD26
USB3RN2
RSVD27
AY5
BA2
SG-SEYMOUR
1
0
0
0
0
1
SG-THAMES
1
0
0
0
1
0
RSVD12
TP13
RSVD13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
TP21
30
38
30
30
30
30
30
30
38
1
2 10K_5%_2
R968
1
2 10K_5%_2
BOARD_ID4
R900
1
2 10K_5%_2
BOARD_ID5
R920
1
210K_5%_2_DY
D
BOARD_ID5 ONLY FOR WEBCAN USE
FOR HD WEB CAM BOARD_ID5 PULL P3V3A
FOR VGA WEB CAM BOARD_ID5 PULL GND
TP22
TP23
TP24
ID5 ID4 ID3 ID2 ID1 ID0
USB3RN3
USB3RN4
RSVD28
USB3RP1
RSVD29
AT12
BF3
0
C
USB3RP2
USB3RP3
USB3RP4
USBP13P
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS#
C33
USBRBIAS
B33
USBP0N
USB3TN1
USBP0P
USB3TN2
USBP1N
USB3TN3
USBP1P
USB3TN4
USBP2N
USB3TP1
USBP2P
USB3TP2
USBP3N
USB3TP3
USBP3P
USB3TP4
USBP4N
PIRQA#
USBP7N
PIRQB#
USBP7P
PIRQC#
USBP8N
PIRQD#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
GNT1#/GPIO51
USBP11P
GNT2#/GPIO53
USBP12N
USBP12P
GNT3#/GPIO55
USB_P0_DN
USB_P0_DP
USB_P1_DN
USB_P1_DP
BI
BI
BI
BI
47
47
47
47
USB_P5_DN
USB_P5_DP
BI
BI
38
38
USB_P8_DN
USB_P8_DP
USB_P9_DN
USB_P9_DP
BI
BI
BI
BI
46
46
47
47
PIRQF#/GPIO3
PIRQG#/GPIO4
C6
PLTRST#
OC0#/GPIO59
OC2#/GPIO41
CLKOUT_PCI0
OC3#/GPIO42
CLKOUT_PCI1
OC4#/GPIO43
CLKOUT_PCI2
OC5#/GPIO9
CLKOUT_PCI3
OC6#/GPIO10
CLKOUT_PCI4
OC7#/GPIO14
USB2.0 DB (DeBug Port)
WEBCAM
B
WLAN COMBO
USB2.0 DB (DeBug Port)
CLOSE TO PCH
PIRQH#/GPIO5
PME#
USB3.0
R951
WITHIN 500 MILS
OF THE PCH
PIRQE#/GPIO2
K10
H49
H43
J48
K42
H40
1
R905
BOARD_ID2
UMA-INTEL
TP12
OC1#/GPIO40
R1026
R960
BOARD_ID1
AT8
RSVD11
USBP11N
G42
G40
C42
D44
BOARD_ID0
AV10
RSVD10
TP11
USBP13N
SSM3K7002FU
2
S
55
G
27
30
30
30
30
OUT
OUT
OUT
OUT
OUT
OUT
RSVD25
TP10
USB
48
8.2K_5%_2
8.2K_5%_2
8.2K_5%_2
8.2K_5%_2
K40
K38
H38
G38
10K_5%_2
2
RSVD24
RSVD9
PCI
R1022
1
10K_5%_2
R403
R401
R402
R400
DGPU_PWR_EN
DGPU_PWR_EN#
1
2ND_WWAN_GPS_OFF# 1
AV5
TP9
USBP6P
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
2 10K_5%_2
RSVD23
RSVD8
USBP5P
2
2
2
2
R848
RSVD22
RSVD7
TP8
USBP6N
B
1
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
TP7
USBP5N
1
1
1
1
AT10
BC8
30
P3V3S
P3V3S
30
TP6
USBP4P
GPIO4
1
2
10K_5%_2
USB3_P1_TX_DN
OUT
47
GPIO3
1
2
10K_5%_2
USB3_P1_RX_DP
IN
47
R14063
1
2
10K_5%_2
USB3_P1_RX_DN
IN
30
30
TP4
RSVD21
P3V3S
AY7
AV7
AU3
BG4
TP3
NVRAM
IN
GPIO59
R901
RSVD
26
OUT
OUT
U519
R875
BBSTRAP0
1
P3V3A
1 R1031
2
1K_5%_2_DY
GPIO55
IN
6
PCH_USBBIAS
1 R951
2
22.6_1%_2
GPIO59
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
2ND_WWAN_GPS_OFF#
A14
K20
B17
C16
L16
A16
D14
C14
IN
IN
IN
IN
IN
IN
IN
IN
30
30
30
30
30
30
38
30
30
A
ITL_PANTHERPOINT_FCBGA_989P
+
U527
1
4
PLT_RST#
IN
30
41
43
INVENTEC
48
-
2
3
1
OUT BUF_PLT_RST#
R1064
17
2
35
100K_5%_2
46
TC7SZ08FU
TITLE
MODEL,PROJECT,FUNCTION
PCH -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
5
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
30
57
of
1
X01
6
5
4
3
2
1
P3V3S
P3V3A
31
WLAN_RF_OFF#
OUT
BTOFF
OUT
D
2 10K_5%_2
R924
1
R1088
1
35
10K_5%_2
2
GPIO24
1
R1081
2 10K_5%_2
GPIO15
1
R1082
2 10K_5%_2
T7
BMBUSY#/GPIO0
TACH4/GPIO68
C40
GPIO68
1
R994
2
IN
EC_SMI#
A42
TACH1/GPIO1
TACH5/GPIO69
B41
GPIO69
1
R992
2
31
IN
DGPU_HPD_INTR# H36
TACH2/GPIO6
TACH6/GPIO70
C41
TACH3/GPIO7
TACH7/GPIO71
A40
GPIO71
R993
1
2
10K_5%_2
EC_SCI#
E38
GPIO8
C10
BTOFF
C4
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
G2
GPIO15
GPIO16
U2
SATA4GP/GPIO16
IN
R847
1
1K_5%_2_DY
P3V3S
31
OUT
31
OUT
DGPU_HPD_INTR#
OUT
10K_5%_2
1
R974
2
10K_5%_2
10K_5%_2
2
40
C
35
31
31
OUT
ODD_PRSNT#
1
R886
2 200K_5%_2
2
GPIO37
1
R866
OUT
HDD_LOCK_LED
1
R1080 2
31
OUT
TEMP_ALERT#
1
R882
2
10K_5%_2
OUT
KB_RST#
1
R870
2
10K_5%_2
31
P3V3A
52
35
31
R872
1
P3V3S
10K_5%_2_DY
R963
2
R877
31
14
31
OUT
DGPU_PWROK
OUT
GPIO37
1
TACH0/GPIO17
GPIO22
T5
GPIO24
E8
GPIO24
GPIO27
E16
GPIO27
1 GPIO28
P8
GPIO28
1
SCLOCK/GPIO22
1K_5%_2_DY
2
R869
10K_5%_2
2
1 GPIO34
K1
STP_PCI#/GPIO34
1 GPIO35
K4
GPIO35
A20GATE
PECI
AU16
PCH_PECI
RCIN#
P5
KB_RST#
AY11
H_CPUPWRGD
THRMTRIP#
AY10
PM_THRMTRIP#_PCH
INIT3_3V#
T14
31
2
2
31
ODD_PRSNT#V8
IN
IN
1
R874 10K_5%_2
2
1
R871 10K_5%_2
100K_5%_2_DY
1 R865
2
100K_5%_2
46
31
OUT
31
OUT
31
OUT
B
PROCPWRGD
DF_TVS
AY1
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
TS_VSS4
AK10
1
IN
35
IN
31
OUT
17
TP312
1
R14080 2
35
PM_THRMTRIP#
IN
17
390_5%_2
NV_CLE
OUT
17
C
R925 10K_5%_2_DY
P3V3S
52
35
D40
DGPU_PWROK
IN
10K_5%_2_DY
40
R995
14
10K_5%_2
2
1K_5%_2_DY
OUT
31
1
CPU/MISC
31
2
SATA2GP/GPIO36
GPIO37
M5
SATA3GP/GPIO37
GPIO38
N2
SLOAD/GPIO38
GPIO39
M3
SDATAOUT0/GPIO39
NC_1
P37
V13
HDD_LOCK_LED
SDATAOUT1/GPIO48
VSS_NCTF_15
BG2
TEMP_ALERT#V3
SATA5GP/GPIO49/TEMP_ALERT#
VSS_NCTF_16
BG48
D6
WLAN_RF_OFF#
GPIO57
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
A4
VSS_NCTF_1
VSS_NCTF_19
BJ4
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
A46
VSS_NCTF_4
VSS_NCTF_22
BJ46
A5
VSS_NCTF_5
VSS_NCTF_23
BJ5
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
NCTF
35
R880
D
P1V05S_CPU
P4
A20GATE
GPIO
R883
2
1
10K_5%_2
GPIO8
P3V3S
PCI_SERR#
10K_5%_2
PCI_SERR#
35
2
U519
IN
35
31
1
31
R14081
46
2
7
56_5%_2_DY
8
B
ITL_PANTHERPOINT_FCBGA_989P
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
6
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
31
57
of
1
X01
8
7
6
5
4
3
2
1
P1V05S_PCH
P3V3S
1.61A
AP37
2
VCC3_3[7]
V34
1
2
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
VCCDMI[1]
AT20
R941
2
VCCDFTERM[1]
AG16
VCCDFTERM[2]
AG17
VCCDFTERM[3]
AJ16
VCCDFTERM[4]
AJ17
47mA
AU20 SOURCE IS
P1V05S_CPU
B
1
C960
2
22uF_6.3V_5
1
C961
10mA
V1
1
VCCDMI[2]
C849
ITL_PANTHERPOINT_FCBGA_989P
2
AU20
P1V05S_PCH
AT20 SOURCE IS
P1V05S_CPU
P3V3A
VCCSPI
A
2mA
1
0_5%_2_DY
2
P1V8S
FDI
1
0.1uF_16V_2
AB36
1
VCCCLKDMI
147mA
P1V05S_PCH
P1V05S_PCH
2
P1V05S_PCH
147mA
75mA
NAND / SPI
0.1uF_16V_2
C911
2
P1V5S_VCCAFDI_VRM
P1V05S_PCH
47mA
1
VCCIO[21]
AP24
AT16
C
2
VCCIO[20]
AP23
VCCVRM[3]
200mA_0603
P1V5S_VCCAFDI_VRM
2
AP21
DMI
VCCIO[19]
1
B
VCCIO[18]
AN27
C903
178MA
AN26
VCCIO
1
1uF_6.3V_2
C866
2
1
C887
2
1uF_6.3V_2
1uF_6.3V_2
1
C905
2
1uF_6.3V_2
1
C907
2
1uF_6.3V_2
1
C937
2
1
C4722
2
P3V3S
VCCIO[17]
C933
VCCIO[16]
178mA
C888
AN17
3.8A
V33
0.1uF_16V_2
VCCIO[15]
VCC3_3[6]
0.1uF_16V_2
AN16
AN21
1
P3V3S
HVCMOS
P1V05S_PCH
10UF_6.3V_3
1
C851
2
10uF_6.3V_5_DY
2
0603_DY
2
FBM_11_160808_121T
C935
AP36
VCCTX_LVDS[4]
L526
1
1
VCCTX_LVDS[3]
40mA
P1V8S_PCH_VCCTX_LVDS
L520
1
C959
AM38
1uF_6.3V_2
VCCAPLLEXP
VCCTX_LVDS[2]
P1V8S
C1000
VCCCORE[17]
BJ22
AM37
2
VCCCORE[16]
VCCIO[28]
VCCTX_LVDS[1]
22uF_6.3V_5
VCCCORE[15]
AN19
AK37
D
250mA_0603
1uF_6.3V_2_DY
VCCCORE[14]
3.8A
P1V05S_PCH
VSSALVDS
1
VCCCORE[13]
C949
VCCCORE[12]
1mA
2
VCCCORE[11]
AK36
0.01uF_50V_2
VCCCORE[10]
VCCALVDS
2
VCCCORE[9]
P3V3S
0.01uF_50V_2
VCCCORE[8]
U47
1
VCCCORE[7]
VSSADAC
L528
1
2
MLZ1608M100WT
P3V3S_PCH_VCCADAC
C945
VCCCORE[6]
LVDS
VCCCORE[5]
U48
0.01uF_50V_2
VCCCORE[3]
VCCCORE[4]
VCCADAC
POWER
P1V5S_VCCAFDI_VRM
P1V5S
1uF_6.3V_2
VCCCORE[2]
CRT
VCCCORE[1]
VCC CORE
1
1uF_6.3V_2
C889
2
1
1uF_6.3V_2
C892
2
1
1uF_6.3V_2
C897
2
1
10UF_6.3V_3
C904
2
1
+
220uF_2V_DY
C4783
2
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
P1V05S_PCH
C
63mA
U519
D
A
PAD4700
1
1
2
2
INVENTEC
POWERPAD1X1M
TITLE
MODEL,PROJECT,FUNCTION
PCH -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
7
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
32
57
of
1
X01
8
7
6
5
4
3
2
1
P3V3A
P1V05S_PCH
0.1uF_16V_2_DY
1
C861
75mA
L531
1
2
MLZ1608M100WT
2
0.1uF_16V_2
1
C974
2
1
C973
2.2uF_6.3V_3
2
B
2
C938
1
250mA_0603
22uF_6.3V_5
P1V05S_PCH_VCCADPLLB
0.1uF_16V_2
0.1uF_16V_2
1
C968
2
2
C967
C966
2
2.2uF_6.3V_3
250mA_0603
1
P1V05S_PCH_VCCADPLLA
1
1 L530
2
MLZ1608M100WT
22uF_6.3V_5
75mA
147mA
VCCASW[1]
AA21
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
2
C891
2
1
1uF_6.3V_2
C896
2
1
1uF_6.3V_2
95mA
2
1
0.1uF_16V_2
2
1
C883
1
C858
2
0.1uF_16V_2
1
2
6
0.1uF_16V_2
C857
2
C870
1
7
1uF_6.3V_2
0.1uF_16V_2
1
C918
2
0.1uF_16V_2
1
C919
2
1
C912
4.7uF_6.3V_3
2
8
1mA
V24
VCCSUS3_3[6]
P24
VCCIO[34]
T26
V5REF_SUS
M26
DCPSUS[4]
AN23
VCCSUS3_3[1]
AN24
1
2
P5V0A_PCH_V5REF_SUSU
1
V5REF
2
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
2
DCPRTC
Y49
VCCVRM[4]
BD47
VCCADPLLA
P3V3S
1uF_6.3V_2
P5V0S
1mA
2
C
10_5%_2
178mA
C894
2
1
0.1uF_16V_2
0.1uF_16V_2
1
2
0.1uF_16V_2
C863
1
N16
1
65mA
T34
VCCASW[20]
1
R1042
C880
1
VCC3_3[4]
VCCASW[19]
3
P3V3A
VCCASW[16]
W33
65mA
1uF_6.3V_2_DY
P5V0S_PCH_V5REF
P34
W24
W31
D532
BAT54_30V_0.2A
W16
VCCASW[18]
P3V3S
P3V3A
C908
AA16
W29
65mA
D
P1V05S_PCH
VCC3_3[8]
VCCASW[17]
1
2
0.1uF_16V_2
VCC3_3[1]
W26
P3V3A
C881
VCCASW[14]
P3V3S
2
178mA
VCC3_3[2]
AJ2
VCCIO[5]
AF13
VCCIO[12]
AH13
VCCIO[13]
AH14
VCCIO[6]
AF14
VCCAPLLSATA
AK1
B
P1V05S_PCH
3.8A
AF17
AF33
AF34
AG34
2
1uF_6.3V_2
P1V05S_PCH
L519
1
P1V5S_VCCAFDI_VRM
2
0603_DY
VCCVRM[1]
AF11
VCCIO[2]
AC16
VCCIO[3]
AC17
VCCIO[4]
AD17
147mA
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
P1V05S_PCH
VCCDIFFCLKN[3]
VCCSSC
V16
DCPSST
T17
V19
DCPSUS[1]
BJ8
V_PROC_IO
A22
1
VCCADPLLB
VCCRTC
C890
3.8A
1
2
A
1uF_6.3V_2
DCPSUS[2]
2
1uF_6.3V_2_DY
2mA
P3V3_RTC
VCCSUS3_3[10]
VCCASW[15]
0_5%_2_DY
R978
1
P1V05S_PCH
BJ8 SOURCE IS
P1V05S_CPU
V23
W23
AG33
C893
2
0.1uF_16V_2
VCCSUS3_3[9]
1uF_6.3V_2
1
50mA
P1V05S_PCH
1
C884
W21
BF47
A
T24
1mA
2
10_5%_2
C864
P1V05S_PCH
P1V05S_PCH
VCCSUS3_3[8]
65mA
C865
P1V5S_VCCAFDI_VRM
C900
T23
R970
2
AA19
SATA
1
C898
2
1uF_6.3V_2
1uF_6.3V_2
1
C899
2
1uF_6.3V_2
1
C895
2
1
10UF_6.3V_3
C909
2
1
22uF_6.3V_5
C910
2
C
VCCSUS3_3[7]
P5V0A
BAT54_30V_0.2A
P3V3A
NC
P1V05S_PCH
P1V05S_PCH
T29
1
0.1uF_16V_2
DCPSUS[3]
1uF_6.3V_2_DY
803mA
VCCIO[33]
3
C879
VCCIO[14]
AL24
T27
2
1
VCCAPLLDMI2
AL29
USB
C906
BH23
MISC
2
P28
VCCIO[32]
1
PCI/GPIO/LPC
2
VCCIO[31]
P3V3A
D530
VCC3_3[5]
HDA
1
0_5%_2_DY
P26
NC
DCPSUSBYP
N26
VCCIO[30]
1uF_6.3V_2
VCCDSW3_3
V12
VCCIO[29]
1
1
T16
Clock and Miscellaneous
D
POWER
C964
2
C862
T38
R4874
VCCACLK
2
AD49
1
2
0_5%_2_DY
1uF_6.3V_2
1
3.8A
U519
RTC CPU
P1V05S_PCH
R1051
C885
0.1uF_16V_2
1
C882
2
1
10uF_6.3V_5
C931
2
1
C963
2
0.1uF_16V_2
P1V05S_PCH
1mA
178mA
2
P3V3S
VCCASW[22]
T21
VCCASW[23]
V21
VCCASW[21]
T19
VCCSUSHDA
P1V05S_PCH
803mA
INVENTEC
P3V3A
10mA
P32
TITLE
MODEL,PROJECT,FUNCTION
C886
ITL_PANTHERPOINT_FCBGA_989P
1
PCH -
2
0.1uF_16V_2
CHANGE by
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
8
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
33
57
of
1
X01
8
7
6
5
4
3
2
1
U519
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
D
C
B
A
VSS[159]
VSS[259]
VSS[160]
VSS[260]
VSS[161]
VSS[261]
VSS[162]
VSS[262]
VSS[163]
VSS[263]
VSS[164]
VSS[264]
VSS[165]
VSS[265]
VSS[166]
VSS[266]
VSS[167]
VSS[267]
VSS[168]
VSS[268]
VSS[169]
VSS[269]
VSS[170]
VSS[270]
VSS[171]
VSS[271]
VSS[172]
VSS[272]
VSS[173]
VSS[273]
VSS[174]
VSS[274]
VSS[175]
VSS[275]
VSS[176]
VSS[276]
VSS[177]
VSS[277]
VSS[178]
VSS[278]
VSS[179]
VSS[279]
VSS[180]
VSS[280]
VSS[181]
VSS[281]
VSS[182]
VSS[282]
VSS[183]
VSS[283]
VSS[184]
VSS[284]
VSS[185]
VSS[285]
VSS[186]
VSS[286]
VSS[187]
VSS[287]
VSS[188]
VSS[288]
VSS[189]
VSS[289]
VSS[190]
VSS[290]
VSS[191]
VSS[291]
VSS[192]
VSS[292]
VSS[193]
VSS[293]
VSS[194]
VSS[294]
VSS[195]
VSS[295]
VSS[196]
VSS[296]
VSS[197]
VSS[297]
VSS[198]
VSS[298]
VSS[199]
VSS[299]
VSS[200]
VSS[300]
VSS[201]
VSS[301]
VSS[202]
VSS[302]
VSS[203]
VSS[303]
VSS[204]
VSS[304]
VSS[205]
VSS[305]
VSS[206]
VSS[306]
VSS[207]
VSS[307]
VSS[208]
VSS[308]
VSS[209]
VSS[309]
VSS[210]
VSS[310]
VSS[211]
VSS[311]
VSS[212]
VSS[312]
VSS[213]
VSS[313]
VSS[214]
VSS[314]
VSS[215]
VSS[315]
VSS[216]
VSS[316]
VSS[217]
VSS[317]
VSS[218]
VSS[318]
VSS[219]
VSS[319]
VSS[220]
VSS[320]
VSS[221]
VSS[321]
VSS[222]
VSS[322]
VSS[223]
VSS[323]
VSS[224]
VSS[324]
VSS[225]
VSS[325]
VSS[226]
VSS[328]
VSS[227]
VSS[329]
VSS[228]
VSS[330]
VSS[229]
VSS[331]
VSS[230]
VSS[333]
VSS[231]
VSS[334]
VSS[232]
VSS[335]
VSS[233]
VSS[337]
VSS[234]
VSS[338]
VSS[235]
VSS[340]
VSS[236]
VSS[342]
VSS[237]
VSS[343]
VSS[238]
VSS[344]
VSS[239]
VSS[345]
VSS[240]
VSS[346]
VSS[241]
VSS[347]
VSS[242]
VSS[348]
VSS[243]
VSS[349]
VSS[244]
VSS[350]
VSS[245]
VSS[351]
VSS[246]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
U519
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[80]
VSS[2]
VSS[81]
VSS[3]
VSS[82]
VSS[4]
VSS[83]
VSS[5]
VSS[84]
VSS[6]
VSS[85]
VSS[7]
VSS[86]
VSS[8]
VSS[87]
VSS[9]
VSS[88]
VSS[10]
VSS[89]
VSS[11]
VSS[90]
VSS[12]
VSS[91]
VSS[13]
VSS[92]
VSS[14]
VSS[93]
VSS[15]
VSS[94]
VSS[16]
VSS[95]
VSS[17]
VSS[96]
VSS[18]
VSS[97]
VSS[19]
VSS[98]
VSS[20]
VSS[99]
VSS[21]
VSS[100]
VSS[22]
VSS[101]
VSS[23]
VSS[102]
VSS[24]
VSS[103]
VSS[25]
VSS[104]
VSS[26]
VSS[105]
VSS[27]
VSS[106]
VSS[28]
VSS[107]
VSS[29]
VSS[108]
VSS[30]
VSS[109]
VSS[31]
VSS[110]
VSS[32]
VSS[111]
VSS[33]
VSS[112]
VSS[34]
VSS[113]
VSS[35]
VSS[114]
VSS[36]
VSS[115]
VSS[37]
VSS[116]
VSS[38]
VSS[117]
VSS[39]
VSS[118]
VSS[40]
VSS[119]
VSS[41]
VSS[120]
VSS[42]
VSS[121]
VSS[43]
VSS[122]
VSS[44]
VSS[123]
VSS[45]
VSS[124]
VSS[46]
VSS[125]
VSS[47]
VSS[126]
VSS[48]
VSS[127]
VSS[49]
VSS[128]
VSS[50]
VSS[129]
VSS[51]
VSS[130]
VSS[52]
VSS[131]
VSS[53]
VSS[132]
VSS[54]
VSS[133]
VSS[55]
VSS[134]
VSS[56]
VSS[135]
VSS[57]
VSS[136]
VSS[58]
VSS[137]
VSS[59]
VSS[138]
VSS[60]
VSS[139]
VSS[61]
VSS[140]
VSS[62]
VSS[141]
VSS[63]
VSS[142]
VSS[64]
VSS[143]
VSS[65]
VSS[144]
VSS[66]
VSS[145]
VSS[67]
VSS[146]
VSS[68]
VSS[147]
VSS[69]
VSS[148]
VSS[70]
VSS[149]
VSS[71]
VSS[150]
VSS[72]
VSS[151]
VSS[73]
VSS[152]
VSS[74]
VSS[153]
VSS[75]
VSS[154]
VSS[76]
VSS[155]
VSS[77]
VSS[156]
VSS[78]
VSS[157]
VSS[79]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
D
C
B
A
ITL_PANTHERPOINT_FCBGA_989P
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
INVENTEC
VSS[255]
VSS[256]
VSS[257]
VSS[258]
TITLE
MODEL,PROJECT,FUNCTION
ITL_PANTHERPOINT_FCBGA_989P
PCH -
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
9
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
34
57
of
1
X01
8
7
6
5
4
3
2
1
P3V3AL
P3V3AL_EC_VSTBY
1
BI
BI
35
35
35
35
OUT
OUT
OUT
IN
S
2
31
TP303
EC ROM 1MB
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
( BIOS & EC ROM VENDOR MUST SAME )
MXIC_MX25L8006EM2I-12G PN:6019B0795601
WINBOND_W25Q80BVSSIG PN:6019B0719601
P3V3AL
C798
P3V3AL
2
1
99
98
97
96
93
19
20
127
3
74
DSR0#_GPG6_X
TACH0A_GPD6_3_DN
GINT_CTS0#_GPD5_UP
TACH1A_TMA1_GPD7_3_DN
DAC5_RIG0#_GPJ5_3_X
PS2CLK1_DTR0#_GPF2_UP
TMRI0_WUI2_GPC4_3_DN
UART port
TMRI1_WUI3_GPC6_3_DN
R773
3.3K_5%_2
CE#
VDD
SO
HOLD#
WP#
SCK
VSS
SI
8
7
6
5
EC_SPI_CLK
EC_SPI_SI
ACES_91960_0084L_8P
6026B0150101
IN
IN
35
35
36
36
36
36
36
36
36
36
7
6
1
C
TP310
IN
IN
23
15
OUT
OUT
14
15
17
P3V3AL
125
18
21
EC_PWRBTN#
QWEB#
SLP_S4#
RING#_PWRFAIL#_CK32KOUT_LPCRST#_GPB7_DN
112
CORE_PWEN
WAKE UP
RTS1#_WUI5_GPE5_DN
IN
47
IN
28
OUT
14
1
TP309
PWM7_RIG1#_GPA7_UP
DTR1#_SBUSY_GPG1_ID7_DN
15
21
35
CTX1_WUI18_SOUT1_GPH2_SMDAT3_ID2_DN
35
CRX1_WUI17_SIN1_SMCLK3_GPH1_ID1_DN
ITE_ITE8517E_G_LQFP_128P
105
101
102
103
KSO16
KSO17
CORE_PWEN_D#
56
57
32
OUT1
PCI_SERR#
100
106
SSCE0#_GPG2_X
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SCAN_OUT<0>
SCAN_OUT<1>
SCAN_OUT<2>
SCAN_OUT<3>
SCAN_OUT<4>
SCAN_OUT<5>
SCAN_OUT<6>
SCAN_OUT<7>
SCAN_OUT<8>
SCAN_OUT<9>
SCAN_OUT<10>
SCAN_OUT<11>
SCAN_OUT<12>
SCAN_OUT<13>
SCAN_OUT<14>
SCAN_OUT<15>
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
KSO0_PD0
GPJ1_3_X
KSO1_PD1
DAC2_TACH0B_GPJ2_3_X
KSO2_PD2
DAC3_TACH1B_GPJ3_3_X
IN
IN
IN
IN
IN
IN
IN
IN
SCAN_IN<0>
SCAN_IN<1>
SCAN_IN<2>
SCAN_IN<3>
SCAN_IN<4>
SCAN_IN<5>
SCAN_IN<6>
SCAN_IN<7>
FSCK
FSCE#
FMOSI
ADC0_GPI0_3_X
ADC1_GPI1_3_X
KSO16_SMOSI_GPC3_3_DN
ADC2_GPI2_3_X
KSO17_SMISO_GPC5_3_DN
ADC3_GPI3_3_X
PWM6_SSCK_GPA6_UP
SSCE1#_GPG0_X
ADC4_WUI28_GPI4_3_X
A/D
SPI ENABLE
66 MB_ID0
67 MB_ID1
1
68
69
70 ADP_ID
IN
IN
35
35
IN
5
TP307
THERMTRIP#
C795
76
77
78
79
AMP_EN
WWAN_IND#
BT_IND
WLAN_IND#
OUT
44
IN
46
KSO3_PD3
KSO4_PD4
KSO6_PD6
MB_ID1
1
1
23
IN
2
D/A
TACH2_GPJ0_3_X
KSO5_PD5
MB_ID0
OUT
OUT
EXTERNAL SERIAL FLASH
FMISO
10K_5%_2_DY
RI2#_WUI1_GPD1_UP
B
49
1
0.1uF_16V_2
TP302
TP304
P3V3S
R708
10K_5%_2
KBMX
1
1
KSO7_PD7
2
2
R324
KSO8_ACK#
10K_5%_2
KSO9_BUSY
KSO10_PE
KSO11_ERR#
KSO12_SLCT
KSO13
KSO14
KSO15
CLOCK
CK32KE_GPJ7_3_X
CK32K_GPJ6_3_X
5
4
2
1 12
A
2
128
DB
SI
PV
MV
MB_ID0
0
1
0
1
MB_ID1
0
0
1
1
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
ITE8517
CHANGE by
8
TP305
1
PWRSW_GPE4_3_UP
RI1#_WUI0_GPD0_3_UP
ADC7_CTS1#_WUI31_GPI7_3_X
2
3.3K_5%_2
120 ALWAYS_PW_EN
124 CPU_PWEN
ADC6_DSR1#_WUI30_GPI6_3_X
0.1uF_16V_2
4
U511
47 FAN_TACH1
48 ALL_PWGD_IN
ADC5_DCD1#_WUI29_GPI5_3_X
C816
EC_SPI_CS0# 1
IN
2
OUT EC_SPI_SO
1
2
3
1
RXD_SIN0_GPB0_UP
2
35
35
R777
47
12 17
35
23
TXD_SOUT0_GPB1_UP
0.1uF_16V_2
1
36
OUT
OUT
OUT
PS2DAT1_RTS0#_GPF3_UP
58
59
60
61
62
63
64
65
A
OUT
PWM
DAC4_DCD0#_GPJ4_3_X
EC_SPI_CLK
EC_SPI_CS0#
EC_SPI_SI
EC_SPI_SO
1
1
1
10K_5%_2_DY
10K_5%_2
27
TP300
TP301
TP311
SSM3K7002FU
2
SSM3K7002FU
TP308
G
S
1
27
10K_5%_2_DY
2
R828
BATT_IN#
71
I_ADP
72
AC_OK
73
ADP_PRES
35
RF_WHITE_LED#
34
ADP_EN
107
PCH_THM_SMDAT 95
PCH_THM_SMCLK 94
2
R775
R824
IN
IN
IN
IN
OUT
1
R823
1
1
6
5
5
5
36
80
104
33
88
81
87
109
108
1
P3V3A
2
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
DGPU_PWROK
GPU_THROT#
SLP_S3#
RF_AMBER_LED#
ME_FLASH_EN
ODD_PWEN#
WOL_PWEN#
TP_OFF_LED#
47
47
BI
BI
17
IN
1
14
49
28
36
26
40
41
47
PWR_LED#
KB_BLON
CPU_PROCHOT#
AC_LED
CPUFAN1_ON#
EC_LCD_PWM
1
AC_LED
IN
PWM4_GPA4_UP
24
25
28
29
30
31
R14102
35
G
D
Q103
D
Q102
CHG_LED 1
IN
CIR
VCORE
1
AC_LED#
OUT
560_5%_2
R14
5
CTX0_TMA0_GPB2_3_DN
PWM3_GPA3_UP
AVSS
31
52
3 2
1
R10
CHG_LED#
CRX0_GPC0_DN
PWM5_GPA5_UP
P5V0A
470_5%_2
3 2
B
OUT
OUT
IN
15
40
H_PECI
2
R770
43_5%_2
2
15
PWM2_GPA2_UP
119
123
28
PWUREQ#_BBO_SMCLK2ALT_GPC7_3_UP
PWM1_GPA1_UP
ADP_SEL :
PU : 90W (SG)
PD : 65W (UMA)
P5V0A
35
GPIO
PWM0_GPA0_UP
ADP_SEL
RESUME_PWEN
CORE_PWEN#
ODD_MD#
TP_CLK
TP_DAT
1
IN
KBRST#_GPB6_3_X
2
TO TP-LED <-----
OUT
PS2DAT2_WUI21_GPF5_UP
85
86
89
90
LPC
ECSCI#_GPD3_UP
WRST#
75
100K_5%_2_DY
2
1
2
C792
1
100K_5%_2
5
PS2DAT0_TMB1_GPF1_UP
PS2CLK2_WUI20_GPF4_UP
100K_5%_2
2
R769
R766
0.1uF_16V_2
1
PS2CLK0_TMB0_GPF0_UP
EC_PECI
SUS_PWR_DN_ACK
R845
1
C
R802
OUT
OUT
SMDAT2_WUI23_GPF7_3_UP
2
P3V3AL
ECSMI#_GPD4_3_UP
PECI_SMCLK2_WUI22_GPF6_3_UP
BI
BI
BI
BI
10K_5%_2_DY
DIODE-BAT54-TAP-PHP
1
EC_RST#
KB_RST#
CHG_LED
VSS
3
31
35
SERIRQ_GPM6_3_X
VSS
VSS
VSS
113
122
NC
D527
LPCPD#_WUI6_GPE6_DN
GA20_GPB5_3_X
1
P3V3AL
LFRAME#_GPM5_3_X
SMDAT1_GPC2_X
1
126
5
15
23
14
4
16
LPCCLK_GPM4_3_X
SMCLK1_GPC1_X
R844
17
A20GATE
SERIRQ
LPCRST#_WUI4_GPD2_UP
SMDAT0_GPB4_X
SM BUS
23 50
23 50
5 6
5 6
10K_5%_2
BI
RSMRST#
LAD3_GPM3_3_X
D
THM_CLK
THM_DAT
BATT_CLK
BATT_DAT
110
111
115
116
117
118
2
26
OUT
LAD2_GPM2_3_X
SMCLK0_GPB3_X
1
28
OUT
LAD1_GPM1_3_X
2
2
R771
2.2K_5%_2
U514
LAD0_GPM0_3_X
1
1
2
0_5%_2
31
R303
P3V3S
R772
2.2K_5%_2
2
2
10K_5%_2
3EC_SCI#_D
26
26
26
26
28
0_5%_2
1 R767
DIODE-BAT54-TAP-PHP
EC_SCI# 1
36
OUT
OUT
OUT
OUT
OUT
R14103
2
2
D529
2
OUT
46
NC
1
31
46
P3V3S
R998
10K_5%_2
10
9
8
7
22
13
6
27
49
91
113
122
P3V3S
BI
BI
BI
BI
IN
IN
IN
OUT
HSPI_SI
HSPI_SO
HSPI_CLK
HSPI_CS0#
SB_PWRGD
PS/2
1
10K_5%_2
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
BUF_PLT_RST#
CLK_LPC_EC
LPC_FRAME#
HMOSI_GPH6_ID6_DN
HMISO_GPH5_ID5_DN
HSCK_GPH4_ID4_DN
HSCE#_WUI19_GPH3_ID3_DN
CLKRUN#_WUI16_GPH0_ID0_DN
R822
2
EC_SMI#_D
3
26
26
26
26
17
30
26
CAPS_LED#
47
100K_5%_2
L80HLAT_BAO_WUI24_GPE0_DN
L80LLAT_WUI7_GPE7_UP
1
46
46
46
46
30
VBAT
AVCC
DIODE-BAT54-TAP-PHP
VCC
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
2
OUT
D528
EC_SMI#
NC
31
TP306
38
28
47
1
11
26
50
92
114
121
2
84
83
82
2
R821
10K_5%_2
VSTBY
C794
FBM_11_160808_121T
60140EA0319T
200mA_0603
1
TP24
P3V3S_EC_VCC
2
EGCLK_WUI27_GPE3_DN
EGCS#_WUI26_GPE2_DN
EGAD_WUI25_GPE1_DN
L515
1
IN
OUT
OUT
1
2mA
P3V3S
D
LID_SW#
SB_PWRBTN#
USBPWR_EN
P3V3S
0.1uF_16V_2
1
C817
2
0.1uF_16V_2
2
C797
1
0.1uF_16V_2
1
C796
2
1
2
C848
200mA_0603
0.1uF_16V_2
2
KSI0_STB#
KSI1_AFD#
KSI2_INIT#
KSI3_SLIN#
KSI4
KSI5
KSI6
KSI7
L516
1
FBM_11_160808_121T
60140EA0319T
0.1uF_16V_2
20mA
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
35
57
of
1
X01
6
5
4
3
C
35
36
36
IN
IN
IN
CAPS_LED#
R810
1
RF_W_LED#_AND
RF_LED#_AND
2 100_5%_2
R815
1
1
2 150_5%_2
2
150_5%_2
R814
NC
CN508
D534
1
2
3
47
4
35
IN
PWR_LED#1
1
R1078
1
2
360_5%_2
2
2
5
6
D
EVL_12_21_T3D_CP1Q2B12Y_2C_2P
7
6011B0115101
8
9
10
11
12
13
14
15
16
SATA LED & HDD HALTED LED
17
18
19
20
21
P5V0S
WHITE
23
ESD
24
25
U547
NC
22
TC7SET08FU
27
26
28
29
G
30
G
IN
G2
G1
LED_SATA#
1
P3V3S
D533
6019A0059801
26
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
SCAN_IN(1)
SCAN_IN(7)
SCAN_IN(6)
SCAN_OUT(9)
SCAN_IN(4)
SCAN_IN(5)
SCAN_OUT(0)
SCAN_IN(2)
SCAN_IN(3)
SCAN_OUT(5)
SCAN_OUT(1)
SCAN_IN(0)
SCAN_OUT<2>
SCAN_OUT<4>
SCAN_OUT<7>
SCAN_OUT<8>
SCAN_OUT<6>
SCAN_OUT<3>
SCAN_OUT<12>
SCAN_OUT<13>
SCAN_OUT<14>
SCAN_OUT<11>
SCAN_OUT<10>
SCAN_OUT<15>
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
P3V3A
4
1
2
1
2
C
R1059
2
1
2
330_5%_2
-
P3V3S
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
1
LED_SINGLE_3PIN_B
31
EVL_12_21_T3D_CP1Q2B12Y_2C_2P
32
6011B0115101
3
D
2
POWER LED
KeyBoard CONN(30 pin)
5
7
+
8
ACES_50690_0324N_001_32P
6012B0372601
P5V0S
R118
C790
1
1
2
0_5%_2_DY
5
2
0.1uF_16V_2
U512
+
1
RF_LED#_AND
4
IN
RF_AMBER_LED# 2
OUT
36
-
35
TC7SET08FU
B
6019A0059801
3
B
P5V0S
C791
1
5
2
0.1uF_16V_2
U513
+
1
4
IN
RF_W_LED#_AND
RF_WHITE_LED# 2
OUT
36
-
35
3
TC7SET08FU
6019A0059801
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
KB CONN & LED
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
36
57
of
1
X01
8
7
6
5
4
1
R717
3
CRT_R
2
OUT
CRT_R
2
R1107
1
OUT
CRT_G
2
R1109
1
37
OUT
CRT_B
2
R1108
1
37
OUT
CRT_HSYNC
2
R1106
1
37
OUT
CRT_VSYNC
2
R1100
1
PCH_CRT_R_CLK
2
R1105
1
PCH_CRT_R_DAT
2
R1101
1
37
75_1%_2_DY
P5V0S_CRTVDD
P5V0S
37
1
U3050
EN
R3050
1
2
1K_5%_2
IN
PCH_CRT_R
29
IN
PCH_CRT_G
29
IN
PCH_CRT_B
29
1
NUVO_NCT3521U_SOT23_5P
10uF_6.3V_5
DIS
P3V3S
C3051
1
C3050
1uF_6.3V_2
4
CRT_G
2
75_1%_2_DY
1
2
3
OUT
GND
2
D
IN
2
5
R718
1
R715
CRT_B
2
75_1%_2_DY
1
L512
2
CRT_R
OUT
37
CRT_G
OUT
37
CRT_B
OUT
37
L511
2
P5V0S
P5V0S
P5V0S
2
2
37
37
37
2
37
37
37
37
1
1
2
5
1
1uF_6.3V_2
0_5%_2_DY
33_5%_2_DY
33_5%_2_DY
0_5%_2_DY
0_5%_2_DY
GPU_CRT_R
IN
49
GPU_CRT_G
IN
49
GPU_CRT_B
IN
49
GPU_CRT_HSYNC
IN
49
GPU_CRT_VSYNC
IN
49
GPU_CRT_CLK
BI
49
GPU_CRT_DAT
BI
49
D
P5V0S_CRTVDD
CRT_R
CRT_G
CRT_B
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CRT_DAT
CRT_HSYNC_CN
CRT_VSYNC_CN
CRT_CLK
BI
IN
IN
BI
CN502
1
2
3
4
5
C
6
7
8
9
10
11
12
G
13
G
G1
G2
14
15
SUYIN_070546HR015M251ZR_15P
R671
C674
100K_5%_2
P3V3S
2
0_5%_2_DY
1
1
3
BAV99_DY
BAV99_DY
BAV99_DY
C
3
1
3
1
1
1
12pF_50V_2
2
C689
C690
2
12pF_50V_2
1
C691
2
12pF_50V_2
12pF_50V_2
1
2
C693
1
C694
2
12pF_50V_2
1
C692
12pF_50V_2
2
R716 1
150_1%_2
2
R714 1
150_1%_2
FBM_10_160808_300T
D520
2
2
D519
150_1%_2
L513
D521
2
R719 1
FBM_10_160808_300T
1
0_5%_2_DY
CRT
FBM_10_160808_300T
1
2
6012B0318901
5
PCH_CRT_VSYNC
2
CRT_VSYNC
4 4
2
OUT
37
3
IN
1
+
29
U506
TC7SZ126FU
P3V3S
3
1
R722
2
R672
2.2K_5%_2
C695
PCH_CRT_DAT 1
R1111
PCH_CRT_R_DAT
2
0_5%_2
33_5%_2
IN
CRT_HSYNC
1
37
IN
CRT_VSYNC
1
R713
R670
1
2
37
2
CRT_HSYNC_CN
OUT
37
2
CRT_VSYNC_CN
OUT
37
37
3
CRT_DAT
BI
37
D518
A
PHP_PESD5V2S2UT_SOT23_3P_DY
33_5%_2
D517
PHP_PESD5V2S2UT_SOT23_3P_DY
3
A
BI
2
BI
CRT_CLK
3
29
G
2
U507
TC7SZ126FU
3
Q527
2
Q528
PCH_CRT_R_CLK
1
2
0_5%_2
G
1
1
PCH_CRT_CLK
SSM3K7002FU
SSM3K7002FU
1
5
3
BI
37
3
-
OUT
S
29
CRT_HSYNC
4 4
2
D
PCH_CRT_HSYNC
2
R1112
S
IN
2
2.2K_5%_2
+
D
29
R721
1
1
1uF_6.3V_2
2
2.2K_5%_2
2
5
1
2
1
R720
1
2.2K_5%_2
P3V3S
B
P5V0S_CRTVDD
1
B
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CRT CONN
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
37
57
of
1
X01
8
7
6
5
4
3
2
1
P3V3S_LCDVDD
2
1
1
2
3
OUT
1uF_6.3V_2
DIS
EN
PCH_LCDVDD_EN
1
NUVO_NCT3521U_SOT23_5P
6019B0849401
R597
2
C599
1
GND
4
2
IN
IN
29
100K_5%_2
5
2
P3V3S_LCDVDD
R595
2
BOARD_ID5 ONLY FOR WEBCAN USE
FOR HD WEB CAM BOARD_ID5 PULL P3V3A
FOR VGA WEB CAM BOARD_ID5 PULL GND
100_5%_3
USB_P5_DP
1
2
USB_P5_R_DP
R2251
0_5%_2
38
1
2
IO
3
IO
C597
D511
2
3
1
1
GND
Vcc 4
P3V3S
44
4
PHP_PRTR5V0U2X_SOT143_4P_DY
R626
38
DMIC_DAT
IN
IN
PCH_LCD_TXA0_DN
PCH_LCD_TXA0_DP
29
29
IN
IN
PCH_LCD_TXA1_DN
PCH_LCD_TXA1_DP
29
29
IN
IN
PCH_LCD_TXA2_DN
PCH_LCD_TXA2_DP
29
29
IN
IN
PCH_LCD_TXACL_DN
PCH_LCD_TXACL_DP
2
BOARD_ID5
PCH_LCD_PWM
LCD_BKEN
OUT
IN
IN
38
38
IN
IN
USB_P5_R_DN
USB_P5_R_DP
38
38
IN
OUT
DMIC_CLK
DMIC_DAT_CN
C596
1
1000PF_50V_2_DY
D
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C
25
26
27
G
28
G
G1
G2
29
30
6012B0431201
33_5%_2
1
DMIC_DAT_CN
2
OUT
38
DMIC_CLK
C508
2
2
C1026
CSC0402_DY
1
1
B
B
10pF_50V_2_DY
44
OUT
IN
2
6019B0134501_DY
44
29
29
1
2
ACES_50203_03001_001_30P
C592
P5V0S
PCH_LCD_CLK
PCH_LCD_DAT
30
29
38
38
2
C2253
CSC0402_DY
2
C2252
C
OUT
OUT
PVBAT_LCD
1
USB_P5_R_DN
BI
BI
CN503
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
4.7UF_6.3V_3
2
1
1
2
30
USB_P5_DN
1
WEBCAM
IN
IN
0_5%_2
CSC0402_DY
30
R2250
1UF_25V_3
1
29
29
2.2K_5%_2
1
R572
U501
D
P3V3S_LCDVDD
0.1uF_16V_2
2.2K_5%_2
2 R571 1
C572
2
P3V3S
LCM
4.7uF_6.3V_3
1
P3V3S
C557
PVBAT
PVBAT_LCD
PAD508
1
1
2
2
POWERPAD1x1m
3
1
LCD_BKEN
OUT
38
G
AO3409_DY
6015B0022201_DY
1
1
0.22uF_16V_2_DY
C591
2
R623 1
R622
NC
LID_SW#
20K_5%_2_DY
2
1
IN
2
35
3
Q511
10K_5%_2_DY
2
47
S
D503
A
D
2
A
DIODE-BAT54-TAP-PHP
60110GA0367T
PCH_LCD_BKEN
1
R627
2
100K_5%_2
IN
1
29
R628
2
3K_5%_2
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
LCD CONN
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
38
57
of
1
X01
8
7
6
5
4
3
2
1
D
D
HDMI
3
P0V0S_HDMI
P5V0S_CRTVDD
D
Q542
S
2
SSM3K7002FU
1 R833
2
100K_5%_2
C
29
29
29
29
29
29
29
2
2
2
2
2
2
2
2
680_5%_2
680_5%_2
680_5%_2
680_5%_2
680_5%_2
680_5%_2
680_5%_2
680_5%_2
IN
HDMI_TX2_C_DP
39
39
IN
IN
HDMI_TX2_C_DN
HDMI_TX1_C_DP
39
39
IN
IN
HDMI_TX1_C_DN
HDMI_TX0_C_DP
39
39
IN
IN
HDMI_TX0_C_DN
HDMI_TXCL_C_DP
39
IN
HDMI_TXCL_C_DN
BI
BI
HDMI_CLK
HDMI_DAT
OUT
HDMI_HPD
39
PCH_HDMI_TX2_DP
C824 1
20.1uF_16V_2
HDMI_TX2_C_DP
39
PCH_HDMI_TX2_DN
C823 1
20.1uF_16V_2
HDMI_TX2_C_DN
39
PCH_HDMI_TX1_DP
C803 1
20.1uF_16V_2
PCH_HDMI_TX1_DN
C804 1
20.1uF_16V_2
PCH_HDMI_TX0_DP
C799 1
20.1uF_16V_2
PCH_HDMI_TX0_DN
C801 1
20.1uF_16V_2
PCH_HDMI_TXCL_DP
C800 1
20.1uF_16V_2
PCH_HDMI_TXCL_DN
C802 1
20.1uF_16V_2
OUT
OUT
HDMI_TX1_C_DP
OUT
HDMI_TX1_C_DN
OUT
HDMI_TX0_C_DP
OUT
HDMI_TX0_C_DN
OUT
HDMI_TXCL_C_DP
OUT
HDMI_TXCL_C_DN
OUT
39
39
39
P5V0S_CRTVDD
39
39
39
39
39
2
C12718
1
29
IN
IN
IN
IN
IN
IN
IN
IN
1
1
1
1
1
1
1
1
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CN509
1
2
3
C
4
5
6
7
8
9
10
11
12
13
GND
14
GND
15
GND
16
GND
G1
G2
G3
G4
17
18
19
SYN_100042GR019M191ZR_19P
P5V0S_CRTVDD
6012B0361401
3
R780
R784
R785
R781
R782
R783
R829
R830
G
4.7uF_6.3V_3
1
D526
2
BAV99_DY
1
B
B
1 R778
2
2.2K_5%_2
P3V3S
1 R746
2
2.2K_5%_2
1 R779
2
2.2K_5%_2
1 R787
2
2.2K_5%_2
Q536
SSM3K7002FU
PCH_HDMI_CLK
HDMI_CLK
3
1
2
P5V0S_CRTVDD
3
3
PANASONIC_DB3X313J0L_SOT_3P
6011B0148301
BI
39
G
2
S
BI
D
29
D525
1
2
P3V3S
A
1
A
PCH_HDMI_DAT
HDMI_DAT
P3V3S
BI
39
3
Q533
SSM3K7002FU
INVENTEC
1
G
2
S
BI
D
29
TITLE
MODEL,PROJECT,FUNCTION
HDMI CONN
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
39
57
of
1
X01
8
7
6
5
4
3
2
1
SATA HDD CABLE CONN on MB
26
26
26
26
1
0.1uF_16V_2
C1007
2
2
C1008
D
22uF_6.3V_5
1
P5V0S
OUT
OUT
SATA_HDD_RX_DP C971
SATA_HDD_RX_DN C972
1
1
2 0.01uF_50V_2
2 0.01uF_50V_2
IN
IN
SATA_HDD_TX_DN C970
SATA_HDD_TX_DP C969
1
1
2 0.01uF_50V_2
2 0.01uF_50V_2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SATA_HDD_RX_C_DP 15
SATA_HDD_RX_C_DN 16
17
SATA_HDD_TX_C_DN 18
SATA_HDD_TX_C_DP 19
20
CN525
1
2
3
4
D
5
6
7
8
9
10
11
12
13
14
15
16
17
G
18
G
19
G
20
G
G1
G2
G3
G4
FOX_GS12201_1011_9H_20P
6012B0238201
C
C
SATA ODD CABLE CONN on MB
P15V0A P5V0A
P5V0S_ODD
P5V0S_ODD
P3V3S
R819
1
2
3
0.1uF_16V_2
1
G
1
R818
2
1K_5%_2
1
C813
2
SSM3K7002FU
4
IN
FDC655BN
2
D
IN
S
35
G
S
35
NMOS_4D1S
Q541
ODD_PWEN#
1
D
2
1
2
5
6
C814
Q540
0.1uF_25V_2
1
R820
2
3
560K_1%_2
B
22uF_6.3V_5
C815
2
1
10K_5%_2
ODD_MD#
31
OUT
ODD_PRSNT#1
R843
2
0_5%_2_DY
26
26
OUT
OUT
SATA_ODD_RX_DP
SATA_ODD_RX_DN
C847
C846
1
1
2 0.01uF_50V_2SATA_ODD_RX_C_DP
2 0.01uF_50V_2 SATA_ODD_RX_C_DN
26
26
IN
IN
SATA_ODD_TX_DN
SATA_ODD_TX_DP
C854
C844
1
1
2 0.01uF_50V_2SATA_ODD_TX_C_DN
2 0.01uF_50V_2 SATA_ODD_TX_C_DP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CN514
1
2
B
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
G
18
G
19
G
20
G
G1
G2
G3
G4
FOX_GS12201_1011_9H_20P
6012B0238201
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SATA HDD & SATA ODD
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
40
57
of
1
X01
3
1
C418
2
0.1UF_16V_2
2
C413
0.1UF_16V_2
1
PIN29 PIN45
1
1
1
PIN13
0.1UF_16V_2
1
0.1UF_16V_2_DY
1
X5R
C405
4.7UF_6.3V_3_DY
L400
1ST : 6014B0200401
2ND : 6014B0190301
C404
LDO MODE(RTL8165EH)
L400,C404,C405 OPEN
2
1
0.1UF_16V_2
C423
2
1
C422
2
0.1UF_16V_2
1
0.1UF_16V_2
C421
2
1
0.1UF_16V_2
C419
2
1
C416
2
1
2
0.1UF_16V_2
1
C420
2
LDO MODE(RTL8165EH)
R413,C417,C420 OPEN
1
0_5%_3_DY
0.1UF_16V_2_DY
2
2
C408
2
LAN
R413
C414
P3V3_LAN_REG
1
4.7UF_6.3V_3_DY
2
R411
750K_1%_2
X5R C417
1
1 1
WOL_PWEN#
0.1UF_16V_2
IN
0.1UF_16V_2
G
2
35
6014B0200401
PIN41
C412
2
TAITECH_SWF2520CF-2R2M-R15
PIN9
2
L400
3
PIN6
2
1
1
C406
S
S
PIN39 PIN42 PIN47 PIN48
D
2
CLOSE TO LAN CHIP
PIN12 PIN27
2
D
0.5A
Q401
AM2321P
G
P3V3A RISING TIME (10%~90%) MUST >1MS AND <100MS
2
P3V3A
SSM3K7002FU_DY
PIN3
0.1UF_16V_2_DY
C409
3
2
0.1UF_16V_2_DY
C411
P3V3A_LAN
200_5%_2_DY
1
D
CLOSE TO LAN CHIP
P1V0_LAN_REG
R412
1
1
P1V0_LAN
DISCHARGE ELECTRICITY
Q400 , R412
Q400
2
2
4
1
5
2
6
0.1UF_16V_2_DY
7
0.1UF_16V_2_DY
C415
8
D
USE RTL8161FH
C406,C409,C411,C415 MOUNT
P1V0_LAN_EVDD
PAD400
XTAL2
2
0_5%_2
XTAL1
2
P1V0_LAN
27PF_50V_2_DY
XTAL2
1
2
3
X400
C
GPO_SMBALERT
R406
25MHZ_DY
LED_LANLINK#
2.49K_1%_2
1
42
MOUNT R407, OPEN R4078
ENABEL SWITCHING REGULATOR
MOUNT R408, OPEN R407
XTAL1
DISABEL SWITCHING REGULATOR
42
42
IN
IN
LAN_TRD0_DP
LAN_TRD0_DN
42
42
OUT
OUT
LAN_TRD1_DP
LAN_TRD1_DN
42
42
IN
IN
LAN_TRD2_DP
LAN_TRD2_DN
42
42
OUT
OUT
LAN_TRD3_DP
LAN_TRD3_DN
P3V3_LAN_REG
1
2
3
4
5
6
7
8
9
10
11
12
P1V0_LAN
MDIP0
REGOUT
MDIN0
VDDREG
U400
NC
MDIP1
36
35
34
33
32
31
30
29
28
27
26
25
VDDREG
ENSWREG
MDIN1
EEDI
NC
EEDO_LED3
RTL8165EH
NC
NC
EECS
DVDD10
NC
LANWAKEB
DVDD33
NC
ISOLATEB
NC
PERSTB
GND
HSON
HSOP
EVDD10
REFCLK_N
REFCLK_P
HSIN
HSIP
CLKREQB
NC
NC
DVDD10
NC
P3V3A_LAN
0_5%_2_DY
27PF_50V_2_DY
EESK_LED1
GPO
DVDD33
LED0
NC
NC
CKXTAL1
CKXTAL2
AVDD10
RSET
AVDD33
AVDD33
TML
B
P3V3A_LAN
41
P1V0_LAN_REG
37
38
39
40
41
42
43
44
45
46
47
48
49
C403
42
OUT
OUT
OUT
2
4
1
6018B0044501_DY
1
1
P3V3A_LAN
LED_LANRXACT#
2
C407 , C410
CLOSE TO
RTL8165EH
PIN21
P1V0_LAN
2
2
R407
C402
1
C
P3V3A_LAN
2
R414
1
0.1UF_16V_2
LAN_25M_IN
IN
C407
16
C410
2
POWERPAD1X1M
1UF_16V_3
1
2
1
1
MOUNT R408, OPEN R407
ENABLE LDO REGULATOR
(ONLY 10/100)
P3V3A_LAN
2 R408
1
0_5%_2
EEDI_SDA
1
R4031
1
EECS_SCL
R404
PCIE_WAKE#
PLT_RST#
IN
P3V3S
2
B
10K_5%_2
2
10K_5%_2
OUT
30
43
28
41
48
R4091
2 1K_1%_2
R4101
2 15K_1%_2
RTL8161FH(10/100/1000) / RTL8165EH(10/100)
REA_RTL8165EH_VB_CGT_QFN_48P
24
23
22
21
20
19
18
17
16
15
14
13
P1V0_LAN
TP400
MOUNT
OPEN PART
LDO MODE
R408 (0V)
L400,R413,R407
C404,C405,C417,C420
SWITCHING
MODE
L400,R413,R407
C404,C405,C417,C420
R408
RTL8165EH
(10/100)
3.3V:ENABLE SWITCHING REGULATOR
OR EXTERNAL 1.05V INPUT MODE.
0V:ENABLE LDO REGULATOR
RTL8161FH
(10/100/1000)
3.3V:ENABLE SWITCHING REGULATOR
0V:DISABLE SWITCHING REGULATOR
(ONLY 10/100)
RTL8161FH = 6019B0928101(10/100/1000)
RTL8165EH = 6019B0928301(10/100)
1
TP30
P1V0_LAN_EVDD
1
A
27
27
27
27
27
27
27
R405
OUT
CLKREQ_LAN#
IN
IN
PCIE_LAN_TX_C_DP
IN
IN
CLK_PCIE_LAN_DP
OUT
OUT
PCIE_LAN_RX_C_DP
C400
2
PCIE_LAN_RX_C_DN
2
2
P3V3A_LAN
10K_5%_2
PCIE_LAN_TX_C_DN
41
28
OUT
PCIE_WAKE#
1
2
R4011
10K_5%_2_DY
A
CLK_PCIE_LAN_DN
C401
0.1UF_16V_2
1
PCIE_LAN_RX_DP
1
PCIE_LAN_RX_DN
41
OUT
GPO_SMBALERT
1
R4021
2
INVENTEC
1K_1%_2_DY
IF THERE ARE NO OTHER APPLICATION, REMOVE R4021
0.1UF_16V_2
TITLE
C401, C400 CLOSE TO LAN CHIP PIN 22, 23
MODEL,PROJECT,FUNCTION
LAN
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
41
57
of
1
X01
8
7
6
5
4
3
2
1
TRANSFORMER
U470 FOR GIGALAN
D
D
MCT3
TD3-
MX3-
TD3+
MX3+
TCT4
MCT4
TD4-
MX4-
TD4+
MX4+
LAN_TRD1_CN_DN
OUT
LAN_TRD1_CN_DP OUT
42
42
LAN_TRD2_CN_DN
LAN_TRD2_CN_DP
IN
IN
42
42
LAN_TRD3_CN_DN
LAN_TRD3_CN_DP
OUT
OUT
42
42
R470
LANKOM_LG_2405S_1_SMD_24P_DY
6016B0010601_DY
CAP VALUE SHOULD BE
0.01UF ~ 0.4UF
2
0.01UF_50V_2
U502
RD+
RX+
RD-
RX-
CT1
CT4
NC1
NC4
NC2
NC3
CT2
CT3
TD+
TX+
TD-
TX-
16
15
14
13
12
11
10
9
1 1
1
2
3
4
5
6
7
8
C470
C
C471
1000PF_2000V_6
2
1
C
2
MX2+
TCT3
42
42
75_5%_2
MX2-
TD2+
IN
IN
R473
TD2-
LAN_TRD0_CN_DN
LAN_TRD0_CN_DP
1
MCT2
2
TCT2
75_5%_2
MX1+
R472
IN
IN
LAN_TRD3_DN
LAN_TRD3_DP
MX1-
TD1+
1
OUT
OUT
LAN_TRD2_DN
LAN_TRD2_DP
24
22
23
21
19
20
18
16
17
15
13
14
MCT1
TD1-
2
LAN_TRD1_DN
LAN_TRD1_DP
TCT1
R471
41
41
IN
IN
U470
75_5%_2
41
41
1
3
2
4
6
5
7
9
8
10
12
11
LAN_TRD0_DN
LAN_TRD0_DP
1
41
41
OUT
OUT
2
41
41
75_5%_2
U502 FOR 10/100 LAN
BOTH_NS0014_LF_16P
6016B0008101
B
B
JACK500
42
42
42
42
42
42
42
42
OUT
OUT
IN
OUT
OUT
IN
IN
IN
LAN_TRD0_CN_DP 1
LAN_TRD0_CN_DN 2
LAN_TRD1_CN_DP 3
LAN_TRD2_CN_DP 4
LAN_TRD2_CN_DN 5
LAN_TRD1_CN_DN 6
LAN_TRD3_CN_DP 7
LAN_TRD3_CN_DN 8
P3V3A_LAN
1
2
3
G1
4
G2
5
A1
6
A2
7
B1
8
B2
G1
G2
A1
A2
B1
B2
R731
510_5%_2
LED_R_LANLINK#
1
2
LED_LANLINK#
IN
41
LED_R_LANRXACT#
1
2
LED_LANRXACT#
IN
41
R745
510_5%_2
SANTA_130452_06_8P
6026B0200401-002
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
RJ45
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
& TRANSFORMER
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
42
57
of
1
X01
5
4
CARE READER
IN
OUT
1
C716
PLT_RST#
SD_CD#
CLKREQ_CR#
SD_WP
PCIE_CR_RX_C_DP
PCIE_CR_RX_C_DN
2
C703
1
PCIE_CR_RX_DP
1
PCIE_CR_RX_DN
D
2
U532
SP6
HSIN
SP5
REFCLKP
SP4
REFCLKN
DV33_18
HSON
R119
10K_5%_2
HSIP
HSOP
P3V3S
43
SP3
SP2
7
8
9
10
11
12
0.1uF_16V_2
18 SD_DATA2_R
R701 1
17 SD_DATA3_R
R702 1
16 SD_CMD_R
R706 1
15 P1V8S_CARD
14 SD_CLK_R
R7031 1
13 SD_DATA0_R
R704 1
2 0_5%_2
2 0_5%_2
2 0_5%_2
SD_DATA2
SD_DATA3
SD_CMD
BI
BI
BI
43
43
43
2 0_5%_2
2 0_5%_2
SD_CLK
SD_DATA0
OUT
BI
43
43
BI
43
1
0.1uF_16V_2
C702
2
OUT
OUT
1
2
3
4
5
6
PCIE_CR_TX_C_DP
PCIE_CR_TX_C_DN
CLK_PCIE_CR_DP
CLK_PCIE_CR_DN
SP1
DV12_S
CARD_3V3
3V3_IN
RREF
AV12
IN
IN
IN
IN
GPIO
SP7
SD_CD#
MS_INS#
PERST#
CLKREQ#
TML
27
27
27
27
27
27
43
IN
IN
1
ZDIFF : 100 OHM
2
30
27
25
24
23
22
21
20
19
D
41
REALTEK_RTS5239_GR_QFN_24P
6019B0928001
R700
1
2
2
6.2K_1%_2
SD_DATA1_R
P3V3S
1
R705
2
SD_DATA1
C
0_5%_2
P1V2_S_CR
1
C7061
2
C705
2
0.1uF_16V_2
1
100MA
10uF_6.3V_5
1
C704
2
C713
2
0.1uF_16V_2
4.7uF_6.3V_3
1
P1V2_CR
C
1
0.1uF_16V_2
48
2
P1V8S_CARD
C7091
C701
2
★RTS5239GR = 6019B0928001
3
CSC0402_DY
6
1
7
1000PF_50V_2
8
2
C7111
1
4.7uF_6.3V_3
2
C7101
1
0.1uF_16V_2
P3V3S_CR
800MA
B
B
43
P3V3S_CR
43
SD_DATA3
1
DAT3
GND
G1
BI
SD_CMD
2
CMD
GND
G2
3
VSS
CD_WP_COM
12
4
VDD
CD
11
SD_CD#
OUT
43
5
CLK
WP
10
SD_WP
OUT
43
6
VSS
DAT2
9
SD_DATA2
BI
43
7
DAT0
DAT1
8
SD_DATA1
BI
43
800MA
10uF_6.3V_5
2
C1050
1
43
43
CN523
BI
IN
BI
SD_CLK
SD_DATA0
PLAS_CS1S_125_14P-002
6026B0103603-002
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CARD READER
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
43
57
of
1
X01
8
7
6
5
44
AUDIO
44
OUT
OUT
OUT
OUT
35
OUT
44
44
4
3
2
1
SPKR_L_DP
SPKR_L_DN
SPKR_R_DN
C500,C503
PLACE NEST TO PIN 38
P5V0S_PVDD_AUDIO
SPKR_R_DP
P5V0S
P5V0S_PVDD_AUDIO
1A
AMP_EN
P5V0S_AUDIO_AVDD
1
P3V3S
1
1
C523
2
2
C522
0.1uF_16V_2
1
10uF_10V_5
X5R
C521
1
MIC_REF-R
OUT
45
1
2
LINE1-L
0.1uF_16V_2
C515
1
SPKR_L_DP
SPKR_L_DN
45
IN
45
1
R510
0.1uF_16V_2
1
C519
1
1
2
2
A
POWERPAD_2_0610
2
BLM18PG600SN1D
20K_1%_2
X5R
2
R509,R510
PLACEMENT NEAR
CODEC
500MA_0603
1
SENSE_A
2
60140EA0314T
X5R
2
39.2K_1%_2
B
2
PAD500
1
10UF_10V_5
MICS
L500
C511
IN
1
45
1
C527
1000PF_50V_2
C519,C520
PLACE NEXT TO PIN 25
33.5 MA
1
1uF_6.3V_2
IN
2
C509
45
R509
1
2
SPKR_R_DP
P5V0S_AUDIO_AVDD
1
2
C526
1000PF_50V_2
P5V0S
A
1
EMI
2
1
C520
IN
MIC_L
4.7UF_10V_3
23
22
21
24
2
2
R512
1
20K_1%_2
MIC_R
C
G1
G2
C525
1000PF_50V_2
33.5mA
X5R
R512
PLACEMENT
NEAR
CODEC
G2
EMI
SPKR_R_DN
SENSE_A
G1
4
2
C513,C515
PLACE NEXT TO PIN 27
P5V0S_AUDIO_AVDD
MOAT 40MIL
3
C524
1000PF_50V_2
LINE1-R
MIC1-L
MIC1-R
JDREF
DIGITAL
1
2
ACES_50224_0040N_001_4P
6012B0069911
X5R
2
AVDD1
25
2
1UF_6.3V_2
26
CN526
1
2
3
4
SPKR_L_DP
SPKR_L_DN
SPKR_R_DN
SPKR_R_DP
IN
IN
IN
IN
10uF_6.3V_5
1
C513
AVSS1
C514
44
44
44
44
(INCLUDE THERMAL PAD)
ANALOG
HPS
0.1uF_16V_2
2
38
39
40
41
42
43
44
45
46
47
37
45
PCBEEP
Sense-B
R505
OUT
RESET#
MIC2-L
1
MIC1-VREFO-L
MIC_REF-L
27
MIC2-R
B
INT-SPKR CONN
31
28
LINE2-L
PCSPKR
1
1
X5R
45
VREF
0.1uF_16V_2
2.2uF_6.3V_3
C512
OUT
LDO-CAP
12
2
HP_L
SYNC
LINE2-R
IN
C516
1
32
DVDD-IO
Sense A
26
48
49
2
1K_5%_2
PIN46
X5R
45
29
20
1
CSC0402_DY
D
C506 2.2uF_6.3V_3
OUT
30
19
C504
2
HP-OUT-L
2
HP_R
MIC2-VREFO
MONO-OUT
2
R506
HP-OUT-R
33
MIC1-VREFO-R
11
1
34
SDATA-IN
18
HDA_RST#
CPVEE
DVSS2
9
4.7K_5%_2_DY
26
35
8
10
2
44
CBN
7
17
IN
22_5%_2
26
36
BIT-CLK
16
HDA_SYNC
HDA_SDIN0_CODEC
REALTEK_ALC3201_GRT_MQFN_48P
CBP
6
15
IN
CSC0402_DY
R501 2
1
SDATA-OUT
14
HDA_SDIN0
1
5
U528
13
1
1UF_6.3V_2
2
C501
0.1uF_16V_2
1
C502
2
OUT
PIN39
6014B0157601
PIN38 PIN38
AVSS2
2
22_5%_2
26
HDA_BITCLK_CODEC
C505
PD#
AVDD2
R500 2
1
GPIO1/DMIC-CLK
PVDD1
SHORT_0402
3
4
SPK-L+
IN
HDA_BITCLK
R502 2
33_5%_2
SPK-L-
26
HDA_SDO
1
PVSS1
C
IN
DMIC_CLK
PVSS2
26
IN
OUT
2
GPIO0/DMIC-DATA
SPK-R-
26
R514
2
SPK-R+
44
38
1
DMIC_DAT
DVDD1
PVDD2
4.7K_5%_2_DY
HDA_RST#
IN
1
EAPD/COMBO_JACK
38
SPDIFO
2
PIN39
2A_0603
X5R
TML
1
R513
2
HCB1608KF_221T20
2
33.5mA
5mA
C503
1
10K_5%_2_DY
2
C501,C502
PLACE NEXT TO PIN 1
P5V0S_AUDIO_AVDD
0.1uF_16V_2
P3V3S
2
C500
D
R503
4.7UF_10V_3
X5R
1
L3
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
AUDIO
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
CODEC
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
44
57
of
1
X01
8
7
6
5
4
3
2
1
D
R600
1
MIC
JACK
Normal OPEN
7
C
C929
SINGA_2SJ2285_214252F_6P
6026B0223001
2
BLM18PG600SN1D
MIC_R_JACK
1
MIC_L_JACK
1
1
2
60140EA0314T
1
3
X5R
L522
44
OUT
2
4
1
MICS
R604
1
2
100PF_50V_2
2
1
5
100PF_50V_2
C872
6
5
2
4
1
3
7
6
2
JACK501
2.2K_5%_2
MIC_REF-L
R601
MIC_REF-R
IN
1
IN
44
2
44
2.2K_5%_2
D
L524
1K_5%_2
C876 2.2UF_16V_3
2
MIC_R_C
2
1
MIC_R
OUT
44
2
MIC_L_C
2
1
MIC_L
OUT
44
R605
C930
2.2UF_16V_3
1K_5%_2
BLM18PG600SN1D
C
X5R
D531
2
3
JACK CHANGE TO 6026B0223001
1
PHP_PESD5V2S2UT_SOT23_3P
2
X7R
C610
2
2
HP_L
IN
44
HP_R_R
1
2
HP_R
IN
44
1
1
C1004
HPS
1
1000PF_50V_2_DY
OUT
HP_L_R
BLM18PG600SN1D
2
44
2
1000PF_50V_2_DY
1
0.1UF_16V_2_DY
1
L527
2
C609
2
2
C957
6
100PF_50V_2
5
SINGA_2SJ2285_214252F_6P
6026B0223001
1
60140EA0314T
HP_R_JACK
C1003
2
BLM18PG600SN1D
HP_L_JACK
1
4
R1060
75_5%_2
L535
7
3
1
4
2
5
6
2
3
100PF_50V_2
7
1
1
JACK502
B
C956
HP
JACK
Normal OPEN
B
R1019
75_5%_2
1
0.1UF_16V_2_DY
X7R
C611
2
A
1
A
0.1UF_16V_2_DY
X7R
C612
2
1
0.1UF_16V_2_DY
X7R
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
HP JACK
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
& MIC JACK
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
45
57
of
1
X01
8
7
6
5
4
3
2
1
WLAN CONN (MINICARD)
P3V3S
P1V5S
30
17
30
27
27
27
27
P3V3S
26
IN
IN
OUT
OUT
IN
IN
IN
BUF_PLT_RST#
CLK_LPC_DEBUG
PCIE_WLAN_RX_C_DN
PCIE_WLAN_RX_C_DP
PCIE_WLAN_TX_C_DN
PCIE_WLAN_TX_C_DP
2nd_WLAN_RF_OFF#
CLKREQ#
Reserved
GND
Reserved
REFCLK-
Reserved
REFCLK+
Reserved
GND
Reserved
Reserved
GND
Reserved
Reserved
GND
PERST#
PERN0
+3.3VAUX
PERP0
GND
GND
1.5V
GND
SMB_CLK
PETN0
SMB_DATA
PETP0
GND
GND
USB_D-
Reserved
USB_D+
Reserved
GND
Reserved
LED_WWAN#
Reserved
LED_WLAN#
Reserved
LED_WPAN#
Reserved
1.5V
Reserved
GND
Reserved
3.3V
G
G
1
C685
2
1
C684
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2
2
1.5V
LPC_FRAME#
LPC_AD<3>
LPC_AD<2>
LPC_AD<1>
LPC_AD<0>
IN
BI
BI
BI
BI
26 35
26 35
26 35
26 35
26 35
D524
1
NC
3.3V
GND
Reserved
1uF_6.3V_2
1
C683
2
WAKE#
Reserved
3
WLAN_RF_OFF#
IN
31
DIODE-BAT54-TAP-PHP
C
BUF_PLT_RST#
USB_P8_DN
USB_P8_DP
BI
BI
30
30
WLAN_IND#
OUT
35
P1V5S
IN
17
30
35
46
1000PF_50V_2
35
CLK_PCIE_WLAN_DN
CLK_PCIE_WLAN_DP
CN507
1
46
C
IN
IN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
C686
CLKREQ_WLAN#
27
27
1
1
2
OUT
1
0.1uF_16V_2
1
27
TP1300
TP1301
4.7uF_6.3V_3
C785
2
TP1302
D
0.5A
1.5A
2.2uF_6.3V_3_DY
D
LOTES_AAA_PCI_093_P06_52P
B
B
SI build change to 6026B0221502
VENDOR ID :
DEVICE ID :
(SSID)
SUBSYSTEM ID :
SUBSYSTEM VENDOR ID :
HP P/N :
MARILYN
ATHEROS
AR5B125
RIPPLE3
FOXCONN
RALINK RT5390
0X168C
0X0032
0X1838
0X103C
670036-001
0X1814
0X539A
0X1839
0X103C
670285-001
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
WLAN & BT
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
46
57
of
1
X01
2
1
6
D
7
8
G1
G2
G
9
G
10
11
12
USBPWR_EN
IN
USB_P1_DP
USB_P1_DN
BI
BI
30
30
BI
BI
30
30
USB_P9_DP
USB_P9_DN
35
47
35
35
27
27
BI
BI
BI
BI
TP_DAT
TP_CLK
TP_SMBUS_DAT
TP_SMBUS_CLK
1
2
3
4
5
6
D500
1
2
35
3
4
G
5
G
G1
G2
TP_OFF_LED#
IN
1
S4701
1
S4503
S4700
1
2
CN516
S4502
510_5%_2
R23
1
1
10uF_6.3V_5
SCREW330_600_1P
5
1
SCREW330_600_1P
4
C825
SCREW330_600_0_1P
3
2
1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
1
P3V3S
CN1
for GPU
for CPU
TOUCHPAD LED ON MB
P3V3A
SCREW330_600_0_1P
TouchPad Module CONN
P5V0A
3
S4501
4
1
USB 2.0 BOARD Cable CONN on MB
5
SCREW330_600_0_1P
6
S4500
7
SCREW330_600_0_1P
8
NUT PN :
2
D
6052B0160501
19_217_W1D_AP1Q2QY_3T
6
ENTERY_6916K_Q06M_00L_6P
ACES_50503_0124N_001_12P
6012B0245911
6012B0245913
FIX1
1
FIX2
1
FIX3
1
1
FIX4
FIX_MASK FIX_MASK FIX_MASK FIX_MASK
FIX5
FIX6
FIX7
FIX8
1
1
1
1
FIX_MASK FIX_MASK FIX_MASK FIX_MASK
P5V0A
P5V0A_USB3
USB 3.0 CONN
0.1uF_16V_2
1
S1
S11
R474
1
2
IO
2
GND
1
Vcc
4
4
IO
3
3
2
1
30
30
BI
BI
USB_P0_DN
USB_P0_DP
30
30
OUT
OUT
USB3_P1_RX_DN
USB3_P1_RX_DP
30
30
USB3_P1_TX_DN
USB3_P1_TX_DP
IN
IN
1
4
L537
1
1
2
0.1UF_16V_2_DY
2
1
2
C2405
1
L470
4
3
USB3_P1_RX_L_DN
USB3_P1_RX_L_DP
WCM_1210HS_600T_DY
USB3_P1_TX_C_DN
USB3_P1_TX_C_DP
0.1UF_16V_2_DY
L471
2
1
USB3_P1_TX_L_DN
USB3_P1_TX_L_DP
3
4
WCM_1210HS_600T_DY
D2400
CN518
1
2
3
4
5
6
7
8
9
VBUS
DD+
GND
1
SCREW280_800_NP_1P
1
S12
1
SCREW280_800_1P
2
R477
G1
SSRX+
G2
G3
SSTX-
G4
G1
G2
G3
G4
SSTX+
D2400
6012B0370301
1
10
4
7
2
9
5
6
SHORT_0402
SCREW600_900_800_1P
S4
R476
SSRXGND
FOX_UEA111GC_R14EC_7H_9P
SCREW600_900_800_1P
S3
B
2
USB_P2_L_DN
USB_P2_L_DP
WCM_2012_900T
C2406
R475
SHORT_0402
2
3
6014B0177901_DY
1
1
1
SCREW280_800_1P
A
330uF_6.3V
P5V0A_USB3
U529
C50
CHANGE TO 600_900_900_1P
2
USB2.0 CONN.
PN : 6012B0370102
SEMTECH_RCLAMP0524P.TCT_SLP2510P8_10P_DY
SEMTECH_RCLAMP0524P.TCT_SLP2510P8_10P_DY
SHORT_0402
3
1
1
P5V0A_USB3
S2
1
+
1
+
C997
G1
G2
22uF_6.3V_5_DY
G
6
1
G
5
SCREW280_700_NP_1P
1
C
C2404
4
6014A0013901
1
C996
2
UPI_UP7534ARA8_15_MSOP_8P
SHORT_0402
FOR M/B
OC#
PHP_PRTR5V0U2X_SOT143_4P_DY
2
B
OUT3
C12694
R51
1
2
100K_5%_2
OUT2
IN2
3
6012B0245911
R50
1
2
100K_5%_2
OUT1
IN1
EN#
2
ENTERY_6916K_Q06M_00L_6P
P3V3A
P3V3AL
1
GND
2
PWR_LED#
EC_PWRBTN#
LID_SW#
IN
USBPWR_EN
2
IN
OUT
OUT
35
0.1uF_16V_2
35
35
35
38
47
8
7
6
5
8
36
1
2
3
4
5
6
CN504
2
2
P3V3A
330UF_6.3V_DY
1
POWER BUTTON CONN ON MB
C12712
C
22uF_6.3V_5
U525
1
2
3
4
S5
A
SCREW280_800_1P
1
S6
1
SCREW280_800_NP_1P
1
STD13
STDPAD_1.15_6.0_TOP
SCREW280_800_NP_1P
1
FAN
S7
3.4mm
S8
6052B0035901
INVENTEC
SCREW280_800_1P
1
S9
1
SCREW280_800_NP_1P
1
S10
S14
TITLE
SCREW280_800_NP_1P
MODEL,PROJECT,FUNCTION
USB 3.0
SCREW280_800_NP_1P
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
CONN & M/B TO D/B CONN
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
47
57
of
1
X01
8
7
6
5
4
3
2
1
F
F
U4
CLOSE TO GPU
E
PCIE_RX0P
PCIE_TX0P
PCIE_RX0N
PCIE_TX0N
AE29
AD28
PCIE_RX1P
PCIE_TX1P
PCIE_RX1N
PCIE_TX1N
AD30
AC31
PCIE_RX2P
PCIE_TX2P
PCIE_RX2N
PCIE_TX2N
AC29
AB28
PCIE_RX3P
PCIE_TX3P
PCIE_RX3N
PCIE_TX3N
AB30
AA31
PCIE_RX4P
PCIE_TX4P
PCIE_RX4N
PCIE_TX4N
AA29
Y28
PCIE_RX5P
PCIE_TX5P
PCIE_RX5N
PCIE_TX5N
Y30
W31
PCIE_RX6P
PCIE_TX6P
PCIE_RX6N
PCIE_TX6N
W29
V28
PCIE_RX7P
PCIE_TX7P
PCIE_RX7N
PCIE_TX7N
18
18
BI
BI
PEG_TX7_C_DP
PEG_TX7_C_DN
V30
U31
PCIE_RX8P
PCIE_TX8P
PCIE_RX8N
PCIE_TX8N
18
18
BI
BI
PEG_TX6_C_DP
PEG_TX6_C_DN
U29
T28
PCIE_RX9P
PCIE_RX9N
PCI EXPRESS INTERFACE
AF27
AF26
AD27
AD26
PEG_TX5_C_DP
PEG_TX5_C_DN
T30
R31
PCIE_RX10P
18
18
BI
BI
PEG_TX4_C_DP
PEG_TX4_C_DN
R29
P28
PCIE_RX11P
18
18
BI
BI
PEG_TX3_C_DP
PEG_TX3_C_DN
P30
N31
PCIE_RX12P
PCIE_TX12P
PCIE_RX12N
PCIE_TX12N
18
18
BI
BI
PEG_TX2_C_DP
PEG_TX2_C_DN
N29
M28
PCIE_RX13P
PCIE_TX13P
PCIE_RX13N
PCIE_TX13N
18
18
BI
BI
PEG_TX1_C_DP
PEG_TX1_C_DN
M30
L31
PCIE_RX14P
PCIE_TX14P
PCIE_RX14N
PCIE_TX14N
18
18
BI
BI
PEG_TX0_C_DP
PEG_TX0_C_DN
L29
K30
PCIE_RX15P
PCIE_TX15P
PCIE_RX15N
PCIE_TX15N
27
27
BI
BI
CLK_PEG_DP
CLK_PEG_DN
AK30
AK32
48
IN
PEG_RX0_DN
C42 1
2
0.1UF_16V_2
PEG_RX0_C_DN
OUT
18
48
IN
PEG_RX1_DN
C41 1
2
0.1UF_16V_2
PEG_RX1_C_DN
OUT
18
48
IN
PEG_RX2_DN
C46 1
2
0.1UF_16V_2
PEG_RX2_C_DN
OUT
18
48
IN
PEG_RX3_DN
C19 1
2
0.1UF_16V_2
PEG_RX3_C_DN
OUT
18
48
IN
PEG_RX4_DN
C47 1
2
0.1UF_16V_2
PEG_RX4_C_DN
OUT
18
48
IN
PEG_RX5_DN
C16 1
2
0.1UF_16V_2
PEG_RX5_C_DN
OUT
18
48
IN
PEG_RX6_DN
C24 1
2
0.1UF_16V_2
PEG_RX6_C_DN
OUT
18
48
IN
PEG_RX7_DN
C22 1
2
0.1UF_16V_2
PEG_RX7_C_DN
OUT
18
48
IN
PEG_RX0_DP
C43 1
2
0.1UF_16V_2
PEG_RX0_C_DP
OUT
18
48
IN
PEG_RX1_DP
C40 1
2
0.1UF_16V_2
PEG_RX1_C_DP
OUT
18
48
IN
PEG_RX2_DP
C45 1
2
0.1UF_16V_2
PEG_RX2_C_DP
OUT
18
48
IN
PEG_RX3_DP
C18 1
2
0.1UF_16V_2
PEG_RX3_C_DP
OUT
18
48
IN
PEG_RX4_DP
C25 1
2
0.1UF_16V_2
PEG_RX4_C_DP
OUT
18
48
IN
PEG_RX5_DP
C17 1
2
0.1UF_16V_2
PEG_RX5_C_DP
OUT
18
48
IN
PEG_RX6_DP
C23 1
2
0.1UF_16V_2
PEG_RX6_C_DP
OUT
18
48
IN
PEG_RX7_DP
C21 1
2
0.1UF_16V_2
PEG_RX7_C_DP
OUT
18
AC25
AB25
Y23
Y24
AB27
AB26
Y27
Y26
PCIE_TX9N
BI
BI
PCIE_RX11N
AG29
AF28
PCIE_TX9P
18
18
PCIE_RX10N
AH30
AG31
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
W24
W23
PEG_RX7_DP
PEG_RX7_DN
BI
BI
48
48
V27
U26
PEG_RX6_DP
PEG_RX6_DN
BI
BI
48
48
U24
U23
PEG_RX5_DP
PEG_RX5_DN
BI
BI
48
48
T26
T27
PEG_RX4_DP
PEG_RX4_DN
BI
BI
48
48
T24
T23
PEG_RX3_DP
PEG_RX3_DN
BI
BI
48
48
P27
P26
PEG_RX2_DP
PEG_RX2_DN
BI
BI
48
48
P24
P23
PEG_RX1_DP
PEG_RX1_DN
BI
BI
48
48
M27
N26
PEG_RX0_DP
PEG_RX0_DN
BI
BI
48
48
E
D
P3V3S_DGPU
C37
1
2
0.1UF_16V_2
5
D
AF30
AE31
2
R62
10K_5%_2
1
48
IN
PEG_SLT_RST#
DGPU_HOLD_RST#
4
N10
PWRGOOD
AL27
PERSTB
PCIE_CALRP
Y22
1
PCIE_CALRN
AA22
1
PEG_SLT_RST#
OUT
48
C
-
R30
1
R64
1.27K_1%_2
CALIBRATION
1
2
P1V0S_DGPU
PCIE_REFCLKN
FOR PARK-S3 PIN_N10 MUST NEED TO PULL DOWN TO GND
GPU_PWRGD
IN
2
100K_5%_2
3
C
30
+
U1
CLOCK
PCIE_REFCLKP
TC7SZ08FU
6019B0090701
2
2
R66
2K_1%_2
43
41
30
IN
PLT_RST#
1
R13
2
0_5%_2_DY
THIS PART IS ONLY FOR INTEL PLATFORM
AMD_SEYMOUR_XT_S3_FCBGA_631P
B
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
48
1
X01
of
57
8
F
7
6
5
MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0
0
0
0
0
SAMSUNG C-DIE K4W2G1646C-HC11
128M * 16 *4
0
0
0
1
HYNIX D-DIE H5TQ2G63DFR-11C
128M * 16 *4
PN : 6019B0818601
PN : 6019B0938301
0
0
1
0
MICRON MT41J128M16HA-107G:D
128M * 16 *4
P/N : APPLY
0
0
1
1
4
3
2
2Gb * 4 = 1GB
1
U4
TXCAP_DPA3P
TXCAM_DPA3N
TP5
Y11
AE9
L9
N9
1
P1V8S_DGPU
TX0P_DPA2P
DVCNTL_0
DVCNTL_1
DVO
DVCNTL_2
TX0M_DPA2N
DPA
1
PCIE FULL TX OUTPUT SWING
GPIO1
PCIE TRANSMITTER DE-EMPHASIS ENABLED
BIF_GEN2_EN_A
GPIO2
PCIE GEN2 ENABLED
2
TX_DEEMPH_EN
BIF_DEBUG_ACCESS
GPIO4
DEBUG SIGNALS MUXED OUT
GPIO7_BLON
CONTROL BACKLIGHT ON/OFF
BIF_VGA_DIS
GPIO9
VGA ENABLED
ROMIDCFG(2:0)
GPIO[11:13]
MEMORY APERTURE SIZE SELECT
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7
R3
2
1
10K_5%_2_DY
R33
2
1
10K_5%_2_DY
R61
2
1
10K_5%_2_DY
DESCRIPTION OF DEFAULT SETTING
GPIO0
R2
PIN
TX_PWRS_ENB
10K_5%_2_DY
TX1P_DPA1P
STRAPS
MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0
TX1M_DPA1N
DVDATA_12
TX2P_DPA0P
DVDATA_10
TX2M_DPA0N
DVDATA_9
DVDATA_7
TXCBP_DPB3P
DVDATA_6
TXCBM_DPB3N
TX3P_DPB2P
DVDATA_4
DVDATA_3
TX3M_DPB2N
DPB
DVDATA_2
DVDATA_1
TX4P_DPB1P
DVDATA_0
TX4M_DPB1N
TX5M_DPB0N
W6
V6
DPC_VDD18#3
DPC_VDD18#1
TXCCM_DPC3N
AA5
AA6
DPC_VDD10#1
GPIO_11
0
0
1
512/256 MB (DEFAULT)
1
1
0
RESERVED
MEMORY APERTURE SIZE
AK8
AL7
V4
U5
TX0M_DPC2N
W3
V2
DPC_VDD10#2
TX1M_DPC1N
GPIO_12
AJ7
AH6
DPC_VDD18#2
TX1P_DPC1P
GPIO_13
AK6
AM5
DPC
TX0P_DPC2P
110MA
AK5
AM3
DP_VSSR#13
AC6
AC5
IF GPIO_22_EN=0 , THEN GPIO[11:13] DEFINES THE PRIMARY MEMORYAPERTURE SIZE
AK3
AK1
DVDATA_5
TXCCP_DPC3P
E
F
AH3
AH1
DVDATA_8
P1V8S_DGPU
P1V0S_DGPU
AG3
AG5
DVDATA_11
TX5P_DPB0P
150MA
AF2
AF4
DVCLK
U1
W1
U3
Y6
AA1
E
Y4
W5
DP_VSSR#14
TX2P_DPC0P
DP_VSSR#15
TX2M_DPC0N
AA3
Y2
DPC_CALR
J8
R77
DP_VSSR#16
DP_VSSR#17
1
2
DP_VSSR#18
150_5%_2
I2C
P3V3S_DGPU
R1
R3
49
49
2
49
49
49
50
50
D1
35
OUT
GPU_THROT#
3
1
GPU_GPIO9
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPU_GPIO23
GPU_CRT_VSYNC
GPU_CRT_HSYNC
GPU_GPIO22
BBEN
GPU_GPIO8
OUT
IN
IN
IN
GPIO26_TCK
CTF
TESTEN
GPU_LCM_BLEN
R45 1
R48 1
R44 1
R43 1
R41 1
R39 1
R38 1
R42 1
R55 1
R53 1
2
2
2
2
2
2
2
2
2
2
49
49
49
60110GA0367T
10K_5%_2_DY
10K_5%_2
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
R15
1
THERMTRIP#
2
49
3
G
1
1
1
C14
2
0.1UF_16V_2_DY
2
C
CTF
2
IN
R21
GPU_GPIO1
GPU_GPIO2
GPU_THM_DAT
GPU_THM_CLK
OUT
OUT
OUT
GPU_LCM_BLEN
GPU_GPIO8
GPU_GPIO9
OUT
OUT
OUT
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
56
OUT
POW_SW0
GPUTHERM_INT#
49
56
49
49
49
OUT
OUT
OUT
OUT
OUT
CTF
POW_SW1
BBEN
GPU_GPIO22
GPU_GPIO23
49
49
49
49
OUT
OUT
OUT
OUT
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7
RB
49
2
OUT
TESTEN TP6
TP1
L6
L5
L3
L1
K4
1
K7
1 AF24
GPIO_1
G
GPIO_2
P1V8S_DGPU
PX_EN
52
OUT
GB
GPIO_4_SMBCLK
B
GPIO_5_AC_BATT
BB
DAC1
GPIO_6
GPIO_7_BLON
HSYNC
GPIO_8_ROMSO
VSYNC
1
AC16
RSET
GPIO_11
GPIO_12
AVDD
GPIO_13
AVSSQ
GPIO_14_HPD2
GPIO_16
VDD1DI
GPIO_17_THERMAL_INT
VSS1DI
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
NC/R2
SEYMOUR/PARK
NC/R2B
NC/G2
GPIO_23_CLKREQB
JTAG_TDI
NC/B2
JTAG_TCK
1
NC/B2B
TESTEN
SWAPLOCKB/C
TESTEN_LEGACY
NC/Y
GENLK_CLK
GENERICC
GENLK_V2SYNC
HPD1
R29
C
AL13
AJ13
AD19
AC19
NC/A2VDD
AE20
NC/A2VDDQ
AE17
TSVSSQ/A2VSSQ
AE19
SWAPLOCKA/R2SET
AG13
VREFG
DDC1CLK
DDC1DATA
DPLL_PVDD
DPLL_PVSS
AUX1P
AD14
DPLL_VDDC
DDC2CLK
AM28
AK28
XTALIN
AUX2P
XTALOUT
AUX2N
AE6
AE5
AD2
AD4
AC11
AC13
B
P3V3S_DGPU
AD13
AD11
XO_IN
DDCCLK_AUX3P
XO_IN2
DDCDATA_AUX3N
AD20
AC20
R103
2.2K_5%_2
AE16
AD16
R106
2.2K_5%_2
2
T4
T2
R5
AD17
AC17
P1V8S_DGPU
DDC6CLK
THERMAL
DPLUS
DDC6DATA
AC1
AC3
GPU_CRT_CLK
GPU_CRT_DAT
OUT
OUT
37
37
DMINUS
TS_FDO
TSVDD
TSVSS
L7
1
2
FBM_11_160808_121T
1
0.9V
GPU_THERMDA
GPU_THERMDC
C59
0.95V
1
OUT
OUT
2
0
50
50
1
1
1
AH12
AM10
AJ9
NC/VSS2IDI
AF14
AE14
AC22
AB22
C29
1.1V
1V
AK10
AL9
PX_EN
DDCDATA_AUX5N
6018B0054301_DY
+VDDC_GPU
0
1
2
2
2
A
POW_SW0
0
0
AL11
AJ11
GENERICE_HPD4
DDCCLK_AUX5P
22PF_50V_2_DY
2
AM12
AK12
0_5%_2_DY
10UF_6.3V_3
POW_SW1
1
FBM_11_160808_121T
GENERICD
2
5MA
L9
45MA
GENERICA
GENERICB
AMD_SEYMOUR_XT_S3_FCBGA_631P
0.1UF_16V_2
1
2
0.1UF_16V_2
C55
1
C57
2
10UF_6.3V_3
FBM_11_160808_121T
1M_5%_2_DY
3
2
X1
C36
1
70MA
AE23
AD23
0_5%_2_DY
1
1
R67
D
P1V8S_DGPU
AD22
1
2
499_1%_2
AG24
AE22
JTAG_TDO
2
2
1
4
L6
27MHZ_DY
1
2
1
0.1UF_16V_2
C52
C53
2
125MA
49
49
JTAG_TMS
DDC2DATA
0_5%_2
R65
37
37
JTAG_TRSTB
1 R120 2
GPU_27M_IN_1V8
2
22PF_50V_2_DY
1
IN
16
C35
1
OUT
OUT
GPIO_22_ROMCSB
AUX1N
1
P1V0S_DGPU
10UF_6.3V_3
B
GPU_CRT_HSYNC
GPU_CRT_VSYNC
GPIO_19_CTF
PLL/CLOCK
2
FBM_11_160808_121T
37
AH26
AJ27
GPIO_18_HPD3
L5
1
OUT
GPIO_15_PWRCNTL_0
DDC/AUX
75MA
GPU_CRT_B
2
C54
0.1UF_16V_2
37
AH24
AG25
R37
1
2 2
R26
249_1%_2
37
OUT
GPIO_10_ROMSCK
NC/VDD2IDI
P1V8S_DGPU
OUT
GPU_CRT_G
GPIO_9_ROMSI
NC/COMP
AC14
AB16
R63
2
1
5.11K_1%_2
499_1%_2
R24
GPU_CRT_R
AL25
AJ25
GPIO_3_SMBDATA
20K_5%_2_DY
AB13
W8
W9
W7
AD10
AM26
AK26
GPIO_0
NC/G2B
49
0_5%_2
1
GPU_GPIO0
49
49
49
OUT
CTF:
GPU CRITICAL TEMPER ATURE SHANG DOWN 110°C
R16
D
10K_5%_2
10K_5%_2
5.11K_1%_2
10K_5%_2
S
2
2
2
2
23
35
0_5%_2
Q3
R74 1
R47 1
R60 1
R59 1
OUT
OUT
OUT
OUT
OUT
OUT
1
TP3
DIODE-BAT54-TAP-PHP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
R
GENERAL PURPOSE I/O
SSM3K7002FU
49
49
49
49
R57
4.7K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2_DY
10K_5%_2
10K_5%_2
10K_5%_2
2
2
2
2
2
2
2
2
NC
R40 1
R58 1
R46 1
R54 1
R49 1
R52 1
R73 1
1
49
49
49
49
49
37
37
49
49
49
GPIO25_TDI
GPIO24_TRSTB
GPUTHERM_INT#
GPU_GPIO2
GPU_GPIO0
GPU_GPIO1
GPIO27_TMS
1
D
IN
IN
IN
IN
IN
IN
OUT
SDA
2
1
P3V3S_DGPU
49
49
49
49
49
49
49
SCL
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
49
1
X01
of
57
8
7
6
5
4
3
2
1
U4
D
AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32
P3V3S_DGPU
R32
2
1
1
10K_5%_2
BI
GPU_THM_CLK 1
GPU_THM_R_CLK
2
GPU_THM_DAT 1
2
GPU_THM_R_DAT 2
2
S
3
3
THM_CLK
BI
THM_DAT
BI
23
23
35
35
Q12
SSM3K7002FU
1
G
R1017
0_5%_2
C
D
S
49
BI
D
49
Q11
SSM3K7002FU
G
R108
0_5%_2
R31
2
1
10K_5%_2
PCIE_VSS#1
GND#1
PCIE_VSS#2
GND#2
PCIE_VSS#3
GND#3
PCIE_VSS#4
GND#4
PCIE_VSS#5
GND#5
PCIE_VSS#6
GND#6
PCIE_VSS#7
GND#7
PCIE_VSS#8
GND#8
PCIE_VSS#9
GND#9
PCIE_VSS#10
GND#10
PCIE_VSS#11
GND#11
PCIE_VSS#12
GND#12
PCIE_VSS#13
GND#13
PCIE_VSS#14
GND#14
PCIE_VSS#15
GND#15
PCIE_VSS#16
GND#16
PCIE_VSS#17
GND#17
PCIE_VSS#18
GND#18
PCIE_VSS#19
GND#19
PCIE_VSS#20
GND#20
PCIE_VSS#21
GND#21
PCIE_VSS#22
GND#22
PCIE_VSS#23
GND#23
PCIE_VSS#24
GND#24
PCIE_VSS#25
GND#25
PCIE_VSS#26
GND#26
PCIE_VSS#27
GND#27
PCIE_VSS#28
GND#28
PCIE_VSS#29
GND#29
PCIE_VSS#30
GND#30
PCIE_VSS#31
GND#31
GND#32
P3V3S_DGPU
GND#33
GND#34
GND#35
M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
R11
T11
1
C77
1
2
3
4
GPU_THERMDA
GPU_THERMDC
2
C5103
1
IN
IN
1000PF_50V_2_DY
49
49
0.1UF_16V_2_DY
2
R56
B
2
1
NA
10K_5%_2_DY
P3V3S_DGPU
U3
VDD
SCL
D+
SDA
D-
ALERT
T_CRIT_A#
GND
8
7
6
5
GPU_THM_R_CLK
GPU_THM_R_DAT
WINB_W83L771AWG_TSSOP_8P_DY
6019B0582601_DY
GND#56
GND#36
NC#5
GND#37
GND#38
NC#6
GND#59
GND#60
GND#61
GND
GND#39
GND#40
GND#41
GND#62
GND#42
GND#63
GND#43
GND#64
GND#44
GND#65
GND#45
GND#66
GND#46
GND#67
GND#47
GND#68
GND#48
GND#49
GND#69
GND#70
GND#50
GND#71
GND#51
GND#72
GND#52
GND#73
GND#53
GND#74
GND#54
GND#75
GND#55
D
A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
C
B
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
VSS_MECH#1
GND#84
VSS_MECH#2
GND#85
VSS_MECH#3
A32
AM1
AM32
GND#86
A
A
AMD_SEYMOUR_XT_S3_FCBGA_631P
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
50
57
of
1
X01
4
3
PCIE_VDDR#6
VDDR1#7
PCIE_VDDR#7
VDDR1#8
PCIE_VDDR#8
PLL
AM30
PCIE_VDDR
L8
NC_MPV18
H7
SPV18
H8
SPV10
J7
SPVSS
L13
C115
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
1
C107
0.1UF_16V_2
2
P1V0S_DGPU
VDDCI#7
2
1
C106
200MA_0603
VDDCI#8
M13
M15
M16
M17
M18
M20
M21
N20
10UF_6.3V_3
1
1UF_6.3V_2
1UF_6.3V_2
C69
2
1
1
C84
2
1UF_6.3V_2
C87
2
1
1
C94
2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C90
2
1
1UF_6.3V_2
C96
2
1
1UF_6.3V_2
C86
2
1
1
2
10UF_6.3V_3
C32
2
1
1
2
C89
1UF_6.3V_2
C92
2
1
1UF_6.3V_2
10UF_6.3V_3
C27
2
1
10UF_6.3V_3
B
PVCORE_DGPU
A
AMD_SEYMOUR_XT_S3_FCBGA_631P
L12
2
200MA_0603
C110
FBM_11_160808_121T
0.1UF_16V_2
2
10UF_6.3V_3
C112
2
1
1
1
100MA
VDDCI#1
VDDCI#2
2
FBM_11_160808_121T
A
ISOLATED
CORE I/O
L11
1
10UF_6.3V_3
50MA
2
P1V8S_DGPU
C93
200MA_0603
0.1UF_16V_2
1
FBM_11_160808_121T
52
14A
R21
U21
1
BIF_VDDC#2
2
10UF_6.3V_3
C79
2
1
1
IN
C
4.7UF_6.3V_3
NC_VSSRHA
BIF_VDDC
1
L16
BIF_VDDC#1
75MA
1
1
NC_VDDRHA
C49
L17
C99
P1V8S_DGPU
VDDC#22
2
40MA
VDDC#20
VDDC#23
MEM CLK
P1V8S_DGPU_VDDR
VDDC#19
VDDC#21
2
0.1UF_16V_2
1UF_6.3V_2
C80
2
1
1
C81
2
B
VDDC#18
NC#4
C31
NC#3
10UF_6.3V_3
VDDC#16
V11
U11
1
VDDC#15
NC#2
C97
VDDC#13
NC#1
2
VDDC#12
VDDR4#3
1UF_6.3V_2
VDDR4#2
AA11
AA12
1UF_6.3V_2
VDDC#11
1UF_6.3V_2
C85
2
1
VDDC#9
VDDR4#1
1
VDDR3#4
2
VDDC#8
2.2UF_6.3V_2
C33
2
1
VDDC#7
1UF_6.3V_2
VDDC#6
VDDR3#3
C91
VDDC#5
VDDR3#2
C100
VDDC#4
VDDR3#1
2
VDDC#2
2
1
C95
2
0.1UF_16V_2
10UF_6.3V_3
1
C30
2
VDDC#1
1UF_6.3V_2
C98
2
1
CORE
VDD_CT#4
POWER
200MA_0603
PVCORE_DGPU
14A
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
M11
M12
1
VDD_CT#3
VDDC#17
FBM_11_160808_121T
2A
VDD_CT#2
VDDC#14
2
D
VDD_CT#1
C88
1
0.1UF_16V_2
2
C61
1UF_6.3V_2
10UF_6.3V_3
C60
2
1
1
C63
2
PCIE_VDDC#11
VDDC#10
L10
6014B0157601
1UF_6.3V_2
C4
2
1
PCIE_VDDC#7
C62
PCIE_VDDC#6
VDDR1#17
2
PCIE_VDDC#5
VDDR1#16
VDDC#3
P1V8S_DGPU
2A_0603
1UF_6.3V_2
C104
2
1
VDDR1#15
1UF_6.3V_2
PCIE_VDDC#4
1UF_6.3V_2
C64
2
1
VDDR1#14
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
1
PCIE_VDDC#3
1UF_6.3V_2
C102
2
1
PCIE_VDDC#2
VDDR1#13
C103
PCIE_VDDC#1
VDDR1#12
I/O
V12
Y12
U12
HCB1608KF_221T20
P1V0S_DGPU
2
VDDR1#11
PCIE_VDDC#12
AA17
AA18
AB17
AB18
440MA
2
VDDR1#10
PCIE_VDDC#9
60MA
L2
VDDR1#9
LEVEL
TRANSLATION
AA20
AA21
AB20
AB21
1
10UF_6.3V_3
PCIE_VDDR#5
VDDR1#6
1UF_6.3V_2
C66
2
1
PCIE_VDDR#4
VDDR1#5
1
P1V8S_DGPU
1UF_6.3V_2
C65
2
1
VDDR1#4
PCIE_VDDC#10
P3V3S_DGPU
1
2
PCIE_VDDR#3
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26
1
PCIE_VDDR#2
VDDR1#3
2
250MA_0603
170MA
C67 0.1UF_16V_2
1
VDDR1#2
PCIE_VDDC#8
L8
MLZ1608M100WT
C
PCIE_VDDR#1
2
219MA
VDDR1#1
2
P1V8S_DGPU_VDDR
2.2UF_6.3V_2
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22
0.1UF_16V_2
C82
2
1
4.7UF_6.3V_3
4.7UF_6.3V_3
C161
2
1
2.2UF_6.3V_2
C138
2
1
1UF_6.3V_2
C158
2
1
1UF_6.3V_2
C157
2
1
C5185
2
1UF_6.3V_2
C76
2
1
1
1UF_6.3V_2
C116
2
1
PCIE
P1V8S_DGPU
1
C105
MEM I/O
1.2A
D
2
U4
P1V5S_DGPU
0.1UF_16V_2
C68
1
5
2
6
0.1UF_16V_2
C83
2
1
7
1UF_6.3V_2
C101
2
1
8
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
51
57
of
1
X01
8
7
6
5
4
3
2
1
U4
DP E/F POWER
P1V8S_DGPU
440MA
P3V3S
27
2
TC7SET08FU_DY
1
PX_MODE
4
PX_EN#
1
14
52 55
DPEF_VDD18#1
DPAB_VDD18#1
DPEF_VDD18#2
DPAB_VDD18#2
300MA
AE11
AF11
P1V0S_DGPU
DPAB_VDD10#1
DPEF_VDD10#2
DPAB_VDD10#2
DP_VSSR#19
DP_VSSR#1
DP_VSSR#20
DP_VSSR#2
DP_VSSR#21
DP_VSSR#3
DP_VSSR#22
DP_VSSR#4
DP_VSSR#23
DP_VSSR#5
220MA
AF6
AF7
AE1
AE3
AG1
AG6
AH5
440MA
AF16
AG17
DPEF_VDD18#3
DPAB_VDD18#3
DPEF_VDD18#4
DPAB_VDD18#4
DPEF_VDD10#3
DPAB_VDD10#3
DPEF_VDD10#4
DPAB_VDD10#4
300MA
AE13
AF13
2
R110
1
P1V0S_DGPU
P1V0S_DGPU
FOR PX5.0
R110 MOUNT
SSM3K7002FU_DY
2
AF22
AG22
240MA
D
P1V8S_DGPU
S
G
DPEF_VDD10#1
P1V8S_DGPU
-
D
PX_EN
IN
OUT
3
49
2
3
Q16
AG14
AH14
AM14
AM16
AM18
0.1UF_16V_2_DY
U10
5
1
DGPU_PWR_EN
IN
1
AG20
AG21
240MA
C56
+
30
2
R109
55
D
P1V8S_DGPU
DP A/B POWER
P1V0S_DGPU
P3V3S
10K_5%_2_DY
BACO MODE
AG15
AG16
220MA
AF8
AF9
0_5%_2
C
1
2
R112
1K_5%_2_DY
R111
1
5
2
P3V3S
1K_5%_2_DY
P5V0S
P5V0S
14
IN
3
4
PX_MODE
OUT
2
Q17
1
52
D
S
D
1
Q18
SSM3K7002FU_DY
G
P1V8S_DGPU
SSM3K7002FU_DY
DP_VSSR#10
DPEF_CALR
DPAB_CALR
AE10
1
DP_VSSR#7
DP_VSSR#26
DP_VSSR#8
R35
AF17
2
2
150_1%_2
DP PLL POWER
AG18
AF19
DPEF_VDD18#5
DP_VSSR#29
DP_VSSR#11
AG19
AF20
DPEF_VDD18#6
DPAB_VDD18#6
DP_VSSR#30
DP_VSSR#12
C
P1V8S_DGPU
300MA
AG8
AG7
DPAB_VDD18#5
AG10
AG11
2
2
DP_VSSR#9
DP_VSSR#28
DP_VSSR#6
DP_VSSR#25
150_1%_2
440MA
G
S
3
1
OUT
DP_VSSR#27
AF10
AG9
AH8
AM6
AM8
DP_VSSR#24
R36
52
3
52
OUT
-
55
14
1.0V_ON
+
35 31
1
VDDC_ON
U12
TC7SET08FU_DY
DGPU_PWROK
AF23
AG23
AM20
AM22
AM24
AMD_SEYMOUR_XT_S3_FCBGA_631P
U4
LVDS CONTROL
P1V0S_DGPU
BIF_VDDC
2
D
BACO MODE
S
IN
DIGON
51
IN
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
PVCORE_DGPU
PMV56XN_DY
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
1.0V_ON
TXOUT_U1N_DPF1N
1
R113
AB11
AB12
B
3
Q19
G
1
52
VARY_BL
DEFULT IS PX5.0
B
2
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AH20
AJ19
AL21
AK20
AH22
AJ21
AL23
AK22
1
2
4.7UF_6.3V_3
D
TXOUT_U3P
TXOUT_U3N
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
S
S
Q20
G
G
TXOUT_L1P_DPE1P
G
TXOUT_L1N_DPE1N
IN
VDDC_ON
AL15
AK14
A
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
52
AK24
AJ23
LVTMDP
D
D
S
A
C109
1
C58
ALPHA_AO3416_SOT23_3P_DY
2
PVCORE_DGPU
4.7UF_6.3V_3
0_5%_2
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
TXOUT_L3P
TXOUT_L3N
AH16
AJ15
AL17
AK16
AH18
AJ17
INVENTEC
AL19
AK18
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
AMD_SEYMOUR_XT_S3_FCBGA_631P
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
52
57
of
1
X01
8
7
6
5
4
3
2
1
U4
GDDR5/DDR3
D
C
1
P1V5S_DGPU
0.1UF_16V_2
12
R69
1
2
P1V5S_DGPU
100_5%_2
C119
2
1
R79
40.2_1%_2
0.1UF_16V_2
40.2_1%_2
100_5%_2
C120
2
1
2
R81
12
R80
B
54
DQA0(0)
DQA0(1)
DQA0(2)
DQA0(3)
DQA0(4)
DQA0(5)
DQA0(6)
DQA0(7)
DQA0(8)
DQA0(9)
DQA0(10)
DQA0(11)
DQA0(12)
DQA0(13)
DQA0(14)
DQA0(15)
DQA0(16)
DQA0(17)
DQA0(18)
DQA0(19)
DQA0(20)
DQA0(21)
DQA0(22)
DQA0(23)
DQA0(24)
DQA0(25)
DQA0(26)
DQA0(27)
DQA0(28)
DQA0(29)
DQA0(30)
DQA0(31)
DQA0(32)
DQA0(33)
DQA0(34)
DQA0(35)
DQA0(36)
DQA0(37)
DQA0(38)
DQA0(39)
DQA0(40)
DQA0(41)
DQA0(42)
DQA0(43)
DQA0(44)
DQA0(45)
DQA0(46)
DQA0(47)
DQA0(48)
DQA0(49)
DQA0(50)
DQA0(51)
DQA0(52)
DQA0(53)
DQA0(54)
DQA0(55)
DQA0(56)
DQA0(57)
DQA0(58)
DQA0(59)
DQA0(60)
DQA0(61)
DQA0(62)
DQA0(63)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
P1V5S_DGPU
VM_RESET
R72
1
MAA0_0/MAA_0
DQA0_1
MAA0_1/MAA_1
DQA0_2
MAA0_2/MAA_2
DQA0_3
MAA0_3/MAA_3
MAA0_5/MAA_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
MAA0_6/MAA0_6
MAA0_7/MAA0_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
DQA0_15
MAA1_7/MAA_BA1
DQA0_17
WCKA0_0/DQMA0_0
DQA0_18
WCKA0B_0/DQMA0_1
DQA0_19
WCKA0_1/DQMA0_2
DQA0_20
WCKA0B_1/DQMA0_3
DQA0_21
WCKA1_0/DQMA1_0
DQA0_22
WCKA1B_0/DQMA1_1
DQA0_23
WCKA1_1/DQMA1_2
DQA0_24
WCKA1B_1/DQMA1_3
DQA0_26
EDCA0_0/QSA0_0
DQA0_27
EDCA0_1/QSA0_1
DQA0_28
EDCA0_2/QSA0_2
DQA0_29
EDCA0_3/QSA0_3
DQA0_30
EDCA1_0/QSA1_0
DQA0_31
EDCA1_1/QSA1_1
DQA1_0
EDCA1_2/QSA1_2
DQA1_1
EDCA1_3/QSA2_3
DQA1_3
DDBIA0_0/QSA0_0B
DQA1_4
DDBIA0_1/QSA0_1B
DQA1_5
DDBIA0_2/QSA0_2B
DQA1_6
DDBIA0_3/QSA0_3B
DQA1_7
DDBIA1_0/QSA1_0B
DQA1_8
DDBIA1_1/QSA1_1B
DQA1_9
DDBIA1_2/QSA1_2B
DQA1_10
DDBIA1_3/QSA1_3B
DQA1_12
ADBIA0/ODTA0
DQA1_13
ADBIA1/ODTA1
DQA1_15
CLKA0
DQA1_16
1
DDR_CLKA1
R84
CLKA0B
DQA1_18
CLKA1
DQA1_19
1
CLKA1B
DQA1_21
RASA0B
DQA1_22
56_5%_2
RASA1B
DQA1_24
CASA0B
DQA1_25
CASA1B
DQA1_27
CSA0B_0
DQA1_28
1
VM_R_ADQSA(0)
VM_R_ADQSA(1)
VM_R_ADQSA(2)
VM_R_ADQSA(3)
VM_R_ADQSA(4)
VM_R_ADQSA(5)
VM_R_ADQSA(6)
VM_R_ADQSA(7)
BI
BI
BI
BI
BI
BI
BI
BI
54
54
54
54
54
54
54
54
H27
A27
C23
C19
C15
E9
C5
H4
VM_R_ADQSA#(0)
VM_R_ADQSA#(1)
VM_R_ADQSA#(2)
VM_R_ADQSA#(3)
VM_R_ADQSA#(4)
VM_R_ADQSA#(5)
VM_R_ADQSA#(6)
VM_R_ADQSA#(7)
BI
BI
BI
BI
BI
BI
BI
BI
54
54
54
54
54
54
54
54
L18
K16
VM_R_ODTA0
VM_R_ODTA1
BI
BI
54
54
H26
H25
DDR_CLKA0
DDR_CLKA0#
OUT
OUT
53
53
54
54
G9
H9
DDR_CLKA1
DDR_CLKA1#
OUT
OUT
53
53
54
54
G22
G17
DDR_RASA0#
DDR_RASA1#
OUT
OUT
54
54
G19
G16
DDR_CASA0#
DDR_CASA1#
OUT
OUT
54
54
CSA0B_1
H22
J22
DDR_CSA0#_0 OUT
54
G13
K13
DDR_CSA1#_0 OUT
54
K20
J17
DDR_CKEA0
DDR_CKEA1
OUT
OUT
54
54
G25
H10
DDR_WEA0#
DDR_WEA1#
OUT
OUT
54
54
G20
G14
MAA13
BI
54
DQA1_29
DQA1_30
CSA1B_0
DQA1_31
CSA1B_1
MVREFDA
CKEA0
MVREFSA
CKEA1
MEM_CALRN0
WEA0B
MEM_CALRP0
WEA1B
CLKTESTA
4.99K_1%_2
H28
C27
A23
E19
E15
D10
D6
G5
DQA1_26
DRAM_RST
R71
54
54
54
54
54
54
54
54
DQA1_23
K8
L7
2
DDR_CLKA1#
5453
OUT 53
BI
BI
BI
BI
BI
BI
BI
BI
DQA1_20
L10
R86
2
VM_R_ADQM#(0)
VM_R_ADQM#(1)
VM_R_ADQM#(2)
VM_R_ADQM#(3)
VM_R_ADQM#(4)
VM_R_ADQM#(5)
VM_R_ADQM#(6)
VM_R_ADQM#(7)
DQA1_17
MAA1_8/RSVD
B
AMD_SEYMOUR_XT_S3_FCBGA_631P
A
54
IN
DDR_CLKA01
R95
2
56_5%_2
56_5%_2
R94
1
2 DDR_CLKA0#
56_5%_2
OUT
53
INVENTEC
54
C144
0.01UF_50V_2
TITLE
MODEL,PROJECT,FUNCTION
2
2
SEYMOUR XT-S3
CHANGE by
7
C
CLKTESTB
C130
0.01UF_50V_2
8
D
GDDR5 / DDR3
1
IN
E32
E30
A21
C21
E13
D12
E3
F4
DQA1_14
240_1%_2
2
J25
2
K25
240_1%_2
2
1
53
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
DQA1_11
1
54
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DQA1_2
1
120PF_50V_2
C108
2
A
MAA0(0)
MAA0(1)
MAA0(2)
MAA0(3)
MAA0(4)
MAA0(5)
MAA0(6)
MAA0(7)
MAA0(8)
MAA0(9)
MAA0(10)
MAA0(11)
MAA0(12)
VM_A_BA2
VM_A_BA0
VM_A_BA1
DQA0_25
MAA0_8/MAA_13
51_5%_2
K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15
DQA0_16
10_5%_2
2
MAA0_4/MAA_4
DQA0_5
R70
2
GDDR5/DDR3
DQA0_0
DQA0_4
K26
J26
R78
1
1
R68
BI
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5
MEMORY INTERFACE
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
53
57
of
1
X01
DQL4
A2
DQL5
A3
DQL6
A4
DQL7
A5
A6
A7
DQU0
A8
DQU1
A9
DQU2
A10_AP
DQU3
A11
DQU4
A12
DQU5
A13
DQU6
A14
DQU7
BA0
VDD#B2
BA1
VDD#D9
BA2
VDD#G7
VDD#K8
VDD#N1
54
54
54
53
53
53
IN
IN
IN
DDR_CLKA0
DDR_CLKA0#
DDR_CKEA0
54
54
54
54
54
53
53
53
53
53
IN
IN
IN
IN
IN
VM_R_ODTA0
DDR_CSA0#_0
DDR_RASA0#
DDR_CASA0#
DDR_WEA0#
K1
L2
J3
K3
L3
53
53
BI
BI
VM_R_ADQSA(2)
VM_R_ADQSA(1)
F3
C7
DQSL
VDDQ#H2
DQSU
VDDQ#H9
53
53
BI
BI
VM_R_ADQM#(2) E7
VM_R_ADQM#(1) D3
DML
VSS#A9
CK
VDD#N9
C_K_
VDD#R1
CKE_CKE0
VDD#R9
ODT_ODT0
VDDQ#A1
C_S__C_S_0_
VDDQ#A8
R_A_S_
VDDQ#C1
C_A_S_
VDDQ#C9
W_E_
VDDQ#D2
VDDQ#E9
VDDQ#F1
VSS#B3
DMU
VSS#E1
VSS#G8
VSS#J2
D_Q_S_L_
VSS#J8
D_Q_S_U_
VSS#M1
VSS#M9
VSS#P1
T2
R_E_S_E_T_
L8
ZQ_ZQ0
VSS#P9
VSS#T1
DQL5
A3
DQL6
A4
DQL7
A5
A6
A7
DQU0
A8
DQU1
A9
DQU2
A10_AP
DQU3
A11
DQU4
A12
DQU5
A13
DQU6
A14
DQU7
M2
N8
M3
BA0
VDD#B2
BA1
VDD#D9
BA2
VDD#G7
VDD#K8
VDD#N1
A1
A8
C1
C9
D2
E9
F1
H2
H9
DDR_CLKA0
DDR_CLKA0#
DDR_CKEA0
J7
K7
K9
IN
IN
IN
IN
IN
VM_R_ODTA0
DDR_CSA0#_0
DDR_RASA0#
DDR_CASA0#
DDR_WEA0#
K1
L2
J3
K3
L3
53
53
BI
BI
VM_R_ADQSA(3) F3
VM_R_ADQSA(0) C7
DQSL
VDDQ#H2
DQSU
VDDQ#H9
53
53
BI
BI
VM_R_ADQM#(3) E7
VM_R_ADQM#(0) D3
DML
VSS#A9
53
53
53
54
54
54
54
54
53
53
53
53
53
CK
VDD#N9
C_K_
VDD#R1
CKE_CKE0
VDD#R9
ODT_ODT0
VDDQ#A1
C_S__C_S_0_
VDDQ#A8
R_A_S_
VDDQ#C1
C_A_S_
VDDQ#C9
W_E_
VDDQ#D2
VDDQ#E9
VDDQ#F1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS#G8
BI
BI
VM_R_ADQSA#(3) G3
VM_R_ADQSA#(0) B7
VSS#M1
VSS#M9
VSS#P1
54
53
VM_RESET
BI
T2
R_E_S_E_T_
L8
ZQ_ZQ0
2
VSSQ#D8
VSSQ#E2
VSS#T1
VSSQ#E8
NC_ODT1
NC_C_S_1_
VSSQ#F9
NC_CE1
VSSQ#G1
NC_ZQ1
VSSQ#G9
B1
B9
D1
D8
E2
E8
F9
G1
G9
R96
243_1%_2
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
J1
L1
J9
L9
IN
IN
IN
VM_A_BA0
VM_A_BA1
VM_A_BA2
A0
DQL3
A1
DQL4
A2
DQL5
A3
DQL6
A4
DQL7
A6
A7
DQU0
A8
DQU1
A9
DQU2
A10_AP
DQU3
A11
DQU4
A12
DQU5
A13
DQU6
A14
DQU7
M2
N8
M3
BA0
VDD#B2
BA1
VDD#D9
BA2
VDD#G7
VDD#K8
J7
K7
K9
IN
IN
IN
IN
IN
VM_R_ODTA1
DDR_CSA1#_0
DDR_RASA1#
DDR_CASA1#
DDR_WEA1#
K1
L2
J3
K3
L3
53
53
BI
BI
VM_R_ADQSA(4)
VM_R_ADQSA(7)
F3
C7
DQSL
VDDQ#H2
DQSU
VDDQ#H9
53
53
BI
BI
VM_R_ADQM#(4) E7
VM_R_ADQM#(7) D3
DML
VSS#A9
54
54
54
54
54
53
53
53
53
53
CK
VDD#N9
C_K_
VDD#R1
CKE_CKE0
VDD#R9
ODT_ODT0
VDDQ#A1
C_S__C_S_0_
VDDQ#A8
R_A_S_
VDDQ#C1
C_A_S_
VDDQ#C9
W_E_
VDDQ#D2
VDDQ#E9
VDDQ#F1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS#B3
DMU
VSS#E1
VSS#G8
BI
BI
53
53
VM_R_ADQSA#(4) G3
VM_R_ADQSA#(7) B7
VSS#J2
D_Q_S_L_
VSS#J8
D_Q_S_U_
VSS#M1
VSS#M9
VSS#P1
54
BI
53
VM_RESET
T2
R_E_S_E_T_
L8
ZQ_ZQ0
BI
BI
BI
BI
BI
BI
BI
BI
P1V5S_DGPU
VDD#N1
A1
A8
C1
C9
D2
E9
F1
H2
H9
D7 DQA0(62)
C3 DQA0(57)
C8 DQA0(63)
C2 DQA0(59)
A7 DQA0(60)
A2 DQA0(61)
B8 DQA0(56)
A3 DQA0(58)
A15_BA3
DDR_CLKA1
DDR_CLKA1#
DDR_CKEA1
53
53
53
53
53
53
53
53
53
53
53
A5
IN
IN
IN
54
54
54
BI
BI
BI
BI
BI
BI
BI
BI
VSS#P9
VSS#T1
VSS#T9
54
2.64A
B2
D9
G7
K2
K8
N1
N9
R1
R9
53
53
53
53
53
53
53
53
54
54
NC_C_S_1_
VSSQ#F9
NC_CE1
VSSQ#G1
NC_ZQ1
VSSQ#G9
R87
243_1%_2
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
J1
L1
J9
L9
VSSQ#E8
NC_ODT1
NC_C_S_1_
VSSQ#F9
NC_CE1
VSSQ#G1
NC_ZQ1
VSSQ#G9
53
54
54
53
53
53
53
53
53
53
53
53
53
53
53
53
53
VREFC_U10
VREFD_U10
M8
H1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MAA0(0)
MAA0(1)
MAA0(2)
MAA0(3)
MAA0(4)
MAA0(5)
MAA0(6)
MAA0(7)
MAA0(8)
MAA0(9)
MAA0(10)
MAA0(11)
MAA0(12)
MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
53
53
IN
IN
IN
SAM_K4W2G1646B_HC12_FBGA_96P
DQL1
VM_A_BA0
VM_A_BA1
VM_A_BA2
DQL3
DQL4
A2
DQL5
A3
DQL6
DQL7
A4
A7
DQU0
A8
DQU1
A9
DQU2
A10_AP
DQU3
A11
DQU4
A12
DQU5
A13
DQU6
A14
M2
N8
M3
DQU7
VDD#B2
VDD#D9
BA2
VDD#G7
VDD#N1
J7
K7
K9
54
54
54
54
54
53
53
53
53
53
IN
IN
IN
IN
IN
VM_R_ODTA1
DDR_CSA1#_0
DDR_RASA1#
DDR_CASA1#
DDR_WEA1#
K1
L2
J3
K3
L3
53
53
BI
BI
VM_R_ADQSA(5)
VM_R_ADQSA(6)
F3
C7
DQSL
VDDQ#H2
DQSU
VDDQ#H9
53
53
BI
BI
VM_R_ADQM#(5)
VM_R_ADQM#(6)
E7
D3
DML
CK
VDD#N9
C_K_
VDD#R1
CKE_CKE0
VDD#R9
ODT_ODT0
VDDQ#A1
C_S__C_S_0_
VDDQ#A8
R_A_S_
VDDQ#C1
C_A_S_
VDDQ#C9
W_E_
VDDQ#D2
VDDQ#E9
VDDQ#F1
VSS#A9
VSS#B3
DMU
VSS#E1
VSS#G8
G3
B7
VSS#J2
D_Q_S_L_
VSS#J8
D_Q_S_U_
VSS#M1
VSS#M9
VSS#P1
54
53
BI
VM_RESET
D7 DQA0(55)
C3 DQA0(48)
C8 DQA0(54)
C2 DQA0(51)
A7 DQA0(52)
A2 DQA0(49)
B8 DQA0(53)
A3 DQA0(50)
BI
BI
BI
BI
BI
BI
BI
BI
53
53
53
53
53
53
53
53
P1V5S_DGPU
BA0
BA1
DDR_CLKA1
DDR_CLKA1#
DDR_CKEA1
VM_R_ADQSA#(5)
VM_R_ADQSA#(6)
53
53
53
53
53
53
53
53
A15_BA3
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
T2
R_E_S_E_T_
L8
ZQ_ZQ0
VSS#P9
VSS#T1
VSS#T9
2.64A
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
E
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
R83
243_1%_2
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
J1
L1
J9
L9
VSSQ#E8
NC_ODT1
NC_C_S_1_
VSSQ#F9
NC_CE1
VSSQ#G1
NC_ZQ1
VSSQ#G9
B1
B9
D1
D8
E2
E8
F9
G1
G9
D
96-BALL
SDRAM DDR3
P1V5S_DGPU
1
2
R88
BI
VREFD_U10
1
1
2
R82
C123
54
C117
2
R85
VREFC_U10
1
BI
2
54
0.1UF_16V_2
2
R76
1
2
VREFD_U9
R75
BI
1
54
4.99K_1%_2 4.99K_1%_2
VREFC_U9
1
2
R97
1
BI
C113
C133
54
1
VREFD_U8
C149
1
R91
BI
1
54
2
1
2
1
2
4.99K_1%_2 4.99K_1%_2
R105
R104
1
VREFC_U8
C159
BI
2
54
P1V5S_DGPU
P1V5S_DGPU
1
P1V5S_DGPU
2
P1V5S_DGPU
0.1UF_16V_2
1
R92
2
R93
2
C143
2
1
VREFD_U7
4.99K_1%_2 4.99K_1%_2
BI
1
54
F
A6
53
53
53
53
53
E3 DQA0(41)
F7 DQA0(47)
F2 DQA0(45)
F8 DQA0(46)
H3 DQA0(44)
H8 DQA0(43)
G2DQA0(40)
H7 DQA0(42)
A5
54
54
54
B1
B9
D1
D8
E2
E8
F9
G1
G9
SAM_K4W2G1646B_HC12_FBGA_96P
DQL0
VREFDQ
A1
VDD#K8
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
96-BALL
SDRAM DDR3
VREFCA
A0
VDD#K2
A1
A8
C1
C9
D2
E9
F1
H2
H9
96-BALL
SDRAM DDR3
U5
BI
BI
DQL2
54
54
54
54
54
54
54
54
54
54
54
54
54
54
4.99K_1%_2 4.99K_1%_2
P1V5S_DGPU
0.1UF_16V_2
1
2
1
2
4.99K_1%_2 4.99K_1%_2
R101
R100
C
P1V5S_DGPU
0.1UF_16V_2
0.1UF_16V_2
C147
2
1
0.1UF_16V_2
C127
2
1
0.1UF_16V_2
C146
2
1
0.1UF_16V_2
C44
2
1
0.1UF_16V_2
C38
2
1
0.1UF_16V_2
C125
2
1
2.2UF_6.3V_2
C124
2
1
1
C131
2
10UF_6.3V_3
C128
2
1
0.1UF_16V_2
0.1UF_16V_2
C136
2
1
0.1UF_16V_2
C148
2
1
0.1UF_16V_2
C121
2
1
0.1UF_16V_2
C39
2
1
0.1UF_16V_2
C48
2
1
0.1UF_16V_2
C129
2
1
2.2UF_6.3V_2
C132
2
1
1
C122
2
10UF_6.3V_3
C150
2
1
0.1UF_16V_2
C70
2
1
0.1UF_16V_2
C145
2
1
P1V5S_DGPU
2.2UF_6.3V_2
C135
2
1
1
C118
2
0.1UF_16V_2
0.1UF_16V_2
C160
2
1
0.1UF_16V_2
C134
2
1
0.1UF_16V_2
C154
2
1
0.1UF_16V_2
C75
2
1
0.1UF_16V_2
C73
2
1
0.1UF_16V_2
C152
2
1
10UF_6.3V_3
C140
2
1
1
C155
0.1UF_16V_2
2
1
2
1
53
53
53
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VDD#K2
P1V5S_DGPU
2.2UF_6.3V_2
C153
2
1
C142
54
54
54
MAA0(0)
MAA0(1)
MAA0(2)
MAA0(3)
MAA0(4)
MAA0(5)
MAA0(6)
MAA0(7)
MAA0(8)
MAA0(9)
MAA0(10)
MAA0(11)
MAA0(12)
MAA13
E3 DQA0(38)
F7 DQA0(33)
F2 DQA0(39)
F8 DQA0(35)
H3 DQA0(37)
H8 DQA0(32)
G2DQA0(34)
H7 DQA0(36)
P1V5S_DGPU
P1V5S_DGPU
C141
DQL0
DQL1
SAM_K4W2G1646B_HC12_FBGA_96P
SAM_K4W2G1646B_HC12_FBGA_96P
P1V5S_DGPU
VREFC_U7
VSSQ#E8
NC_ODT1
96-BALL
SDRAM DDR3
2
VSS#T9
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
53
53
53
53
53
53
53
53
53
53
53
53
53
53
54
54
54
54
54
54
54
54
54
54
54
54
54
54
2
J1
L1
J9
L9
D
10UF_6.3V_3
VSS#P9
VREFCA
VREFDQ
DQL2
2.64A
B2
D9
G7
K2
K8
N1
N9
R1
R9
M8
H1
2
VSSQ#B9
C
VSS#J8
D_Q_S_U_
53
53
53
53
53
53
53
53
U6
VREFC_U9
VREFD_U9
1
VSSQ#B1
VSSQ#D1
BI
VSS#J2
D_Q_S_L_
2
R99
243_1%_2
54
VSS#B3
DMU
VSS#E1
53
53
BI
BI
BI
BI
BI
BI
BI
BI
P1V5S_DGPU
IN
IN
IN
54
54
54
D7 DQA0(3)
C3 DQA0(5)
C8 DQA0(2)
C2 DQA0(0)
A7 DQA0(4)
A2 DQA0(1)
B8 DQA0(6)
A3 DQA0(7)
A15_BA3
VDD#K2
1
VSS#T9
DQL4
A2
BI
BI
54
54
2
VM_RESET
A1
2
BI
DQL3
1
53
IN
IN
IN
VM_A_BA0
VM_A_BA1
VM_A_BA2
A0
R90
54
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
53
53
53
53
53
53
53
53
0.1UF_16V_2
VM_R_ADQSA#(2) G3
VM_R_ADQSA#(1) B7
53
53
53
MAA0(0)
MAA0(1)
MAA0(2)
MAA0(3)
MAA0(4)
MAA0(5)
MAA0(6)
MAA0(7)
MAA0(8)
MAA0(9)
MAA0(10)
MAA0(11)
MAA0(12)
MAA13
2
BI
BI
54
54
54
53
53
53
53
53
53
53
53
53
53
53
53
53
53
BI
BI
BI
BI
BI
BI
BI
BI
4.99K_1%_2 4.99K_1%_2
53
53
2.64A
B2
D9
G7
K2
K8
N1
N9
R1
R9
54
54
54
54
54
54
54
54
54
54
54
54
54
54
E3 DQA0(30)
F7 DQA0(24)
F2 DQA0(27)
F8 DQA0(26)
H3 DQA0(28)
H8 DQA0(25)
G2DQA0(31)
H7 DQA0(29)
2
J7
K7
K9
53
53
53
53
53
53
53
53
DQL2
R98
M2
N8
M3
BI
BI
BI
BI
BI
BI
BI
BI
P1V5S_DGPU
A15_BA3
VDD#K2
E
D7 DQA0(15)
C3 DQA0(9)
C8 DQA0(13)
C2 DQA0(11)
A7 DQA0(12)
A2 DQA0(8)
B8 DQA0(14)
A3 DQA0(10)
DQL0
DQL1
1
A1
VREFCA
VREFDQ
R89
DQL3
M8
H1
1
VM_A_BA0
VM_A_BA1
VM_A_BA2
A0
U8
VREFC_U8
VREFD_U8
4.99K_1%_2 4.99K_1%_2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
BI
BI
0.1UF_16V_2
IN
IN
IN
MAA0(0)
MAA0(1)
MAA0(2)
MAA0(3)
MAA0(4)
MAA0(5)
MAA0(6)
MAA0(7)
MAA0(8)
MAA0(9)
MAA0(10)
MAA0(11)
MAA0(12)
MAA13
54
54
0.1UF_16V_2
53
53
53
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
53
53
53
53
53
53
53
53
0.1UF_16V_2
C151
2
1
54
54
54
53
53
53
53
53
53
53
53
53
53
53
53
53
53
BI
BI
BI
BI
BI
BI
BI
BI
0.1UF_16V_2
C139
2
1
F
54
54
54
54
54
54
54
54
54
54
54
54
54
54
E3 DQA0(16)
F7 DQA0(17)
F2 DQA0(22)
F8 DQA0(19)
H3 DQA0(20)
H8 DQA0(21)
G2DQA0(18)
H7 DQA0(23)
2
DQL2
1
4.99K_1%_2 4.99K_1%_2
DQL1
2
0.1UF_16V_2
DQL0
VREFDQ
3
1
VREFCA
0.1UF_16V_2
M8
H1
4
1
U7
VREFC_U7
VREFD_U7
5
0.1UF_16V_2
C137
2
1
BI
BI
6
0.1UF_16V_2
C71
2
1
54
54
7
2
8
B
B
HYNIX 1GB D-DIE
PN : 6019B0938301
SAMSUNG 1GB C-DIE PN : 6019B0818601
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
VRAM DDR3
CHANGE by
8
7
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
54
1
X01
of
57
6
5
GPU 1.05V
4
3
P3V3S_DGPU
2
30
IN
DGPU_PWR_EN#
R22
1
R28
G
2
1
10K_5%_2
R27
1
D
3
D
55
60MA
3
1
2
1K_5%_2
1
G
Q9
S
1
0_5%_2
2200pF_50V_2
2
2
2
1
2
0.1UF_16V_2
2
R301
C301
1
2
2.2UF_6.3V_2_DY
1
2
2.2UF_6.3V_2_DY
C303
1
2
2.2UF_6.3V_2_DY
C304
1
2.2UF_6.3V_2_DY
C305
C306
2
GPU_P15V0A_RC 1
FDC655BN
6015B0032701
Q10
AM2321P
C28
3
G
NMOS_4D1S
6.3A/30V
P3V3S
4
S
1
D
D
10uF_6.3V_3
1
2
5
6
200_5%_2
Q301
VRP1V05S_VCCP
IN
C302
9
1
GPU 3.3V
P1V0S_DGPU
3.4A
12
2
S
7
D
8
SSM3K7002FU 2
C
C
DEFULT IS PX5.0
P3V3A
3.1A
Q14
R11
30
27
IN
DGPU_PWR_EN
1
D
R20
2
Q13
SSM3K7002FU_DY
1
S
G
8A/30V
C74
PX_MODE 1
AON7410
2
IN
0.01UF_50V_2_DY
14 52
C51
1
2
0_5%_2_DY
G
2
Q6
SSM3K7002FU
S
52
FDC655BN
6.3A/30V
C72
1
SSM3K7002FU
2
S
G
2
1
C13
D
2
0_5%_2_DY
3
DGPU_PWR_EN# 1
D
IN
0.01UF_50V_2
3
2
30
Q5
1
G
NMOS_4D3S
NMOS_4D1S
R128
1
2
G
2
2
3
R18
3
2
1
100K_5%_2_DY
D
100K_5%_2
1
1
2
5
6
S
GPU_P15V0A_RC
D
B
6015B0097401-001
Q15
1
8
S
D
2
7
3
6
4
5
G
2
R12
S
2.2UF_6.3V_2
2
1
4
R124
0_5%_2
P1V5
1.2A
SSM3K7002FU_DY
Q4
560K_1%_2
MONUT R128
DEL R12 , Q6
P1V5S_DGPU
1
B
3 2
1
R19
P1V8S
P1V8S_DGPU
560K_1%_2_DY
1
P15V0A
P3V3A
55
GPU 1.5V
P15V0A
BACO MODE
2.2UF_6.3V_2
GPU 1.8V
GPU_P15V0A_RC
A
1
R102
2
A
0_5%_2
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
DGPU POWER EE
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
55
57
of
1
X01
8
7
6
5
4
3
2
1
OCP=19AMP
PVCORE_DGPU
PAD6750
2
2
1
1
IN
56
VRPVCORE_DGPU
POWERPAD_2_0610
P5V0A
PVBAT
R6755
240K_5%_2
D
11
VRPVCORE_DGPU_PH
LGATE
8
G0
7
FB
3
G1
14
5
1
2
D0
6
1
2
VOUT
1
R6754
16.2K_1%_2
1
1
C6762
CSC0805_DY
2
2
2
+
1
1
R6750
2K_1%_2
2
1
R7675
RSC_0603_DY
2
REA_RT8208BGQW_WQFN_16P
OUT
56
C6750
560UF_2.5V
2
D1
GND
VRPVCORE_DGPU
2
4
C
2
EN_DEM
4
1
15
17
2
9.76K_1%_2
R6751
EN_DGPU
R6753
7.68K_1%_2
49
1
3
1
2
3
4
IN
IN
S
14
POW_SW1
49
1
1
POW_SW0 IN
G
R6758
9.53K_1%_2
Q6751
PGOOD
CS
1
3
CYN_PCMB063T_R68MS_4P
C7675
CSC0402_DY
VRPVCORE_DGPU_LG
D
4
10
VDD
FDMS0308AS
DGPU_PG
C
OCP=19A
L6750 CHOKE_4PIN_2PIN
2
1
C6757
1UF_6.3V_2
2
1
2
C6754
1UF_6.3V_2
PHASE
Q6750
VRPVCORE_DGPU_HG
8
7
6
5
OUT
12
1
2
3
4
2
14
UGATE
S
VDDP
C6753
0.1UF_16V_2
1
2
13
D
9
R6752
2.2_5%_3
1
2
BOOT
G
TON
NMOS_4D3S
U6750
16
FDMC7696
2
R6756
10_5%_2
2
8
7
6
5
1
C6761
10UF_25V_5
2
1
1
C6760
4.7UF_25V_5_DY
D
B
B
P.S. R6750(R1)R6751(R2)R6753(R3)R6754(R4)
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
DGPU POWER
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
56
57
of
1
X01
USB_P9_UB_DN
11
11
12
12
USB_P1_UB_DN 1
USB_P1_UB_DP 4
C9103
2
SCREW230_600_1P
L9100
2
3
CN9101
1
2
3
4
USB_P1_UB_L_DN
USB_P1_UB_L_DP
DGND_USB
2
2
IO
1
G1
2
G2
3
G3
4
G4
GND
G1
G2
G3
G4
57
OUT
2
3
3
IO
2
2
2
2
2
2
D9100
57
IN
PWR_LED#_PBN 1
R9200
2 1
57
1
2
3
4
1
G1
2
G2
3
G3
4
G4
G1
G2
G3
G4
57
57
OCTEK_USB_04WREB_4P
6012B0397201
3
1
TP_DAT_TPB
2
2
TP_CLK_TPB
3
3
4
4
BI
BI
TP_SMBUS_DAT_TPB
5
5
TP_SMBUS_CLK_TPB
6
6
1
SW9000
57
OUT
L_KEY_TPB 1
2
3
1
4
2
5
3
6
DIP_TMG_533_Q_T_R_6P
DGND_TP
DGND_TP
S9001
DGND_USB
GND
Vcc
4
SW9000,SW9001
★PIN2,5 IS GND
TO T/P MODULE
4
57
IN
L_KEY_TPB
1
PAD9001
57
IN
R_KEY_TPB
2
2
3
3
BI
TP_CLK_TPB
4
4
57
BI
TP_DAT_TPB
5
5
P3V3A_TP
6
6
57
BI
TP_SMBUS_DAT_TPB
7
7
57
BI
TP_SMBUS_CLK_TPB
8
8
DGND_TP
1
SW9001
57
OUT
R_KEY_TPB 1
2
3
1
4
2
5
3
6
R KEY
4
5
6
DIP_TMG_533_Q_T_R_6P
57
A
DGND_TP
1 FIX9001
SMDPAD8_100_28X118
FIX9101
FIX9102
FIX9103
1 FIX9200
1 FIX9201
1 FIX9202
1 FIX9203
6026B0001201
1 FIX9002
1 FIX9004
A
FIX_MASKFIX_MASKFIX_MASK
1 FIX9003 1 FIX9005
FIX_MASKFIX_MASK
TP SMB(I2C) ADDRESS IS 0X2C
FIX9100
B
6026B0001201
SCREW230_600_1P
PHP_PRTR5V0U2X_SOT143_4P_DY
L KEY
4
5
6
SMDPAD6_100_28X118
S9000
SCREW230_600_1P
1
P/N：6050A2493601
P5V0A_USB2
1
C
TOUCHPAD R / L BOARD
PAD9000
1
BI
BI
DGND_USB
1
2
19_217_W1D_AP1Q2QY_3T
6011B0028601
TO MB
CN9102
WCM_2012_900TU9102
2
IO
3
P5V0A_USB2
USB 2.0 CONN 2
1
USB_P9_UB_L_DN
USB_P9_UB_L_DP
2
4
3
P3V3A_TP
22uF_6.3V_5
L9101
4
1
DGND_PBN
DGND_TP
DGND_TP
C9104
2
1
6026B0052301
DGND_USB
2
EC_PWRBTN#_PBN2
4
Vcc 4
POWER LED
TEMIC_NTC033_XJ1J_X160T_4P
PHP_PRTR5V0U2X_SOT143_4P_DY
DGND_USB
USB_P9_UB_DN 1
USB_P9_UB_DP 4
P3V3A_PBN
SCREW230_600_1P
100_5%_2
57
BI
BI
DGND_PBN
OCTEK_USB_04WREB_4P
6012B0397201
3
3
IO
1
DGND_USB
1
DGND_PBN
SW9200
P5V0A_USB2
57
57
DGND_PBN
S9200
1
POWER BUTTON
USB 2.0 CONN 1
1
22uF_6.3V_5
WCM_2012_900TU9101
B
S9201
DGND_PBN
1
DGND_PBN
1
P5V0A_USB2
SCREW280_800_1P
BI
BI
DGND_USB
DGND_USB
C
57
57
MAG_MH248BESO_SOT23_3P
6019B0602501
SMDPAD12_100_28X118
SCREW280_800_1P
1
2
DGND_USB
OUT
D
100_5%_2
BI
3
GND
2
2 R9201
10
57
VDD
DGND_TP
10
U9200
SMDPAD6_100_28X118
DGND_TP
USB_P9_UB_DP
6019B0789501
1
OUT LID_SW#_PBN
57
6
1
9
BI
OC#
5
6
LITEON_L13ESD5V0CA2_SOD523_2P_Y
9
57
OUT
GMT_G547E1P81U_MSOP_8P
4
5
D9203
8
IN
EN
8
7
6
5
4
LID_SW#_PBN
1
8
USBPWR_EN_UB
OUT
EC_PWRBTN#_PBN
D9202
USB_P1_UB_DN
IN
OUT
IN
3
1
BI
57
GND
3
1
7
1
2
3
4
1uF_6.3V_2
C9200
0.1uF_16V_2
2
1
2
PWR_LED#_PBN
LITEON_L13ESD5V0CA2_SOD523_2P_Y
7
U9100
P3V3A_PBN
OUT
OUT
IN
1
2
D9201
6
1
57
1
1
5
6
C9101
2
P5V0A_USB2
DGND_PBN
5
P5V0A_DB
1
4
+
4
C9102
3
330uF_6.3V
3
57
LID SW
DGND_USB
DGND_USB
DGND_USB
2
57
S9100
PAD9200
DGND_PBN
2
1
USB_P1_UB_DP
S9101
1
P3V3A_PBN
57
DGND_PBN
C9100
22UF_6.3V_5
USBPWR_EN_UB
1
2
1
BI
57
3
PAD4
DGND_USB
DGND_USB
1
D
IN
4
P/N：6050A2493201
P5V0A_DB
DGND_USB
P/N：6050A2493701
2
5
POWER BUTTON BOARD
USB BOARD
57
6
1
7
LITEON_L13ESD5V0CA2_SOD523_2P_Y
8
1
1
1
1
for Dauther Board FIX_MASK
FIX_MASK FIX_MASK FIX_MASK
INVENTEC
FIX_MASK FIX_MASK FIX_MASK FIX_MASK
TITLE
MODEL,PROJECT,FUNCTION
USB,
CHANGE by
8
7
6
5
4
XXX
3
DATE
21-OCT-2002
2
SIZE
CODE
A3
CS
POWER BUTTON DB
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
57
57
of
1
X01
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