CO557:
Computer Systems
Mark Batty
http://cs.kent.ac.uk/~mjb211
M.J.Batty@kent.ac.uk
David Barnes
http://cs.kent.ac.uk/~djb
D.J.Barnes@kent.ac.uk
What is this module about?
Photo: by Cemx86 (John DeRosa) at English Wikipedia
by Cemx86 (John DeRosa) at English Wikipedia, CC BY-SA 3.0.
It’s about how computers
work!
Essential for any “computer
scientist”
... not because you “need to
know” details
but for
●
conceptual understanding
●
“ways of thinking”
This could be
your phone,
tablet, laptop,
...
all similar!
What is this module about?
In practice, the content is split into:
•
“computer architecture”
—
•
Photo: via
Garrett Fogerlie
on the electronics St
ack Exchange
how the core hardware works
(logically, not physically)
“systems software”
—
how the core software works
(principles, not trivia)
●
programming languages
●
operating system
Photo by Pauli Rautakorpi
The book
The Elements of Computing Systems
by Noam Nisan and
Shimon Schocken
… is the core book for this module.
E-book available via the library (also
linked from Moodle).
You must read this book!
“from Nand to Tetris”
Another suggested book
●
J. Clark Scott. “But how do it know?” –
the basic principles of computers for
everyone. John C Scott publishing, 2009
●
physical copies in the library
●
… no e-book access at the moment :-(
Worth a go if you’re struggling with the
overall picture. Most of you probably will
be fine without it.
•
Module structure
●
Weeks 1–7: computer architecture (Mark)
●
Weeks 7–12: systems software (David)
Module mark is 50% coursework, 50% exam
Coursework is in four near-equal
assessments (each 12–14% of module)
●
●
One assessment ≈ three “projects”/chapters
Based on, but not identical to, the book’s
projects
●
Briefs will appear on Moodle, starting in
week 2
How computers really work...
●
Computers work by doing tiny, incredibly simple
things...
●
in terms of 1s and 0s (true/false, high/low/ ...)
●
… and doing them mind-bogglingly quickly!
●
●
Mind-bogglingly many insanely simple operations
combine to create an “illusion”...
Abstractions are how we build up many tiny
operations into larger, more meaningful ones
“from Nand to Tetris”
NAND
We’re going on a journey…
●
To build a working computer from the ground up!
●
Starting from the very simple (a single logic gate, Nand)
●
… through several abstraction layers
Hardware layers
- combinational logic
- sequential logic
- the fetch/execute cycle
Software layers
- machine code
- assembly language
- a stack-based virtual machine
- a high-level language and simple operating system
NAND
Our journey will be “bottom-up”...
NAND
… so let’s take a few minutes to survey from the top down.
●
If we look at real computer hardware or software,
●
… and break it down into smaller and smaller pieces,
●
… what do we find? (See the next lecture chunk!)
Our journey will be “bottom-up”…
NAND
(from Nand to Tetris!)
… so let’s take a few minutes to survey from the top down.
●
If we look at real computer hardware or software,
●
… and break it down into smaller and smaller pieces,
●
… what do we find?
Open up any modern computer and you find
some kind of circuit board with various
funny-looking stuff on...
Photo by Jonathan Zander, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=4994025
Most of it is not very interesting to us!
We’re looking almost entirely at what’s
inside this tiny, tiny chip
Photo by Jonathan Zander, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=4994025
Abstractly, most computers from the last
50+ years look like….
Processor
memory
memory bus
(wires)
input/output
controller(s)
I/O bus (more
wires)
(many I/O devices
possible; examples...)
display
device
I/O bus (more
wires)
network
interface
disk
controller
keyboard,
mouse etc audio device
printer
Photo by Jonathan Zander, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=4994025
Abstractions, layers...
●
The block diagram we just saw is an abstraction of a computer
●
Abstraction is one of the biggest ideas in computer science.
●
It means: leave some stuff out! Simplify!
●
We can’t understand everything at once.
●
Sometimes we zoom in
●
Sometimes we ignore detail
●
●
We sometimes talk about “abstractions” as things – roughly “points of
view”
Complex systems are built by working at multiple levels of abstraction,
often organised one atop another, in layers
Biggest component: the
processor (CPU)
ARM Cortex A57
block diagram

first high-performance
ARMv8-A processor

used in Qualcomm’s
Snapdragon 810 64bit processor

Samsung Galaxy S6
phone
images.anandtech.com/doci/8718/Hiroshige.Goto.png
Zoom in on one part: the ALU
(arithmetic logic unit)
The smallest arithmetic
block
A
B
Sum
Half adder
Carry
Logic gates
A
B
A and B both 1?
AND gate
XOR gate
A
B
Sum
Carry
●
False = 0, True = 1
From digital to analogue
Volts
●
High voltage, low voltage
●
“logic 1” (true), “logic 0” (false)
●
Binary digit 1, binary digit 0
●
...
“Our obedient servant”:
the fetch-execute cycle
Our hardware is an electrical circuit
that repeats forever:
Fetch
• Fetch the next instruction in the
program
●
Instructions represent simple
operations doable very quickly
• Execute it, i.e. do it!
●
e.g. “add the two numbers
stored in locations 20 and 21, and
put the result in location 22”
●
e.g. “test whether location 24 holds
a value greater than 0; if so, jump
to...”
Execute
High-level languages
●
●
Most programs are written
in these, e.g. Java,
JavaScript, C++, Python,…
Processors execute
machine code
source
code
variables
Translator
→ we need some kind of
“translator”
●
●
interpreter
or compiler
Variables become memory
locations, etc
machine
code
memory
Javascript →
instructions
Calculate first 8 steps of the Fibonacci series: 0 1 1 2 3 5 8 13 …
Each number is the sum of the previous two numbers
Intel/AMD64 (x86-64) instructions
JavaScript
a = 0;
b = 1;
for (c = 0; c < 8; c++) {
d = a + b;
a = b;
b = d;
}
MOV RAX, 0
MOV RBX, 1
MOV RCX, 0
LOOP:
MOV RDX, RBX
ADD RDX, RAX
MOV RAX, RBX
MOV RBX, RDX
INC RCX
CMP RCX, 8
JL LOOP
What an operating system does
●
A program that deals with other programs:
●
load them into memory
●
run them (+ maybe pause, resume, stop….)
●
share Input/Output devices between them
●
... potentially many users, many programs
●
●
this is how your computer appears to be doing
more than one thing at a time!
Programs are data in memory! So we can write
programs to read/write/change them!
The operating system: a program for
running programs
●
Before operating systems: human operators
Photo: still from the 1951 EDSAC film,
University of Cambridge Computer Laboratory
Recommended viewing:
Feynman on computers
https://www.youtube.com/embed/EKWGGDXe5MA
Prior knowledge you’ll need
The book, and this module, both assume
some prior knowledge.
All of this was covered in the Foundations
modules from stage 1.
•
representing numbers
•
… including different bases (e.g. binary)
•
•
•
•
computer arithmetic, including two’s
complement (signed arithmetic)
propositional logic
sets, proofs (we will say things like
“theorem” or “is an element of”)
notations like f(x, y)
Prior knowledge you’ll need
I will recap the trickier topics among
these, briefly, near the point of use.
But only briefly! It’s not a substitute for
prior learning.
If you’re feeling rusty, please go back and
revisit these parts of Foundations I and II.
(They’re called Foundations for a
reason :-)
How to read the book
The book is slim, because it is dense.
Every sentence counts!
For example, on p11:
“A gate is a physical device that
implements a Boolean function.”
You already knew what a Boolean
function is. (Right?)
Now it’s telling you what a gate is.
After that, it’s constantly talking about
gates.
Read carefully; don’t skim.
Decimal numbers
What number does the decimal numeral 943
represent? We can work it out as follows.
●
10s
1s
9
4
3
9 hundreds
+ 4 tens
+3 units
9x 102
+ 4 x 101
+ 3 x 100
A digit’s significance depends on its position
●
●
100s
significance goes in powers of 10
More systematic than Roman numerals, and more
space-efficient than tally marks
Recap of powers
What are the powers of ten?
●
“x to the power n” just means “multiply together n
copies of x”... written as xn
●
e.g. ten to the power 2 is a hundred
●
ten to the power 3 is a thousand
●
You get the idea….
●
Non-obvious case: 100 is 1 (not 0)
●
Why? 1 is the “do nothing” of multiplication
Powers and bases
I wrote “hundred”, “thousand” etc, but maybe I could
have written 100, 1000, etc.
but that assumes decimal (base=10) notation!
1
0
0
1 hundred
+ 0 tens
+0 units
1x b2
+ 0 x b1
+ 0 x b0
In base 8, for example, “100” means sixty-four
1
0
0
1 sixty-four
+ 0 eights
+0 units
1x b2
+ 0 x b1
+ 0 x b0
How many oranges?
There are twelve. We could write that as
12
14
1100
C
(decimal, i.e. base ten)
(octal, i.e. base eight)
(binary, i.e. base two)
(hexadecimal, i.e. base sixteen)
We like base 2, because it makes it easy to turn
numbers into logic (Booleans)
Boolean functions
“Function”: a thing that takes some input(s)
and gives an output
– the same input always gives the same output
“Boolean”: taking only the value true or false
A
B
F(A,B)
f
f
t
What is F?
f
t
t
t
f
t
t
t
f
Boolean algebra
If a function has 10 inputs, how big is its truth table?
Symbolic logic is a more scalable way to reason..
A ∧ ¬A ≡ f
A ∨ ¬A ≡ t
¬¬A ≡ A
A∧B≡B∧A
A ∧ (B ∨ C) ≡ (A ∧ B) ∨ (A ∧ C)
A∧A≡A
….
Remember:
¬ means NOT
∧ means AND
∨ means OR
George Boole (1815--64)
invented a way of writing logic
using symbolic formulae
with rules for manipulating them –
this is called Boolean algebra
Some slightly less obvious rules:
De Morgan’s laws
¬(A ∨ B)
≡
(¬ A) ∧ (¬ B)
(¬ A) ∨ (¬ B)
≡
¬(A ∧ B)
Augustus De Morgan (1806--71)
was another mathematician
influenced by Boole
Some slightly less obvious rules:
De Morgan’s laws
A∨B
≡
A∧B
A∨B
≡
A∧B
Augustus De Morgan (1806--71)
was another mathematician
influenced by Boole
More compact
notation:
use over-bar
for NOT
instead of ¬
”You can break or join the bar
if you flip the sign underneath”
End of recap
It’s fine if you’re rusty on some of these topics.
...but they should be ringing bells!
Please do revisit your Foundations material if
you need to.
Lecture 2
Boolean Basics
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Values
F
T
N
Y
0
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Operations
xAnd y
xOr y
⇤
⌅⇧
Not(x)
¬
x
y
And
x
y
Or
x
Not
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
1
And
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Expressions
Not(0 Or (1 And 1)) =
Not(0 Or 1) =
Not(1) =
0
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Functions
f(x, y, z) = (xAnd y) Or (Not(x) And z)
x
y
z
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
f
1
(0 And 0) Or (Not(0) And 1) =
0 Or (1 And 1) =
0 Or 1 = 1
f
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Functions
f(x, y, z) = (xAnd y) Or (Not(x) And z)
x
y
z
f
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
formula
truth table
f
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Identities
• (xAnd y) = (yAnd x)
• (xOr y) = (yOr x)
commutave
laws
• (xAnd (yAnd z)) = ((xAnd y) And z)
associave
laws
• (xOr (y Or z)) = ((x Or y) Or z)
• (xAnd (y Or z)) = (xAnd y) Or (xAnd z)
• (xOr (yAnd z)) = (xOr y) And (x Or z)
• Not(xAnd y) = Not(x) Or Not(y)
• Not(xOr y) = Not(x) And Not(y)
distribuve
laws
De Morgan
laws
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Algebra
De Morgan law
Not(Not(x) And Not(xOr y)) =
Not(Not(x) And (Not(x) And Not(y))) =
associative law
Not((Not(x) And Not(x)) And Not(y)) =
Not(Not(x) And Not(y)) =
Not(Not(x)) Or Not(Not(y)) =
idempotence
De Morgan law
double negation
xOr y
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean Algebra
Not(Not(x) And Not(xOr y)) =
x
y
Or
0
0
0
0
1
1
1
0
1
1
1
1
xOr y
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean expression → truth table
f(x, y, z) = (xAnd y) Or (Not(x) And z)
x
y
z
f
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Boolean expression ← truth table
f(x, y, z) = (xAnd y) Or (Not(x) And z)
?
x
y
z
f
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
From truth table to a Boolean expression
x
y
z
f
0
0
0
1
1
0
0
1
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
0
(Not(x)
And Not(y)
And Not(z))
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
From truth table to a Boolean expression
x
y
z
f
0
0
0
1
0
0
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
0
(Not(x)
And y
And Not(z))
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
From truth table to a Boolean expression
x
y
z
f
0
0
0
1
0
0
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
0
0
1
1
1
0
0
(x
And Not(y)
And Not(z))
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
From truth table to a Boolean expression
x
y
z
f
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
0
1
(Not(x)
And Not(y)
And Not(z))
1
(Not(x)
And y
And Not(z))
And Not(y)
And Not(z))
1
(x
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
From truth table to a Boolean expression
x
y
z
f
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
0
(Not(x)
And Not(y)
(Not(x)
(x
And Not(z)) Or
And y
And Not(z))
And Not(y)
And Not(z))
Or
(Not(x) And Not(y) And Not(z)) Or
(Not(x) And yAnd Not(z)) Or
(xAnd Not(y) And Not(z)) =
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
From truth table to a Boolean expression
x
y
z
f
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
0
(Not(x)
And Not(y)
(Not(x)
(x
And Not(z)) Or
And y
And Not(z))
And Not(y)
And Not(z))
Or
(Not(x) And Not(y) And Not(z)) Or
(Not(x) And yAnd Not(z)) Or
(xAnd Not(y) And Not(z)) =
(Not(x) And Not(z)) Or (xAnd Not(y) And Not(z)) =
(Not(x) And Not(z)) Or (Not(y) And Not(z)) =
Not(z) And (Not(x) Or Not(y))
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Theorem
Lemma: Any Boolean function can be represented using an expression containing
And, Or And Not operations.
Proof:
Use the truth table to Boolean expression method
Lemma: Any Boolean function can be represented using an expression containing
And and Not operations.
Proof:
(x Or y) = Not(Not(x) And Not(y))
Can we do better than this?
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Nand
x
y
Nand
0
0
1
0
1
1
1
0
1
1
1
0
(x Nand y) = Not(xAnd y)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Theorem (revisited)
Lemma: Any Boolean function can be represented using an expression containing
And, Or And Not operations.
Proof:
Use the truth table to Boolean expression method
Lemma: Any Boolean function can be represented using an expression containing
And and Not operations.
Proof:
(x Or y) = Not(Not(x) And Not(y))
Theorem: Any Boolean function can be represented using an expression
containing Nand operations only.
Proof:
• Not(x) = (x Nand x)
• (x And y) = Not(x Nand y)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Building a logic gate
a
Xor
out
b
?
outputs 1 if one, and only
one, of its inputs, is 1.
The Process:
- Design the gate architecture
- Specify the architecture in HDL
- Test the chip in a hardware simulator
• Optimize the design
• Realize the optimized design in silicon.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Design: from requirements to interface
a b out
a
Xor
out
b
outputs 1 if one, and only
one, of its inputs, is 1.
0
0
0
0
1
1
1
0
1
1
1
0
Requirement:
Build a gate that
delivers this
functionality
/** Xor gate: out = (a And Not(b)) Or (Not(a) And b)) */
CHIP Xor {
IN a, b;
OUT out;
Gate interface
Expressed as an
HDL stub file
PARTS:
// Implementation missing
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Design: from requirements to gate diagram
a b out
a
Xor
out
b
outputs 1 if one, and only
one, of its inputs, is 1.
0
0
0
0
1
1
1
0
1
1
1
0
Build a gate that
delivers this
functionality
a
General idea:
Requirement:
And
Not
out=1 when:
Or
a And Not(b)
Not
Or
b And Not(a)
out
b
And
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Design: from gate diagram to HDL
a
a
b
in
Not
And
out
out
aAndNotb
notb
a
b
in
Not
out
out
out
nota
notaAndb
a
b
b
Or
And
out
/** Xor gate: out = (a And Not(b)) Or (Not(a) And b))
*/
CHIP Xor {
IN a, b;
OUT out;
PARTS:
// implementation missing
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Design: from gate diagram to HDL
a
a
b
in
Not
And
out
out
aAndNotb
notb
a
b
in
Not
out
out
out
nota
notaAndb
a
b
b
Or
And
out
/** Xor gate: out = (a And Not(b)) Or (Not(a) And b))
*/
interface
CHIP Xor {
IN a, b;
OUT out;
Other Xor
implementations
are possible!
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
implementation
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Lecture 3
From Booleans to Arithmetic
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
• Hardware simulation
• Multi-bit buses
• Start building
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
HDL: recap
/** Xor gate: out = (a And Not(b)) Or (Not(a) And b))
*/
CHIP Xor {
IN a, b;
OUT out;
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
• HDL is a functional / declarative language
• The order of HDL statements is insignificant
• Before using a chip part, you must know its interface. For example:
, And(a= ,b= ,out= ,) Or(a= ,b= ,out= )
Not(in= ,out=)
• Connection patterns like chipName(a=a,…)and chipName(…,out=out)are common
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hardware description languages
Common HDLs:
• VHDL
• Verilog
• Many more HDLs…
Our HDL
• Similar in spirit to other HDLs
• Minimal and simple
• Provides all you need for this course
• HDL Documentation:
q
Textbook / Appendix A
q
www.nand2tetris.org / HDL Survival Guide
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
• Hardware simulation
• Multi-bit buses
• Start building
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hardware simulation in a nutshell
CHIP Xor {
IN a, b;
OUT out;
HDL code
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
simulate
test script
load Xor.hdl,
output-file And.out,
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;
hardware
simulator
Simulation options:
• Interactive
• Script-based
• With / without output and compare files
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Interactive simulation (using Xoras an example)
Xor.hdl
CHIP Xor {
IN a, b;
OUT out;
a
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
b
Or (a=aAndNotb, b=notaAndb, out=out);
And
Not
aAndNotb
notb
Or
Not
nota
out
notaAndb
And
}
Simulation process:
• Load the HDL file into the hardware simulator
• Enter values (0’s and 1’s) into the chip’s input pins (e.g. a and b)
• Evaluate the chip’s logic
• Inspect the resulting values of:
q
Output pins (e.g. out)
q
Internal pins (e.g. nota, notb, aAndNotb, notaAndb )
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Interactive simulation
2. evaluate the
chip logic
1. manipulate
input pins
3. inspect
output pins
4. inspect
internal pins
HDL
code
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Script-based simulation
Xor.hdl
CHIP Xor {
IN a, b;
OUT out;
Xor.tst
tested
chip
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
load Xor.hdl;
set a 0, set b 0, eval;
set a 0, set b 1, eval;
set a 1, set b 0, eval;
set a 1, set b 1, eval;
test script = series of
commands to the simulator
Benefits:
• “Automatic” testing
• Replicable testing
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Script-based simulation, with an output file
Xor.hdl
CHIP Xor {
IN a, b;
OUT out;
Xor.tst
tested
tested
chip
chip
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
}
Xor.out
The logic of a typical test script
q
Initialize:
q
q
q
q
load Xor.hdl,
test
script
output-file Xor.out,
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;
Load an HDL file
Create an empty output file
List the names of the pins whose
values will be written to the output file
| a | b |out|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Output File, created
by the test script as a
side-effect of the
simulation process
Repeat:
q
set– eval- output
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Script-based simulation
inspect the
output file
run
the script
test
script
HDL
code
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hardware simulators
• There are many of them!
Our hardware simulator
• Minimal and simple
• Provides all you need for this course
• Hardware simulator documentation:
www.nand2tetris.org / Hardware Simulator Tutorial
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Revisiting script-based simulation with output files
Xor.tst
Xor.hdl
CHIP Xor {
IN a, b;
OUT out;
tested
chip
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
load Xor.hdl,
test
output-file Xor.out,
script
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;
}
Xor.out
Output file, created by the
test script as a side-effect of
the simulation process
| a | b |out|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Script-based simulation, with compare files
Xor.tst
Xor.hdl
CHIP Xor {
IN a, b;
OUT out;
tested
chip
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=aAndNotb);
And (a=nota, b=b, out=notaAndb);
Or (a=aAndNotb, b=notaAndb, out=out);
load Xor.hdl,
test
output-file Xor.out,
script
compare-to Xor.cmp,
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;
}
Simulation-with-compare-file logic
• When each outputcommand is executed,
the outputted line is compared to the
corresponding line in the compare file
• If the two lines are not the same, the
simulator throws a comparison error.
Xor.cmp
Xor.out
| a | b |out|
| 0 | 0 | 0 |
| a | b |out|
| 0 | 0 | 0| |0 | 1 | 1 |
| 0 | 1 | 1| |1 | 0 | 1 |
| 1 | 0 | 1| |1 | 1 | 0 |
| 1 | 1 | 0 |
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Behavioral simulation
Xor.tst
Xor.hdl
CHIP Xor {
IN a, b;
OUT out;
built-in chip
implementation
BUILTIN Xor
// Built-in chip implementation,
// can execute in the hardware
// simulator like any other chip.
load Xor.hdl,
test
output-file Xor.out,
script
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;
}
Behavioral simulation:
• The chip logic (abstraction) can be
implemented in some high-level
language
• Enables high-level planning and
testing of a hardware architecture
before writing any HDL code.
Xor.out
| a | b |out|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Xor.cmp
| a | b |out|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hardware construction projects
• The players (first approximation) :
q
System architects
q
Developers
• The system architect decides which chips are needed
• For each chip, the architect creates
q
A chip API
q
A test script
q
A compare file
• Given these resources, the developers can build the chips.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The developer’s view (of, say, a Xor gate)
Xor.tst
Xor.hdl
/** returns 1 if (a != b) */
CHIP Xor {
IN a, b;
OUT out;
stub
file
PARTS:
// Implementation missing
}
• Taken together, the three files provide
a convenient specification of:
q
The chip interface (.hdl)
What the chip is supposed to do (.cmp)
q
How to test the chip (.tst)
q
• The developer’s task:
implement the chip, using these resources.
load Xor.hdl,
test
output-file Xor.out,
script
compare-to Xor.cmp
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;
Xor.cmp
| a | b |out|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
compare
file
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
• Hardware simulation
• Multi-bit buses
• Start building
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Arrays of Bits
• Sometimes we wish to manipulate an array of bits as one group
• It’s convenient to think about such a group of bits as a single entity,
sometime termed “bus”
• HDLs usually provide notation and means for handling buses.
47
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Example: adding 16-bit integers
/*
* Adds two 16-bit values.
*/
CHIP Add16 {
IN a[16], b[16];
OUT out[16];
PARTS:
...
}
a
b
16
16
16-bit
adder
16
out
/*
* Adds three 16-bit inputs.
*/
CHIP Add3Way16 {
IN first[16], second[16], third[16];
OUT out[16];
PARTS:
Add16(a=first, b=second, out=temp);
Add16(a=temp, b=third, out=out);
}
48
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Working with individual bits within buses
/*
* 4-way And: Ands 4 bits.
*/
CHIP And4Way {
IN a[4];
OUT out;
PARTS:
And(a=a[0], b=a[1], out=t01);
And(a=t01, b=a[2], out=t012);
And(a=t012, b=a[3], out=out);
}
49
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Working with individual bits within buses
/*
* Bit-wise And of two 4-bit inputs
*/
CHIP And4 {
IN a[4], b[4];
OUT out[4];
PARTS:
And(a=a[0], b=b[0], out=out[0]);
And(a=a[1], b=b[1], out=out[1]);
And(a=a[2], b=b[2], out=out[2]);
And(a=a[3], b=b[3], out=out[3]);
}
50
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Sub-buses
Buses can be composed from (and decomposed into) sub-buses
...
IN lsb[8], msb[8], …
...
Add16(a[0..7]=lsb, a[8..15]=msb, b=…, out=…);
Add16(…, out[0..3]=t1, out[4..15]=t2);
Some syntactic choices of our HDL
• buses are indexed right to left: if foo is a 16-bit bus,
then foo[0] is the right-most bit, and foo[15] is the left-most bit
• overlaps of sub-buses are allowed in output buses of parts
• width of internal pin buses is deduced automatically
• The false and true constants may be used as buses of any width.
51
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
• Hardware simulation
• Multi-bit buses
• Start building
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Nand to Tetris course methodology
how?
here’s a logic gate;
build a computer
one step
at a time
The first steps
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Note:
We are building
8-bit gates, but the book’s
are 16-bit.
First steps
Given: Nand
Goal: Build the following gates:
Elementary
logic gates
8-bit
variants
Multi-way
variants
q
Not
q
Not8
q
Or8Way
q
And
q
And8
q
Mux4Way8
q
Or
q
Or8
q
Mux8Way8
q
Xor
q
Mux8
q
DMux4Way
q
Mux
q
DMux8Way
q
DMux
Why these 15 particular gates?
• Commonly used gates
• Comprise all the elementary logic gates needed to build our computer.
First steps
Given: Nand
Goal: Build the following gates:
Elementary
logic gates
8-bit
variants
Multi-way
variants
q
Not
q
Not8
q
Or8Way
q
And
q
And
q
Mux4Way8
q
Or
q
Or8
q
Mux8Way8
q
Xor
q
Mux8
q
DMux4Way
q
Mux
q
DMux8Way
q
DMux
Multiplexor
if (sel==0)
out=a
else
out=b
a
b
sel
out
sel
out
0
0
0
0
0
a
0
1
0
0
1
b
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
1
1
0
1
0
1
1
1
1
• A 2-way multiplexor enables selecting, and outputting,
one of two possible inputs
• Widely used in:
– Digital design
– Communications networks
abbreviated
truth table
Example: using mux logic to build a programmable gate
if (sel==0)
out = (a And b)
else
out = (a Or b)
a
b
sel
out
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
When sel==0
the gate acts like
an Andgate
When sel==1
the gate acts like
an Or gate
Mux.hdl
CHIP AndMuxOr {
IN a, b, sel;
OUT out;
PARTS:
And (a=a, b=b, out=andOut);
Or (a=a, b=b, out=orOut);
Mux (a=andOut, b=orOut, sel=sel, out=out);
}
Multiplexor implementation
if (sel==0)
out=a
else
out=b
sel
out
0
a
1
b
Mux.hdl
CHIP Mux {
IN a, b, sel;
OUT out;
PARTS:
// Put your code here:
}
Implementation tip:
Can be implemented with
And, Or, and Not gates
Demultiplexor
if (sel==0)
{a,b}={in,0}
else
{a,b}={0,in}
in
sel
a
b
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
DMux.hdl
• Acts like the “inverse” of a multiplexor
• Distributes the single input value into
one of two possible destinations
CHIP DMux {
IN in, sel;
OUT a, b;
PARTS:
// Put your code here:
}
Example: Multiplexing / demultiplexing in communications networks
source
des na on
• Each sel bit is connected to an oscillator that produces a repetitive
train of alternating 0 and 1 signals
• Enables transmitting multiple messages on a single, shared
communications line
• A common use of multiplexing / demultiplexing logic
• Unrelated to this course.
First steps
Elementary
logic gates
8-bit
variants
Multi-way
variants
q
Not
q
Not8
q
Or8Way
q
And
q
And8
q
Mux4Way8
q
Or
q
Or8
q
Mux8Way8
q
Xor
q
Mux8
q
DMux4Way
q
Mux
q
DMux8Way
q
DMux
And8
CHIP And8 {
IN a[8], b[8];
OUT out[8];
PARTS:
// Put your code here:
}
b = 0 0 1 0 1 1 0 1
a = 1 0 1 0 1 0 1 1
out = 0 0 1 0 1 0 0 1
• A straightforward 8-bit extension of the elementary And gate
• (See previous slides on working with multi-bit buses)
First steps
Elementary
logic gates
8-bit
variants
Multi-way
variants
q
Not
q
Not8
q
Or8Way
q
And
q
And8
q
Mux4Way8
q
Or
q
Or8
q
Mux8Way8
q
Xor
q
Mux8
q
DMux4Way
q
Mux
q
DMux8Way
q
DMux
8-bit, 4-way multiplexor
sel[1]
sel[0]
out
0
0
a
0
1
b
1
0
c
1
1
d
Mux4Way8.hdl
CHIP Mux4Way16 {
IN a[8], b[8], c[8], d[8],
sel[2];
OUT out[8];
PARTS:
// Put your code here:
}
Implementation tip:
Can be built from several Mux8 gates
First steps
Given: Nand
Goal: Build the following gates:
Elementary
logic gates
8-bit
variants
Multi-way
variants
q
Not
q
Not8
q
Or8Way
q
And
q
And8
q
Mux4Way8
q
Or
q
Or8
q
Mux8Way8
q
Xor
q
Mux8
q
DMux4Way
q
Mux
q
DMux8Way
q
DMux
So how to actually build
these gates?
Chip building materials (using Xor as an example)
Xor.cmp
a
Xor
out
b
outputs 1 if a != b
a b out
0 0 0
0 1 1
1 0 1
1 1 0
Xor.hdl
CHIP Xor {
IN a, b;
OUT out;
PARTS:
// Put your code here.
}
The contract:
When running your Xor.hdlon
the supplied Xor.tst,
your Xor.outshould be the
same as the supplied Xor.cmp
Xor.tst
load Xor.hdl,
output-file Xor.out,
compare-to Xor.cmp,
output-list a b out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;
More resources
• Text editor (for writing your HDL files)
• HDL Survival Guide
• Hardware Simulator Tutorial
• Peers in your group!
Available at:
www.nand2tetris.org
Hack chipset API
a
a
b
in
Not
And
out
out
a
b
in
Not
Or
out
out
out
a
b
b
And
out
CHIP Xor {
IN a, b;
OUT out;
When deciding to use
some chip-parts, how
do I know the names
of their input and
output pins?
PARTS:
Not (in= , out=);
Not (in= , out=);
And (a= , b= , out=);
And (a= , b=b , out=);
Or (a= , b= , out=);
}
Hack chipset API
Add16 (a= ,b= ,out= );
ALU (x= ,y= ,zx= ,nx= ,zy= ,ny= ,f= ,no= ,out= ,zr= ,ng= );
And16 (a= ,b= ,out= );
Mux8Way (a= ,b= ,c= ,d= ,e= ,f= ,g= ,h= ,sel= ,out= );
And (a= ,b= ,out= );
Aregister (in= ,load= ,out= );
Bit (in= ,load= ,out= );
Mux (a= ,b= ,sel= ,out= );
Nand (a= ,b= ,out= );
Not16 (in= ,out= );
CPU (inM= ,instruction= ,reset= ,outM= ,writeM= ,addressM= ,pc= );
Not (in= ,out= );
DFF (in= ,out= );
Or16 (a= ,b= ,out= );
DMux4Way (in= ,sel= ,a= ,b= ,c= ,d= );
Or8Way (in= ,out= );
DMux8Way (in= ,sel= ,a= ,b= ,c= ,d= ,e= ,f= ,g= ,h= );
Or (a= ,b= ,out= );
Dmux (in= ,sel= ,a= ,b= );
PC (in= ,load= ,inc= ,reset= ,out= );
Dregister (in= ,load= ,out= );
PCLoadLogic (cinstr= ,j1= ,j2= ,j3= ,load= ,inc= );
FullAdder (a= ,b= ,c= ,sum= ,carry= );
RAM16K (in= ,load= ,address= ,out= );
HalfAdder (a= ,b= ,sum= , carry= );
RAM4K (in= ,load= ,address= ,out= );
Inc16 (in= ,out= );
RAM512 (in= ,load= ,address= ,out= );
Keyboard (out= );
RAM64 (in= ,load= ,address= ,out= );
Memory (in= ,load= ,address= ,out= );
RAM8 (in= ,load= ,address= ,out= );
Mux16 (a= ,b= ,sel= ,out= );
Register (in= ,load= ,out= );
Mux4Way16 (a= ,b= ,c= ,d= ,sel= ,out= );
ROM32K (address= ,out= );
Mux8Way16 (a= ,b= ,c= ,d= ,e= ,f= ,g= ,h= ,sel= ,out= );
Screen (in= ,load= ,address= ,out= );
Xor (a= ,b= ,out= );
HDL Survival Gui
de : www.nand2tetris.org
Built-in chips
CHIP Foo {
IN ...;
OUT ...;
PARTS:
...
Mux16(...)
...
Q: What happens if there is no Mux16.hdlfile in
the current directory?
A: The simulator invokes, and evaluates, the builtin version of Mux16 (if such exists).
}
• The supplied simulator software features built-in chip implementations
of all the chips in the Hack chip set
• If you don’t implement some chips from the Hack chipset,
you can still use them as chip-parts of other chips:
q
Just rename their given stub files to, say, Mux16.hdl1
q
This will cause the simulator to use the built-in chip implementation.
Best practice advice
• Try to implement the chips in the given order
• If you don’t implement some chips, you can still use them as chip-parts
in other chips (the built-in implementations will kick in)
• You can invent new, “helper chips”;
however, this is not required: you can build any chip using previouslybuilt chips only
• Strive to use as few chip-parts as possible.
We’re now finished with Chapter 1: Boolean logic
• Boolean logic
• Boolean function synthesis
• Hardware description language
• Hardware simulation
• Multi-bit buses
• First steps
Chapter 2: Boolean arithmetic
• Binary numbers (brief recap!)
• Binary addition (brief recap!)
•
Negative numbers (slightly less brief recap)
• Arithmetic Logic Unit
• More building
00
0
1
01
10
11
3 bits – 8 possibilities
N bits – 2N possibilities
Representing numbers
Binary
Decimal
0
0
1
1
10
2
11
3
100
4
101
5
...
Representing numbers
102
101
100
100s
10s
1s
7 8 9 ten
Representing numbers
102
101
100
100s
10s
1s
7 8 9 ten
= 7 102 + 8 101 + 9 100 = 789 ten
Binary → Decimal
22
21
20
4s
2s
1s
1 0 1two
= 1 2 2 + 0 2 1 + 1 2 0 = 5 ten
Binary → Decimal
bn bn-1 bn-2 … b1 b0
'
Maximum value represented by k bits:
1 + 2 + 4 + … + 2k-1 = 2k-1
Fixed word size
We will use a fixed number of bits.
Say 8 bits.
0000 0000
0000 0001
0000 0010
0000 0011
…
0111 1111
1000 0000
1000 0001
…
1111 1110
1111 1111
28 = 256 values
Representing signed numbers
We will use a fixed number of bits.
Say 8 bits.
0000 0000
0000 0001
0000 0010
0000 0011
…
0111 1111
1000 0000
1000 0001
…
1111 1110
1111 1111
positive values
• That’s one possible representation
• We’ll use a better one, later
negative values
Decimal → Binary
87ten = ? ? ? ? ? ? ? ? two
Decimal → Binary
87ten = 64 + 16 + 4 + 2 + 1
=? ? ? ?
? ? ? ?two
Decimal → Binary
87ten = 64 + 16 + 4 + 2 + 1
=0 1 0 1
32
0 1 1 1two
8
Chapter 2: Boolean arithmetic
• Binary numbers (brief recap!)
• Binary addition (brief recap!)
• Negative numbers
• Arithmetic Logic Unit
• More building
Boolean arithmetic
implement
• Addition
get for free
• Subtraction
• Comparison (<,>,=)
• Multiplication
• Division
get for free
postpone
to soware
postpone
to soware
Addition
0 0 0 1 0 1 0 1
+
0 1 0 1 1 1 0 0
? ? ? ? ? ? ? ?
Addition
0 0 0 1 0 1 0 1
+
0 1 0 1 1 1 0 0
0 1 1 1 0 0 0 1
+
21
92
113
Addition
5 7 8 3
+
2 4 5 6
? ? ? ?
Nand to
Tetris /
www.nand2tetris.org
/
Chapter
2/
Copyright
©
NoamNisan and
Shimon
Schocken
Addition
5 7 8 3
+
2 4 5 6
Addition
1 1
5 7 8 3
+
2 4 5 6
8 2 3 9
Addition
0 0 0 1 0 1 0 1
+
0 1 0 1 1 1 0 0
? ? ? ? ? ? ? ?
Addition
1 1 1
0 0 0 1 0 1 0 1
+
0 1 0 1 1 1 0 0
0 1 1 1 0 0 0 1
Overflow
1 0 0 1 0 1 0 1
+
1 1 0 1 1 1 0 0
? ? ? ? ? ? ? ?
Overflow
1 0 0 0 1 1 1 0 0
1 0 0 1 0 1 0 1
+
1 1 0 1 1 1 0 0
1 0 1 1 1 0 0 0 1
Building an Adder
0
1
+
0
1
• Half adder: adds two bits
• Full adder: adds three bits
• Adder: adds two integers
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
carry
Half adder
bit
a
b
sum
carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
sum
bit
Half adder
a
b
sum
carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
HalfAdder.hdl
/** Computes the sum of two bits. */
CHIP HalfAdder {
IN a, b;
OUT sum, carry;
PARTS:
// Put your code here:
}
Full adder
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
Full adder
carry
bit
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
sum
bit
0
1
1
0
1
0
1
Full adder
FullAdder.hdl
/** Computes the sum of three bits. */
CHIP HalfAdder {
IN a, b, c;
OUT sum, carry;
PARTS:
// Put your code here:
}
Multi-bit Adder
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
Multi-bit Adder
0
1
+
0
1
Nand to
Tetris /
www.nand2tetris.org
/
0
0
1
1
1
0
0
1
Chapter
0
1
1
0
1
0
0
1
1
1
0
0
2/
Copyright
©
0
1
1
0
1
0
1
NoamNisan and
Shimon
Schocken
Multi-bit Adder
0
1
+
0
1
0
0
1
1
1
0
0
1
Add16.hdl
/* Adds two 16-bit, two’s-complement values.
* The most-significant carry bit is ignored. */
CHIP Add16 {
IN a[16], b[16];
OUT out[16];
PARTS:
// Put you code here:
}
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
Chapter 2: Boolean arithmetic
• Binary numbers (brief recap!)
• Binary addition (brief recap!)
• Negative numbers
• Arithmetic Logic Unit
• More building
Representing numbers (using 4 bits)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Using n bits, we can represent
the positive integers in the range
0 … 2n-1
Representing negative numbers
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Possible solution: use a sign bit
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 -0
1001 -1
1010 -2
1011 -3
1100 -4
1101 -5
1110 -6
1111 -7
Use the left-most bit to
represent the sign, -/+
Use the remaining bits to
represent a positive number
Complications:
• -0?
• x + (-x) is not 0
• more complications
Two's Complement
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
-8
-7
-6
-5
-4
-3
-2
-1
Represent the negative number -x
using the positive number 2n - x
(16 - 8)
(16 - 9)
(16 - 10)
(16 - 11)
(16 - 12)
(16 - 13)
(16 - 14)
(16 - 15)
Two's Complement
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
-8
-7
-6
-5
-4
-3
-2
-1
positive numbers range:
0 … 2n-1 - 1
(16 - 8)
(16 - 9)
(16 - 10)
(16 - 11)
(16 - 12)
(16 - 13)
(16 - 14)
(16 - 15)
negative numbers range:
-1 … -2n - 1
Addition using two's complement
+
-2
-3
-5
+
14
13
11
Two’s complement rationale:
•
representation is modulo 2n
• addition is modulo 2n
+
1110
1101
11011
11011= 27 ten
1011= 11 ten
Computing -x
Input:
x
Output:
-x (in two's complement)
Insight:
if we solve this we’ll know how to subtract:
y – x = y + (-x)
Computing -x
Input:
x
Output:
-x (in two's complement)
Idea:
2n – x = 1 + (2n - 1) - x
11111111two
11111111
- 10101100 (some x example)
01010011 (flip all the bits)
Now add 1 to the result
Computing -x (example)
Input:
4
Output:
should be 12 (representing -4 in two’s complement)
Input:
Flip the bits:
Add one:
Output:
0100
+
1011
1
1100
= 12 ten
To add 1:
Flip all the bits from right to left,
stop when the first 0 flips to 1
Chapter 2: Boolean arithmetic
• Binary numbers
• Binary addition
• Negative numbers
• Arithmetic Logic Unit
• More building
We’ll resume here next time
Lecture 4
Building the ALU
(Arithmetic Logic Unit)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Addition
0 0 0 1 0 1 0 1
+
0 1 0 1 1 1 0 0
? ? ? ? ? ? ? ?
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Addition
1 1 1
0 0 0 1 0 1 0 1
+
0 1 0 1 1 1 0 0
0 1 1 1 0 0 0 1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Overflow
1 0 0 1 0 1 0 1
+
1 1 0 1 1 1 0 0
? ? ? ? ? ? ? ?
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Overflow
1 0 0 0 1 1 1 0 0
1 0 0 1 0 1 0 1
+
1 1 0 1 1 1 0 0
1 0 1 1 1 0 0 0 1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Building an Adder
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
• Half adder: adds two bits
• Full adder: adds three bits
• Adder: adds two integers
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
carry
Half adder
bit
a
b
sum
carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
sum
bit
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Half adder
a
b
sum
carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
HalfAdder.hdl
/** Computes the sum of two bits. */
CHIP HalfAdder {
IN a, b;
OUT sum, carry;
PARTS:
// Put your code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Full adder
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Full adder
carry
bit
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
sum
bit
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Full adder
FullAdder.hdl
/** Computes the sum of three bits. */
CHIP HalfAdder {
IN a, b, c;
OUT sum, carry;
PARTS:
// Put your code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Multi-bit Adder
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Multi-bit Adder
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Multi-bit Adder
0
1
+
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
Add16.hdl
/* Adds two 16-bit, two’s-complement values.
* The most-significant carry bit is ignored. */
CHIP Add16 {
IN a[16], b[16];
OUT out[16];
PARTS:
// Put your code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 2: Boolean arithmetic
• Binary numbers
• Binary addition
• Negative numbers
• Arithmetic Logic Unit
• More chips
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Von Neumann Architecture
Computer
System
CPU
ALU
Input
Memory
Output
Control
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The Arithmetic Logical Unit
Computer
System
CPU
ALU
Input
Memory
Output
Control
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The Arithmetic Logical Unit
The ALU computes a
function on the two inputs,
and outputs the result
f
input1
f (input1, input2)
f : one out of a family of
pre-defined arithmetic
and logical functions
ALU
input2
Arithmetic functions: integer addition, multiplication, division, ...
- logical functions: And, Or, Xor, …
-
Which functions should the ALU perform?
A hardware / software tradeoff.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
As with project 1, the book’s ALU is a 16-bit version
but your projects are an 8-bit version… otherwise identical!
The Hack ALU
• Operates on two 16-bit, two’s complement values
• Outputs a 16-bit, two’s complement value
• Which function to compute is set by six 1-bit inputs
• Computes one out of a family of 18 functions
• Also outputs two 1-bit values (to be discussed later).
zx nx
zy
ny
f
no
x
16 bits
y
ALU
16 bits
zr
out
16 bits
out
0
1
-1
x
y
!x
!y
-x
-y
x+1
y+1
x-1
y-1
x+y
x-y
y-x
x&y
x|y
ng
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
As with project 1, the book’s ALU is a 16-bit version
but your projects are an 8-bit version… otherwise identical!
The Hack ALU
To cause the ALU to compute a
function, set the control bits to
one of the binary combinations
listed in the table.
zx nx
zy
ny
f
no
x
16 bits
y
ALU
16 bits
zr
ng
out
16 bits
control bits
zx nx zy ny
1
0 1 0
1
1 1 1
1
1 1 0
0
0 1 1
1
1 0 0
0
0 1 1
1
1 0 0
0
0 1 1
1
1 0 0
0
1 1 1
1
1 0 1
0
0 1 1
1
1 0 0
0
0 0 0
0
1 0 0
0
0 0 1
0
0 0 0
0
1 0 1
f no
1 0
1 1
1 0
0 0
0 0
0 1
0 1
1 1
1 1
1 1
1 1
1 0
1 0
1 0
1 1
1 1
0 0
0 1
out
0
1
-1
x
y
!x
!y
-x
-y
x+1
y+1
x-1
y-1
x+y
x-y
y-x
x&y
x|y
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The Hack ALU in action: compute y-x
2. Evaluate
the chip logic
Load
tools/builtInChips/ALU.hdl
3. Inspect the
ALU outputs
1. Set the ALU’s inputs and control
bits to some test values
(000111 codes “output y-x”)
The built-in ALU
implementation has some
GUI side-effects
Built-in ALU
implementation
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The Hack ALU in action: compute x & y
Set to binary
I/O format
Inspect the
ALU outputs
Set the ALU’s inputs and control bits
to some test values
(000000 codes “compute x&y”)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Opening up the Hack ALU black box
control
bits
x
y
out =
f(control bits, x,
y)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The Hack ALU operation
pre-seng
the x input
pre-seng
the y input
zx
nx
if zx
then
x=0
if nx
then
x=!x
zx nx
zy
ny
if zy if ny
then
then
y=0
y=!y
zy
ny
selecng
between
post-seng
compung + or &
the
output
f
f
no
Resulng
ALU output
out
if f
if no
then out=x+y then
else out=x&y out=!out out(x,y)=
no
x
16 bits
y
ALU
out
16 bits
16 bits
zr
ng
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The Hack ALU operation
pre-seng
the x input
zx
nx
if zx
then
x=0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
if nx
then
x=!x
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
pre-seng
the y input
zy
ny
if zy if ny
then
then
y=0
y=!y
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
selecng
between
post-seng
compung + or &
the
output
f
no
Resulng
ALU output
out
if f
if no
then out=x+y then
else out=x&y out=!out out(x,y)=
1
0
0
1
1
1
1
0
-1
0
0
x
0
0
y
0
1
!x
0
1
!y
1
1
-x
1
1
-y
1
1
x+1
1
1
y+1
1
0
x-1
1
0
y-1
1
0
x+y
1
1
x-y
1
1
y-x
0
0
x&y
0
1
x|y
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
ALU operation example: compute !x
pre-seng
the x input
pre-seng
the y input
zx
nx
zy
if zx
then
x=0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
if nx
then
x=!x
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
if zy
then
y=0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
ny
selecng
between
post-seng
compung + or &
the
output
f
no
Resulng
ALU output
out
if ny if f
if no
then
then out=x+y then
y=!y
else out=x&y out=!out out(x,y)=
0
1
0
0
1
1
1
1
0
1
0
-1
1
0
0
x
0
0
0
y
1
0
1
!x
0
0
1
!y
Example: compute !x
1
1
1
-x
x:0
1 110 0
1
-y
y:1
1 011 1
1
x+1
1
1
1
y+1
Following
pre-setting:
1
1
0
x-1
x:0
1 110 0
0
y-1
y:0
1 111 1
0
x+y
0
1
1
x-y
Computation
and
post-setting:
1
1
1
y-x
0
0
x&y
x&y:
1 100 0
1
x|y
!(x&y):
0 001 1 (!x) 1
ALU operation example: compute y-x
pre-seng
the x input
zx
nx
pre-seng
the y input
zy
ny
if zx if nx if zy if ny
then
then
then
then
x=0
x=!x
y=0
y=!y
1
0
1
0
1
1
1
1
1
1
1
0
Example:
compute
y-x
0
0
1
1
x:
0 0 1 0 (2)
y: 1
01 1 1 10 (7) 0
0
0
1
1
1
1
0
0
Following
pre-setting:
0
0
1
1
x:
0 0 1 0
1
1
0
0
y:
1 0 0 0
0
1
1
1
1
1
0
1
Computation and post-setting:
0
0
1
1
x+y:
1
0
1
0
1
1
0
0
!(x+y):
00 1 0 10 (5) 0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
selecng
between
post-seng
compung + or &
the
output
f
no
Resulng
ALU output
out
if f
if no
then out=x+y then
else out=x&y out=!out out(x,y)=
1
0
0
1
1
1
1
0
-1
0
0
x
0
0
y
0
1
!x
0
1
!y
1
1
-x
1
1
-y
1
1
x+1
1
1
y+1
1
0
x-1
1
0
y-1
1
0
x+y
1
1
x-y
1
1
y-x
0
0
x&y
0
1
x|y
The Hack ALU output control bits
zx nx
zy
ny
f
no
x
16 bits
y
ALU
out
16 bits
16 bits
zr
ng
if (out == 0) then zr = 1, else zr = 0
if (out < 0)
then ng = 1, else ng = 0
These two control bits will come into play when we build the
complete computer’s architecture.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Perspective
The Hack ALU is:
• Simple
• Elegant
• To implement it this ALU,
you only need to know how to:
q
Set a 16-bit value to 0000000000000000
q
Set a 16-bit value to 1111111111111111
q
Negate a 16-bit value (bit-wise)
q
Compute plus or And on two 16-bit values
q
That’s it!
“Simplicity is the ultimate
sophistication.”
― Leonardo da Vinci
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 2: Boolean arithmetic
• Binary numbers
• Binary addition
• Negative numbers
• Arithmetic Logic Unit
• More chips
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
More chips
Given: All the chips we presented earlier
Goal:
We can build the following chips:
q
HalfAdder
q
FullAdder
q
Add8
q
Inc8
q
ALU
A family of combinational chips,
from simple adders to an
Arithmetic Logic Unit.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Half Adder
a
b
sum
carry
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
HalfAdder.hdl
/** Computes the sum of two bits. */
CHIP HalfAdder {
IN a, b;
OUT sum, carry;
Implementation tip
Can be built using two very
elementary gates.
PARTS:
// Put your code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Full Adder
FullAdder.hdl
a
b
c
sum
carry
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
/** Computes the sum of three bits. */
CHIP HalfAdder {
IN a, b, c;
OUT sum, carry;
PARTS:
// Put your code here:
}
Implementation tips
Can be built using two
half-adders.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
8-bit adder
Implementation tips
• An n-bit adder can be built
from n full-adder chips
• The carry bit is “piped” from
right to left
• The MSB carry bit is ignored.
Add8.hdl
/*
* Adds two 8-bit, two’s-complement values.
* The most-significant carry bit is ignored.
*/
CHIP Add8 {
IN a[8], b[8];
OUT out[8];
PARTS:
// Put you code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
8-bit incrementor
Implementation tip
The single-bit 0 and 1 values
are represented in HDL as
false and true.
Inc8.hdl
/*
* Outputs in + 1.
* The most-significant carry bit is ignored.
*/
CHIP Inc8 {
IN in[8];
OUT out[8];
PARTS:
// Put you code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
ALU
Implementation tips
q Building blocks: Add8 , and
some gates built in project 1
q Can be built with ~20 lines of
HDL code
ALU.hdl
/** The ALU. */
// Manipulates the x and y inputs as follows:
// if (zx == 1) sets x = 0
// 16-bit true constant
// if (nx == 1) sets x = !x
// bitwise Not
// if (zy == 1) sets y = 0
// 16-bit true constant
// if (ny == 1) sets y = !y
// bitwise Not
// if (f
== 1) sets out = x + y // int. 2's-complement addition
// if (f
== 0) sets out = x & y // bitwise And
// if (no == 1) sets out = !out
// bitwise Not
// if (out == 0) sets zr = 1
// 1-bit true constant
// if (out < 0) sets ng = 1
// 1-bit true constant
...
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
More resources
• HDL Survival Guide
www.nand2tetris.org
• Hardware Simulator Tutorial
• Peers in your group!
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Best practice advice
• Try to implement the chips in the given order
• If you don’t implement some of the chips,
you can still use them as chip-parts in other chips. Just rename the
given stub-files; this will cause the simulator to use the built-in
versions of these chips
• You can invent new, “helper chips”; however, this is not required:
you can build any chip using previously-built chips only
• Strive to use as few chip-parts as possible
• You will have to use chips implemented previously
• For efficiency and consistency’s sake, use their built-in versions
rather than your own implementation.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 2: Boolean arithmetic
• Binary numbers
• Binary addition
• Negative numbers
• Arithmetic Logic Unit
• More chips
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Lecture 5
Memory
Based on slides supporting chapter 3 of
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 3: Memory
• Time matters
• Sequential logic
• Flip Flops
• Memory units
• Counters
• Project 3 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Time-independent logic
• So far we ignored the issue of time
• The chip’s inputs were just “sitting there” – fixed and unchanging
• The chip’s output was a pure function of the current inputs,
and did not depend on anything that happened previously
• The output was computed “instantaneously”
• This style of gate logic is sometimes called:
q
time-independent logic
q
combinational logic.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hello, time
Abstraction issues:
• The hardware must support
maintaining “state”
example:
x = 17
example:
• The hardware must support
computations over time
for i = 0 … 99:
sum = sum + a[i]
Implementation issues:
• The hardware must handle the
physical time delays associated
with calculating and moving
data from one chip to another.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Physical time / clock time
physical
time:
clock:
time:
Arrow of time:
Continuous
1
0
1
2
3
4
5
...
Discrete time:
State changes occur
only when advancing
from one time unit to
another
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chip behavior over time (example)
physical
time:
clock:
Arrow of time:
Continuous
1
0
time:
in:
1
2
3
4
5
...
Discrete time:
State changes occur
only when advancing
from one time unit to
another
1
(
e
xa
mpl
e
) 0
out:
1
(
Noti
n)
0
(
e
xa
mpl
e
)
• Desired / idealized behavior of the
in and out signals
• That’s how we want the hardware to
handle time-dependent behavior
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chip behavior over time (example)
physical
time:
clock:
Arrow of time:
Continuous
1
0
time:
in:
1
2
3
4
5
...
Discrete time:
State changes occur
only when advancing
from one time unit to
another
1
(
e
xa
mpl
e
) 0
out:
1
(
Noti
n)
0
(
e
xa
mpl
e
)
actual behavior of the
in and out signals, due
to physical time delays
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chip behavior over time (example)
physical
time:
clock:
Arrow of time:
Continuous
1
0
time:
in:
1
2
3
4
5
...
Discrete time:
State changes occur
only when advancing
from one time unit to
another
1
(
e
xa
mpl
e
) 0
out:
1
(
Noti
n)
0
(
e
xa
mpl
e
)
Time delays
• propagation delays
• computation delays
Clock cycle
• designed to neutralize the time delays
• cycle length: slightly longer than the time delays
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chip behavior over time (example)
physical
time:
clock:
Arrow of time:
Continuous
1
0
time:
in:
1
2
3
4
5
Discrete time:
State changes occur
only when advancing
from one time unit to
another
...
1
(
e
xa
mpl
e
) 0
out:
1
(
Noti
n)
0
(
e
xa
mpl
e
)
Not: an example of a combinational chip
:
• The gate reacts “immediately” to the inputs
• Well, not really, but the clock’s behavior creates this effect.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Combinational logic / sequential logic
Combinational logic:
The output is a pure function
of the present input only
Sequential logic:
The output depends on:
• the present input (optionally)
• the history of the input
• (creates a memory effect).
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Flip-Flop
in
DFF
out
out(t) = in(t- 1)
The simplest state-keeping gate:
• 1-bit input, 1-bit output
• The gate outputs its previous input: out(t) = in(t- 1)
• Implementation: a gate that can flip between two stable states:
“remembering 0”, or “remembering 1”
• Gates that feature this behavior are called data ip-ops
.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Flip-Flop
in
out
DFF
out(t) = in(t- 1)
time:
in:
1
2
3
4
5
...
1
(
e
x
a
mpl
e
) 0
out:
1
0
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Flip-Flop
in
out
DFF
out(t) = in(t- 1)
time:
in:
1
2
3
4
5
...
1
(
e
x
a
mpl
e
) 0
out:
1
0
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Flip-Flop
in
out
DFF
out(t) = in(t- 1)
time:
in:
1
2
3
The triangle icon indicates that the gate is:
• clocked / sequential
• connected to a clock input
• designed to maintain state
4
5
...
1
(
e
x
a
mpl
e
) 0
out:
1
0
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
DFF implementation notes
data
A DFF bi-state architecture can be built from Nand gates:
r
0
q
enb
• step 1: create an input-output loop,
achieving a 1-bit un-clocked memory (“latch”)
1
s
0
• step 2: isolate across time steps using a pair of latches gated by clock
achieving a 1-bit clocked memory (“flip-flop”)
•
The resulting implementation is elegant, but conceptually confusing
Technical note
The implementation described above is impossible in our simulator:
• The simulator does not permit combinational loops
• A cycle in hardware connections is allowed only if the cycle passes through a
sequential (“clocked”) gate
Implementing sequential chips
• The supplied simulator features a built-in DFF gate
• Sequential chips are implemented by using built-in DFF chip parts.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Sequential chips
Sequential chips are capable of:
• maintaining state, and, optionally,
• acting on the state, and on the current inputs
s
t
a
t
e
(
t
)=f(
s
t
a
t
e
(
t
1)
,
i
nput
(
t
)
)
Example: DFF
• The DFF state: the value of the input from the previous time unit
• The simplest, most elementary sequential chip
Example: RAM
• The RAM state: the current values of all its registers
• given some address (input), the RAM emits the value of the selected register
Implementation note
• All combinational chips are constructed from Nand gates
• All sequential chips are constructed from DFF gates, and combinational chips.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Sequential chips
s
t
a
t
e
(
t
)=f(
s
t
a
t
e
(
t
1)
,
i
nput
(
t
)
)
Implementation note
• All combinational chips are constructed from Nand gates
• All sequential chips are constructed from DFF gates, and combinational chips.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Sequential chip: 1-bit register
load
load
load
in
in
Bit
out
out
t) then
t+ 1) = in(
ifif load(
out(
load(t-1)
then
out(t)=in(t-1)
t
else
out(t+ 1) = out(
else out(t)=out(t-1)
binary cell (Bit)
• Designed to “remember”, or “store”, a single bit
in
w
Bit Bit
. . . Bit
w
out
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
w-bit register
• More accurately:
q
Stores a bit until...
q
Instructed to load, and store, another bit.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register
load
load
in
time:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
in
w
Bit Bit
. . . Bit
w
t) then
t+ 1) = in(
t)
ifif load(
out(
load(t-1)
then
out(t)=in(t-1)
t)
else
out(t+ 1) = out(
else out(t)=out(t-1)
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
binary cell (Bit)
w-bit register
1
load:
out
Bit
2
3
4
out
5
1
0
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register
load
load
in
time:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
in
w
Bit Bit
. . . Bit
w
t) then
t+ 1) = in(t)
ifif load(
out(
load(t-1)
then
out(t)=in(t-1)
else
out(t+ 1) = out(t)
else out(t)=out(t-1)
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
binary cell (Bit)
w-bit register
1
load:
out
Bit
2
3
4
out
5
1
0
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register
load
load
in
time:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1
0
in
w
Bit Bit
. . . Bit
w
t) then
t+ 1) = in(t)
ifif load(
out(
load(t-1)
then
out(t)=in(t-1)
else
out(t+ 1) = out(t)
else out(t)=out(t-1)
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
binary cell (Bit)
w-bit register
1
load:
out
Bit
2
3
4
out
5
Resulting behavior:
Stores and emits a
value, until instructed
to load (and store) a
new value
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation – first attempt
in
out
out
in
DFF
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
in
in
MUX
out
out
DFF
1
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
1
1
in
in
MUX
?
1
?
DFF
out
out
1
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
1
1
in
in
MUX
?
1
?
DFF
out
out
1
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
0
0
in
in
MUX
1
1
1
DFF
out
out
1
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
0
0
in
in
MUX
1
1
1
DFF
out
out
1
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
1
0
in
in
MUX
1
0
1
DFF
out
out
1
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
0
0
in
in
MUX
0
0
0
DFF
out
out
0
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register implementation
load
load
0
0
in
in
MUX
0
0
0
DFF
out
out
0
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
load:
1
(
e
xa
mp
l
e
)
0
in:
1
(
e
x
a
mpl
e
)
0
out:
1-bit register (Bit)
Resulting behavior:
Stores and emits a
value, until instructed
to load (and store) a
new value
1
0
time:
1
2
3
4
5
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 3: Memory
• Time matters
• Sequential logic
• Flip Flops
• Memory units
• Counters
• Project 3 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory units
We’ll describe (and build) a progression of memory units:
• 1-bit register:
• Designed to store a single bit
• Multi-bit register:
• Designed to store an w-bit value
• Random Access Memory (RAM):
• Designed to store n addressable w-bit values,
each having a unique index, or address, ranging from 0 to n-1.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Multi-bit register (also known as “register”)
(multi-bit register)
Word width (w):
• 16-bit, 32-bit, 64-bit, …
• We will focus on 8-bit registers, without loss of generality.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Register: abstraction
(multi-bit register)
To read a Register:
probe out
To set Register = v
set in = v
set load = 1
Result:
out emits the Register’s state
Result:
q
q
The Register’s state becomes v;
From the next cycle onward,
out emits v
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Register: implementation
(multi-bit register)
(1-bit register)
1-bit
Register
A w-bit register can be created from an array of w1-bit registers.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Register chip in action
Run the clock
Inspect the
register’s output
Set in to 17
Inspect the
register’s contents
For the demo, we use a built-in
16-bit register from the Hack chipset,
named Dregister, or simply D.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Register chip in action
Run the clock
Inspect the
register’s output
Inspect the
register’s contents
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Register chip in action
Run the clock
Inspect the
register’s output
Set in to 17
Set load to 1
Inspect the
register’s contents
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Register chip in action
Run the clock
Inspect the
register’s output
Inspect the
register’s contents
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory units
We’ll describe (and build) a progression of memory units:
• 1-bit register:
• Multi-bit register:
• Random Access Memory (RAM)
•
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
RAM
Architecture:
A sequence of n addressable registers,
with addresses 0 to n-1
Address width:
k = log2 n
Word width:
No impact on the RAM logic
Hack computer: w = 16
Your projects: w = 8
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
RAM: abstraction
At any given point of time:
q
one register in the RAM is selected
q
all the other registers are irrelevant
To read Register i :
set address= i
probe out
Result:
out emits the value of Registeri
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
RAM: abstraction
At any given point of time:
q
one register in the RAM is selected
q
all the other registers are irrelevant
To set Register i to v :
set address= i
set in = v
set load = 1
Result:
• The state of Registeri becomes v
• From the next cycle onward, out emits v
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
RAM: abstraction
Why “Random Access Memory”?
Irrespective of the RAM size (n),
every randomly selected register can be accessed “instantaneously”,
in more or less the same time (here: 1 clock cycle!).
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
A family of 8-bit RAM chips
chip name
n
k
RAM8
8
3
RAM64
64
6
RAM512
512
9
RAM4K
4096
12
RAM16K
16384
14
Why these particular RAM chips?
Because we’ll use them later for building the Hack computer.
(Actually, later we’ll use 16-bit versions of them...)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
RAM chip in action
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Lecture 6
More about memory
Based on slides supporting chapter 3 of
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 3: Memory
• Time matters
• Sequential logic
• Flip Flops
• Memory units
• Counters
• Project 3 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Where counters come to play
• The computer must keep track of which instruction should be fetched and executed
next
• This control mechanism can be realized by a register called
Program Counter
• The PC contains the address of the instruction that will be fetched and executed next
• The PC is designed to support three possible control operations:
q
Reset: fetch the first instruction
PC = 0
q
Next: fetch the next instruction
PC++
q
Goto: fetch instruction n
PC = n
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Program Counter
/**
* A 16-bit counter with load and reset control bits.
* if
reset(t) out(t+1) = 0
* else if load(t) out(t+1) = in(t)
* else if inc(t) out(t+1) = out(t) + 1 (integer addition)
* else
out(t+1) = out(t)
*/
CHIP PC {
IN in[16],load,inc,reset;
OUT out[16];
PARTS:
// Put your code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Counter chip in action
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 3: Memory
• Time matters
• Sequential logic
• Flip Flops
• Memory units
• Counters
• Project 3 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Project 3
Given:
q All the chips built in Projects 1 and 2
q Flip-Flop (built-in DFF gate)
Goal: Build the following chips:
q
Bit
q
Register
q
RAM8
q
RAM64
q
RAM512
q
RAM4K
q
RAM16K
q
PC
A family of sequential chips, from
a 1-bit register to a 16K RAM unit.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
1-bit register
Bit.hdl
/**
* 1-bit register:
* If load(t) then out(t+1) = in(t)
* else
out(t+1) = out(t))
*/
CHIP Bit {
IN in, load;
OUT out;
Implementation tip:
Can be built from a DFF
and a multiplexor.
PARTS:
// Put your code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
8-bit Register
Register.hdl
/**
* 8-bit register:
* If load(t) then out(t+1) = in(t)
* else
out(t+1) = out(t))
*/
CHIP Register {
IN in[8], load;
OUT out[8];
Implementation tip:
Can be built from an array
of eight 1-bit registers.
PARTS:
// Put your code here:
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
8-Register RAM
RAM8.hdl
/*
* Let M stand for the state of the
* register selected by address.
* if load(t) then {M=in(t), out(t+1)=M}
* else
out(t+1)=M
*/
CHIP RAM8 {
IN in[8], load, address[3];
OUT out[8];
PARTS:
// Put your code here:
}
Implementation tips:
q
Feed the in value to all the registers, simultaneously
q
Use mux / demux chips to select the register specified by address.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Project 3
Given:
q All the chips built in Projects 1 and 2
q Flip-Flop (DFF gate)
Goal: Build the following chips:
✓
✓
✓
q
Bit
q
Register
q
RAM8
q
RAM64
q
RAM512
q
RAM4K
q
RAM16K
q
PC
Our next task
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
RAM8, RAM64, …
RAM16K
RAM512
RAM64
RAM8
…
Same technique
can be used to
implement RAM4K
and RAM16K
Implementation tips
• A RAM unit can be built by grouping smaller RAM-parts together
• Think about the RAM’s addressinput as consisting of two fields:
– one field can be used to select a RAM-part;
– the other field can be used to select a register within that RAM-part
• Use mux/demux logic to effect this addressing scheme.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Project 3
Given:
q All the chips built in Projects 1 and 2
q Flip-Flop (DFF gate)
Goal: Build the following chips:
✓
✓
✓
✓
✓
✓
✓
q
Bit
q
Register
q
RAM8
q
RAM64
q
RAM512
q
RAM4K
q
RAM16K
q
PC
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Program Counter
Implementation tip:
Can be built from a register,
an incrementor, and some
logic gates.
/**
* A 16-bit counter with load, inc, and reset control bits.
*
* if reset(t)
out(t+1)=0
// resetting: counter = 0
* else if load(t) out(t+1)=in(t) // setting counter = value
* else if inc(t) out(t+1)=out(t)+1 // incrementing: counter++
* else
out(t+1)=out(t) // counter does not change
*/
CHIP PC {
IN in[16], load, inc, reset;
OUT out[16];
PARTS:
// Implementation comes here.
}
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
More resources
• HDL Survival Guide
www.nand2tetris.org
• Hardware Simulator Tutorial
• Anonymous Q&A
• Peers in your group
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Best practice advice
• Try to implement the chips in the given order
• If you don’t implement some of the chips required in project 3, you can
still use them as chip-parts in other chips. Just rename the given stubfiles; this will cause the simulator to use the built-in versions of these
chips
• You can invent new, “helper chips”; however, this is not required: you
can build any chip using previously-built chips only
• Strive to use as few chip-parts as possible.
• You will have to use chips from Projects 1 and 2
• Best practice: use their built-in versions where available – but use your own Mux8, Or8Way, ...
• For technical reasons, the HDL files of this project are organized in two
directories named a and b
• This directory structure should remain as is.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Chapter 3: Memory
• Time matters
• Sequential logic
• Flip Flops
• Memory units
• Counters
• Project 3 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Lecture 7
Machine Language
part one
Based on the slide supporting chapter 4 of the book
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computers are flexible
The same hardware can run many different software programs
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Universality
The same hardware can run many different software programs
Theory
Practice
Alan Turing:
John Von Nuemann:
Universal Turing Machine
Stored Program Computer
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Stored program concept
Computer System
Memory
CPU
program
ALU
input
output
data
registers
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Stored program concept
Computer System
Memory
instructions
0
0101110011100110
1
1011000101010100
2
1110001011111100
...
CPU
...
ALU
input
data
n
1100101010010101
n+1
1100100101100111
n+2
0011001010101011
...
...
output
registers
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine language
Computer System
Memory
instructions
0
0101110011100110
1
1011000101010100
2
1110001011111100
...
CPU
...
ALU
input
data
n
1100101010010101
n+1
1100100101100111
n+2
0011001010101011
...
...
output
registers
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine language
Computer
System
Memory
instructions
0
0101110011100110
1
1011000101010100
2
1110001011111100
...
CPU
current
instruction
...
ALU
intput
data
n
1100101010010101
n+1
1100100101100111
n+2
0011001010101011
...
...
output
registers
Handling instructions:
operation
• 1011 means “addition”
addressing
• 000101010100 means “operate on memory address 340”
control
• Next we have to execute the instruction at address 2
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Compilation
machine language
high-level program
while (n < 100) {
sum += arr[i];
n++
}
compile
0101111100111100
1010101010101010
1101011010101010
1001101010010101
1101010010101010
1110010100100100
0011001010010101
1100100111000100
1100011001100101
0010111001010101
...
load and
execute
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Mnemonics
Instruction:
1 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0
add
R3
sample instruction
R2
Interpretation 1:
• The symbolic form add R3 R2 doesn’t really exist
• It is just a convenient mnemonic that can be used to present machine
language instructions to humans
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Mnemonics
Instruction:
1 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0
add
R3
sample instruction
R2
Interpretation 2:
• Allow humans to write symbolic machine language instructions,
using assembly language
• Use an assembler program to translate the symbolic code into binary
form.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Symbols
Instruction:
Assembly:
1 0 1 1 0 0 0 1 1 0 0 0 0 0 0 1
add
1
add 1, Mem[129]
Friendlier syntax:
we assume that index
stands for Mem[129]
Mem[129]
add 1, index
The assembler will resolve the symbol index into a specific address.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine language
• Specification of the hardware/software interface:
-
What supported operations?
-
What do they operate on?
-
How is the program controlled?
• Usually in close correspondence to the hardware architecture
-
But not necessarily so
• Cost-performance tradeoffs:
-
Silicon area
-
Time to complete instruction.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine operations
• Usually correspond to the operations that the hardware is designed to
support:
-
Arithmetic operations: add, subtract, …
-
Logical operations: and, or, …
-
Control flow: “go to instruction n ”
q
“if (condition) then go to instruction n”
• Differences between machine languages:
-
Instruction set richness (division? bulk copy? …)
-
Data types (word width, floating point…).
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Addressing
Computer
System
Memory
instructions
0
0101110011100110
1
1011000101010100
2
1110001011111100
...
CPU
current
instruction
...
ALU
intput
data
n
1100101010010101
n+1
1100100101100111
n+2
0011001010101011
...
...
output
registers
How does the language allow us to specify on which data the
instruction should operate?
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory hierarchy
• Accessing a memory location is expensive:
q
Need to supply a long address
q
Getting the memory contents into the CPU takes time
• Solution: memory hierarchy:
Main Memory
CPU
Disk Memory
ALU
Registers
Ÿ
Ÿ
CacheMemory
Ÿ
Ÿ
Ÿ
Ÿ
Ÿ
Ÿ
Ÿ
more storage space, slower access time
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Registers
• The CPU typically contains a few, easily accessed, registers
• Their number and functions are a central part of the machine language
Data registers:
add R1, R2
CPU
Memory
0
1
2
ALU
Registers
R1
R2
Ÿ
10
25
before
.
.
136
137
138
.
.
Ÿ
.
Ÿ
Ÿ
Ÿ
Ÿ
Ÿ
.
Ÿ
Ÿ
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Registers
• The CPU typically contains a few, easily accessed, registers
• Their number and functions are a central part of the machine language
Data registers:
add R1, R2
CPU
Memory
0
1
2
ALU
Registers
R1
R2
Ÿ
10
35
after
.
.
136
137
138
.
.
Ÿ
.
Ÿ
Ÿ
Ÿ
Ÿ
Ÿ
.
Ÿ
Ÿ
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Registers
• The CPU typically contains a few, easily accessed, registers
• Their number and functions are a central part of the machine language
Data registers:
add R1, R2
CPU
Address registers:
Memory
0
1
2
ALU
store R1, @A
Registers
R1
R2
A
Ÿ
77
.
.
136
137
138
.
.
Ÿ
.
Ÿ
Ÿ
Ÿ
Ÿ
Ÿ
.
before
Ÿ
Ÿ
137
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Registers
• The CPU typically contains a few, easily accessed, registers
• Their number and functions are a central part of the machine language
Data registers:
add R1, R2
CPU
Address registers:
Memory
0
1
2
ALU
.
store R1, @A
Registers
R1
R2
A
Ÿ
77
136
137
138
.
.
Ÿ
.
Ÿ
Ÿ
77
.
Ÿ
Ÿ
Ÿ
.
after
Ÿ
Ÿ
137
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Addressing modes
Register
add R1, R2
// R2 := R2 + R1
Direct
add R1, M[200] // Mem[200]:= Mem[200]+ R1
Indirect
add R1, @A
// Mem[A]:= Mem[A]+ R1
Immediate
add 73, R1
// R1 := R1 + 73
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Input / Output
• Many types of input and output devices:
q
Keyboard, mouse, camera, sensors, printers, screen, sound…
• The CPU needs some agreed-upon protocol to talk to each of them
q
Software drivers implement these protocols
• One general method of interaction uses memory mapping
:
q
Memory location 12345 holds the direction of the last movement of the
mouse
q
Memory location 45678 tells the printer to print single-side or double side
q
Etc.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Control flow
Computer System
Memory
instructions
0
0101110011100110
1
1011000101010100
2
1110001011111100
...
CPU
current
instruction
...
ALU
intput
data
n
1100101010010101
n+1
1100100101100111
n+2
0011001010101011
...
...
output
registers
How does the language allow us to decide, and specify,
which instruction to process next?
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Control flow
• Usually the CPU executes machine instructions in sequence
• Sometimes we need to “jump” unconditionally to another location,
e.g. in order to implement a loop:
Symbolic version:
Example:
101: load R1,0
102: add 1, R1
load R1,0
LOOP:
103: ...
add 1, R1
...
// do something with R1 value
...
...
...
// do something with R1 value
156: jmp 102
// goto 102
...
jmp LOOP
// goto loop
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Control flow
• Usually the CPU executes machine instructions in sequence
• Sometimes we need to “jump” unconditionally to another location,
e.g. in order to implement a loop
• Sometimes we need to jump only if some condition is met:
Example:
jgt R1, 0, CONT // if R1>0 jump to CONT
sub R1, 0, R1
// R1 := (0 - R1)
CONT:
...
// Do something with positive R1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack computer: hardware
data
instruc*on
instruc*ons
memory
out
data
memory
CPU
data
in
A 16-bit machine consisting of:
• Data memory (RAM): a sequence of 16-bit registers:
RAM[0], RAM[1], RAM[2],…
• Instruction memory (ROM): a sequence of 16-bit registers:
ROM[0], ROM[1], ROM[2],…
• Central Processing Unit (CPU): performs 16-bit instructions
• Instruction bus / data bus / address buses.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack computer: software
data
ROM
instruc*ons
out
CPU
RAM
data
in
Hack machine language:
q
q
16-bit A-instructions
16-bit C-instructions
Hack program = sequence of instructions written in the
Hack machine language
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack computer: control
data
ROM
instruc*ons
out
CPU
RAM
data
in
reset
Control:
q
q
q
The ROM is loaded with a Hack program
The reset button is pushed
The program starts running
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack computer: registers
A register
M register
data
ROM
instruc*ons
out
CPU
RAM
data
in
D register
The Hack machine language recognizes three 16-bit registers:
• D: used to store data
• A: used to store data / address the memory
• M: represents the currently addressed memory register: M = RAM[A]
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The A-instruction
Syntax:
@ value
Where value is either:
- a non-negative decimal constant or
- a symbol referring to such a constant (later)
Semantics:
• Sets the A register to value
• Side effects:
– RAM[A] becomes the selected RAM register
– ROM[A] becomes the selected ROM register
Example:
// Sets A to 17
@17
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The C-instruction
Syntax:
dest= comp; jump
(both dest and jump are optional)
where:
comp =
dest=
jump =
0, 1, -1, D, A, !D, !A, -D, -A, D+1, A+1, D-1, A-1, D+A, D-A, A-D, D&A, D|A
M,
!M,
-M,
M+1,
null, M, D, MD, A, AM, AD, AMD
M-1, D+M, D-M, M-D, D&M, D|M
(M refers to RAM[A])
null, JGT, JEQ, JGE, JLT, JNE, JLE, JMP
Semantics:
• Computes the value of comp
• Stores the result in dest
• If the Boolean expression ( comp jump 0) is true,
jumps to execute the instruction at ROM[A]
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The C-instruction
Syntax:
dest= comp; jump
(both dest and jump are optional)
where:
comp =
dest=
jump =
0, 1, -1, D, A, !D, !A, -D, -A, D+1, A+1, D-1, A-1, D+A, D-A, A-D, D&A, D|A
M,
!M,
-M,
M+1,
null, M, D, MD, A, AM, AD, AMD
M-1, D+M, D-M, M-D, D&M, D|M
(M refers to RAM[A])
null, JGT, JEQ, JGE, JLT, JNE, JLE, JMP
Semantics:
• Computes the value of comp
• Stores the result in dest
• If the Boolean expression ( comp jump 0) is true,
jumps to execute the instruction at ROM[A]
Example:
// Sets the D register to -1
D=-1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The C-instruction
Syntax:
dest= comp; jump
(both dest and jump are optional)
where:
comp =
dest=
jump =
0, 1, -1, D, A, !D, !A, -D, -A, D+1, A+1, D-1, A-1, D+A, D-A, A-D, D&A, D|A
M,
!M,
-M,
M+1,
null, M, D, MD, A, AM, AD, AMD
M-1, D+M, D-M, M-D, D&M, D|M
(M refers to RAM[A])
null, JGT, JEQ, JGE, JLT, JNE, JLE, JMP
Semantics:
• Computes the value of comp
• Stores the result in dest
• If the Boolean expression ( comp jump 0) is true,
jumps to execute the instruction at ROM[A]
Example:
// Sets RAM[300] to the value of the D register plus 1
@300
// A = 300
M=D+1
// RAM[300] = D + 1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The C-instruction
Syntax:
dest= comp; jump
(both dest and jump are optional)
where:
comp =
dest=
jump =
0, 1, -1, D, A, !D, !A, -D, -A, D+1, A+1, D-1, A-1, D+A, D-A, A-D, D&A, D|A
M,
!M,
-M,
M+1,
null, M, D, MD, A, AM, AD, AMD
M-1, D+M, D-M, M-D, D&M, D|M
(M refers to RAM[A])
null, JGT, JEQ, JGE, JLT, JNE, JLE, JMP
Semantics:
• Computes the value of comp
• Stores the result in dest
• If the Boolean expression ( comp jump 0) is true,
jumps to execute the instruction at ROM[A]
Example:
// If (D-1 == 0) jumps to execute the instruction stored in ROM[56]
@56
// A = 56
D-1;JEQ
// if (D-1 == 0) goto to instruction ROM[A]
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack machine language
data
Hack
program
ROM
instruc*ons
out
CPU
RAM
data
in
Two ways to express the same semantics:
Binary:
Symbolic:
@17
D+1;JLE
translate
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0
load & execute
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
A-instruction: specification and encoding
Semantics: Sets the A register to value
Symbolic syntax:
@ value
Example:
@ 2 1
sets A to 21
Where value is either:
a non-negative decimal constant ≤ 65535 (=2 15-1) or
q a symbol referring to a constant (later)
q
Binary syntax:
0 value
Example:
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
Where valueis a 15-bit binary constant
opcode
signifying an
A-instruction
sets A to 21
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
C-instruction: specification and encoding
Symbolic syntax:
dest = comp ; jump
Binary syntax:
1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
opcode
not used
comp bits
dest bits
jump bits
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
C-instruction: specification and encoding
Symbolic syntax:
dest = comp ; jump
Binary syntax:
1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
comp
0
1
-1
D
A
!D
!A
-D
-A
D+1
A+1
D-1
A-1
D+A
D-A
A-D
D&A
D|A
a==0
M
!M
-M
M+1
M-1
D+M
D-M
M-D
D&M
D|M
c1 c2 c3 c4 c5 c6
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
a==1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
C-instruction: specification and encoding
Symbolic syntax:
dest = comp ; jump
Binary syntax:
1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
dest
d1 d2 d3
effect: the value is stored in:
null
M
D
MD
A
AM
AD
AMD
0
0
0
0
1
1
1
1
The value is not stored
RAM[A]
D register
RAM[A]and D register
A register
A register and RAM[A]
A register and D register
A register, RAM[A], and D register
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
C-instruction: specification and encoding
Symbolic syntax:
dest = comp ; jump
Binary syntax:
1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
jump
j1 j2 j3
effect
null
JGT
JEQ
JGE
JLT
JNE
JLE
JMP
0
0
0
0
1
1
1
1
no jump
if out>0jump
if out=0jump
if out≥0jump
if out<0jump
if out≠0jump
if out≤0jump
unconditional jump
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
C-instruction: specification and encoding
Symbolic syntax:
dest = comp ; jump
Binary syntax:
1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
comp
0
1
-1
D
A
!D
!A
-D
-A
D+1
A+1
D-1
A-1
D+A
D-A
A-D
D&A
D|A
a==0
Examples:
M
!M
-M
M+1
M-1
D+M
D-M
M-D
D&M
D|M
a==1
c1 c2 c3 c4 c5 c6
dest d1 d2 d3 effect: the value is stored in:
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
null
M
D
MD
A
AM
AD
AMD
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The value is not stored
RAM[A]
D register
RAM[A]and D register
A register
A register and RAM[A]
A register and D register
A register, RAM[A], and D register
jump j1 j2 j3 effect:
null
0
0
0
no jump
JGT
JEQ
JGE
JLT
JNE
JLE
JMP
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
if out > 0 jump
if out = 0 jump
if out ≥ 0 jump
if out < 0 jump
if out ≠ 0 jump
if out ≤ 0 jump
Unconditional jump
Symbolic:
Binary:
MD=D+1
1110011111011000
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
C-instruction: specification and encoding
Symbolic syntax:
dest = comp ; jump
Binary syntax:
1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
comp
0
1
-1
D
A
!D
!A
-D
-A
D+1
A+1
D-1
A-1
D+A
D-A
A-D
D&A
D|A
a==0
Examples:
M
!M
-M
M+1
M-1
D+M
D-M
M-D
D&M
D|M
a==1
c1 c2 c3 c4 c5 c6
dest d1 d2 d3 effect: the value is stored in:
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
null
M
D
MD
A
AM
AD
AMD
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The value is not stored
RAM[A]
D register
RAM[A]and D register
A register
A register and RAM[A]
A register and D register
A register, RAM[A], and D register
jump j1 j2 j3 effect:
null
0
0
0
no jump
JGT
JEQ
JGE
JLT
JNE
JLE
JMP
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
if out > 0 jump
if out = 0 jump
if out ≥ 0 jump
if out < 0 jump
if out ≠ 0 jump
if out ≤ 0 jump
Unconditional jump
Symbolic:
Binary:
M=1
1110111111001000
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
C-instruction: specification and encoding
Symbolic syntax:
dest = comp ; jump
Binary syntax:
1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
comp
0
1
-1
D
A
!D
!A
-D
-A
D+1
A+1
D-1
A-1
D+A
D-A
A-D
D&A
D|A
a==0
M
!M
-M
M+1
M-1
D+M
D-M
M-D
D&M
D|M
a==1
c1 c2 c3 c4 c5 c6
dest d1 d2 d3 effect: the value is stored in:
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
null
M
D
MD
A
AM
AD
AMD
0
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
Symbolic:
Examples:
D+1;JLE
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The value is not stored
RAM[A]
D register
RAM[A]and D register
A register
A register and RAM[A]
A register and D register
A register, RAM[A], and D register
jump j1 j2 j3 effect:
null
0
0
0
no jump
JGT
JEQ
JGE
JLT
JNE
JLE
JMP
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
if out > 0 jump
if out = 0 jump
if out ≥ 0 jump
if out < 0 jump
if out ≠ 0 jump
if out ≤ 0 jump
Unconditional jump
Binary:
1110011111000110
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack program
Symbolic code
// Computes RAM[1] = 1+...+RAM[0]
// Usage: put a number in RAM[0]
@16
// RAM[16] represents i
Observations:
M=1
// i = 1
@17
M=0
// RAM[17] represents sum
// sum = 0
• Hack program:
@16
D=M
@0
D=D-M
@17
D;JGT
@16
D=M
@17
M=D+M
@16
M=M+1
@4
0;JMP
@17
D=M
@1
M=D
@21
0;JMP
a sequence of Hack instructions
• White space is permitted
// if i>RAM[0] goto 17
• Comments are welcome
• There are better ways to write symbolic
Hack programs; stay tuned.
// sum += i
// i++
// goto 4 (loop)
No need to understand ...
we’ll review the code in the next lecture.
// RAM[1] = sum
// program’s end
// infinite loop
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack programs: symbolic and binary
Symbolic code
Binary code
// Computes RAM[1] = 1+...+RAM[0]
// Usage: put a number in RAM[0]
@16
// RAM[16] represents i
M=1
// i = 1
@17
M=0
// RAM[17] represents sum
// sum = 0
@16
D=M
@0
D=D-M
@17
D;JGT
@16
D=M
@17
M=D+M
@16
M=M+1
@4
0;JMP
@17
D=M
@1
M=D
@21
0;JMP
// if i>RAM[0] goto 17
// sum += i
// i++
// goto 4 (loop)
translate
0000000000010000
1110111111001000
0000000000010001
1110101010001000
0000000000010000
1111110000010000
0000000000000000
1111010011010000
0000000000010001
1110001100000001
0000000000010000
1111110000010000
0000000000010001
1111000010001000
0000000000010000
1111110111001000
0000000000000100
1110101010000111
0000000000010001
1111110000010000
0000000000000001
1110001100001000
0000000000010101
1110101010000111
execute
// RAM[1] = sum
// program’s end
// infinite loop
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Input / output
Screen: used to
display outputs
ROM
instruc*ons
data
CPU
I/O handling (high-level):
RAM
Keyboard: used
to enter inputs
Software libraries enabling text, graphics, audio, video, etc.
I/O handling (low-level):
Bits manipulation.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory mapped output
ROM
instruc*ons
data
CPU
screen
RAM
memory
map
Memory mapped output
A designated memory area, dedicated to manage a display unit
The physical display is continuously refreshed from the memory map,
many times per second
Output is effected by writing code that manipulates the screen memory map.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory mapped output
Display Unit (256 by 512, b/w)
Screen
0 1 2 3 4 5 6 7
1111010100000000
1 0000000000000000
0
1
r
ow0
Ÿ
Ÿ
Ÿ
refresh
31 0011000000000001
32 0000101000000000
33 0000000000000000
Ÿ
Ÿ
Ÿ
r
o
w1
Ÿ
Ÿ
Ÿ
Ÿ Ÿ Ÿ
Ÿ Ÿ Ÿ
511
Ÿ Ÿ Ÿ
Ÿ
Ÿ
Ÿ
Ÿ Ÿ Ÿ
255
63 0000000000000000
To set pixel (row,col) on/off:
Ÿ
Ÿ
Ÿ
(1) word= RAM[16384 + 32*row+ col /16]
8159 0000000000000000
8160 0000000000000000
Ÿ
Ÿ
Ÿ
r
ow255
(2) Set the ( col % 16)th bit of word to 0 or 1
(3) RAM[ i ]
= word
8191 1011010100000000
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory mapped output: demo (in the hardware simulator)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Input
ROM
instruc*ons
data
CPU
RAM
Kbd
mem
map
The physical keyboard is associated with a memory-mapped register
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory mapped input
Keyboard
0000000001001011
0000000000000000
0000000000110100
k
Scan-code of ‘k’= 75
When a key is pressed on the keyboard, the key’s scan code appears in the
memory-mapped register
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Memory mapped input
Keyboard
0000000000000000
When no key is pressed, the resulting code is 0.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
The Hack character set
key
code
key code
key code
key code
32
0 48
A 65
a 97
newline
128
! 33
1 49
B 66
b 98
backspace
129
“ 34
… …
C …
c 99
leA arrow
130
# 35
9 57
… …
… …
up arrow
131
Z 90
z 122
right arrow
132
(space)
$ 36
% 37
& 38
:
58
;
59
[
91
{
123
<
60
/
92
|
124
=
61
]
93
}
125
>
62
^
94
~
126
?
63
_
95
@
64
`
96
key
code
down arrow 133
home
134
end
135
Page up
136
Page down
137
insert
138
delete
139
, 44
esc
140
- 45
f1
141
. 46
…
…
/ 47
f12
152
‘ 39
( 40
) 41
* 42
+ 43
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the keyboard
Keyboard
k
0000000001101011
0000000000000000
0000000001001011
Scan-code of ‘k’= 75
To check which key is currently pressed:
• Probe the contents of the Keyboard chip
• In the Hack computer: probe the contents of RAM[24576].
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the keyboard: demo
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
q
Part 1: registers and memory
q
Part 2: branching, variable, iteration
q
Part 3: pointers, input/output
• Project 4 overview
Lecture 8
Machine Language
part two
Based on the slide supporting chapter 4 of the book
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
q
Part 1: registers and memory
-
Part 2: branching, variables, iteration
-
Part 3: pointers, input/output
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack assembly language (overview)
A-instruction:
where value is either a constant or a
@value // A = value
symbol referring to such a constant
C-instruction:
dest= comp; jump
(both dest and jump are optional)
where:
comp =
dest=
jump =
0, 1, -1, D, A, !D, !A, -D, -A, D+1, A+1, D-1, A-1, D+A, D-A, A-D, D&A, D|A
M,
!M,
-M,
M+1,
null, M, D, MD, A, AM, AD, AMD
M-1, D+M, D-M, M-D, D&M, D|M
(M refers to RAM[A])
null, JGT, JEQ, JGE, JLT, JNE, JLE, JMP
Semantics:
• Computes the value of comp
• Stores the result in dest
• If the Boolean expression ( comp jump 0) is true,
jumps to execute the instruction at ROM[A]
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack assembler
Binary code
Assembly program
// Program: Flip.asm
// flips the values of
// RAM[0] and RAM[1]
@R1
D=M
@temp
M=D
// temp = R1
@R0
D=M
@R1
M=D
// R1 = R0
@temp
D=M
@R0
M=D
// R0 = temp
Hack
assembler
0000000000000001
1111110000010000
0000000000010000
1110001100001000
0000000000000000
1111110000010000
0000000000000001
1110001100001000
0000000000010000
1111110000010000
0000000000000000
1110001100001000
0000000000001100
1110101010000111
load &
execute
(END)
@END
0;JMP
We’ll develop a Hack assembler later in the course.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU Emulator
CPU Emulator
Assembly program
// Program: Flip.asm
// flips the values of
// RAM[0] and RAM[1]
@R1
D=M
@temp
M=D
// temp = R1
@R0
D=M
@R1
M=D
// R1 = R0
@temp
D=M
@R0
M=D
// R0 = temp
(END)
@END
0;JMP
load
(the simulator
software
translates from
symbolic to
binary as it
loads)
• A software tool
• Convenient for debugging and
executing symbolic Hack programs.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Registers and memory
D: data register
A: address / data register
M: the currently selected memory register: M = RAM[A]
D register
M register
data
ROM
instrucons
out
CPU
RAM
data
in
A register
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Registers and memory
D: data register
A: address / data register
M: the currently selected memory register: M = RAM[A]
Typical operations:
// D=10
@10
D=A
// D++
D=D+1
// D=RAM[17]
@17
D=M
// RAM[17]=10
@10
D=A
@17
M=D
// RAM[5] = RAM[3]
@3
D=M
@5
M=D
// RAM[17]=D
@17
M=D
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Program example: add two numbers
Memory (ROM)
Hack assembly code
// Program: Add2.asm
// Computes: RAM[2] = RAM[0] + RAM[1]
// Usage: put values in RAM[0], RAM[1]
0
1
@0
D=M
2
3
@1
D=D+M // D = D + RAM[1]
4
5
@2
M=D
// D = RAM[0]
// RAM[2] = D
translate
and load
(white space
ignored)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
@0
D=M
@1
D=D+M
@2
M=D
symbolic
view
ŸŸ
Ÿ
32767
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Program example: add two numbers
Memory (ROM)
Hack assembly code
// Program: Add2.asm
// Computes: RAM[2] = RAM[0] + RAM[1]
// Usage: put values in RAM[0], RAM[1]
0
1
@0
D=M
2
3
@1
D=D+M // D = D + RAM[1]
4
5
@2
M=D
// D = RAM[0]
// RAM[2] = D
translate
and load
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000000000000000
1111110000010000
0000000000000001
1111000010010000
0000000000000010
1110001100001000
binary
view
ŸŸ
Ÿ
32767
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Program example: add two numbers (using the CPU emulator)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Terminating a program
Memory (ROM)
Hack assembly code
// Program: Add2.asm
// Computes: RAM[2] = RAM[0] + RAM[1]
// Usage: put values in RAM[0], RAM[1]
0
1
@0
D=M
2
3
@1
D=D+M // D = D + RAM[1]
4
5
@2
M=D
// D = RAM[0]
// RAM[2] = D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
@0
D=M
@1
D=D+M
@2
M=D
ŸŸ
Ÿ
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Terminating a program
Memory (ROM)
Hack assembly code
// Program: Add2.asm
// Computes: RAM[2] = RAM[0] + RAM[1]
// Usage: put values in RAM[0], RAM[1]
0
1
@0
D=M
2
3
@1
D=D+M // D = D + RAM[1]
4
5
@2
M=D
// D = RAM[0]
// RAM[2] = D
Resulting from some
attack on the computer
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
@0
D=M
@1
D=D+M
@2
M=D
malicious code
starts here...
ŸŸ
Ÿ
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Terminating a program
Memory (ROM)
Hack assembly code
// Program: Add2.asm
// Computes: RAM[2] = RAM[0] + RAM[1]
// Usage: put values in RAM[0], RAM[1]
0
1
@0
D=M
2
3
@1
D=D+M // D = D + RAM[1]
4
5
@2
M=D
6
7
@6
0;JMP
// D = RAM[0]
// RAM[2] = D
• Jump to instruction number A
(which happens to be 6)
• 0: syntax convention for jmp instructions
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
@0
D=M
@1
D=D+M
@2
M=D
@6
0;JMP
ŸŸ
Best practice:
Ÿ
To terminate a program safely, end it with an infinite loop.
– for now!
– there’ll be a better way once we have an operating system
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Built-in symbols
The Hack assembly language features built-in symbols
:
symbol
value
R0
R1
R2
...
R15
0
1
2
...
15
Attention: Hack is case-sensitive!
R5 and r5 are different symbols.
These symbols can be used to denote “virtual registers”
Example: suppose we wish to use RAM[5] to represent some variable,
say x, and we wish to let x=7
implementation:
better style:
// let RAM[5] = 7
@7
D=A
// let RAM[5] = 7
@7
D=A
@5
M=D
@R5
M=D
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Built-in symbols
The Hack assembly language features built-in symbols
:
symbol
value
symbol
value
R0
R1
R2
...
R15
SCREEN
KBD
0
1
2
...
15
16384
24576
SP
LCL
ARG
THIS
THAT
0
1
2
3
4
• R0, R1 ,…, R15 : “virtual registers”, can be used as variables
•
SCREEN and KBD : base addresses of I/O memory maps
• Remaining symbols: used in the implementation of the Hack virtual
machine, discussed in chapters 7-8.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
Part 1: registers and memory
q
Part 2: branching, variables, iteration
Part 3: pointers, input/output
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Branching
example:
// Program: Signum.asm
// Computes: if R0>0
//
R1=1
//
else
//
R1=0
// Usage: put a value in RAM[0],
//
run and inspect RAM[1].
0
1
@R0
D=M
2
3
@8
D;JGT // If R0>0 goto 8
4
5
6
7
@R1
M=0
@10
0;JMP
8
9
@R1
M=1
10
11
@10
0;JMP
// D = RAM[0]
// RAM[1]=0
// goto end
// R1=1
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Branching
example:
// Program: Signum.asm
// Computes: if R0>0
//
R1=1
//
else
//
R1=0
// Usage: put a value in RAM[0],
//
run and inspect RAM[1].
0
1
@R0
D=M
// D = RAM[0]
2
3
@8
D;JGT
// If R0>0 goto 8
4
5
6
7
@R1
M=0
@10
0;JMP
8
9
@R1
M=1
10
11
@10
0;JMP
“I
ns
t
e
a
do
fi
magi
ni
ngt
hato
ur
mai
nt
as
kaspr
ogr
amme
r
si
st
o
i
ns
t
r
uc
tac
omput
e
rwhatt
odo
,
l
e
tusc
onc
e
nt
r
at
er
at
he
ron
e
x
p
l
ai
ni
n
gt
ohu
manb
e
i
ngswh
at
wewantac
omput
e
rt
odo.
”
–Dona
l
dKnut
h
// RAM[1]=0
// goto end
// R1=1
cryptic code
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Branching
example:
// Program: Signum.asm
// Computes: if R0>0
//
R1=1
//
else
//
R1=0
// Usage: put a value in RAM[0],
//
run and inspect RAM[1].
0
1
@R0
D=M
// D = RAM[0]
2
3
referring
to a label
@POSITIVE
D;JGT // If R0>0 goto 8
4
5
6
7
@R1
M=0
@10
0;JMP
// RAM[1]=0
// goto end
8
9
(POSITIVE)
@R1
M=1
// R1=1
10
11
(END)
@END
0;JMP
declaring
a label
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Labels
Memory
example:
// Program: Signum.asm
// Computes: if R0>0
//
R1=1
//
else
//
R1=0
// Usage: put a value in RAM[0],
//
run and inspect RAM[1].
0
1
@R0
D=M
resolving
labels
Label resolution rules:
// D = RAM[0]
2
3
referring
to a label
@POSITIVE
D;JGT // If R0>0 goto 8
4
5
6
7
@R1
M=0
@10
0;JMP
// RAM[1]=0
// goto end
8
9
(POSITIVE)
@R1
M=1
// R1=1
10
11
(END)
@END
0;JMP
declaring
a label
• Label declarations
generate no code
• Each reference to a
label is replaced with
a reference to the
instruction number
following that label’s
declaration.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
@0
D=M
@8
// @POSITIVE
D;JGT
@1
M=0
// @END
@10
0;JMP
@1
M=1
// @END
@10
0;JMP
ŸŸ
Ÿ
32767
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Labels
Memory
example:
// Program: Signum.asm
// Computes: if R0>0
//
R1=1
//
else
//
R1=0
// Usage: put a value in RAM[0],
//
run and inspect RAM[1].
0
1
@R0
D=M
// D = RAM[0]
2
3
referring
to a label
@POSITIVE
D;JGT // If R0>0 goto 8
4
5
6
7
@R1
M=0
@10
0;JMP
// RAM[1]=0
// goto end
8
9
(POSITIVE)
@R1
M=1
// R1=1
10
11
(END)
@END
0;JMP
declaring
a label
resolving
labels
Implications:
• Instruction numbers no
longer needed in
symbolic assembly
• Using symbols means
our code becomes
relocatable
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
@0
D=M
@8
// @POSITIVE
D;JGT
@1
M=0
// @END
@10
0;JMP
@1
M=1
// @END
@10
0;JMP
ŸŸ
Ÿ
32767
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Variables
Variable usage example:
// Program: Flip.asm
// flips the values of
// RAM[0] and RAM[1]
// temp = R1
// R1 = R0
// R0 = temp
@R1
D=M
@temp
M=D
// temp = R1
@R0
D=M
@R1
M=D
// R1 = R0
@temp
D=M
@R0
M=D
// R0 = temp
(END)
@END
0;JMP
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Variables
Memory
Variable usage example:
// Program: Flip.asm
// flips the values of
// RAM[0] and RAM[1]
// temp = R1
// R1 = R0
// R0 = temp
Symbol resolution rules:
symbol
used for the
first time
@R1
D=M
@temp
M=D
// temp = R1
@R0
D=M
@R1
M=D
// R1 = R0
@temp
D=M
@R0
M=D
(END)
@END
0;JMP
resolving
symbols
symbol
used again
// R0 = temp
• A reference to a symbol
that has no corresponding
label declaration is treated
as a reference to a variable
• If the reference @ symbol
occurs in the program for
first time, symbol is
allocated to address 16
onward (say n), and the
generated code is @n
• All subsequent
@ symbol commands are
translated into @n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
@1
D=M
@16 // @temp
M=D
@0
D=M
@1
M=D
@16 // @temp
D=M
@0
M=D
@12
0;JMP
ŸŸ
Ÿ
32767
In other words: variables are
allocated to RAM[16]onward.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Variables
Memory
Variable usage example:
// Program: Flip.asm
// flips the values of
// RAM[0] and RAM[1]
resolving
symbols
// temp = R1
// R1 = R0
// R0 = temp
@R1
D=M
@temp
M=D
Implications:
// temp = R1
@R0
D=M
@R1
M=D
// R1 = R0
@temp
D=M
@R0
M=D
// R0 = temp
symbolic code is easy
to read and debug
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(END)
@END
0;JMP
@1
D=M
@16 // @temp
M=D
@0
D=M
@1
M=D
@16 // @temp
D=M
@0
M=D
@12
0;JMP
ŸŸ
Ÿ
32767
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Iterative processing
pseudo code
// Computes RAM[1] = 1+2+ ... +RAM[0]
n = R0
i = 1
sum = 0
LOOP:
if i > n goto STOP
sum = sum + i
i = i + 1
goto LOOP
STOP:
R1 = sum
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Iterative processing
pseudo code
Memory
// Computes RAM[1] = 1+2+ ... +RAM[0]
n = R0
i = 1
sum = 0
...
assembly code
// Program: Sum1toN.asm
// Computes RAM[1] = 1+2+ ... +n
// Usage: put a number (n) in RAM[0]
@R0
D=M
@n
M=D
// n = R0
@i
M=1
// i = 1
@sum
M=0
...
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
// sum = 0
@0
D=M
@16
M=D
@17
M=1
@18
M=0
...
// @n
// @i
// @sum
Variables are allocated
to consecutive RAM
locations from address
16 onward
ŸŸ
Ÿ
32767
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Iterative processing
pseudo code
// Computes RAM[1] = 1+2+ ... +RAM[0]
n = R0
i = 1
sum = 0
...
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Iterative processing
pseudo code
// Computes RAM[1] = 1+2+ ... +RAM[0]
n = R0
i = 1
sum = 0
LOOP:
if i > n goto STOP
sum = sum + i
i = i + 1
goto LOOP
STOP:
R1 = sum
assembly program
// Computes RAM[1] = 1+2+ ... +n
// Usage: put a number (n) in RAM[0]
@R0
D=M
@n
M=D
// n = R0
@i
M=1
// i = 1
@sum
M=0
// sum = 0
(LOOP)
@i
D=M
@n
D=D-M
@STOP
D;JGT // if i > n goto STOP
@sum
D=M
@i
D=D+M
@sum
M=D
// sum = sum + i
@i
M=M+1 // i = i + 1
@LOOP
0;JMP
(STOP)
@sum
D=M
@R1
M=D
// RAM[1] = sum
(END)
@END
0;JMP
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Program execution
assembly program
// Computes RAM[1] = 1+2+ ... +n
// Usage: put a number (n) in RAM[0]
@R0
D=M
@n
M=D
// n = R0
@i
M=1
// i = 1
@sum
M=0
// sum = 0
(LOOP)
@i
D=M
@n
D=D-M
@STOP
D;JGT // if i > n goto STOP
@sum
D=M
@i
D=D+M
@sum
M=D
// sum = sum + i
@i
M=M+1 // i = i + 1
@LOOP
0;JMP
(STOP)
@sum
D=M
@R1
M=D
// RAM[1] = sum
(END)
@END
0;JMP
iterations
0
RAM[0]
: 3
1
2
3
...
2
3
4
...
1
3
6
...
n: 3
i: 1
sum: 0
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Writing assembly programs
assembly program
// Computes RAM[1] = 1+2+ ... +n
// Usage: put a number (n) in RAM[0]
@R0
D=M
@n
M=D
// n = R0
@i
M=1
// i = 1
@sum
M=0
// sum = 0
(LOOP)
@i
D=M
@n
D=D-M
@STOP
D;JGT // if i > n goto STOP
@sum
D=M
@i
D=D+M
@sum
M=D
// sum = sum + i
@i
M=M+1 // i = i + 1
@LOOP
0;JMP
(STOP)
@sum
D=M
@R1
M=D
// RAM[1] = sum
(END)
@END
0;JMP
Best practice:
•
Design the program using pseudo code
•
Write the program in assembly language
•
Test the program (on paper) using
a variable-value trace table
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
q
Part 1: registers and memory
q
Part 2: branching, variables, iteration
q
Part 3: pointers, input/output
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Pointers
Example:
// for (i=0; i<n; i++) {
//
arr[i] = -1
// }
Observations:
• The array is implemented as a block
of memory registers
• In order to access these memory
registers one after the other, we need a
variable that holds the current address
RAM
RAM
0
0
...
100
10
0
...
arr: 16
n: 17
i: 18
100
101
102
103
.
.
.
a/er 4
iteraons
...
100
10
3
...
-1
-1
-1
-1
arr : 16
n: 17
i: 18
100
101
102
103
.
.
.
• Variables that represent addresses are
called pointers
• There is nothing special about pointer
variables, except that their values are
interpreted as addresses.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Pointers
Example:
// for (i=0; i<n; i++) {
//
arr[i] = -1
// }
// Suppose that arr=100 and n=10
// Let arr = 100
@100
D=A
@arr
M=D
RAM
RAM
0
0
...
100
10
0
...
arr: 16
n: 17
i: 18
100
101
102
103
.
.
.
a/er 4
iteraons
...
100
10
3
...
-1
-1
-1
-1
arr : 16
n: 17
i: 18
100
101
102
103
.
.
.
// Let n = 10
@10
D=A
@n
M=D
// Let i = 0
@i
M=0
// Loop code continues
// in next slide...
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Pointers
Example:
(LOOP)
// if (i==n) goto END
@i
D=M
@n
D=D-M
@END
D;JEQ
// RAM[arr+i] = -1
@arr
D=M
@i
A=D+M
M=-1
RAM
RAM
0
0
...
100
10
0
...
arr: 16
n: 17
i: 18
100
101
102
103
.
.
.
a/er 4
iteraons
...
100
10
3
...
-1
-1
-1
-1
arr : 16
n: 17
i: 18
100
101
102
103
.
.
.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Pointers
Example:
(LOOP)
// if (i==n) goto END
@i
D=M
@n
D=D-M
@END
D;JEQ
// RAM[arr+i] = -1
@arr
typical pointer
D=M
@i
manipulation
A=D+M
M=-1
// i++
@i
M=M+1
@LOOP
0;JMP
(END)
@END
0;JMP
RAM
RAM
0
0
...
100
10
0
...
arr: 16
n: 17
i: 18
100
101
102
103
.
.
.
a/er 4
iteraons
...
100
10
3
...
-1
-1
-1
-1
arr : 16
n: 17
i: 18
100
101
102
103
.
.
.
• Pointers: Variables that store memory
addresses (like arr)
• Pointers in Hack: Whenever we have to
access memory using a pointer, we need
an instruction like A = expression
• Semantics:
“set the address register to some value”.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Output
Hack RAM
0
data
memory
(16K)
SCREEN 16,384
screen
memory map
(8K)
24,576
Hack language convention:
• SCREEN:
base address of the screen memory map
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the screen (example)
50 pixels long
16 pixels wide
Code
RAM
Screen
Task: draw a filled rectangle
at the upper left corner of
the screen, 16 pixels wide
and RAM[0] pixels long
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the screen (example, in the CPU emulator)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the screen (example)
Pseudo code
// for (i=0; i<n; i++) {
//
draw 16 black pixels at the
//
beginning of row i
// }
addr = SCREEN
n = RAM[0]
i = 0
LOOP:
if i > n goto END
RAM[addr] = -1 // 1111111111111111
// advances to the next row
addr = addr + 32
i = i + 1
goto LOOP
END:
goto END
physical
screen
16 black pixels,
corresponding to
the first row of
the rectangle
screen
memory
map
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the screen (example)
Assembly code
// Program: Rectangle.asm
(continued)
// Draws a filled rectangle at the
// screen's top left corner, with
// width of 16 pixels and height of (LOOP)
@i
// RAM[0] pixels.
D=M
// Usage: put a non-negative number
@n
// (rectangle's height) in RAM[0].
D=D-M
@END
@SCREEN
D;JGT // if i>n goto END
D=A
@addr
@addr
M=D // addr = 16384
A=M
// (screen’s base address)
M=-1
// RAM[addr]=1111111111111111
@0
D=M
@i
@n
M=M+1 // i = i + 1
M=D // n = RAM[0]
@32
D=A
@i
@addr
M=0 // i = 0
M=D+M // addr = addr + 32
@LOOP
0;JMP // goto LOOP
(END)
@END
0;JMP
// program’s end
// infinite loop
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the screen (example)
Assembly code
// Program: Rectangle.asm
(continued)
// Draws a filled rectangle at the
// screen's top left corner, with
// width of 16 pixels and height of (LOOP)
@i
// RAM[0] pixels.
D=M
// Usage: put a non-negative number
@n
// (rectangle's height) in RAM[0].
D=D-M
@END
@SCREEN
D;JGT // if i>n goto END
D=A
@addr
@addr
M=D // addr = 16384
A=M
// (screen’s base address)
M=-1
// RAM[addr]=1111111111111111
@0
D=M
@i
@n
M=M+1 // i = i + 1
M=D // n = RAM[0]
@32
D=A
@i
@addr
M=0 // i = 0
M=D+M // addr = addr + 32
@LOOP
0;JMP // goto LOOP
(END)
@END
0;JMP
// program’s end
// infinite loop
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Input
Hack RAM
0
data
memory
(16K)
SCREEN 16,384
screen
memory map
(8K)
KBD 24,576
keyboard map
Hack language convention:
• SCREEN:
base address of the screen memory map
• KBD:
address of the keyboard memory map
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Handling the keyboard
Hack RAM
24576 0000000001001011
k
Scan-code of ‘k’= 75
To check which key is currently pressed:
• Read the contents of RAM[24576] (address KBD)
• If the register contains 0, no key is pressed
• Otherwise, the register contains the scan code of the currently pressed key.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
End notes
Machine language
High level code
for (i=0; i<n; i++) {
arr[i] = -1
}
Low-level programming is:
• Low level
• Profound
• Subtle
• Efficient (or not)
• Intellectually challenging.
Compiler
...
@i
M=0
(LOOP)
@i
D=M
@n
D=D-M
@END
D;JEQ
@arr
D=M
@i
A=D+M
M=-1
@i
M=M+1
@LOOP
0;JMP
(END)
@END
0;JMP
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
-
Part 1: registers and memory
-
Part 2: branching, variable, iteration
-
Part 3: pointers, input/output
• Project 4 overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
In a Nutshell
Project objectives
Have a taste of:
• low-level programming
• Hack assembly language
• Hack hardware
Tasks
• Write a simple algebraic program
• Write a simple interactive program.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Mult: a program performing
R2 = R0 * R1
code
not
shown
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Fill: a simple interactive program
code
code
not
not
shown
shown
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Fill: a simple interactive program
code
code
not
not
shown
shown
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Fill: a simple interactive program
Implementation strategy
• Listen to the keyboard
• To blacken / clear the screen, write code that fills the entire screen
memory map with either “white” or “black” pixels
• (Accessing the memory requires working with pointers)
Testing
• Select “no animation”
• Manual testing (no test scripts).
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Program development process
Prog.asm
Write / edit the
program using a
text editor
Load the program
into the CPU
Emulator, and run it
Find and
fix the
errors
happy
with
results?
Yes
No
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Best practice
Well-written low-level code is
• Short
• Efficient
• Elegant
• Self-describing
Technical tips
• Use symbolic variables and labels
• Use sensible variable and label names
• Variables: lower-case
• Labels: upper-case
• Use indentation
• Start with pseudo code.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Project 4 preview
Your project 4 will be very similar,
but not identical, to the book’s project 4
Not released until week 5, but for now,
try building and running the book’s
examples, using the simulators:
nand2tetris /projects /04
Machine Language: lecture plan
• Machine languages
• Basic elements
• The Hack computer and machine language
• The Hack language specification
• Input / Output
• Hack programming
q
Part 1: registers and memory
q
Part 2: branching, variable, iteration
q
Part 3: pointers, input/output
• Project 4 overview
Lecture 9
Computer Architecture
part one
Based on slides supporting chapter 5 of the book
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer Architecture: lecture plan
• Von Neumann Architecture
• Fetch-Execute Cycle
• The Hack CPU
• The Hack Computer
• Project 5 Overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Universality
Same hardware can run many different software programs
Theory
Practice
Alan Turing:
John Von Nuemann:
Universal Turing Machine
Stored Program Computer
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
intput
data
Ÿ
Ÿ
output
Ÿ
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
Ÿ
Ÿ
data
control
Ÿ
bus
address bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
data
Ÿ
Ÿ
Ÿ
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
ALU
Ÿ
Ÿ
data
control
Ÿ
bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
data
Ÿ
Ÿ
Ÿ
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
Ÿ
Ÿ
data
Ÿ
address bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
Ÿ
Ÿ
data
Ÿ
address bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
Registers
ALU
Ÿ
Ÿ
data
Ÿ
address bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
Ÿ
Ÿ
control
Ÿ
bus
address bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
Ÿ
Ÿ
data
control
Ÿ
bus
address bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer Architecture: lecture plan
• Von Neumann Architecture
• Fetch-Execute Cycle
• The Hack CPU
• The Hack Computer
• Project 5 Overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Basic CPU loop
Repeat:
• Fetch an instruction from the program memory
• Execute the instruction.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Fetching
• Put the location of the next instruction in the Memory address input
• Get the instruction code by reading the contents at that Memory location
Memory
program
Memory
output
instrucon
data
Memory
address
input
• Default: PC++
• Jump: PC =address
Program
Counter
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Executing
• The instruction code specifies “what to do”
q
Which arithmetic or logical instruction to execute
q
Which memory address to access (for read / write)
q
If / where to jump
q
…
different subsets of the
instruction bits control different
aspects of the operation
• Executing the instruction involves:
q
accessing registers
q
and / or:
q
accessing the data memory.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer architecture
Memory
CPU
program
Registers
ALU
Ÿ
Ÿ
data
control
Ÿ
bus
address bus
data bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Fetch – Execute
Memory
data
program
ALU
instrucon
data
instrucon
address
data
address
control
bus
address bus
(data ows not shown, to minimize clu!er)
address bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Fetch – Execute clash
Memory
data
program
ALU
instrucon
data
instrucon
address
data
address
If the Memory is one address space:
This scheme will not work:
• one Memory input
• one Memory output
control
bus
address bus
address bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Fetch – Execute clash
Memory
program
Memory
output
data
If the Memory is one address space:
This scheme will not work:
• one Memory input
• one Memory output
Memory
address
input
instrucon
address
data
address
control
bus
address bus
address bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Solution: multiplex
Memory
program
Memory
output
data
data, when
execung
instrucon,
when
fetching
Memory
address
input
mux
instrucon
address
fetch /
execute
bit
data
address
control
bus
address bus
address bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Solution: multiplex, using an instruction register
Memory
program
data, when
Memory
output
execung
ALU
instrucon
register
data
instrucon
load
on
fetch
Memory
address
input
mux
instrucon
address
fetch /
execute
bit
data
address
control
bus
address bus
address bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Solution: multiplex, using an instruction register
Memory
program
data, when
Memory
output
execung
ALU
instrucon
register
data
instrucon
instrucon
load
on
fetch
Memory
address
input
mux
instrucon
address
fetch /
execute
bit
data
address
control
bus
address bus
address bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Solution: multiplex, using an instruction register
Memory
data
program
Memory
output
ALU
instrucon
register
data
instrucon
instrucon
load
on
fetch
Memory
address
input
mux
instrucon
address
fetch /
execute
bit
data
address
control
bus
address bus
address bus
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Simpler solution: separate memory units
Variant of von Neumann Architecture(used by the Hack computer):
Two physically separate memory units:
q
Instruction memory
q
Data memory
Each can be addressed and manipulated
seperately, and simultaneously
• Advantage:
q
Complication avoided
• Disadvantage:
q
Two memory chips instead of one
q
The size of the two chips is fixed.
Sometmes called
“Harvard Architecture”
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer Architecture: lecture plan
• Von Neumann Architecture
• Fetch-Execute Cycle
• The Hack CPU
• The Hack Computer
• Project 5 Overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack computer
Computer System
CPU
instrucon
input
data out
ALU
instrucon
memory
address
of next
instrucon
data
memory
output
data in
D register
A register
PC
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack CPU
Computer System
CPU
instrucon
input
data out
ALU
instrucon
memory
address
of next
instrucon
data
memory
output
data in
D
register
A
register
PC
Hack CPU: A 16-bit processor, designed to:
• Execute the current instruction: dataOut = instruction(dataIn)
• Figure out which instruction to execute next.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack CPU Interface
d
a
t
ai
n
da
t
aout
r
e
s
t
a
r
t
i
ng
s
i
gna
l
a
d
d
r
e
s
sof
ne
xt
i
ns
t
r
uc
t
i
on
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack CPU Implementation
pc
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack CPU Implementation
pc
(each "C" symbol represents a control bit)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack CPU Implementation
Disclaimer:
•
In what follows we don’t explain all the details of the
CPU implementation, intentionally
•
We give enough information to let you figure out the
implementation on your own, when you will actually
build the CPU in project 5.
pc
(each "C" symbol represents a control bit)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack CPU Implementation
Another disclaimer:
•
These slides describe the 16-bit Hack CPU
•
As before, you’re building a “mostly 8-bit” variant.
The address bus and registers are 16 bits wide, but
the data bus, memory and ALU are 8 bits wide.
The Assessment 2 brief describes what’s different.
•
pc
(each "C" symbol represents a control bit)
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation
pc
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: instruction handling
pc
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: instruction handling
@5
0000000000000101
A-instruction
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: handling A-instructions
@5
0000000000000101
A-instruction
CPU handling of an A-instruction:
• Decodes the instruction into:
q
op-code
q
15-bit value
• Stores the value in the A-register
• Outputs the value (not shown in this diagram).
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: instruction handling
D=D+1;JMP 1110011111010111
C-instruction
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: handling C-instructions
D=D+1;JMP 1110011111010111
C-instruction
CPU handling of a C-instruction:
• Decodes the instruction bits into:
q
q
q
q
Op-code
ALU control bits
Destination load bits
Jump bits
• Routes these bits to their chip-part destinations
• The chip-parts (most notably, the ALU) execute the instruction.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: handling C-instructions
011111
11…01
1110011111010111
10…10
writeM
ALU data inputs:
ALU control inputs:
• Input 1: from the D-register
• control bits
(from the instruction)
• Input 2: from either:
q
A-register, or
q
data memory
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: handling C-instructions
1
0
011111
11…01
01
…
11
1110011111010111
10…10
writeM
0
ALU data output:
• Result of ALU calculation
• Fed simultaneously to: D-register, A-register, data memory
• Which destination actually commits to the ALU output is determined by
the instruction’s destination bits.
CPU operation: handling C-instructions
011111
11…01
01
…
11
1110011111010111
10…10
writeM
ALU control outputs:
• is the output negative?
• is the output zero?
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: control
pc
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: control
reset
reset
computer exterior
(well, kind of)
• The computer is loaded with some program;
• Pushing reset causes the program to start running.
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: control
pc
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: control
16
1
loa
d
pc
16
PC operation (abstraction)
Emits the address of the next instruction:
q
restart:
PC = 0
q
no jump:
PC++
q
goto:
PC=A
q
conditional goto: if ( condition) PC = A else PC++
address of next
instruction
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
CPU operation: control
111 a c c c c c c d d d j j j
16
1
loa
d
pc
16
PC operation (implementation)
if (reset==1 ) PC= 0
else
address of next
instruction
// in the course of handling the current instruction:
load= f (jump bits, ALU control outputs)
if (load == 1) PC= A // jump
else
PC++ // next instruction
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Hack CPU Implementation
pc
That’s It!
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer Architecture: lecture plan
• Von Neumann Architecture
• Fetch-Execute Cycle
• The Hack CPU
• The Hack Computer
• Project 5 Overview
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Lecture 10
Computer Architecture
part two
Based on slides supporting chapter 5 of the book
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press
Copyright Stephen Kell, Noam Nisan, Shimon Schocken. Based on the Nand to Tetris slides by Nisan and Schocken, nand2tetris.org
Computer Architecture: lecture plan
• Von Neumann Architecture
• Fetch-Execute Cycle
• The Hack CPU
• The Hack Computer
• Project 5 Overview
Hack Computer
instrucon
memory
instrucon
data
out
data
memory
CPU
address
data
in
Abstraction:
A computer capable of running programs written in the Hack machine language
Implementation:
Built from the Hack chip-set.
Hack CPU
instrucon
memory
instrucon
data
out
data
memory
CPU
address
data
in
Hack CPU
CPU abstraction:
Executes a Hack instruction and figures out which instruction to execute next
CPU Implementation:
Discussed before.
Hack Computer
✔
instrucon
memory
instrucon
data out
data
memory
CPU
address
data in
Memory
instrucon
memory
instrucon
data out
CPU
address
Memory
data in
Memory: abstraction
load
Memory
0
in
RAM
16
(16K)
out
16,383
address
15
16,384
Screen
(8K
24,575
24,576
16
memory
map)
Keyboard
q
Address 0 to 16383: data memory
q
Address 16384 to 24575: screen memory map
q
Address 24576: keyboard memory map
Memory: implementation
load
Memory
0
in
RAM
16
(16K)
out
16,383
address
15
16,384
Screen
(8K
24,575
24,576
16
memory
map)
Keyboard
q
Address 0 to 16383: data memory
q
Address 16384 to 24575: screen memory map
q
Address 24576: keyboard memory map
RAM
load
Memory
0
in
RAM
16
(16K)
out
16,383
address
15
16,384
Screen
(8K
24,575
24,576
memory
map)
16
built in
project 3
Keyboard
The Hack RAM is realized by the RAM16K chip implemented in project 3.
Screen
Memory
0
in
RAM
16
(16K)
out
16,383
address
16,384
16
Screen
(8K
15
24,575
24,576
memory
map)
Keyboard
Screen memory map
Display Unit (256 by 512, b/w)
Screen
(16384)
0 1 2 3 4 5 6 7
1111010100000000
0
1 0000000000000000
0
1
r
ow0
Ÿ
Ÿ
Ÿ
refresh
31 0011000000000001
32 0000101000000000
33 0000000000000000
Ÿ
Ÿ
Ÿ
r
o
w1
Ÿ
Ÿ
Ÿ
Ÿ Ÿ Ÿ
Ÿ Ÿ Ÿ
511
Ÿ Ÿ Ÿ
Ÿ
Ÿ
Ÿ
Ÿ Ÿ Ÿ
255
63 0000000000000000
To set pixel (row,col) on/off:
Ÿ
Ÿ
Ÿ
(1) word= RAM[16384 + 32* row+ col/16]
8159 0000000000000000
8160 0000000000000000
Ÿ
Ÿ
Ÿ
8191 1011010100000000
r
ow255
(2) Set the (col % 16)th bit of word to 0 or 1
(3) RAM[ i ]
= word
Screen
Memory
0
in
RAM
16
(16K)
out
16,383
address
16,384
16
Screen
(8K
15
24,575
24,576
built-in
chip
memory
map)
Keyboard
• The Hack screen is realized by a built-in chip named Screen
• Screen: a regular RAM + display output side-effect.
Keyboard
Memory
0
in
RAM
16
(16K)
out
16,383
address
15
16,384
Screen
(8K
24,575
24,576
memory
map)
Keyboard
16
Keyboard memory map
Keyboard
0000000001101011
0000000000000000
0000000001001011
k
Scan-code of ‘k’= 75
The Keyboard chip emits the scan-code of the currently pressed key,
or 0 if no key is pressed.
The Hack character set
key
code
key code
key code
key code
32
0 48
A 65
a 97
newline
128
! 33
1 49
B 66
b 98
backspace
129
“ 34
… …
C …
c 99
le: arrow
130
# 35
9 57
… …
… …
up arrow
131
Z 90
z 122
(space)
$ 36
% 37
& 38
‘ 39
( 40
) 41
* 42
:
58
;
59
[
91
{
123
<
60
/
92
|
124
=
61
]
93
}
125
>
62
^
94
~
126
?
63
_
95
@
64
`
96
key
code
right arrow 132
down arrow 133
home
134
end
135
Page up 136
Page down 137
insert
138
delete
139
, 44
esc
140
- 45
f1
141
. 46
…
…
/ 47
f12
152
+ 43
Keyboard
Memory
0
in
RAM
16
(16K)
built-in
chip
out
16,383
address
15
16,384
16
Screen
(8K
24,575
24,576
memory
map)
Keyboard
• Realized by a built-in chip named Keyboard
• Keyboard: A read-only 16-bit register + a keyboard input side-effect.
Memory implementation
load
Memory
0
RAM
RAM
(16K)
(16K)
in
16
out
16,383
address
15
16,384
16
Screen
Screen
(8K
(8K
24,575
24,576
memory
memory
map)
map)
Keyboard
Implementation outline:
• Uses the three chip-parts RAM16K, Screen, and Keyboard(as just described)
• Routes the address input to the correct address input of the relevant chip-part.
Hack Computer
instrucon
memory
instruct.
✔
data out
CPU
address
data in
reset
reset
rese
t
✔
data
memory
Instruction memory
Hack
Hack
Computer
Program
0000000000001101
1110101001010101
0000000000000001
1110101001101011
0000001100110101
1110010111011111
Ÿ
load
Ÿ
instrucon
memory
instruct.
data out
CPU
address
data
memory
data in
Ÿ
1111001001100111
reset
To run a program on the Hack computer:
q
Load the program into the Instruction Memory
q
Press “reset”
q
The program starts running.
Load a program
into the Instruction
Memory? How?
Instruction memory
Hack
Hack
Computer
Program
0000000000001101
1110101001010101
0000000000000001
1110101001101011
0000001100110101
1110010111011111
Ÿ
Ÿ
load
instrucon
memory
instruct.
data out
CPU
address
data
memory
data in
Ÿ
1111001001100111
reset
Loading a program into the Instruction Memory:
• Hardware implementation: plug-and-play ROM chips
(each comes pre-loaded with a program’s code)
• Hardware simulation: programs are stored in text files;
The simulator’s software features a load-program service.
Instruction memory
(from: the
CPU’s pc
output)
address
14
out
ROM32K
16
(to:
the CPU’s
instruction
output)
Built-in
chip
• The Hack Instruction Memory is realized by a built-in chip named ROM32K
• ROM32K: a read-only, 16-bit, 32K RAM chip + program loading side-effect.
Hack Computer implementation
Hack Computer implementation
That’s it!
Hack Computer implementation
“We ascribe beauty to that which is simple; which has no superuous
parts; which exactly answers its end; which stands related to all things;
which is the mean of many extremes.
”
-- Ralph Waldo Emerson
Computer Architecture: lecture plan
• Von Neumann Architecture
• Fetch-Execute Cycle
• The Hack CPU
• The Hack Computer
• Project 5 Overview
Hardware organization: a hierarchy of chip parts
computer
memory
CPU
RAM chips
PC
ALU
adder
registers
elementary
logicgates
Hardware projects
computer
p5
memory
CPU
p5
RAM chips
registers
p5
PC
p3
ALU
p3
p2
adder
p3
p2
elementary
logicgates p1
Project 5: building the Hack Computer
computer
p5
memory
CPU
p5
RAM
p5
PC
chips
ALU
adder
registers
elementary
logicgates
Abstraction
Hack Computer
Implementation
CPU Abstraction
Hack CPU
CPU Implementation
111 a
cccccc
ddd jjj
Implementation tips:
• Chip-parts: Mux16, ARegister, DRegister, PC , ALU , …
• Control: use HDL subscripting to parse and route the instruction bits to the
control bits of the relevant chip-parts.
CPU Implementation
CPU.hdl
/**
* The Central Processing unit (CPU).
* Consists of an ALU and a set of registers,
* designed to fetch and execute instructions
* written in the Hack machine language.
*/
CHIP CPU {
IN
inM[16],
// value of M = RAM[A]
instruction[16], // Instruction for execution
reset;
// Signals whether to re-start the current program
// (reset == 1) or continue executing the current
// program (reset == 0).
OUT
outM[16]
writeM,
addressM[15],
pc[15];
// value to write into M = RAM[A]
// Write into M?
// RAM address (of M)
// ROM address (of next instruction)
PARTS:
// Put you code here:
}
Hack Computer implementation
✔
Memory implementation
Memory
Memory implementation
/** Memory of 16K 16-bit registers */
from
CHIP RAM16K {
project 3
IN
address[14],
in[16],
/** Memory of 8K 16-bit registers
load;
OUT * with a display unit side effect. */
CHIP Screen {
out[16];
built-in
built-in
IN
chips
address[13],
BUILTIN
RAM16K;
in[16],
CLOCKED
in, load;
load;
}
OUT
/** 16-bit register with a
out[16];
* keyboard input side effect */
}
Implementation tips:
CHIP Keyboard {
BUILTIN Screen;
CLOCKED in, OUT
load;
out[16];
BUILTIN Keyboard;
}
• Use the three chip-parts:
RAM16K, Screen, and Keyboard
• Route the address input to the correct address input of the relevant chip-part.
Hack Computer implementation
✔
Implementation tip:
Use the built-in ROM32Kchip.
✔
Hack Computer implementation
✔
✔
✔
Hack Computer implementation
Computer.hdl
/**
* The HACK computer, including CPU, ROM and RAM.
* When reset is 0, the program stored in the computer's ROM executes.
* When reset is 1, the execution of the program restarts.
*/
CHIP Computer {
IN reset;
PARTS:
// Put your code here.
}
Project 5 resources
• Assessment 2 brief (on Moodle very soon)
• HDL Survival Guide
• Hardware Simulator Tutorial
• Feedback system on raptor
• Anonymous Q&A
• Peers in your group
www.nand2tetris.org
Best practice advice
• Try to implement the chips in the given order
• Strive to use as few chip-parts as possible
• You will have to use chips that you’ve implemented in previous projects
• The best practice is to use their built-in versions.
Computer Architecture: lecture plan
• Von Neumann Architecture
• Fetch-Execute Cycle
• The Hack CPU
• The Hack Computer
• Project 5 Overview
From Nand to Tetris
Building
a
Modern
Computer from First Principles
Chapter 5
Computer Architecture
These slides support chapter 5 of the book
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press
Nand to
Tetris /
www.nand2tetris.org /
Chapter
5/
Copyright
©
Noam Nisan and
Shimon
Schocken