IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011
2977
A Switched-Capacitor RF Power Amplifier
Sang-Min Yoo, Member, IEEE, Jeffrey S. Walling, Senior Member, IEEE, Eum Chan Woo, Member, IEEE,
Benjamin Jann, Member, IEEE, and David J. Allstot, Fellow, IEEE
Abstract—A fully integrated switched-capacitor power amplifier
(SCPA) utilizes switched-capacitor techniques in an EER/Polar
architecture. It operates on the envelope of a nonconstant envelope
modulated signal as an RF-DAC in order to amplify the signal
efficiently. The measured maximum output power and PAE are
25.2 dBm and 45 %, respectively. When amplifying an 802.11g
64-QAM orthogonal frequency-division multiplexing (OFDM)
signal, the measured error vector magnitude is 2.6% and the
average output power and power-added efficiencies are 17.7 dBm
and 27%, respectively.
Index Terms—Class-D, CMOS, envelope elimination and
restoration (EER), linearization, polar transmitter, power-added
efficiency, power amplifiers, RF DAC, SCPA, switched-capacitor
circuits.
I. INTRODUCTION
S
CALED CMOS technology is unique in its potential to
fully integrate single-chip radio systems because of its
demonstrated ability to accurately and simultaneously process
analog, digital, and RF signals. Although many examples of
integrated radio subsystems for Bluetooth [1], WLAN [2]–[4],
and cellular telephone systems [5], [6] have been demonstrated,
the RF power amplifier (PA) has yet to be integrated in high
volume in such systems. It remains one of the most challenging
blocks to integrate because it must operate at a high output
power level with high energy efficiency and sufficient linearity
to satisfy system specifications [e.g., margin-to-spectral mask,
error vector magnitude (EVM), and bit error rate (BER)].
Although the additional challenge of coexistence of the RF PA
with sensitive transceiver circuits eventually must be considered, only the ability to efficiently and linearly deliver power
is considered herein.
Scaling of the minimum feature size and power supply
voltage in CMOS technology in accordance with Moore’s Law
has allowed MOSFETs to switch at higher speeds with lower
dynamic power consumption. However, a lower operating
voltage is problematic for an RF PA because it requires the
use of a larger impedance transformation ratio to produce a
Manuscript received April 11, 2011; revised June 20, 2011; accepted July
22, 2011. Date of publication September 06, 2011; date of current version
November 23, 2011. This paper was approved by Guest Editor Hooman Darabi.
S.-M. Yoo, E. C. Woo, and David J. Allstot are with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195 USA (e-mail:
smyoo@uw.edu; sangmin.s.yoo@gmail.com).
J. S. Walling is with the Department of Electrical Engineering, University of
Washington, Seattle, WA 98195 USA, and also with the Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854
USA.
B. Jann is with the Intel Corporation, Hillsboro, OR 97124 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2011.2163469
given output power. For high-output-power applications (e.g.,
1 W), this comes at the cost of increased die area and
resistive losses in the capacitive and inductive elements used in
the impedance transformation network.
The demands placed on a CMOS PA in a modern high-speed
communication system are exacerbated by the use of nonconstant envelope (non-CE) modulation that increases spectral
efficiency by encoding information in both the phase and
amplitude domains (e.g., quadrature amplitude modulation
(QAM), orthogonal frequency division multiplexing (OFDM),
and quadrature phase shift keying (QPSK) with root-raised
cosine filtering). This necessitates a PA that can process signals
with large peak-to-average ratios (PARs). Although CMOS PAs
may never provide the high output power and peak efficiency
levels achievable with expensive nonsilicon technologies, fully
integrated solutions that operate with high average efficiency
can be competitive in many applications.
Because the PA is the dominant energy consumer in a most
RF transceivers, high average efficiency is important because it
leads to longer battery life and greater mobility for the user. This
coupled with increased switching speed has stimulated interest
in more efficient switching PA circuits (e.g., Class-D [7], [8],
-E [9]–[12], and -F [10], [13]), and systems that can be used to
operate them linearly for non-CE modulation. Pulsewidth modulation (PWM) [8], [11], outphasing [7], [14], [15], and envelope elimination and restoration (EER) [9], [16], [17] are three
viable candidates that have been studied extensively for linearizing such switching PAs. All have significant drawbacks. In
the PWM architecture, the minimum output power that can be
transmitted, and hence the dynamic range of the PA, is limited
by the minimum pulsewidth that can be processed without pulse
swallowing. Moreover, the period of the pulse is inversely proportional to frequency so the PWM PA also exhibits frequency
dependence. The minimum output power of the outphasing PA
is limited by load mismatches that occur for large outphasing angles. Another drawback of this architecture is the requirement
for two PAs and an area-consuming passive power-combining
network. The EER architecture performs best for small output
amplitudes but it usually uses a separate analog supply modulator that requires large die area and draws significant bias current that reduces the overall energy efficiency.
There has been considerable interest recently in the so-called
digital PA (DPA) architecture, which uses an array of small
unit-cell PAs that are conditionally connected in parallel according to a digital code word [6], [18], [19]. Some implementations of this technique require a current cell design with
high output impedance for high accuracy and linearity. It is
well known that standard design techniques (e.g., cascodes) increase the required voltage headroom which reduces the overall
energy efficiency. Cascodes are advantageous, however, when
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used to distribute voltage stresses on individual devices to enable operation with a higher power supply voltage [11], [20],
[21]. Finally, because the transfer characteristic of the conventional DPA is approximately linear (saturated) for low (high)
output power levels, extra bits of resolution (i.e., more unit-cell
PAs) are needed when digital predistortion is used to enhance
the overall linearity. In this paper, we introduce a DPA architecture that achieves output amplitude control by precisely controlling charge transfer in a capacitor array. The switched-capacitor PA (SCPA) comprises an array of capacitors that are either
switched at the RF carrier frequency between the supply voltage
and ground or held at a signal ground, depending on a digital
code word applied at the sampling rate that represents the amplitude of the envelope [22]. The SCPA technique does not suffer
the same nonidealities as the conventional DPA but achieves
high accuracy by exploiting the precision capacitance ratios that
CMOS traditionally provides. Moreover, the technique eliminates auxiliary analog/mixed signal circuitry (e.g., no separate
power supply modulator), scales easily depending on the resolution required for the chosen application, and, in contrast to most
previous approaches, benefits from CMOS technology scaling.
The theory of operation for the SCPA is detailed in Section II.
Circuit details and experimental results are presented in
Sections III and IV, respectively, and conclusions are given in
Section V.
Fig. 1. Block diagram of an ideal single-ended SCPA.
Fig. 2. Top-plate and output amplitudes versus switched and not switched capacitors.
II. THEORY OF OPERATION
A. Ideal Operation
The switched-capacitor technique has been used in
high-volume data conversion and mixed-signal processing
applications for more than three decades [23]–[25]. SC
circuits exploit capacitors, which are area-efficient, native
devices in CMOS technologies, precision capacitor ratios
realized using well-known design and layout techniques, and
MOSFET switches. SC techniques are also ubiquitous in current state-of-the-art RF transceivers while continued CMOS
scaling promises direct switching at RF frequencies in future
systems.
An SCPA comprises an array of precision capacitors and a
bandpass matching network (Fig. 1). Depending on an applied
digital code proportional to the amplitude of the envelope
signal, selected bottom plates are switched at the RF carrier
and
. Unselected capacitors
frequency between
are not switched but remain connected to a signal ground
or
. The total capacitance connected to the
(i.e.,
matching network remains constant because no top-plate is ever
switched. The bandpass matching network filters the top-plate
voltage and transforms the impedance of the antenna from 50
to 4 so that high output power can be generated. Note that
the SCPA operates like a class-D PA with a capacitive voltage
divider in series resonance with the matching network.
Digital logic driven by the code bits selects the capacitors
and
whose bottom plates are switched between
and those held at
or
and not switched
(Fig. 2). Thus, a square wave at the RF carrier frequency can
be generated at the top-plate terminal that is quantized in
Fig. 3. Thévenin equivalent circuit of the SC array seen from the matching
network.
accordance with the total number of bits and the total array
capacitance,
(1)
Another way to view this is to derive the Thévenin equivalent circuit for the general case shown in Fig. 3. The Thévenin
scaled by
,
voltage is the source voltage (e.g.,
where is the number of unit capacitors whose bottom plates
and
and is the total number
are switched between
of capacitors. The Thévenin impedance is just that of the total
capacitance at the top plate of the array. Again, note that the topplate capacitance is constant versus envelope amplitude (i.e.,
digital code); hence, the frequency response is fixed and the
bandpass matching network does not need to be tuned versus
envelope amplitude.
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YOO et al.: A SWITCHED-CAPACITOR RF POWER AMPLIFIER
Fig. 4. Equivalent circuit for the calculation of P
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.
Fig. 5. Equivalent circuits for the calculation of P . The inductor approximates a constant current source (i.e., an open circuit) during fast switching
transitions.
B. Output Power and Efficiency
To calculate the output power, the Thévenin equivalent circuit is connected in series with an inductor and resistor
(Fig. 4). The inductor represents the excess reactive impedance
is the optimum terof the bandpass matching network and
) for the desired output power
mination resistance (e.g.,
level. Because of the bandpass nature of the structure, only the
fundamental component at the RF carrier frequency flows to the
output:
Fig. 6. Comparison of ideal PAE versus P
eral SCPAs.
for a conventional DPA and sev-
Ideal power-added efficiency is defined as
(7)
Substitution of (3)–(6) into (7) yields
(2)
is the voltage switched at the bottom plates and
where
is the first coefficient of the Fourier series. Thus, the output
power is
(3)
The dynamic power required to charge and discharge the
is needed to compute the overall efficiency
array
(4)
where
is the input capacitance driven through the selected
switches and is the RF carrier frequency. An equivalent circuit model of this operation is shown in Fig. 5. If the switching
waveforms have sharp edges, it is reasonable to assume that the
inductor, , behaves as a constant current source (i.e., an open
is simply the
circuit) during the transition times. Therefore,
series combination of the two capacitances
(5)
Finally, the loaded quality factor of the network is defined as
(6)
(8)
This important result is validated using Spectre RF behavioral
simulations with ideal passive components and ahdl-modeled
versus output power characteristics for
switches. The
a conventional DPA and several SCPAs with different
values are compared in Fig. 6. The ideal peak efficiency is 100%
in all cases. However, the PAE of the DPA rolls off as the square
root of the output power [18], [19], whereas the SCPA designs
are more efficient at typical power backoff levels. An important
conclusion is that the SCPA always offers higher PAE and average efficiencies for typical modulation envelopes.
Several additional losses should be considered to better estimate the PAE of an SCPA:
(9)
where is an empirical attenuation factor associated with parasitic losses in the passive elements used in the matching network, represents losses caused by the ON resistance of the
, and
are dynamic power losses
switches, and
owing to the switch
, switch driver
, and clock disparasitics, respectively, and are detribution network
fined as
means less capacitance and dynamic
Although higher
power loss, its maximum value is limited by the of the inductor; typical on-chip values (e.g., 10–15) limit
to
–3 for fully integrated CMOS implementations.
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(10)
(11)
(12)
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011
Fig. 7. Nonoverlapping clocks are used to mitigate crowbar currents.
Several important observations follow from these equations.
First, the losses are less at typical output power backoff levels
) because fewer devices are switched. Fundamen(i.e.,
tally, the PAE of the SCPA increases with CMOS technology
scaling because of the reduced capacitive parasitics. For higher
RF carrier frequencies, however, the requirement for wider
switches increases dynamic power consumption in the driver
chain which reduces PAE. A useful rule-of-thumb to minimize
attenuation at the output is that the ON resistance of the switches
. Optimization is recommended
should be much less than
in order to finalize the switch sizes.
Another power loss owes to the crowbar current that flows
when series nMOS and pMOS devices both remain ON during
switching transitions. Nonoverlapping clocks, wherein it is
guaranteed by timing that only one switch is ON during an
output transition, are commonly used to mitigate this problem
(Fig. 7). Moreover, if the output matching network is designed
to appear slightly more inductive to the switches, lagging
current from the resonant tank partially charges or discharges
which reduces
.
the parasitic capacitances
C. AM–PM and AM–AM Distortion
An SCPA does not suffer the same efficiency/linearity tradeoffs as a conventional DPA. An SCPA with ideal switches and
capacitors is perfectly linear with no amplitude or phase distortion of the signal, i.e., the switching waveforms applied to the
bottom plates of selected capacitors are ideal square waves.
In reality, of course, various imperfections that depend on the
envelope amplitude code alter the timing and shape of the waveforms and give rise to AM–PM and AM–AM distortion. To gain
an intuitive understanding of this concept, consider the simple
2-b SCPA of Fig. 8(a), where the envelope amplitude code is
, and Fig. 8(b), where
. Assume the
pMOS and nMOS devices have constant ON resistances of
and
, respectively, and neglect all other nonideal effects including parasitic capacitances, resistances, and nonlinearities.
Based on the code bits, the bottom plate of each selected capacitor is charged from
to
via a pMOS switch while
the bottom plate of each unselected capacitor is connected to
via an nMOS device. If
, the charging networks are identical for the two circuits so no AM-PM distor, in a typical design,
tion is generated. Because
the RC charging network of Fig. 8(a) is different than that of
Fig. 8(b). As a consequence, envelope amplitude modulation is
transferred to the time domain as a change in the phase modulation—AM–PM distortion. Similar effects are responsible for
AM–AM distortion.
The origin of AM–PM and AM–AM distortion can also be
understood from Fig. 9(a) and the Thévenin equivalent circuit of
Fig. 9(b), wherein is the effective source resistance seen from
the output matching network. In the ideal case when
,
all of the available power is delivered from the source to the
output load, i.e., there are no losses or nonlinear effects due
to the switch resistances, and hence, no generation of AM–PM
or AM–AM distortion. Moreover, there is no distortion when
if it remains constant for different envelope amplitude
codes.
Imperfections that depend on the envelope amplitude code
and ultimately cause AM–PM and AM–AM distortion include
the following.
• The source impedance depends on the envelope amplitude
code. The bottom-plate voltage is generated using a CMOS
switch for each selected capacitor; hence, changes with
the selected number of bottom-plate CMOS switches. For
[Fig. 9(a)], all capacitor
full amplitude operation,
bottom-plates are switched during every cycle of the RF
carrier frequency so is the overall effective average ON
resistance of
bottom-plate CMOS switches in parallel.
unselected
For smaller amplitudes, however, the
and not switched. Now,
capacitors are connected to
is the overall effective average ON resistance including
the effects of the bottom-plate CMOS switches in parallel
bottom-plate nMOS devices connected
and the
. Moreover,
changes dynamically
in parallel to
during the RF clock cycle; it involves
nMOS devices
nMOS
during one half cycle and pMOS and
devices during the other.
value is also affected by the
power
• The effective
supply and
ground line parasitics.
• The switching times at the input and output of MOS transistors are nonzero. Hence, there is a brief period of very
high output impedance, compared to the ON resistance,
when neither device is completely ON during the output
transition of a bottom-plate CMOS switch. This effect also
depending on the number of capacitors selected
alters
by the envelope amplitude code.
• Another interesting effect occurs during the nonoverlapping period when both devices in the CMOS bottom-plate
switches are OFF. During this brief interval, lagging current that continues to flow from the matching network interacts with various nonlinear parasitics associated with the
CMOS switches.
• All of the effects described above are exacerbated with the
use of cascode pMOS and nMOS switches. First, there
are more nonlinear parasitic resistors and capacitors than
in the simple CMOS switch. Second, it takes longer for
the cascode structure to switch which means more time
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YOO et al.: A SWITCHED-CAPACITOR RF POWER AMPLIFIER
Fig. 8. A 2-b SCPA wherein selected bottom-plates are charged from
n=N
= .
=34
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V
to
V
corresponding to envelope amplitude codes of (a)
n=N
= 1=4 and (b)
Fig. 9. (a) An SCPA wherein the bottom-plates of n selected capacitors are switched between V
and V
by CMOS switches and the bottom-plates of
N n unselected capacitors are not switched but connected to V
by nMOS switches. (b) A Thévenin equivalent circuit where r is the effective resistance
seen from the output matching network, and (c) simulations of an SCPA illustrating the code-dependent origins of AM–PM and AM–AM distortion.
( 0 )
in the problematic output high-impedance state. Hence,
the overall output impedance variation during a switching
event is much greater than for a simple CMOS switch.
The nonideal switching effects described above cause the effective source resistance to change dramatically and dynamically as a function of the envelope amplitude code. As a consequence, the delays and shapes of the switching waveforms
change with amplitude [Fig. 9(c)] which causes AM–PM distortion. The impact of these effects is minimized by careful layout
and circuit design techniques. AM–PM distortion is improved
with CMOS scaling because of the smaller channel resistances
and faster transition times between states.
AM–AM distortion is caused by the same effects as above. It
is small in an SCPA because of the excellent capacitor matching
achievable in CMOS technologies and it should be reduced even
more with scaling.
III. CIRCUIT DETAILS
A top-level schematic of a single-ended SCPA is shown in
Fig. 10. A CORDIC processor (not shown and not implemented
on chip) converts each Cartesian modulation symbol to an
equivalent polar form and inputs the resulting phase (PM) and
envelope amplitude (AM) information to the SCPA. The PM
component is upconverted to the RF carrier frequency to create
the phase input signal, . A clock generator converts into
and
,
nonoverlapping differential switching waveforms,
that are applied to selected drivers to switch selected bottom
, which
plates of the capacitor array. A digital code word,
represents the AM component (i.e., a sampled value of the
envelope amplitude) is also input to the SCPA.
System simulations predict that 6-b code words should
provide sufficient reconstruction accuracy to meet EVM and
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011
Fig. 11. Bit-slice circuitry that selectively switches the bottom plate of one
capacitor in the array.
Fig. 10. Top-level schematic of a single-ended SCPA; the actual implementation is fully-differential.
margin-to-spectral mask specifications for IEEE 802.11g
– , of
are
64-QAM OFDM signals. The four MSBs,
applied to a binary-to-thermometer decoder that selects the
drivers and switches that are connected to the bottom plates
–
of selected unary capacitors; likewise, the two LSBs
control bottom-plate switching for the binary-weighted capacitors. The digital circuits use static logic techniques to minimize
power dissipation. The SCPA is designed in a 90-nm RF LP
CMOS process with eight metal layers (including an ultrathick
metal layer) and MIM capacitors, and laid out in a bit-slice
format (Fig. 10) to facilitate scaling of the resolution. Circuit
details are described in the next sections.
Fig. 12. Microphotograph of the prototype SCPA in 90-nm CMOS.
A. Output Matching Network
Choosing the total array capacitance in an SCPA is important
in the design of the output matching network because it has a
significant impact on efficiency. To demonstrate this point, (3) is
(i.e.,
) to find the termination
inverted at maximum
as
resistance
(13)
Recall that
– as limited by
– of the
determined from (13), the
on-chip spiral inductors. With
total array capacitance is found from (6) to yield
(14)
As described earlier, PAE is reduced by the dynamic power
required to charge and discharge the bottom plates of the selected capacitors. Specifically,
is proportional to the bottom, which is determined by
plate capacitance that is switched,
the envelope amplitude code;
is
Fig. 13. Measured output power and PAE versus frequency.
maximum for
and minimum for
and
.
Hence,
is also parabolic with respect to the envelope amplitude. This effect on efficiency is important for signals with large
peak-to-average ratios wherein midrange envelope amplitudes
are most probable. A practical design approach is to first choose
for maximum
, and then optimize its value to achieve the
highest average PAE for the probability density function of the
envelope amplitudes.
The switching action of the SCPA generates high-order harmonics at the output of the capacitor array. An ideal bandpass
matching network eliminates all such spurious content; in reality, the suppression of harmonics is limited by the finite
factor. For this reason, matching networks that effectively block
harmonic components are favored, i.e., networks with inductors
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YOO et al.: A SWITCHED-CAPACITOR RF POWER AMPLIFIER
Fig. 14. Measured (a) P
versus envelope amplitude and (b) PAE versus P
Fig. 15. Measured distortion versus input code.
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.
Fig. 16. Measured INL and DNL.
connected in series with the output (e.g., the tapped-inductor
matching network of Fig. 10) are desirable.
B. Bit Slice Design
Layout parasitic capacitances are minimized to reduce dynamic power losses and maximize efficiency. Hence, all top
plates are connected whereas the bottom plates are laid out in a
pitch-matched format for the bit-slice circuit shown in Fig. 11.
This approach facilitates scaling of the resolution of the SCPA.
used with nanometer CMOS technologies is
The low
the main limitation on the peak output power of an SCPA. Reis increased either by increasing
or
call from (3) that
decreasing
. However, only reducing
to increase
is not a complete solution because losses in the matching net;
work are related to the ratio of the antenna impedance to
losses caused by power/ground line impedances are also signifis desired.
icant. Hence, a technique that increases
Consider the bit-slice circuitry of Fig. 11. It uses an envelope
and logic circuits to gate
and
into the cordata bit
responding switch drivers. The nonoverlapping outputs of the
Fig. 17. Measurement setup for characterizing the dynamic performance of the
SCPA.
switch drivers control the nMOS (PMOS) switches
that discharge (charge) the bottom plate of the selected capacitor. The cascoded switch topology of Fig. 11 allows the bottomand it
plate switches of the SCPA to operate from 0 to 2
minimizes the voltage stresses on individual devices [20]. The
nMOS and pMOS switches are sized for small ON resistances
and to switch the bottom plate of the secompared with
lected capacitor at the RF carrier frequency. A level-shifting circuit is required in the pMOS switching path because the pMOS
and
. A detailed descripcascode operates between
tion of this circuit is given by Serneels et al. [20].
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011
Fig. 18. Measured dynamic output characteristics for IEEE 802.11g 64-QAM OFDM signals.
IV. EXPERIMENTAL RESULTS
The SCPA was fabricated in a 90-nm RF LP CMOS process
with eight layers of metallization (including an ultrathick
layer), and it occupies an area of 1.4 mm 0.7 mm including
the bonding and probe pads, as shown in Fig. 12. It comprises a 6-b array of precision MIM capacitors, six bit-slice
bottom-plate switching circuits, and a fully integrated output
matching network. All circuits operate from 1.5 V except for
the cascode bottom-plate switches which operate from 3 V. It is
clear from the microphotograph that additional bits for higher
resolution are easily added with little area penalty.
A. Static Measurements
Measured
and PAE for the maximum envelope ampliwas designed to be 2–3 astude are plotted in Fig. 13.
values of 10–15 for the on-chip inductors. Fig. 13
suming
gives a 3-dB bandwidth of about 1 GHz, in good agreement
.
with
versus envelope amplitude code, and
Fig. 14(a) plots
. The peak
is 25.2 dBm
Fig. 14(b) depicts PAE versus
and the peak PAE is 45%.
varies quadratically with envelope amplitude as expected from (3), and the PAE rolls off with
as predicted from (8), (9), and Fig. 6. The theoretreduced
ical
and PAE performance characteristics are also shown
8.2 pF,
,
for
and
; these empirical constants were obtained
from simulations of the extracted layout. Generally, the measured performance is in good agreement with the theoretical
analysis.
AM–AM and AM–PM distortion are measured to determine
the linearity of the SCPA and its suitability for digital predistortion. Predistortion is applied effectively only if the distortion is predictable and mild so that post-predistortion changes
due to process, voltage, and temperature variations are minimal. Predistortion is suitable because the SCPA exhibits only a
mild second-order nonlinearity (Fig. 15). Note that the AM–PM
characteristic shows ripples for small envelope amplitudes. To
a first order, this effect is caused by switching binary-weighted,
rather than unary-weighted, LSB capacitors. Although the LSB
bit slices were also designed to be binary-weighted to the degree
possible, there are unavoidable differences that cause errors in
timing that manifest as AM-PM distortion. The AM–AM performance of the SCPA is superior because of the high precision
of capacitance ratios in CMOS processes.
Because the SCPA is essentially an RF-DAC, the integral
(INL) and differential (DNL) nonlinearity characteristics are
also measured. Excellent performance is achieved: INL is
less than 3 LSB and DNL is less than 0.5 LSB at
25.2 dBm, as shown in Fig. 16. These results are another
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Fig. 19. Measured (a) far-out and (b) close-in output power spectral densities for IEEE 802.11g signals amplified by the SCPA.
TABLE I
COMPARISON OF THE SCPA TO PRIOR-ART CMOS POWER AMPLIFIERS
indication that robust predistortion can be used to improve
linearity.
B. Dynamic Measurements
The dynamic performance of the SCPA is evaluated by inputting a non-CE modulated signal and measuring the spectral
mask and EVM relative to target specifications. For these measurements, a predistorted IEEE 802.11g 64-QAM OFDM WiFi
signal is applied to the PA using the measurement setup detailed
in Fig. 17. The predistortion is accomplished first by measuring
the static AM–AM and AM–PM distortion characteristics and
then subtracting the distortion from the original AM and PM
polar signal components. The AM (PM) signal is loaded into a
digital pattern (vector signal) generator. The two signals are synchronized using the 10-MHz reference signal combined with the
trigger signal from the vector signal generator. A vector signal
analyzer downconverts the signal to baseband and demodulates
it.
Fig. 18 shows the measured EVM (lower right) and in-band
power spectrum (lower left). The measured EVM of 2.6%-rms
is well below the specification of 5.6% rms. Excellent EVM
performance is also observed in the demodulated constellation
diagram (upper left) wherein the measured data points are close
to their ideal locations.
As shown in Fig. 19, the measured PSD characteristics
violate the IEEE 802.11g spectral mask specifications. Because
these violations are not systemic, however, several design options can mitigate problematic spectral impurities. The aliased
signals around the RF carrier frequency caused by sampling
the envelope at 160 MHz [Fig. 19(a)] are attenuated by the
sinc function associated with the zeroth-order hold; hence, the
aliased artifacts are reduced simply by increasing the sampling
frequency. The use of more sophisticated signal processing
techniques (e.g., a first-order hold function) also increases the
attenuation of the aliased terms [18], [26]. Finally, the close-in
shoulder height [Fig. 19(b)] is reduced with better time alignment of the AM and PM components [27]. Mitigation of this
measurement issue can be achieved by better synchronization
of the independent AM and PM signal generators and by processing the signals closer to the chip interfaces. As a practical
matter, it is difficult to synchronize the signal generators with
such wideband signal modulation.
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2986
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011
An overall goal in using EER/Polar techniques is to increase
the average PAE of the PA as
(14)
and
are the maximum and minimum envelope
where
is the probability density funcvoltages, respectively, and
tion of the envelope of the modulated signal. While amplifying
IEEE 802.11g 64-QAM OFDM signals, the SCPA achieves an
of 17.7 dBm.
average PAE of 27% with an average
V. CONCLUSION
A switched-capacitor PA for EER/polar transmitters is described. Through the use of CMOS switches and capacitor ratios
as precision elements, the SCPA achieves superior linearity and
efficiency performance. The theoretical operation is described
and a design methodology is proposed. Unlike many previous
PA approaches, the linearity and efficiency characteristics are
improved using scaled CMOS processes because of the faster
switches with smaller parasitics. A prototype fabricated in a
and PAE values of
90-nm CMOS process achieves peak
25.2 dBm and 45%, respectively. The potential to function
as part of an EER transmitter is validated by applying IEEE
802.11g 64-QAM OFDM signals; excellent EVM (2.6%-rms)
and average PAE performance (27%) is achieved. The SCPA is
compared to other recent CMOS PAs in Table I.
ACKNOWLEDGMENT
The authors would like to thank Intel Corporation for valuable
measurement assistance.
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YOO et al.: A SWITCHED-CAPACITOR RF POWER AMPLIFIER
Sang-Min Yoo (M’11) received the B.S and M.S. degrees from Sogang University, Seoul, Korea, in 2000
and 2002, respectively, and the Ph.D. degree in electrical engineering from the University of Washington,
Seattle, in 2011.
From 2002 to 2007, he was with Samsung Electronics, Yongin, Korea, where he designed data converters and baseband analog circuits. He held internship position at Mobile Wireless Group at Intel, Hillsboro, OR, from 2010 to 2011, where he was involved
with the design of high-efficiency transmitter. His research interest includes RF and analog/mixed-signal circuits.
Dr. Yoo was the recipient of the Analog Devices Outstanding Student Designer Award in 2009.
Jeffrey S. Walling (SM’11) received the B.S. degree
from the University of South Florida, Tampa, in 2000,
and the M.S. and Ph.D. degrees from the University
of Washington, Seattle, in 2005 and 2008, respectively.
Prior to starting his graduate education, he was
with Motorola, Plantation, FL working in cellular
handset development. He interned for Intel, Hillsboro, OR, from 2006 to 2007, where he worked on
highly digital transmitter architectures and CMOS
power amplifiers. He is currently an Assistant
Professor with Rutgers, The State University of New Jersey, Piscataway, NJ.
His current research interests include low-power wireless circuits, energy
scavenging, high-efficiency transmitter architectures, and CMOS power amplifier design. He has authored or coauthored over 20 articles in peer-reviewed
journals and refereed conferences.
Dr. Walling received the Yang Award for outstanding graduate research from
the University of Washington, Department of Electrical Engineering, in 2008,
an Intel Predoctoral Fellowship in 2007–2008, and the Analog Devices Outstanding Student Designer Award in 2006.
Eum Chan Woo (M’09) received the B.S. and M.S.
degrees in electronics from Changwon National
University, Changwan, South Korea, in 2005 and
2007, respectively, and the M.S. degree in electrical engineering from University of Washington,
Seattle, in 2009. His research and thesis focused on
analog/mixed signal/RF CMOS integrated circuit
design.
He has authored or coauthored a number of
publications on RF/mixed signal circuits as well as
memory circuit design. From 2009 to 2011, he was
with Telegent Systems, Sunnyvale, CA, working on free-to-air analog/digital
mobile TV receiver circuits. Currently he is with Broadcom Corporation,
Sunnyvale, CA. His research interests include integrated CMOS RF/wireless
communication circuit design.
2987
Benjamin Jann (M’05) received the B.S. and M.S.
degrees in electrical engineering from Oregon State
University, Corvallis, in 2000 and 2005, respectively.
From 2000 to 2002, he was with Network Elements Inc., designing optical transceiver modules.
In 2005, he joined the Mobile Wireless Group, Intel
Corporation, Hillsboro, OR, where he is currently an
RFIC Design Engineer.
David J. Allstot (S’72–M’72–SM’83–F’92) received the B.S. degree from the University of
Portland, Oregon, the M.S. degree from Oregon
State University, Corvallis, and the Ph.D. degree
from the University of California, Berkeley.
He has held several industrial and academic
positions and has been the Boeing-Egtvedt Chair
Professor of Engineering at the University of Washington since 1999. He was Chair of the Department
of Electrical Engineering from 2004 to 2007. He
is currently on sabbatical as a Visiting Professor of
Electrical Engineering with Stanford University, Stanford, CA. He has advised
approximately 100 M.S. and Ph.D. graduates and published about 300 papers.
Dr. Allstot was the recipient of several awards for outstanding teaching and
graduate advising. Awards include the 1980 IEEE W.R.G. Baker Award, the
1995 and 2010 IEEE Circuits and Systems Society (CASS) Darlington Award,
1998 IEEE International Solid-State Circuits Conference (ISSCC) Beatrice
Winner Award, 1999 IEEE CASS Golden Jubilee Medal, 2004 IEEE CASS
Technical Achievement Award, 2005 Semiconductor Research Corporation
Aristotle Award, 2008 Semiconductor Industries Assoc. University Research
Award, and 2011 IEEE CASS Mac Van Valkenburg Award. His service
includes: 1990–1995 Associate Editor and Editor of IEEE TCAS, 1990–1993
Member of Technical Program Committee of the IEEE Custom IC Conference,
1992–1995 Member, Board of Governors of IEEE CASS, 1994–2004 Member,
Technical Program Committee, IEEE ISSCC, 1996–2000 Member, Executive
Committee of IEEE ISSCC, 1996–2000 Short Course Chair of IEEE ISSCC,
2000–2001 Distinguished Lecturer, IEEE CASS, 2001 and 2008 Co-General
Chair of IEEE ISCAS, 2006–2007 Distinguished Lecturer, IEEE Solid-State
Circuits Society, and 2009 President of IEEE CASS.
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