CoAsia SEMI VN
REPORT: PHYSICAL DESIGN
Author: PHAN VAN MINH THUAN
REVISION HISTORY
Revision Author
Date
Description of changes
0.1
Thuan
05/03/2024
Complete lab 0: IC Compiler II GUI
1.1
Thuan
05/03/2024
Complete lab 2: Floorplanning
2.1
Thuan
12/03/2024
Complete lab 3: Placement and optimization
3.1
Thuan
12/03/2024
Complete lab 5: Design setup
4.1
Thuan
17/03/2024
Complete lab 7: Running CTS
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5.1
Thuan
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25/03/2024
Complete lab 8: Clock Tree Synthesis
Complete lab 11:Routing and Post –Route
Optimization, Signoff
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TABLE OF CONTENTS
Contents
REVISION HISTORY ......................................................................................................................................................0
TABLE OF CONTENTS .................................................................................................................................................2
1. Lab 0: IC COMPLIER GUI ........................................................................................................................................5
1.1. Launch IC Compiler II .....................................................................................................................................5
1.2. Navigating the layout view ...........................................................................................................................5
1.3. Controlling logic and layer visibility .........................................................................................................8
1.4. Layer tab ..............................................................................................................................................................9
1.5. Controlling the view level .......................................................................................................................... 11
1.6. Timing analysis .............................................................................................................................................. 12
2. Lab 2: Floorplaning ............................................................................................................................................... 13
2.1. Initial Floorplanning using the Task Assistant .................................................................................. 13
2.2. Bocking Shaping ............................................................................................................................................ 16
2.3. Macro and Standard Cell Placement ...................................................................................................... 17
2.4. Place the block port ...................................................................................................................................... 18
2.5. Task 6 : Congestion map ............................................................................................................................. 20
2.6. Analyze Macro Placement using DFF .................................................................................................... 21
2.7. Task 8: Register Tracing ............................................................................................................................. 23
2.8. Remove PG Routes:....................................................................................................................................... 26
2.9. Power network synthesis .......................................................................................................................... 27
3. Lab 3: Placement and optimization ................................................................................................................ 27
3.1. Load and check initial design ................................................................................................................... 27
3.2. Task 2: Place and optimize the Design: ................................................................................................ 28
4. Lab 5 : Design setup .............................................................................................................................................. 33
4.1. Directory Structure and Invoking ICC II ............................................................................................... 33
4.2. Setup Variables and Settings .................................................................................................................... 33
4.3. Design Library, Netlist and UPF .............................................................................................................. 35
4.4. Load Floorplan and Scan-DEF .................................................................................................................. 41
4.5. Placement Site and Routing Layer Settings ........................................................................................ 42
5. LAB 6: TIMING SETUP ......................................................................................................................................... 43
5.1. Open the block from lab 5 .......................................................................................................................... 43
5.2. Multi-Corner Multi-Mode Setup .............................................................................................................. 43
5.3. Zero-Interconnect (ZIC) Timing Sanity Check ................................................................................... 47
6. LAB 7: RUNING CTS .............................................................................................................................................. 49
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6.1. Timming QoR summary .............................................................................................................................. 49
6.2. Post-CTS I/O Latency ................................................................................................................................... 52
6.3. Run Comprehensive Clock Tree Checking ........................................................................................... 52
6.4. Option A: Perform Classic CTS: ................................................................................................................ 55
6.5. Option B: Concurrent Clock & Data Flow: ........................................................................................... 58
6.6. Analysis ............................................................................................................................................................. 59
7. Lab 8 : Clock Tree Synthesis .............................................................................................................................. 62
7.1. Load the Design and Analyze the Clocks .............................................................................................. 62
7.2. Clock Tree Balancing ................................................................................................................................... 64
7.3. Define CTS Non-Default Routing Rules: ............................................................................................... 69
7.4. Timing and DRC Constraints..................................................................................................................... 70
7.5. Perform CTS and Analyze the Results ................................................................................................... 75
8. Lab 11: Routing and PostRoute Optimization, Signoff ............................................................................ 77
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1. Lab 0: IC COMPLIER GUI
1.1. Launch IC Compiler II
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Commanded and output log files is created in above finger.
. cmd file including initialization command during set up.
.log file records command and command log after tool set up.
.txt file that also contains all output.
1.2. Navigating the layout view
Figure 1.1: Layout view
Information: Green rectangle: std cell, macros, Pink mess ( vertical and horizontal )
Zoom and pans button
[+] or [=] is zoom-in 2x, [-] is zoom-out 2x.
Press esc to exit the zoom and pan mode.
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Figure 1.2: Hotkeys
View hot keys in report.1-Hotkeys
Hots-key can be defined by gui_set_hotkeys.
Use mouse strokes to pan and zoom
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Figure 1.3: Zoom in an area
Display overview of view
Figure 1.4: Display overview of view
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1.3. Controlling logic and layer visibility
Preset: floorplan
Figure 1.5: View setting
Uncheck: route  apply
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Figure 1.6. Layout after uncheck route
1.4. Layer tab
Uncheck “All layer” and then check “Routing”, click green check to apply.
In order to understand PG mesh, uncheck M7, M8:
Figure 1.7. Layout after uncheck layer tab
Tick M7 to view wide horizontal :
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Figure 1.8. View wire horizontal
Tick M8 to view vertical straps
Figure 1.9 View vertical straps
Querying and selection objects  To obtain a full query.
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Figure 1.10. Queying and selection objects
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1.5. Controlling the view level
Outline pattern of hard macros.
Hard macros: Block level designs with completed layout,cant configure
Macros are SRAMs
Figure 1.10. View hard macros
Routing blockages: Specific locations where placing of cells are blocked.
Hard blockage: : Block std. cell placement completely
Soft blockage: Only buffers/inverters can be placed
Halo: Similar to Soft Blockage, respect Macro (while other blockages respect location), move
along with the macro when moves.
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Figure 1.12. Routing Blockages
1.6. Timing analysis
Figure 1.13. Timing analysis
Include: Scenario, Mode, Conrner, Path Group, Analysis, Endpoint, NVE, WNS
Violating paths show up as red bars . In above figure, it is all red bars.
Choose “select worst path”, you will see the timing path in the layout view.
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Figure 1.14. View Worst Path
2. Lab 2: Floorplaning
Invoke ICC II and load the ORCA_TOP Block
Select command “echo "hello world"” then run select and view in the shell window.
Load the ORCA_TOP Block in the figure:
Figure 2.1. View run "echo hello world"
2.1. Initial Floorplanning using the Task Assistant
Floorplan Initialization dialog: help us to define size & shape of the chip/block.
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Figure 2.2. Floorplanning dialog
Select type and orientation in floorplan initialization dialog in order to create shape/size block
(Note: Rectangle block is not orientation)
In order to L-shape block have sides such as : a=2, b=2, c=1, d=2. Orientation set to “West”.
Perform in below figure:
Figure 2.3. Side size control is set to Ratio
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Uniform spacing value of 20 (space between the core and the die): spacing between core and
die:
Figure 2.4. Spacing between core and die
Finally, I see something like this: (Block’s floorplan after initialization)
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Figure 2.5. Initial floorplan
2.2. Bocking Shaping
Block Shaping  Block Shaping  Shape Block  Apply
After shape_blocks completes:
Figure 2.6. Blocking Shaping
Visibility of voltage areas.
Different regions that operate at different voltages, voltage areas must be shaped
Two voltage areas are displayed (PD_RISC_CORE and DEFAULT_VA) in the below figure:
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Figure 2.7. View two domain voltage
There are four macros inside that voltage area are stacked on top of one another ( cant see)
2.3. Macro and Standard Cell Placement
Cell placement using floorplaning placement
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Figure 2.8. Macros placement
Teachnical floorplanning: Place macros at the edge of the core area
Enable pin visibility: (green node)
Soft placement blockage (rectangle with blue border between the macos) to reduce congestion
and improve routing because increase spacing between macros and macros , macros and std
cell.
Macros have been flipped so that the sides with common pins face each other with common
pins face each other.
2.4. Place the block port
Interface between the chip’s core and devices outside of the chip
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Figure 2.9. Block port
all the block’s ports, the logical representations of the physical pins (at the edge of the die I/O)
Zoom in to individual ports to verify that the pins have, indeed, only been placed on layers M3M6
Figure 2.10. View block port
Search for the *clk ports/terminals and zoom into their location:
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Figure 2.11. zoom in clock port location
To see the pin guide, zoom in to the highlighted area as shown below
Figure 2.12. Zoom in to the highlighted area
Change the width of the *clk ports (the terminal shapes) to 0.1 and the length
to 0.4, then rerun pin placement
Figure 2.13. rerun pin placement after configure
2.5. Task 6 : Congestion map
That macros and standard cells have been placed, check if there are any congestion issues.
Global route congestion:
Display the heat map:
Most over flow is 1, a few overflow are 2 and 3. So, most of location is not congestion
Change Bins/from/to
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From -2 to 2 have their individual pin and ( greater than 2 and less than -2) are grouped into a
combined bin
Red portion is badly congestion.
Green portion is lesser congestion.
Detailed calculation of the overflow for an edge:
Figure 2.14. Overflow
2.6. Analyze Macro Placement using DFF
Click Data Flow Flylines
In the dialog that appears you can configure the tracing behavior of DFF.
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Figure 2.15. Compute Data Flow Flylines
Now select one macro to see its connections to other macros and ports. Limit the tracing by
checking “Number of registers” or “Number of gates” and changing the Min/Max numbers.
Figure 2.17. Connected direcly
Detailing information about the connection(s).
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Figure 2.18.Data Floư Aggregated Flyline
Why display Reload R ? When I set max number of registers is 4 ?
Figure 2.19. Detail connection about the connection
2.7. Task 8: Register Tracing
Select Show flylines to see the flylines between the macro and registers
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Figure 2.20. Flylines between the mcro and registers
Show more orange lines when apply level 2.
Figure 2.21. Flylines with orange lines
Display Endpoints and direct end points:
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Figure 2.22. View endpoint
Fix their location:
Figure 2.23. Fix their location
a basic PG mesh inserted:
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Figure 2.24. PG mesh
2.8. Remove PG Routes:
Figure 2.25. Remove PG mesh
Change percentage parameters to test different PG mesh configurations: (PG tracks 40% 40%)
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Figure 2..26. PG mesh confiuration
2.9. Power network synthesis
Source scripts/pns.tcl :
review the power mesh, the macro PG connections, and the standard cell rails in the layout
view:
Figure 2.27. Power mesh
The power mesh will have a few issues here and there, which will have to be taken care of for
final implementation.
3. Lab 3: Placement and optimization
3.1. Load and check initial design
What is the high WNS/TNS/NVE (Worst Negative Slack (Worst path)/Total Negative Slack())
Goals: WNS & TNS >=0 in order to ensure all signals reach their destination promptly and the
circuit operates correctly.
high WNS/TNS no placement or any optimizations have been performed yet:
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Figure 3.1. WNS/TNS
3.2. Task 2: Place and optimize the Design:
Q1: Are there any remaining ideals nets?
No, There aren’t.
Figure 3.2.Report_idea_network
Suppose: There are some remaining ideals nets  remove them  remove_ideal_net command
Q2: What is the maximum routing layer set for the block?
Max Routing level is M8
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Figure 3.3. Report_ignored_layers
Q3: How many scan chains exist in the design?
Scan chains : Technique using flip-flop chains to test and debug VLSI circuits. Helps get test
data in and out of the chip
There are 8 scan chains exist in the design
Figure 3.4. Scan Chains
Report utilization:
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Utiliazation ratio: Usage rate of macros and cells in core area (goals: utiliazation ratio (6070%))
Figure 3.5. Repoet Utilization
What is site ‘unit’ value equal 0.4929 ( equal Utilization Ratio)
Pre_placement_stage (mega-check)
The check options can be modified to suit the need of the designer
Running mega-check 'design_mismatch':

Verifies that the design matches the physical implementation.
Running mega-check 'pre placement stage':
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Verifies the design before placement and routing.
Running atomic-check 'scan_chain':
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Verifies the scan chain used to test the chip.
Running atomic-check 'mv_design':
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Verifies the multi-view design, ensuring different views are consistent.
Running atomic-check 'rp_constraints':
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Verifies the timing constraints of the design.
Running atomic-check 'timing':
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Verifies the timing of the design, checking for timing violations.
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Figure 3.6. Pre - placement check
Analyze: High fan-out nets:
High_fanout
threshold 60:
Figure 3.7. Report net_fanout
Q4: How many non-clock high fanout nets exist with a fanout larger than 60?
See in the Fanout Driver has 10 nets with a fanout larger than 60 :
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Figure 3.8. Report net fan-out with thresole value
Q5: What command/option is used to include cells for optimization?
set_lib_cell_purpose –include optimization command
Leakage and dynamic power optimization are not performed by default during place_opt.
Logic Restructuring
set the application option opt.common.advanced_logic_restructuring_mode to power.
Placement and analysis:
Q6: What is the app option for optimizing the scan chains and what is its default setting?
Figure 3.9. App option and optimization
App_options opt.dft.optimize_scan_chain
Default value: true
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4. Lab 5 : Design setup
4.1. Directory Structure and Invoking ICC II
Figure 4.1. rm_setup and ORCA_TOP_constrain
4.2. Setup Variables and Settings
Question 1. What is the default value of the search_path application variable? (HINT:
printvar sear[TAB] or echo $search_path or get_app_var search_path or report_app_var
search_path )?
Directory (.)
Question 2. Which commands in run5.tcl will use the search_path application variable to
locate their specified file(s)? (list just the commands, without their options and
arguments)
Source :
Read_verilog:
Load_upf:
Read_def:
Q3. Which command in run5.tcl uses the user-defined TECH_LIB and
REFERENCE_LIBRARY variables?
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Tech_lib (technology library): contain the number of metal layer and vias, physical and
electical characteristics of each layer and via…
Create_lib
Q4. From setup.tcl: How many cell reference libraries are being used?
Hvt,lvt,rvt cell libraries
HVT (High-Vt): Low leakage power, slow speed.
LVT (Low-Vt): High leakage power, fast speed.
RVT (Regular-Vt): Balanced power and performance.
Q5: From setup.tcl: Up to how many cores are enabled for multi-threading?
Up to 8
Q6: How many cores are enabled, by default? (1)
Tool-defaults done in order to reduce output verbosity
Problem in create_lib  repair problem
Figure 4.2. Problem in create.lib
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fix setup.tcl by inserting $TECH_LIB as follow:
Figure 4.3. Fix setup.tcl
4.3. Design Library, Netlist and UPF
Q7: What is the name of the newly-created design library?
ORCA_TOP.dlib
Q8: Did the design library show up in the lab56_setup directory?
No
Read the Verilog: read_verilog -top ORCA_TOP ORCA_TOP.v
Q9:What is the name and location of the reference library containing the unresolved
references?
Fix file setup.tcl: (method 2)
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Fix add set_ref_libs (method 1)
Run the command : report_ref_libs
Contains the physical or layout representation of the ORCA_TOP block.
The layout contains all the standard cell and macro instances of the netlist, stacked on top of
each other, in the lower-left corner. The blue-green rectangles are the hard macros, and the
small purple rectangles in the lower-left corner are the standard cells. The block’s I/O ports are
also stacked on top of each other, and show up as a small light-blue square with a Greek-like
Phi Φ symbol (actually an O and an I superimposed), just outside of the lower-left corner of the
stacked cells
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Q10: What is the name (block handle) of the newly-created current block in the design library?
ORCA_TOP.dlib:ORCA_TOP.design
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UPF file is file format for describing power intent.

Contains information about:
o
Power domains and supply nets
o
Power gating and retention cells
o
Voltage levels and level shifters
o
Clock gating and power state management
File ORCA_TOP.upf
Three power supply nets/ports: VSS, VDD and VDDH
- Two power domains: PD_ORCA_TOP (the top level of the block) and PD_RISC_CORE (contains
the RISC_CORE sub-design)
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- Level shifters for inputs and outputs of PD_RISC_CORE
- Defines the power states of the power nets. Here, the power nets only define an ON-state
Figure 4.5. File.upf
Load the floorplan generated by ICC II floorplanning:
Zoom in:
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Improve the visibility of the floorplan:
Figure 5.2. Visibility of the floorplan
Scale fonts:
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4.4. Load Floorplan and Scan-DEF
Read the SCAN-DEF file
A scan chain is a series of flip-flops (DFFs) connected in a serial manner to create a data path.
Question 11. How many scan chains does the design have?(0??? Not create scanchains)
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Connect P/G pins
4.5. Placement Site and Routing Layer Settings
Comfirm placement site and Y-symmetry:
Q12: Does Y-symmetry mean that standard cell can be flipped in the Y-direction (along
the X-axis), or flipped in the X direction (along the Y-axis)?
Standard cell can be flipped in the X-direction, along the Y-axis
Confirm that all metal layers are available for signal routing (none are ignored)
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.
4.6.Save the Block
Q13. Does the ORCA_TOP.dlib design library exist in the current working directory?
No
Q14: Does the ORCA_TOP.dlib design library show up now?
Yes
5. LAB 6: TIMING SETUP
5.1. Open the block from lab 5
5.2. Multi-Corner Multi-Mode Setup
Muti-Corner Multi_Mode equivalent to Mutiple operating conditions Mutiple working mode
with multiple scenarios
Q1: What are the names of the modes, corners and scenarios that will be created?
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Mode:
Corners: ss_125c, ss_m40c, ff_125c, ff_m40c
Scenarios: fun.ss_125c, func.ss_m40c, func.ff_125c, func.ff_m40c, test.ss_125c, test.ff_125c
Mode, corners and scenarios specific constrains
Common file contains port names for constraints:
Q2:Which scenarios will be active?
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ALL scenarios. By default, all scenarios are active when created
Q3: Which analysis types will be enabled for the test.ss_125c scenario?
Setup timming , DRCs( Max_tran, Max_cap, Min_cap)
Leakage Power, Dynamic Power, Cell_em, Signal_em are disabled.
Report mode:
Current refers to whether this mode is the current mode or not.
Default is only true if you didn’t create any modes on your own, in that case ICC II would have
single mode named default.
Empty is true if you have not applied any constraints to this mode.
Generate a pvt report:
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Question 4. Which corner(s) have PVT mismatches?
PVT mismatch stands for Process, Voltage, and Temperature mismatch. It refers to the
variation in electrical parameters of transistors due to:

Process variations: During manufacturing, transistors may have different sizes,
impurities, and electrical characteristics.

Voltage variations: The power supply voltage can fluctuate due to noise or power
supply variations.

Temperature variations: The chip's operating temperature can change due to the
environment or chip activity.
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Figure 6.2 PVT mismatch
Corner ss_m40c have PVT mismatches.
Corner ss_125c don’t have PVT mismatches.
Question 5. What is mismatching – process, voltage and/or temperature?
In above figure, corner ss_m40c have 18 temperature mismatches.
Question 6. What is causing all of the mismatches? (Temperature)
Question 7. Has the block been saved?
5.3. Zero-Interconnect (ZIC) Timing Sanity Check
This QoR report is very useful to get a high-level summary of the worst negative slack (WNS)
timing, as well as the total negative slack (TNS), and the number of violating endpoints (NVE)
for each scenario.

Worst Negative Slack (WNS): This metric indicates the path in your design with
the smallest margin between the required setup and hold times and the actual delay
experienced by the signal.

Total Negative Slack (TNS): This metric represents the cumulative slack
deficit across all paths in your design. A negative TNS suggests that multiple paths
could be experiencing timing violations.

Number of Violating Endpoints (NVE): This metric indicates the total number of flipflops in your design that are potentially affected by timing violations.
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At first glance, when looking at the second, ZIC QoR report, it appears that the design has a
serious problem! Two of the three setup timing scenarios have WNS violations of ~2.6 ns!
make sure that these large violations are not due to unbuffered high fanout nets (HFNs)
 the results are the same, the violations are not caused by HFNs.
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Question 8. Can you think of a reason why one scenario meets setup ZIC timing, while
the others have a huge WNS violation?
it was performed for a single mode and corner: The functional mode (func), and the slow-slow
process at -40 OC corner (ss_m40c).
Timing report for the five worst violating paths:
6. LAB 7: RUNING CTS
6.1. Timming QoR summary
Question 1. From a timing stand-point – is the design ready for CTS? What about the hold
violations?
There should be no setup violations. There are hold violations, which will be addressed during
CTS.
Generate a clock report:
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See in above figure:
Question 2. How many master clocks are defined?
There are 3 master clocks (SDRAM_CLK, SDRAM_CLK, SYN_2X_CLK)
Question 3. How many generated clocks are defined?
There are 3 generated clocks are defined. This is SD_DDR_CLK, SD_DDR_CLKn, SYS_CLK
Question 4. What type of clock are the remaining clocks?
Virtual clock: v_PCI_CLK, v_SDRAM_CLK.
Question 5: What is the source of the SD_DDR_CLK clock?
Sdram_clk
Generate a clock skew report:
Question 6. What is smallest/largest Setup Uncertainty?
0.10 (ff*scenarios)/0.30(ss*scenarios)
What is smallest/largest Hold Uncertainty?
0.05(ff*scenarios)/0.10(ss*scenarios)
Generate a clock groups:
Question 7. Which clock groups are mutually exclusive or asynchronous?
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-group {SYS_2x_CLK SYS_CLK}
-group {PCI_CLK v_PCI_CLK}
-group {SDRAM_CLK v_SDRAM_CLK SD_DDR_CLK SD_DDR_CLKn}
Generate a clock tree summary report for both modes:
Question 8. What is the big difference between the two modes?
(Hint: Look at the clock name)
Mod test has an additional clk : ate_clk
Question 9. How many sinks does SD_DDR_CLK have?
Both of mod , SD_DDR_CLK have 0 sink
Generate a port report on the start point or source of SD_DDR_CLK:
Question 10. Why does SD_DDR_CLK have zero sinks?
(Hint: Look at the port direction)
Perform these setup steps by sourcing a file:
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Question 11. Are the scenarios configured properly for hold fixing? (ff)
Control buffers or delay cells:
6.2. Post-CTS I/O Latency
configured to update the clock:
6.3. Run Comprehensive Clock Tree Checking
Generate a clock tree check report with a summary and detail section:
Show have many problem of each problem each category: (Summary section)
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Four clocks are listed, related to ports SD_DDR_CLK and SD_DDR_CLKn
These two warnings list cells that are used in the clock tree, and are either not enabled for the
CTS lib cell purpose (Reference cells)
Perform clock tree synthesis and route the clock trees (built_clock and route_clock)
Results for the worst corners:
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Cell and nets have a dont_touch constrain
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6.4. Option A: Perform Classic CTS:
Perform clock tree synthesis and route the clock trees:
Summary Table for Corner ss_125c
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Robustness report:
Skew report using the clock timing report:
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The reported Skew is the difference between the max and min Latency numbers, plus or minus
the clock reconvergence pessimism (CRP).
Skew and maximum Latency for the indicated clocks:
Clock: SYS_2x_CLK
Max_Latency= 0.849, Skew=0.136
Clock: SDRAM_CLK
Max_latency: 0.729, Skew: 0.196
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Question 12. Why are the skews reported by report_clock_qor and report_clock_timing
different?
The report_clock_qor command reports global skew, by default, which is the maximum skew
across all sinks in the entire clock domain (the difference between the longest and the shortest
insertion delays.
the worst-case (Design) WNS/TNS/NVE numbers for setup and hold:
Execute post-CTS optimization:
Question 13. Are there any setup or hold violations left?
Yes , You see in above figure
6.5. Option B: Concurrent Clock & Data Flow:
Use the CCD flow to build the clock trees and optimize the logic.
worst-case (Design) WNS/TNS/NVE numbers for setup and hold:
Clock_opt include: _run_stage clock_opt build_clock, run_stage clock_opt route_clock,
_run_stage clock_opt final_opto
Design QoR:
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When I run Clock_opt, ICC2 tool automatical quit and I check in terminal, result is
error:(15/03)
I fixed it (18/03)
Save block in order to do task 8 : Analysis
6.6. Analysis
Synthesized clock tree using the clock abstract graph GUI.
shows the latency graph for SYS_2x_CLK:
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Clock Tree after inserting buffer/inverter.
Clock tree clock:
Exp: sdram_clock
Exp: sys_2x_clock:
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Examine the timing from one of the clocks constrained by v_PCI_CLK:
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Q14: Is the network latency on the input v_PCI_CLK propagated?
No. A latency number is listed under “clock network delay (ideal)”. This is the auto-updated
ideal latency value that ICC II has computed for PCI_CLK, and applied to v_PCI_CLK
7. Lab 8 : Clock Tree Synthesis
7.1. Load the Design and Analyze the Clocks
Set SDRAM_CLK generated set true, source: sd_CK, also symbol M, G in front of clocks.. The
SD_DDR_CLK and SD_DDR_CLKn clocks are generated from the master clock SDRAM_CLK
Perform closer analysis of SDRAM_CLK in func mode:
I can see all valid sink input pin and cant see output ports sd_CK and sd_CKn.
Generate a clock structure report:
Serach sd_CK
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Question 1. What balance point exception is set on sd_CK, and why?
IMPLICT_IGNORE_PIN perform in below figure:
Report clock balance point:
Focus (Block Independent, Balance Points):
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7.2. Clock Tree Balancing
It minimizes clock skew,the variation in arrival times of clock signals across different flip-flops
Question 2. How are the S0 (select) pins of the MUXes labeled now?
Question 3. How is the sd_CK port labeled now? What does this mean?
Sd_CK port is described by BEYOD EXEPTION, port is in the fanout of beyone the BALANE_PIN
Report don’t_touch_cell
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Report dont_touch:
Question 4: What is the source of SYS_CLK generated ?
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I_CLOCKING/sys_clk_in_reg/Q. This is a divide-by-2 register, used to divide SYS_2x_CLK and
generate SYS_CLK.
Instruct CTS to not change the register that is used as the clock divider:
Clock Tree Target:
Set a skew target of 0.05ns for all the slow (ss) corners, and 0.02ns for the fast (ff) corners.
Report clock_tree:
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Choose the buffers and/or inverters:
Report lib_cell:
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Search string “cts”:
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7.3. Define CTS Non-Default Routing Rules:
Question 5. Which net segment(s) of the clock tree do the two clock routing rules apply
to?
CTS_NDR_RULE_NAME
CTS_LEAF_NDR_RULE_NAME
Question 6. What are some key differences between the rules?
Report clock_routing_rule:
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Verify the rules were applied:
The report shows which net segments (net type) the rules apply to (sink overrides all), and the
min/max layer constraints for each clock segment.
7.4. Timing and DRC Constraints
DRC constraints define the physical design rules that must be followed to ensure the chip can
be manufactured correctly and reliably ( minimum width and spacing, metal overlap, gate
leghth and width)
Timing constraints specify the allowable timing margins for various circuit components and
operations( clock frequency, setup times, hold times and so on )
report for the master clock sources:
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Question 7. Are all clock ports constrained by either a Driving Cell or input Transition?
Question 8. Why is it important for clock input ports to be constrained by
set_driving_cell or set_input_transition?
Report_skew:
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Change the uncertainty for all clocks in all scenarios:
Set_clock_uncertainty 0.1 –setup
Set_clock_uncertainty 0.05 -hold
Set a max transition for the clocks in func mode only:
Report_clock_setting:
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See max_transition:
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7.5. Perform CTS and Analyze the Results
NDR’s routing rule:
Report _clock_qor
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Global Skew is small
Clock tree latancy graph:
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8. Lab 11: Routing and PostRoute Optimization, Signoff
Question1: Is timing acceptable for routing?
There are only a few remaining small timing violations. There are also a few smaller max
transition as well as a few max capacitance violations (you will see them with
report_constraints -all)
Pre-routing Checks Before you route the design it is best to ensure that there are no
issues that will prevent the router from doing its job
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Question 2. Is the design ready for routing?
Check Antenna:to detect and eliminate unwanted antenna structures. Antennas can cause
electromagnetic interference (EMI), reduce chip performance, and affect reliability.
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
route.detail.antenna_fixing_preference: This variable specifies the preferred method for
fixing antenna violations during routing.

route.detail.antenna_on_iteration: This variable specifies whether antennas are checked
and fixed after each iteration of the routing algorithm.

route.detail.antenna_verbose_level: This variable specifies the verbosity level of the log
information generated when checking and fixing antennas.
Question 3. What is the name of the secondary PG pins, and where do they connect to?
Crosstalk Prevention
Secondary PG Routing
Report_Power_domain;
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Question 3. What is the name of the secondary PG pins, and where do they connect to?
Routing, DRC Analysis:
Question 4. How many detail route iterations are run by default? (Hint: Review the man page
for route_auto.):
Report qor:
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Question 5. How do you change the default, and how do you force the router to run
through all iterations even though the router might not see any improvements
You change the default using route_auto -max_detail_route_iterations
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