lOMoARcPSD|29615521
Digital Logic Design Eee241 Lab Manual, Comsats
Digital Logic Design (COMSATS University Islamabad)
Scan to open on Studocu
Studocu is not sponsored or endorsed by any college or university
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Digital Logic Design
EEE241
Lab Manual
Name
Registration Number
Class
Instructor’s Name
COMSATS Institute of Information TechnologyPage 1
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Introduction
Thi
si
st
heLabManualf
orEEE –241Di
gi
t
alLo
gi
cDe
s
i
gn.Thel
absc
ons
t
i
t
ut
e
25% oft
het
o
t
almar
ksf
ort
hi
sc
our
s
e
.
Dur
i
ngt
hel
absyouwi
l
lwor
ki
ngr
oups(
nomo
r
et
hant
hr
ees
t
udent
spergr
oup)
.
Youar
er
equi
r
e
dt
oc
ompl
e
t
et
he‘
Pr
eLab’s
e
c
t
i
onoft
hel
abbe
f
or
ec
omi
ngt
ot
he
l
ab.Youwi
l
lbegr
adedf
ort
hi
sandt
he‘
I
nLab’t
as
ksdur
i
ngt
hei
nl
abvi
va.You
wi
l
lc
ompl
e
t
et
he‘
Pos
t
Lab’s
ec
t
i
onofe
ac
hl
abbe
f
or
ec
omi
ngt
ot
hene
xtwee
k’
s
l
ab.
You ar
e no
tal
l
o
wed t
o wander i
nt
he l
ab or c
ons
ul
to
t
her gr
oups when
per
f
or
mi
nge
xper
i
ment
s
.Si
mi
l
ar
l
yt
hel
abr
epor
t
smus
tc
ont
ai
nor
i
gi
naleffor
t
s
.
CI
I
Thasaz
er
ot
ol
er
anc
eant
i
pl
agi
ar
i
s
m pol
i
c
y
.
Apar
tf
r
om t
hes
ewee
kl
yl
absyou wi
l
lc
ompl
e
t
et
wopr
o
j
e
c
t
s
.Onemi
ni
pr
o
j
e
c
t
t
hatwi
l
lc
ountt
o
war
dsyourLabSes
s
i
onalI
Is
c
or
eandaFi
nalPr
o
j
e
c
twhi
c
hwi
l
l
begr
aded asLabFi
nalExam.Thegr
adi
ngpo
l
i
c
yi
sal
r
e
adydi
s
c
us
s
ed i
nt
he
Cour
s
eDes
c
r
i
pt
i
onFi
l
e
.
COMSATS Institute of Information TechnologyPage 2
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Acknowledgement
Thel
absf
orEEE241Di
gi
t
alLo
gi
cDe
s
i
gnwer
edes
i
gnedbyDrFai
s
alSi
ddi
que
andDr
.Nas
eem Al
vi
.Themanual
swer
epr
epar
edbyMrAl
iRaz
aShahi
d,Mr
Si
kenderGuland Mr
.Shahi
d Me
hmood.The fir
s
tver
s
i
on wasc
ompl
e
t
ed i
n
Ses
s
i
on Spr
i
ng 2014,The s
ec
ond ver
s
i
on wasc
ompl
e
t
ed dur
i
ng t
he s
ummer
br
e
akof2016.
Thi
r
dver
s
i
oni
sc
ompl
e
t
edi
ns
es
s
i
onSpr
i
ng201617.Types
e
t
t
i
ng
and f
or
mat
t
i
ng oft
hi
sve
r
s
i
on wass
uper
vi
s
e
d by Dr
.OmarAhmad and was
c
ar
r
i
edoutbyMr
.AbdulRe
hman,MrSul
eman& MrBaqi
rHus
s
ai
n.
History of Revision
Versi
on
andDat
e
ofI
ssue
Team
Comment
s
Ver
s
i
on 1.
Dr
.Fai
s
alSi
ddi
que.
May2014
Thi
si
st
hefir
s
te
di
t
abl
edr
af
tofEEE –
241l
abmanual
.Labswer
ede
s
i
gnedby
Dr
.Fai
s
alSi
ddi
que
For c
omment
s and s
ugges
t
i
ons pl
e
as
e
c
ont
ac
t
:faisal_siddiqui@comsats.edu.pk
Dr
.Ri
azHus
s
ai
n.
Ver
s
i
on 2. Mr
.Al
iRaz
aShahi
d.
Sept
ember Mr
.Si
kenderGul
.
2016
Ms
.Ayes
hahameed.
Mr
.NoumanRi
az
.
Thi
si
st
hes
ec
onde
di
t
abl
edr
af
tofEEE
– 241 l
ab manual
.The manual was
r
emo
de
l
ed ac
c
or
di
ng t
ot
he ne
w OBE
f
or
mat
.Someoft
hel
abswer
ei
mpr
o
ved.
Ver
s
i
on 3. Dr
. Ahmad Nas
ee
m
Januar
y
Al
vi
.
2017
Dr
.Fai
s
alSi
ddi
que.
Mr
.Al
iRaz
aShahi
d.
Mr
.Si
kenderGul
.
Thi
si
st
het
hi
r
de
di
t
abl
edr
af
tofEEE –
241 l
ab manual
.So
me ofamendment
hadbeen madeaf
t
ert
hef
ee
dbac
kf
r
om
t
hei
ns
t
r
uc
t
ordur
i
ngf
al
l
2016.
Safety Precautions

Be calm and relaxed, while working in lab.

First check your measuring equipment.
COMSATS Institute of Information TechnologyPage 3
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design

When working with voltages over 40 V or current over 10 A, there must be at least
two people in the lab at all time.

Keep the work area neat and clean.

Be sure about the locations of fire extinguishers and first aid kit.

No loose wires or metals pieces should be lying on the table or neat the circuit.

Avoid using long wires, that may get in your way while making adjustments or
changing leads.

Be aware of bracelets, rings, and metal watch bands (if you are wearing any of them).
Do not wear them near an energized circuit.

When working with energize circuit use only one hand while keeping rest of your
body away from conducting surfaces.

Always check your circuit connections before power it ON.

Always connect connection from load to power supply.

Never use any faulty or damage equipment and tools.

If an individual comes in contact with a live electrical conductor.
o Do not touch the equipment, the cord, the person.
o Disconnect the power source from the circuit breaker and pull out the plug
using insulated material.
COMSATS Institute of Information TechnologyPage 4
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Table of Contents
Introduction (To be written by the course instructor)...............................................................2
Acknowledgement (Edit)...............................................................................................................3
History of Revision (Kindly edit according to your course)......................................................3
Safety Precautions..........................................................................................................................4
Lab # 01: Introduction to Basic Logic Gate Ic’s on Digital Logic Trainer and Proteus
Simulation.......................................................................................................................................8
Objective......................................................................................................................................8
Pre-Lab:.......................................................................................................................................8
EXNOR gate..............................................................................................................................11
In-Lab:.......................................................................................................................................13
Post-Lab Tasks:..........................................................................................................................20
Critical Analysis/Conclusion.....................................................................................................23
Lab #02:Boolean Function and Universal Gates Implementation on Kl-31001 Trainer
using Gate Ic’s..............................................................................................................................24
Objectives..................................................................................................................................24
Pre-Lab:.....................................................................................................................................24
In lab:.........................................................................................................................................24
Post-Lab:....................................................................................................................................30
Critical Analysis/Conclusion.....................................................................................................32
LAB # 03: Introduction to Verilog and simulation using XILINX ISE..................................33
Objective....................................................................................................................................33
Pre-Lab:.....................................................................................................................................33
In-Lab Task 2:............................................................................................................................45
Post-Lab Tasks:..........................................................................................................................45
Critical Analysis/Conclusion.....................................................................................................47
LAB #04 Implementation and Designing of Boolean Functions By Standard Forms
Using Ics/Verilog..........................................................................................................................48
OBJECTIVE..............................................................................................................................48
PRE LAB...................................................................................................................................48
PRELAB TASKS:.....................................................................................................................52
IN-LAB TASKS........................................................................................................................52
POST-LAB TASKS...................................................................................................................54
COMSATS Institute of Information TechnologyPage 5
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Critical Analysis/Conclusion.....................................................................................................56
Lab 05- Logic Minimization of Complex Functions using Automated Tools.........................57
Objective....................................................................................................................................57
Pre- Lab:....................................................................................................................................57
In-Lab:.......................................................................................................................................59
Critical Analysis/Conclusion.....................................................................................................65
LAB # 06 XILINX ISE design flow with FPGA........................................................................66
Objective....................................................................................................................................66
Pre-Lab:.....................................................................................................................................66
In lab Task..................................................................................................................................71
Post-Lab Tasks:..........................................................................................................................72
Critical Analysis/Conclusion.....................................................................................................73
Lab #07: Design and Implementation of n-bit Adder/Subtractor on FPGA..........................74
Objectives..................................................................................................................................74
Pre-Lab:.....................................................................................................................................74
In lab:.........................................................................................................................................75
Post-Lab:....................................................................................................................................78
Critical Analysis/Conclusion.....................................................................................................79
Lab #08: N-Bit Multiplier and Its Implementation On FPGA................................................80
Objective....................................................................................................................................80
Pre-lab:.......................................................................................................................................80
Pre-lab Tasks..............................................................................................................................82
Post-Lab Tasks...........................................................................................................................83
Critical Analysis/Conclusion.....................................................................................................84
Lab #09: Design and Implementation of Binary to BCD and BCD to 7-Segment decoder
on FPGA.......................................................................................................................................85
Objective....................................................................................................................................85
Pre-Lab:.....................................................................................................................................85
Critical Analysis/Conclusion.....................................................................................................94
LAB # 10:Implementation of up/down Counter with Terminal Count and Reset on
FPGA............................................................................................................................................95
Objective....................................................................................................................................95
Pre-Lab:.....................................................................................................................................95
In lab Task..................................................................................................................................97
COMSATS Institute of Information TechnologyPage 6
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Post-Lab Tasks:..........................................................................................................................97
Critical Analysis/Conclusion.....................................................................................................99
Lab #11Mealy /Moore Machine implementation of Sequence Detector...............................100
Objective..................................................................................................................................100
Pre-Lab:...................................................................................................................................100
In lab:.......................................................................................................................................101
Post Lab...................................................................................................................................107
Critical Analysis/Conclusion...................................................................................................110
Lab #12 Universal Shift Register On FPGA............................................................................111
OBJECTIVE............................................................................................................................111
PRE LAB.................................................................................................................................111
PRELAB TASK.......................................................................................................................114
LAB TASK..............................................................................................................................114
POST LAB TASK....................................................................................................................114
Critical Analysis/Conclusion...................................................................................................115
COMSATS Institute of Information TechnologyPage 7
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Lab # 01: Introduction to Basic Logic Gate Ic’s on
Digital Logic Trainer and Proteus Simulation
Objective
Part 1
To know about the basic logic gates, their truth tables, input output characteristics and
analyzing their functionality. Introduction to logic gate IC’s, Integrated Circuits pin
configurations and their use.
Part 2
Learn to use Proteus Software for Simulation of Digital Logic Circuits.
Pre-Lab:
Background Theory:
The Digital Logic Circuits can be represented in the form of (1) Boolean Functions, (2)
Truth Tables, and (3) Logic Diagram. Digital Logic Circuits may be practically
implemented by using electronic gates. The following points are important to understand.






Electronic gates are available in the form of Integrated Circuits (IC’s) and they require
a power.
Supply Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and
5, 12V representing logic 0 and logic 1 respectively.
The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5,
12V representing logic 0 and logic 1 respectively. In general, there is only one output
to a logic gate except in some special cases.
Truth tables are used to help show the function of a logic gate in terms of input values
combination with desired output.
Logic Diagram is used to represent the Digital Logic Circuit in the form of symbols
connected with each other.
Digital Logic Circuits can be simulated on the virtual environment called simulation
software
The basic operations are described below with the aid of Boolean function, logic symbol, and
truth table.
COMSATS Institute of Information TechnologyPage 8
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
AND gate:
Figure 1. 1
Table 1. 1
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is
sometimes omitted i.e. AB
OR Gate:
Figure 1. 2
Table 1. 2
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs
are high. A plus (+) is used to show the OR operation
NOT gate
Figure 1. 3
COMSATS Institute of Information TechnologyPage 9
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Table 1. 3
The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter.
NAND gate
Figure 1. 4
Table 1. 4
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents inversion.
NOR gate
Figure 1. 5
Table 1. 5
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of
all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small
circle on the output. The small circle represents inversion.
COMSATS Institute of Information TechnologyPage 10
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
EXOR gate
Figure 1. 6
Table 1. 6
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of
its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation.
EXNOR gate
Figure 1. 7
Table 1. 7
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output
if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small
circle on the output. The small circle represents inversion.
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR,
NOT, NAND, NOR, EXOR and EXNOR gates. Logic gate IC’s are available in different
packages and technologies. Two main classifications are as below:
1. 74 Series TTL Logic IC’s
2. 4000 series CMOS Logic IC’s
74 series is TTL (Transistor Transistor Logic) based integrated circuits family. Power rating
for 74 series is 5 to 5.5Volts. This circuitry has fast speed but requires more power than later
families. The Pin configuration of basic gates 2-input IC’s for 74 Series is given in figure 1.8:
COMSATS Institute of Information TechnologyPage 11
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Figure 1. 8
Figure 1.8 shows the 4000 series is CMOS (complementary metal oxide semiconductors)
based integrated circuits. Power ratings are 3V to 15 Volts. CMOS circuitry consumes low
power but it is not fast as compared to TTL.
7
Figure 1. 9
Quad 2-input gates
The IC’s available in Lab to perform the Tasks are listed below:
In-Lab:
Part 1: Basic Logic Gate Integrated Circuits (IC’s)
Equipment Required
 KL-31001 Digital Logic Lab
 Logic gates IC’s
o 4001 quad 2-input NOR
o 4011 quad 2-input NAND
COMSATS Institute of Information TechnologyPage 12
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
o
o
o
o
o
4070 quad 2-input EX-OR
4071 quad 2-input OR
4077 quad 2-input EX-NOR
4081 quad 2-input AND
4069 Six Inverting Buffer NOT
Procedure
1. Place the IC on the Bread board as shown in the figure 1.10;
Figure 1. 10
2. Using the power supply available at KL-31001 Digital Logic Lab, connect pin7
(Ground) and pin14 (Vcc) to power up IC.
3. Give number of possible combinations of inputs using the slide switches SW0-SW3
(as shown in table 1.1 & 1.2) and note down the output with help of LED for all gate
ICs. (You can use LD0-LD14 located on KL-31001 Digital Logic Lab)
(Note: Please make sure the Trainer board is off during the setup of circuit)
In lab Task 1:
Verify all gates using their ICs on KL-31001 Digital Logic Lab
INPUTS
A
B
0
0
1
AND
NAND
OUTPUTS
OR
NOR
0
1
0
COMSATS Institute of Information TechnologyPage 13
Downloaded by Academic Aids (academicaids9@gmail.com)
EXOR
EXNO
R
lOMoARcPSD|29615521
EEE241 Digital Logic Design
1
1
Table 1. 8
INPUTS
A
0
1
OUTPUT
S
OR
Table 1. 9
Part 2 - Proteus (Simulation Software)
Proteus has many features to generate both analogue and digital results over a virtual
environment. However this lab will focus on only tools that will be used in digital schematic
designs and verification of basic logic gates.
Procedure
The proteus software for simulation is installed in Digital Design Lab. Please follow the
details below to figure out usage proteus tools and process of simulation.
Figure 1. 11 Interface of Proteus software window
Parts Browsing:
Proteus has many models of electronic equipment such as logic gates, many kinds of switches
and basic electronic devices. The equipment can be founded by clicking on and then a new
window will pop-up and wait for the parts information as shown in figure 1.12.
COMSATS Institute of Information TechnologyPage 14
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Finding Steps:
1. Type information of device such as “OR gate” in box 1.
2. If some specific category is known, the device can narrow on focusing by selecting
catalogue in the box 2.
3. After the information is entered, the list of related devices will appear in the box 3, so
that needed device can be chosen and then click “OK” button to confirm selection in
figure 1.12.
Figure 1. 12 Pick Devices window in ProteusDigital Logic Design
Figure 1. 13 Pick selected Devices window in Proteus
COMSATS Institute of Information TechnologyPage 15
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Power supply and input signal Generator
All of the electrical circuits require power supplies. The power supplies for logic circuits are
represented in digital system design on Proteus because the schematic may be too
complicated to understand for simulation section. Therefore power supplies will be needed as
input power for a system. Moreover, all of the input generators, such as ac generator, dc and
pulse are contained in this category and it will be shown when is clicked. In addition
“Ground” will not be contained in this group. Because it is not an input signal it is just a
terminal junction. Therefore it will be grouped in terminal category as shown in figure 1.14&
1.15.
Figure 1. 14 Power supplies window in Proteus
Figure 1. 15 Terminals window in Proteus
Logic State:
In addition there is another input that usually be used in digital circuit designed circuit but it
does not exist in real world as an equipment it is called as “LOGIC STATE”. It can be found
in the picking part section (type logic state and pick it figure 1.16).
Figure 1. 16 Logic State in Proteus
Placing Equipment:
Selecting all devices needed to be placed on the circuit window (Grey window) and wiring it.
It can be done by following these steps:
1. Click on and select the first device that will be placed.
COMSATS Institute of Information TechnologyPage 16
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
2. Place mouse wherever the device is preferred to be place and then click the left button
of the mouse. The device will be placed, if it is needed to be moved, click the right
button of the mouse on the device symbol to select the mouse. Then hold this device
with the left mouse button and move it to any desired place. (figure 1.17)
Figure 1. 17 Placing the devices in Proteus
To wire devices together, click at the source pin of device and then move mouse cursor to
destination pin of the device. In this step the pink line will be appeared and it will be wire of
circuit after clicking the mouse on the destination pin of the circuit (as shown in figure 1.18).
Digi
Figure 1. 18 Wiring devices to make a circuit
COMSATS Institute of Information TechnologyPage 17
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
After wiring all devices and connect all inputs according to the circuit, the simulation is ready
to be run by clicking on Play button to run and stop button to stop.
3. Logic probe or LED can be used to observe output state.
NOTE: The digital result on Proteus can be seen also in Small Square at pin of the
equipment & state can be shown in four colors. (Red= Logic 1, Blue = Logic 0, Grey=
Unreadable and Yellow= Logic Congestion)
In-Lab Task 2:
Verify all the basic logic gates using the Proteus simulation tool and note down the values in
the table with the corresponding logic symbol and Boolean function. Then show the
simulated logic circuit diagrams to your Lab Instructor.
COMSATS Institute of Information TechnologyPage 18
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Post-Lab Tasks:
1.
Make a list of logic gate IC’s of TTL family and CMOS family along with the IC’s
names. (Note: at least each family should contain 15 IC’s).
7400 Series
4000 Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COMSATS Institute of Information TechnologyPage 19
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
2.
What is Fan in and Fan Out?
COMSATS Institute of Information TechnologyPage 20
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
COMSATS Institute of Information TechnologyPage 21
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
EEE241 Digital Logic Design
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 22
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab #02:Boolean Function and Universal Gates
Implementation on Kl-31001 Trainer using Gate Ic’s
Objectives


This experiment is designed to simulate and implement any logic function using
universals gates (NAND/NOR).
To build the understanding of how to construct any combinational logic function
using NAND or NOR gates only.
Pre-Lab:
Background theory:
Digital circuits are more frequently constructed with universal gates. NAND and NOR gate
are called universal gates. Any Boolean logic function can be implemented using NAND only
or NOR only gates. NAND and NOR gates are easier to fabricate with electronic components
than basic gates. Because of the prominence of universal gates in the design of digital
circuits, rules and procedures have been developed for conversion from Boolean function
given in terms of AND, OR, and NOT into its equivalent NAND and NOR logic diagram.
Read and understand the universal gates. List the truth tables of AND, OR, NOT, NAND,
NOR and XOR gates. Identify the NAND and NOR ICs and their specification for CMOS
and TTL families.
In lab:
This lab has two parts. In first part, simulation and implementation of any logic expression by
using only NAND is done. In second part, the same procedure is done by using NOR gate
only.
Part 1 - Implementing any logic expression by using only NAND gates
If we can show that the logical operations AND, OR, and NOT can be implemented with
NAND gates, then it can be safely assumed that any Boolean function can be implemented
with NAND gates.
Procedure
 Simulate AND, OR and NOT gates in proteus software, by using only NAND gates.
Verify their truth tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NAND gates of the IC for this experiment.
COMSATS Institute of Information TechnologyPage 23
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
 Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NAND gate.
 For output indication, connect the output pin of the circuit to any one of the LEDs of
the trainer (L0 to L15).
Lab Tasks-Part-1
Lab Task 1.1: Verification of NOT function
 Connect the circuit as per Figure 2.1.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table2.1 below.
Figure 2.1 NOT gate
Input
Output
A
F
0
1
Table 2.1
Lab Task 1.2: Verification of AND function
 Connect the circuit as per Figure 2.2.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table 2.2 below.
Figure 2.2 AND gate
COMSATS Institute of Information TechnologyPage 24
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Inputs
A
0
0
1
1
B
0
1
0
1
Table 2.2
Output
F
Lab Task 1.3: Verification of OR function
 Connect the circuit as per Figure 2.3.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table 2.3 below.
Figure 2.3 OR gate
Inputs
A
0
0
1
1
B
0
1
0
1
Table 2.3
Output
F
Lab Task 1.4: Verification of XOR function
 Connect the circuit as per Figure 2.4.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table 2.4 below.
COMSATS Institute of Information TechnologyPage 25
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 2.4 XOR gate
Inputs
A
0
0
1
1
B
0
1
0
1
Table 2.4
Output
F
Lab Task 1.5: Verification of XNOR function
 Connect the circuit as per Figure 2.5.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table 2.5 below.
Figure 2.5 XNOR gate
COMSATS Institute of Information TechnologyPage 26
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Inputs
A
0
0
1
1
B
0
1
0
1
Table 2.5
Output
F
Part 2 - Implementing any logic expression by using only NOR gates
If we can show that the logical operations AND, OR, and NOT can be implemented with
NOR gates, then it can be safely assumed that any Boolean function can be implemented with
NOR gates.
Procedure
 Simulate AND, OR and NOT gates in proteus software, by using only NOR gates.
Verify their truth tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NOR gates of the IC for this experiment.
 Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NOR gate.
 For output indication, connect the output pin of the circuit to any one of the LEDs of
the trainer (L0 to L15).
Lab Tasks-Part-2
Lab Task 2.1: Verification of NOT function
 Connect the circuit as per Figure 2.6.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table 2.6 below.
Figure 2.6 NOT gate
COMSATS Institute of Information TechnologyPage 27
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Input
A
0
1
Output
F
Table 2.6
Lab Task 2.2: Verification of AND function
 Connect the circuit as per Figure 2.7
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table 2.7 below.
Figure 2.7 AND gate
Inputs
A
0
0
1
1
B
0
1
0
1
Table 2.7
Output
F
Lab Task 2.3: Verification of OR function
 Connect the circuit as per Figure 2.8.
 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observation in the table 2.8 below.
Figure 2.8 OR gate
COMSATS Institute of Information TechnologyPage 28
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Inputs
A
0
0
1
1
B
0
1
0
1
Table 2.8
Output
F
Post-Lab:
Design NAND, XOR and XNOR gate Using NOR gate only.
COMSATS Institute of Information TechnologyPage 29
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
COMSATS Institute of Information TechnologyPage 30
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 31
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB # 03: Introduction to Verilog and simulation
using XILINX ISE
Objective
Part 1
In this lab Verilog (Hardware Description Language) is introduced with Xilinx ISE. Verilog
is used to model electronic systems. It is most commonly used in the design and
verification of digital circuits.
Part 2
Xilinx ISE is a verification and simulation tool for VHDL, Verilog, System Verilog, and
mixed- language designs
Pre-Lab:
Background Theory:
Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers
many useful features:
 Verilog HDL is a general-purpose hardware description language that is easy to
learn and easy to use.
 It is similar in syntax to the C programming language. Designers with C
programming experience will find it easy to learn Verilog HDL.
 Verilog HDL allows different levels of abstraction to be mixed in the same model.
Thus, a
 Designer can define a hardware model in terms of switches, gates, RTL, or
behavioral code.
 Also, a designer needs to learn only one language for stimulus and
hierarchical design.
 Most popular logic synthesis tools support Verilog HDL. This makes it the
language of choice for designers.
 All fabrication vendors provide Verilog HDL libraries for postlogic synthesis
simulation.
 Thus, designing a chip in Verilog HDL allows the widest choice
of vendors.
 The Programming Language Interface (PLI) is a powerful feature that allows
the user to write custom C code to interact with the internal data structures of
COMSATS Institute of Information TechnologyPage 32
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Verilog. Designers can customize a Verilog HDL simulator to their needs with the
PLI.
3.1 Level of Abstraction provided by Verilog
3.1.1 Behavioral or algorithmic level
This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the hardware
implementation details. Designing at this level is very similar to C programming.
3.1.2 Dataflow level
At this level, the module is designed by specifying the data flow. The designer is aware of
how data flows between hardware registers and how the data is processed in the design.
3.1.3 Gate (Structural) level
The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level logic
diagram.
3.1.4 Switch level
This is the lowest level of abstraction provided by Verilog. A module can be implemented
in terms of switches, storage nodes, and the interconnections between them. Design at this
level requires knowledge of switch-level implementation details.
3.2 Syntax
3.2.1 Comments
Verilog comments are the same as in C++. Use // for a single line comment or /* … */ for
a multiline comment.
3.2.2 Punctuation
White spaces are ignored in Verilog. A semicolon is used to indicate the end of a command
line and commas are typically used to separate elements in a list. Like C++, Verilog is case
sensitive.
COMSATS Institute of Information TechnologyPage 33
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
3.2.3 Identifiers
An identifier is usually a variable. You can use any letter, digit, the underscore, or
$. Identifiers may not begin with a digit and may not be the same as a Verilog key word. As
in C++ variable names should be chosen to assist in documentation.
3.2.4 Signal values
Signals in Verilog have one of four values. These are 0 (logic 0), 1 (logic 1), ?, X, or x (
don’t care or unknown), and Z or z for high impedance tri-state.
3.2.5 Constants
The generic declaration for a constant in Verilog is [size]['radix] constant_value In this
declaration size indicates the number of bits and 'radix gives the number base (d =
decimal, b = binary, o = octal, h = hex). The default radix is decimal.
Examples:
16
//The number 16 base 10
4'b1010
//The binary number 1010
8'bx
//An 8-bit binary number of unknown value
12'habc //The hex number abc = 1010 1011 1100 in binary
8'b10
//The binary number 0000 0010
3.2.6 Parameters
A parameter in Verilog can be any Verilog constant. Parameters are used to generalize a
design. For example a 4-bit adder becomes more useful as a design if it is put together as an
n-bit adder where n is a parameter specified by the user before compilation. Parameter
declarations are done immediately after the module declaration.
Here are some typical parameter examples:
parameter n = 12;
parameter [3:0]p1 = 4'b1011;
parameter n = 12, m = 32;
COMSATS Institute of Information TechnologyPage 34
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
3.3 Structure
3.3.1 Module
A module in Verilog is used to define a circuit or a sub circuit. The module is the
fundamental circuit building block in Verilog. Modules have the following structure:
(keywords in bold). Note that the module declaration ends with a semicolon but the keyword
endmodule does not.
3.3.2 Ports
Ports in Verilog can be of type input, output¸ or inout. The module ports are given in
the port name list and are declared in the beginning of the module. Here is a sample
module with input and output ports.
module MyModule(yOut, aIn);
output yOut;
input aIn;
…
endmodule
The port names input and output default to type wire. Either can be a vector and the
output variables can be of re-declared to type reg. The output and input variables in a module
are typically names for the output and input pins on the implementation chip.
3.3.3 Signals
A signal is represented by either a net type or a variable type in Verilog. The net type
represents a circuit node and these can be of several types. The two net types most often
used are wire and tri. Type nets do not have to be declared in Verilog since Verilog
assumes that all signals are nets unless they are declared otherwise. Variables are either of
type reg or integer. Integers are always 32-bits where the reg type of variables may be of
any length. Typically we use integers as loop counters and reg variables for all other
variables. The generic form for representing a signal in Verilog is:
type [range] signal_name
The net types are typically used for input signals and for intermediate signals within
combinational logic. Variables are used for sequential circuits or for outputs which are
assigned a value within a sequential always block.
COMSATS Institute of Information TechnologyPage 35
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Example:
wire w; //w is a single net of type wire
wire[2:0] wVect; //Declares wVect[2], wVect[1], wVect[0]
tri[7:0] bus; //An 8-bit tri state bus
integer i; //i is a 32-bit integer used for loop control
reg r; //r is a 1-bit register
reg[7:0] buf; //buf is an 8-bit register
reg[3:0] r1, r2; //r1 and r2 are both 4-bit registers
COMSATS Institute of Information TechnologyPage 36
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
3.3.4 Most often used Operators
Misc
onal
ithmetic
Bitwise
Symbol
Comments
~
Ones complement unary operator
&
and
|
or
^
exclusive or
~&
nand
~|
nor
~^
exclusive nor
!
Not unary operator also called logical negation
&&
Logical and
||
Logical or
+
Add
-
Subtract
*
Multiply
/
Divide
%
Mod operator
>
Greater than
<
Less than
>=
Greater than or equals
<=
Less than or equals
>>
Shift right
<<
Shift left
?:
(cond)?(statements if true):(statements if false)
{,}
{m{}}
Concatenation
Repetition where m is repetition number
3.4 XILINX ISE 13.2
Start ISE from the Start menu by selecting:
Start → All Programs → Xilinx ISE Design Suite 13.2 → ISE Design Tool →Project
Navigator or by double clicking on XILINX ISE Design Suite 13.2 icon
3.4.1 Creating a Project
 File → New Project (Figure 3.1)
 Select the location for the project (Should be your dld_lab folder)
COMSATS Institute of Information TechnologyPage 37
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
 Enter the name of the project
 Then click next
Figure 3.1: XILINX ISE 13.2 Interface
Figure 3.2: Create New project window
COMSATS Institute of Information TechnologyPage 38
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 3.3: Project Settings Window
 Set the project settings:
o Family to Spartan3E
o Device to XC3S500E
o Package to FG320
o Speed to -4
 Then click to Next
 Project Summary
 Then click finish
3.4.2 Adding a file in the project
Right click on Design Pane and select a New Source or Add Source (If file is already exists)
COMSATS Institute of Information TechnologyPage 39
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 3.4: Adding a Source in the project
 For New Source:
o Select Source Type (e.g. Verilog Module) and enters the file name
o Then click Next
o Give Port Names and direction of the module
o Then click Next
o Then click Finish
Figure 3.5: New Source Wizard window
COMSATS Institute of Information TechnologyPage 40
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 3.6: Define Module widow
For Example Half-Adder (as a New Source):
module half_adder(C,S,x,y);
output C,S;
input x,y;
xor a1(S,x,y);
and a2(C,x,y);
endmodule
For Add Source (Already exists):
Select the existing file
Then click Open
Then click Ok
COMSATS Institute of Information TechnologyPage 41
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 3.7: Add Source window
3.4.3 Synthesizing a code
 Double click on Synthesize- XST
Figure 3.8: Synthesize-XST Option Window
3.5 Simulation result
 Click on simulation Icon as in figure 3.9
COMSATS Institute of Information TechnologyPage 42
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 3.9 simulation windows 1
3.5.1 Add test bench file
 Select Source Type (e.g. Verilog test fixture)
 Enter the file name
o Then click Next
o Then click Next
o Then click Finish
 Now add various value of input ports (e.g., A and B) as in figure 3.10
Figure 3.10 Test bench file
3.5.2 ISE Simulator
 Click on ISE simulator it will open two option as shown in figure
 Then double click on Behavior check syntax and wait to verify by tick sign
 Then double click on simulate behavior model it will open new window
3.5.3 Simulation windows
 Click on simulation tools
COMSATS Institute of Information TechnologyPage 43
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 3.11 ISE simulator for simulation
 Then click on Run
 To zoom in click on icon
Figure 3.11 ISim wave file window
In-Lab Task 2:
Verify all the basic logic gates using the XILINX ISE simulation tool and verify your
waveform with logic gates truth table. Then show the simulated result to your Lab Instructor.
Task 01: Make Verilog code for NOT, OR, NOR, NAND, XOR, and XNOR.
Task 02: Make stimulus/test bench for task 01.
Task 03: Run simulation for all gates (made in Task 01).
Post-Lab Tasks:
Implement and simulate the given function below:
(Provide Gate Level Diagram and Truth Table also in Lab Report)
F = x + x’y + yz’
COMSATS Institute of Information TechnologyPage 44
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
COMSATS Institute of Information TechnologyPage 45
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 46
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB #04 Implementation and Designing of Boolean
Functions By Standard Forms Using Ics/Verilog
OBJECTIVE
In this lab we implement Boolean functions by using SOP (sums of product) and POS
(products of sum)
EQUIPMENT REQUIRED
KL-31001 Digital Logic Lab, Bread Board, Logic gate ICs (NAND &NOR).
PRE LAB
BOOLEAN ALGEBRA
Boolean algebra is algebra for the manipulation of objects that can take on only two
values, typically true and false.
 It is common to interpret the digital value
 0 as false
 1 as true.
BOOLEAN FUNCTION
A Boolean function typically has one or more input values and yields a result, based on these
input value, in the range {0, 1}. A Boolean operator can be completely described using a
table that list inputs, all possible values for these inputs, and the resulting values of the
operation.
A Boolean function can be represented in a truth table and it can be transformed from an
algebraic expression into a circuit diagram composed of logic gates. In evaluating Boolean
equations AND operation is performed before OR operation unless OR operation is
enclosed with in brackets
COMSATS Institute of Information TechnologyPage 47
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
BASIC THEOREMS
CANONICAL FORMS
Any Boolean function that is expressed as a sum of minterms or as a product of maxterms is
said to be in its canonical form.
In general, the unique algebraic expression for any Boolean function can be obtained from
its truth table by using an OR operator to combined all minterms for which the function is
equal to 1.
Minterm
A minterm, denoted as mi, where 0 ≤ i < 2n , is a product (AND) of the n variables in
which each variable is complemented if the value assigned to it is 0, and un
complemented if it is 1.


1-minterms = minterms for which the function F = 1.
0-minterms = minterms for which the function F = 0.
 Any Boolean function can be expressed as a sum (OR) of its 1- minterms.
A shorthand notation:
F(list of variables) = Σ(list of 1-minterm indices)
Example: (table 4.1)
F = x' y z + x y' z + x y z' + x y z = m3 + m5 + m6 + m7
Or
F (x, y, z) = Σ(3, 5, 6, 7)
COMSATS Institute of Information TechnologyPage 48
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
The inverse of the function can be expressed as a sum (OR) of its 0- minterms. A shorthand
notation
F'(list of variables) = Σ(list of 0-minterm indices)
Example: (table 4.1)
F ' = x' y' z' + x' y' z + x' y z' + x y' z' = m0 + m1 + m2 + m4
Or
F ' (x, y, z) = Σ(0, 1, 2, 4)
Table 4.1
Maxterm
A maxterm, denoted as Mi, where 0 ≤ i < 2n , is a sum (OR) of the n variables (literals) in
which each variable is complemented if the value assigned to it is 1, and un
complemented if it is 0.
1-maxterms = maxterms for which the function F = 1.
0-maxterms = maxterms for which the function F = 0.
 Any Boolean function can be expressed as a product (AND) of its 0- maxterms.
A shorthand notation:
F(list of variables) = Π(list of 0-maxterm indices)
COMSATS Institute of Information TechnologyPage 49
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Example: (table 4.2)
F = (x+y+z) • (x+y+z') • (x+y'+z) • (x'+y+z) = M0 • M1 • M2 • M4
Or
F (x, y, z) = Π(0, 1, 2, 4)
The inverse of the function can be expressed as a product (AND) of its 1-maxterms.
A shorthand notation
Example: (table4.2)
F ' = (x+y'+z') • (x'+y+z') • (x'+y'+z) • (x'+y'+z') = M3 • M5 • M6 • M7
Or
F ' (x, y, z) = Π(3, 5, 6, 7)
Table 4.2
STANDARD FORMS
SOP (sum of products):
The term "Sum of Products" or "SoP" is widely used for the canonical form that is a
disjunction (OR) of minterms.
COMSATS Institute of Information TechnologyPage 50
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
POS (product of sum):
The term "Product of Sums" or "PoS" for the canonical form that is a conjunction
(AND) of maxterms.
PRELAB TASKS:
1. Express the Boolean function F = x + y z as a sum of minterms by using truth table.
2. Express F ' = (x + y z)' as a product of maxterms.
3. Given the function as defined in the truth table, express F using sum of
minterms and product of maxterms
Table 4.3
IN-LAB TASKS
CIRCUIT IMPLEMENTATION
1.
2.
3.
4.
5.
First make the circuit diagram of desired Task.
Use logic gate ICs which are needed for tasks.
Insert connection clips according to circuit diagram you made.
Connect input to data switches and output to logic indicator.
Follow the input sequence and record the output.
TASK#1: Implement the circuit for given “F”. Function’s output is given in the table.
Finds its Boolean Expression in SOP and POS forms.
COMSATS Institute of Information TechnologyPage 51
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
O
A
0
0
0
0
0
0
0
0
1
1
1
1
1
B
C
0
0
0
0
1
1
1
1
0
0
0
0
1
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
F
F(SOP)
F(POS)
(Using NAND
Gates only)
(Using
NOR
0
0
0
1
0
0
0
1
0
0
1
1
1
Boolean Equation:
1.
Sum
of
2.
Reduced
3.
Product
4.
Reduced
Min-terms
SOP
of
form
Max-terms
POS
form
equation
equation
equation
equation
of
of
of
of
Circuit Diagram:
1. Sum of Min-terms forms:
COMSATS Institute of Information TechnologyPage 52
Downloaded by Academic Aids (academicaids9@gmail.com)
F:
F:
F:
F:
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
2. Reduced SOP form: (Implement circuit by NAND IC(s)):
3. Reduced POS form: (Implement circuit by using NOR IC(s))
POST-LAB TASKS
1) Write a Verilog code for the reduced SOP form of the function, F. (Structural
Level).
2) Write a Verilog code for the reduced POS form of the function, F. (Structural
Level)
3) Simulate and verify the outputs by making an appropriate stimulus for both
modules (Task1 and Task2)
COMSATS Institute of Information TechnologyPage 53
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
COMSATS Institute of Information TechnologyPage 54
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 55
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab 05- Logic Minimization of Complex Functions
using Automated Tools
Objective
Part 1
In this lab students will learn Karnaugh Map minimization and how to use logic minimization
automated tools for excessive number of variables in a function
Part 2
By using XILIUX ISE Simulation of minimized logic function results are verified after
writing Verilog Behavioral description code
Pre- Lab:
Background Theory:
We can simplify the equations and find a Boolean Function of any truth table using K-Map.
We need some basic concepts for K-Map; like Min Term and Max term.
Min Term:
A product of n variables where each of n variables appear exactly ones in complemented or
uncomplemented form is called the min term of n variables, and denoted by m n. (n starts
from 0 to 2n-1)
Max Term:
A sum of n variables where each of n variables appear exactly ones in complemented or
uncomplemented form is called the max term of n variables, and denoted by M n. (n starts
from 0 to 2n -1)
COMSATS Institute of Information TechnologyPage 56
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
K-Maps:
3-Variables:
4-Variables:
COMSATS Institute of Information TechnologyPage 57
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In-Lab:
Part 1: Automated Tool (Karnaugh Map Minimizer) (for variable >4)
Figure 5.1: Karnaugh Map Minimizer automated Tool Interface
Equipment Required:
KL-31001 Digital Logic Lab
Bread Board
Logic gate ICs
K-map Minimizer automated tool (Figure 5.1)
Procedure:
1. First make the circuit diagram for the desired task or subtask given by Lab
instructor.
2. Using k-map minimizer tool derive the simplified function
a. Set the number of variables.
b. Set the type of solution.
COMSATS Institute of Information TechnologyPage 58
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
c. Set the values of function ‘f’. (Function values can be generated
randomly)*
d. Click on solve button then solution will come on solution screen.
3. Using logic gate ICs (which is/are needed) for the tasks.
4. Insert connection clips according to the circuit diagram you made.
5. Connect inputs to data Switches and output to logic indicator.
6. Follow the input sequence and record the outputs in the table 5.1.
In-Lab Task 1:
Implement the minimized function given below using logic gate IC.
(Note: minterm’s will be specified by Lab Instructor)
Function in sum of min-terms form:______________________________________________
Function in simplified form using KMap:__________________________________________
Number of gates/ICs
used:______________________________________________________
COMSATS Institute of Information TechnologyPage 59
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Circuit Diagram of a min-terms form of the Function:
Circuit Diagram of a simplified Function:
Number of gates/ICs
used:________________________________________________________
COMSATS Institute of Information TechnologyPage 60
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Digital Logic Design
Truth Table:
Table 5.1 Results of logic function
Part 2: Verilog Design Task
Lab Equipment Required
 K-map minimizer tool
 XILIUX ISE Design tool
In-lab Task 2
Write a Verilog code for the 8 variable function.
F(A,B,C,D,E,F,G,H)=
∑(
,
,
,
COMSATS Institute of Information TechnologyPage 61
Downloaded by Academic Aids (academicaids9@gmail.com)
)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Procedure
 Function ‘ f ’should be generated by Karnaugh Map Optimizer automated tool*
 Function ‘ f ‘ should be random
 Simulate and verify the output by making an appropriate stimulus on XILIUX ISE
Results
(Verilog Code & Simulation Wave Forms)
COMSATS Institute of Information TechnologyPage 62
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
COMSATS Institute of Information TechnologyPage 63
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 64
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB # 06 XILINX ISE design flow with FPGA
Objective
Part 1
In this lab we learn about the XILINX software design flow with FPGA. Implement
different examples on FPGA
Part 2
Implementation of Gray code on FPGA Kit Diligent Nexys-2 Board
Pre-Lab:
Background Theory:
In the coding, when numbers, letters or words are represented by a specific group of symbols,
it is said that the number, letter or word is being encoded. The group of symbols is called as a
code. The digital data is represented, stored and transmitted as group of binary bits. This
group is also called as binary code. The binary code is represented by the number as well as
alphanumeric letter.
It is the non-weighted code and it is not arithmetic codes. That means there are no specific
weights assigned to the bit position. It has a very special feature that, only one bit will change
each time the decimal number is incremented as shown in fig. As only one bit changes at a
time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray
code cannot be used for arithmetic operation.
COMSATS Institute of Information TechnologyPage 65
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
6.1 Open existing project
Click on file menu and open existing project as shown in figure
Figure 6. 1 Open existing project
Select existing project and then follow as below
6.1.1 Selecting the User Constraints
Expanding the User Constraints menu
Click on I/O Pin Planning (Plan Ahead)
Figure 6.2: User Constraints Option Window
Click Yes for UCF file
Plan Ahead 13.2 window will open
COMSATS Institute of Information TechnologyPage 66
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 6.3: Plan Ahead 13.2 interface






Set the site for input and outputs o for example:
Output ‘C’ to Led0 (select J14ogic Desi
Output ‘S’ to Led1 (select J14)
Input ‘x’ to slide switch 0 (select G18)
Input ‘y’ to slide switch 1 (select H18)
Save the design and exit
6.2 Implementing the Design
Double click on Implement Design
Figure 6.3 Implement Design Option Window
COMSATS Institute of Information TechnologyPage 67
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
6.2.1 Generating a Programming File

Double click on Generate Programming File
Figure 6.4 Generate Programming File Option
Window

Bit file will be generated after the completion of ‘Generate Programming File’
process
6.2.2 Generating a Target PROM/ACE File

Double click on Generate Target Prom/ACE File
Figure 6.5 Generate Target PROM/ACE File Option Window
 ISE impact window will open
 Click on Boundary Scan option
 Then tight click on the white screen and select initialize chain
COMSATS Institute of Information TechnologyPage 68
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 6.5 ISE Impact Interface
Figure 6. 6 Bit file selection

After identification succeeded select the bit file and click on ‘Open’ button

Then bypass the second option
COMSATS Institute of Information TechnologyPage 69
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s

Right click on FPGA chip symbol and click on ‘Program’, to program the FPGA
Figure 6.7 Programming the FPGA
After the Program Succeeded message comes, test the output on FPGA by changing
different input value
In lab Task
Design and implement binary to gray code convertor on FPGA.
Provide K-Map solution and Boolean expression
Decimal Value in Binary
Gray Code Equivalent
A
B
C
D
w
x
y
z
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
COMSATS Institute of Information TechnologyPage 70
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
Table 6.1: Binary to Decimal Conversion Table
Post-Lab Tasks:
Provide gate-level circuit diagram of Gray code conversion
COMSATS Institute of Information TechnologyPage 71
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 72
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab #07: Design and Implementation of n-bit
Adder/Subtractor on FPGA
Objectives
Part 1
This experiment is to design gate-level hierarchal description of a 4-bit binary adder /
Subtractor in HDL and implement it on FPGA
Part 2
Introduce the different Verilog keywords (Parameter, always etc) and use them to simulate the
incremental function in Verilog.
Pre-Lab:
Background theory:
Binary Adder is digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of the next full adder in the chain. The process of addition
proceeds on a bit-by-bit basis, right to left, beginning with the least significant bit. After the
least significant bit, addition at each position adds not only the respective bits of the words,
but also consider a possible carry bit from addition at the previous position. Addition of n-bit
binary numbers requires the use of a n full adder, or a chain of one-half adder and n-1 full
adders. The four-bit adder is an example of a standard component. It can be used in many
applications involving arithmetic operations.
Binary Adder/Subtractor can be combined into one circuit with one common binary adder by
including an exclusive-OR gate with each full adder. A four-bit adder/subtractor circuit of two
binary numbers A(A3A2A1A0) and B(B3B2B1B0) is shown in Figure 7.1. The mode input M
controls the operation. When M = 0, the circuit is an adder. As B 0 = B, C0 = 0 , full adders
receive the value of B, and the circuit performs A + B. when M = 1, the circuit becomes a
subtractor. Now we have B 1 = B’ and C0 = 1. The B inputs are all complemented and a 1
is added through the input carry (C0 ). The circuit performs the operation A plus the 2’s
complement of B i.e A-B .The exclusive-OR with output V is for detecting an overflow and C
is carry out.
COMSATS Institute of Information TechnologyPage 73
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 7.1 Binary adder/subtractor with overflow
In lab:
The first part is implementation of hierarchal description of a 4-bit binary adder / Subtractor.
Part 1 - Implementing hierarchal description of a 4-bit binary adder /
Subtractor
4-bit binary adder / Subtractor is implemented by using the following method.
Figure 7.2
Procedure
 Write the HDL Verilog code for 4 bit binary adder in Xilinx software
 Create HDL project
COMSATS Institute of Information TechnologyPage 74
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
 Set the project settings:
o Family to Spartan3E
o Device to XC3S500E
o Package to FG320
o Speed to -4.
 Add the design files ‘my_4bit_ adder’ with two inputs A,B and outputs S,C,V. then
define submodules ‘FullAdder’ having three inputs and two outputs .
 Interconnect these ‘FullAdder’ modules as shown in figure 7.2 .
 Simulate your design using XST simulator.
 Define 8 inputs for A and B (4 bits for each binary number) on data silde switches on
FPGA.then 6 outputs are observed on LEDs .
 Burn the .bit file on FPGA and test the behaviour of Adder /Subtractor by choosing
the two different binary numbers.
 Fill the table 7.1 with addition of any two binary numbers and their result observed
on FPGA.
 write your Verilog code on your manual sheet.
Subscript j
3
2
1
0
Input Carry ( Cj
)
Augend ( Aj )
Addend (Bj)
Sum (Sj)
Output
Carry(Cj+1)
Subtract (Sj)
Table 7.1
(Write HDL code here)
COMSATS Institute of Information TechnologyPage 75
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Part 2 –Simulate and Implement the incremental function in Verilog
In this lab task, different keywords are introduced and use to build the example code.
Parameters: A parameter in Verilog can be any Verilog constant. Parameters are used to
generalize a design. For example a 4-bit adder becomes more useful as a design if it is put
together as an n-bit adder where n is a parameter specified by the user before compilation.
Parameter declarations are done immediately after the module declaration.
Here are some typical parameter examples:
parameter n = 12;
parameter [3:0]p1 = 4'b1011;
parameter n = 12, m = 32;
Always: An always block can be considered as a complex circuit part. It can be suspended or
activated. When any signal of the sensitivity list changes or an event occurs, the part is
activated and executes the internal procedural statements. The simplified syntax of an always
block with a sensitivity list (also known as event control expression) is
always @(sensitivity-list)
begin [optional name]
[optional local variable declaration];
[Sequential statements containing If, case, for, while
loop];
[procedural statement] ;
end
The (sensitivity-list) term is a list of signals and events to which the always block responds
(i.e., is "sensitive to"). For a combinational circuit, all the input signals should be included in
this list. The body is composed of any number of procedural statements. The begin and end
delimiters can be omitted if there is only one procedural statement in the body. The
@(sensitivity-list) term is actually a timing control construct. It is usually the only timing
control construct in a synthesizable always block.
Lab Task2 : Simulate
testbench.
Incremental function in Verilog. Also write its
Write HDL code here
COMSATS Institute of Information TechnologyPage 76
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Post-Lab:
Write the HDL (Verilog ) behavioral description of n-bit ripple carry adder /Subtractor:
o Select n=4 and implement on FPGA
o Select n=8 and make stimulus and show the results.
COMSATS Institute of Information TechnologyPage 77
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 78
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab #08: N-Bit Multiplier and Its Implementation
On FPGA
Objective
In this lab we will seek how to implement binary multiplier on FPGA.
Pre-lab:
Background Theory:
Binary Multiplier
Binary multiplier is used to multiply two binary numbers. Multiplication of binary numbers is
performed in the same way as multiplication of decimal numbers. It is build using binary
adders. The common multiplication method is “add and shift” algorithm. If the multiplicand
is N-bits and the Multiplier is M-bits then there is N* M partial product. AND gates are used
to generate the Partial Products. Note that in binary multiplication, the processes involve
shifting the multiplicand, and adding the shifted multiplicand or zero. Each bit of the
multiplier determines whether a 0 is added or a shifter version of the multiplicand (0 implies
zero added, 1 implies shifted multiplicand added). Thus, we can infer a basic shift-and-add
algorithm to implement unsigned binary multiplication.
General Expression
COMSATS Institute of Information TechnologyPage 79
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Example:
General Rules for A × B:





B : Multiplicand (K number of Bits)
A : Multiplier (J number of Bits)
Number of AND gates required = J x K
Number of K-bits Adder(s) required = ( J - 1 )
Number of bits required for product result = J + K
COMSATS Institute of Information TechnologyPage 80
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Fig:1 2-bit by 2-bit binary multiplier
Pre-lab Tasks
1. Do binary multiplication of A=3 and B= -7.
2. Implement 2-bit by 2-bit multiplier.
In-Lab Task 1:
1. Implement 4-bit by 3-bit binary multiplier using gate IC’s
COMSATS Institute of Information TechnologyPage 81
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Post-Lab Tasks
1. Write the HDL (Verilog) gate-level description of a four-bit multiplier and implement
on FPGA.
2. Write the HDL (Verilog) behavioral description of parameterized binary multiplier:
COMSATS Institute of Information TechnologyPage 82
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 83
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab #09: Design and Implementation of Binary to
BCD and BCD to 7-Segment decoder on FPGA
Objective
In this lab we design binary to BCD and BCD to 7-Segment decoders. And also learn how to
use 7-segment display of Nexys2 FPGA board.
Pre-Lab:
Background Theory:
Binary to BCD Decoder
In digital, binary-coded decimal (BCD) is a class of binary encodings of decimal numbers
where each decimal digit is represented by a fixed number of bits, usually four. Table 9.1
gives the four-bit code for one decimal digit. A number with k decimal digits will require 4k
bits in BCD.
Consider decimal 861 and its corresponding value in BCD and binary:
Table 9.1: Binary Coded Decimal (BCD)
Binary to BCD (Algorithm)
1.
2.
3.
4.
If any column (100's, 10's, 1's, etc.) is 5 or greater, add 3 to that column.
Shift all #'s to the left 1 position.
If 10 shifts have been performed, it's done! Evaluate each column for the BCD values.
Go to step 1.
COMSATS Institute of Information TechnologyPage 84
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Binary to BCD (Pseudo Code)
for
(i=9; i<=0;
i=i-1)
{ //Check for all columns (H,T,U) for >=5
if (Hundreds >= 5)
Hundreds = Hundreds + 3;
if (Tens >= 5)
Tens = Tens + 3;
if (Ones >= 5)
Ones = Ones + 3;
//Shift all binary digits left 1
Hundreds =Hundreds <<1;
Hundreds[0] = Tens[3];
Tens =Tens <<1;
Tens[0] = ones[3];
Ones =Ones << 1;
Ones[0] = Binary[i];
}
BCD to 7-Segment Decoder
BCD to 7-segment decoder decodes the BCD value on 7-Segment display.
7-Segment Display
A seven-segment display (SSD) is a form of electronic display device for displaying decimal
numerals. The seven elements of the display can be lit in different combinations to represent
the decimal numerals. Often the seven segments are arranged in an oblique (slanted)
arrangement, which aids readability. Seven-segment displays may use a light-emitting diode
(LED) a liquid crystal display (LCD), for each segment, or other light-generating or
controlling techniques. There are two types of simple LED package 7-Segment display:

Common Anode

Common Cathode
COMSATS Institute of Information TechnologyPage 85
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
7-Segment (Common Anode) Displays on Nexys2 board
Nexys2 board contains a four-digit common anode seven-segment LED display. Each of the
four digits is composed of seven segments arranged in a “figure 9.1” pattern, with an LED
embedded in each segment. Segment LEDs can be individually illuminated, so any one of
128 patterns can be displayed on a digit by illuminating certain LED segments and leaving
the others dark.
The anodes of the seven LEDs forming each digit are tied together into one “common anode”
circuit node, but the LED cathodes remain separate. The common anode signals are available
as four “digit enable” input signals to the 4-digit display. The cathodes of similar segments on
all four displays are connected into seven circuit nodes labeled CA through CG (so, for
example, the four “D” cathodes from the four digits are grouped together into a single circuit
node called “CD”). These seven cathode signals are available as inputs to the 4-digit display.
This signal connection scheme creates a multiplexed display, where the cathode signals are
common to all digits but they can only illuminate the segments of the digit whose
corresponding
anode
signal
is
asserted.
Figure 9.1: Nexys-2 7-Segment Displays
COMSATS Institute of Information TechnologyPage 86
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 9.2: Nexys2 I/O devices and circuits
CASE statement in Verilog
 Syntax:
case (switching variable)
Label Value1: statement(s);
Label Value2: statement(s);
Label Value n: statement(s);
default: statement(s);
endcase
 Example (4-to-1 MUX using CASE statement)
module mux_4_1( Y, I, S );
output
reg Y;
COMSATS Institute of Information TechnologyPage 87
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
input [3:0]I;
input [1:0]S;
always @ ( I or S)
begin
case ( S) //As MUX output is selected by selection line, here ‘S’,
so it is a switching variable
2’b00:
Y = I[0]; // when S=00 then I0 is selected for output
2’b01:
Y = I[1]; // when S=01 then I1 is selected for output
2’b10:
Y = I[2]; // when S=10 then I2 is selected for output
2’b11:
Y = I[3]; // when S=11 then I3 is selected for output
default: Y = 1’b0; // when S=zz or xx then output is 0 (By default)
endcase
end
endmodule
In-Lab Task 1:
Write the HDL (Verilog) behavioral description of BCD to 7-Segment decoder and
implement on FPGA.
First make a truth table for BCD to 7-Segment decoder which has 4-inputs and 8-outputs (A
to G and DP) of 7-Segment display (in given below space).
COMSATS Institute of Information TechnologyPage 88
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
A
Inputs
B
C
a
b
Outputs
c
d
e
f
g
D
Implement it on FPGA (Only one 7-Segment should be on) and write down the Verilog code
below.
COMSATS Institute of Information TechnologyPage 89
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In-Lab Task 2:
Write the HDL (Verilog) behavioral description of binary to BCD decoder and implement on
FPGA.
COMSATS Institute of Information TechnologyPage 90
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
COMSATS Institute of Information TechnologyPage 91
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 92
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
LAB # 10:Implementation of up/down Counter with
Terminal Count and Reset on FPGA
Objective
In this lab we implement up/down counter with terminal count and reset on FPGA. We also
learn how to use internal clock of FPGA and implement clock divisor. The counter value
will be displayed on 7-segment displays of Nexys2 board so we implement scanning display
controller to control multiple 7-segment displays because they have common data bus (CA –
DP).
Pre-Lab:
10.1 Up/down counter with terminal count and reset
A counter is essentially a register that goes through a predetermined sequence of binary
states. The gates in the counter are connected in such a way as to produce the prescribed
sequence of states. Although counters are a special type of register, it is common to
differentiate them by giving them a different name.
Up/Down Counting:

When up_down signal is low: counter will count in ascending order

When up_down signal is high: counter will count in descending order
Reset: (Active High reset)

When reset signal is low: counter will count normally

When reset signal is high: counter will be clear
Enable: (Active High)

When enable signal is low: counter will stop counting

When enable signal is high: counter starts counting
Terminal count:

Terminal count is an output signal which actives under any desired condition or
counter will reach to a specific value
COMSATS Institute of Information TechnologyPage 93
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Clock:

Counter will count up or down on active transition of the clock
10.2. 7-Segment Displays Controller
A scanning display controller circuit can be used to show a four-digit number on Nexys2
board 7- segment display section. This circuit drives the anode signals and corresponding
cathode patterns of each digit in a repeating, continuous succession, at an update rate that is
faster than the human eye can detect. Each digit is illuminated just one-quarter of the time,
but because the eye cannot perceive the darkening of a digit before it is illuminated again, the
digit appears continuously illuminated. If the update or “refresh” rate is slowed to around 45
hertz, most people will begin to see the display flicker. In order for each of the four digits to
appear bright and continuously illuminated, all four digits should be driven once every 1 to
16ms, for a refresh frequency of 1KHz to 60Hz. For example, in a 60Hz refresh scheme, the
entire display would be refreshed once every 16ms, and each digit would be illuminated for
¼ of the refresh cycle, or 4ms. The controller must drive the cathodes with the correct
pattern when the corresponding anode signal is driven. To illustrate the process, if AN0 is
asserted while CB and CC are asserted, then a “1” will be displayed in digit position
1. Then, if AN1 is asserted while CA, CB and CC are asserted, then a “7” will be
displayed in digit position 2. If AN0 and CB, CC are driven for 4ms, and then A1 and CA,
CB, CC are driven for 4ms in an endless succession, the display will show “17” in the first
two digits. An example timing diagram for a four-digit controller is provided.
Figure 10.1: Refresh period trimming diagram for 4 digit 7-segment
display
10.2.1
Clock Divisor by using Nexys2 Board Internal Clock
Clock divisor circuit is implemented to use the slower version of the clock by using internal
clock of the board. Nexys2 board has an internal clock of 50 MHz.
 Example: 40 ns clock:
As f = 50 MHz so T = 20 ns
COMSATS Institute of Information TechnologyPage 94
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
So if we need 40 ns clock then we count the internal clock of 50 MHz twice then
make change once in 40 ns clock. That is count 2 and when 2 occurs terminal count will be
one for a while then the terminal count output of that counter will be clock of 40 ns.
MUX is used for Digit data and segment id
As 4-digit 7-segment displays have common data bus so multiplexer is used to select one
data and segment id at a time of refresh period
In lab Task
1.
2.
3.
Write a HDL (Verilog) behavioral description of up/down counter with terminal
count, enable and reset.
Write a HDL (Verilog) behavioral description for binary to display module
which multiplexed between segment data and segment digit id.
Join all the necessary modules with respective parameters to implement the
task1 counter on FPGA and display counter result on 7-segment display
Post-Lab Tasks:
Provide simulation result of task 3
COMSATS Institute of Information TechnologyPage 95
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
COMSATS Institute of Information TechnologyPage 96
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 97
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab #11Mealy /Moore Machine implementation of
Sequence Detector
Objective
This experiment is to design behavioral description of Sequence detector using Mealy/Moore
models of Finite State Machine (FSM) and implement designs into Xilinx
Pre-Lab:
Background theory:
The most general model of a sequential circuit has inputs, outputs, and internal states. It is
customary to distinguish between two models of sequential circuits: the Mealy model and the
Moore model. They differ only in the way the output is generated. The two models of a
sequential circuit are commonly referred to as a finite state machine, abbreviated FSM.
In the Mealy model, the output is a function of both the present state and the input as shown
in Figure 11.1. the outputs may change if the inputs change during the clock cycle. the output
of the Mealy machine is the value that is present immediately before the active edge of the
clock.
Figure 11.2 Mealy machine
COMSATS Institute of Information TechnologyPage 98
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
In the Moore model, the output is a function of only the present state. A circuit may have both
types of outputs as shown in Figure 11. 2. The outputs of the sequential circuit are
synchronized with the clock, because they depend only on flip-flop outputs that are
synchronized with the clock.
Figure 11.3 Moore machine
In lab:
Implementation of Mealy machine
Design a Finite State Machine (FSM) for a Sequence given below, Sequence detector :10110
Lab Task 1: Circuit diagram, State table, State diagram
Draw the circuit diagram, state table and state diagram and for sequence detector
(Mealy/Moore)
COMSATS Institute of Information TechnologyPage 99
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab Task 2: HDL implementation for Mealy machine
Write the HDL (Verilog) behavioural description for Mealy based sequence detector for the
given sequence. Simulate the design and paste the output waveforms.
COMSATS Institute of Information TechnologyPage 100
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
(Write HDL code here)
COMSATS Institute of Information TechnologyPage 101
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
(Paste the simulation output waveforms of Mealy Model here)
COMSATS Institute of Information TechnologyPage 102
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab Task 2: Implementation of Moore machine
Write the HDL ( Verilog ) behavioural description for Moore based sequence detector for the
given sequence. Simulate the design in Xilinx. Record the simulation output waveforms in
observations.
Write HDL code here
COMSATS Institute of Information TechnologyPage 103
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
(Paste the simulation output waveforms of Moore Model here)
Post Lab
Write a Verilog model of the Mealy FSM described by the state diagram in Figure11.
3.Develop a test bench and demonstrate that the machine state transitions and output
correspond to its state diagram.
COMSATS Institute of Information TechnologyPage 104
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Figure 11.4 State diagram
COMSATS Institute of Information TechnologyPage 105
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
COMSATS Institute of Information TechnologyPage 106
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 107
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Lab #12 Universal Shift Register On FPGA
OBJECTIVE
In this lab we implement Universal Shift Register on FPGA and perform all operations of
Universal Shift Register.
PRE LAB
REGISTER
A register is a digital circuit with two basic functions:


Data storage
Data movement
SHIFT REGISTER
A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs
connected together in such a way that the data is shifted from one device to another when the
circuit is active.
UNIVERSAL SHIFT REGISTER
A universal shift register is an integrated logic circuit that can transfer data in three different
modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it
can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the
universal shift register can combine the capabilities of both parallel and shift registers to
accomplish tasks that neither basic type of register can perform on its own. For instance, on a
particular job a universal register can load data in series (e.g. through a sequence of left
shifts) and then transmit/output data in parallel.
Depending on the signal values on the select lines of the multiplexers, the register can retain
its current state, shift right, shift left or be loaded in parallel. Each operation is the result of a
positive edge on the clock line.
In order for the universal shift register to operate in a specific mode, it must first select the
mode. To accomplish mode selection the universal register uses a set of two selector
switches, S1 and S0. As shown in Table 12.1, each permutation of the switches corresponds
to a loading/input mode.
COMSATS Institute of Information TechnologyPage 108
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Table 12.1
Locked Mode:
In the locked mode (S1S0 = 00) the register is not admitting any data; so that the content of
the register is not affected by whatever is happening at the inputs.
Shift-Right Mode:
In the shift-right mode (S1S0 = 01) serial inputs are admitted from Q3 to Q0. You can
confirm this aspect by setting the value of the shift-right switch according to the sequence
1100100 as you cycle the clock; see Table 12.2. Watch as the signals move from Q3 to Q0. In
the shift-left mode (S1S0 = 10) the register works in a similar fashion, except that the signals
move from Q0 to Q3.
Table 12.2
Parallel-loading mode:
Finally, in the parallel loading mode (S1S0 = 11) data is read from the lines L0, L1, L2, and
L3 simultaneously. Here, setting L3L2L1L0 = 1010 will cause Q3Q2Q1Q0 = 1010 after
cycling the clock as depicted in Table 12.3.
COMSATS Institute of Information TechnologyPage 109
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Table 12.3
Four bit universal register diagram is shown in fig.
Fig 12.1
COMSATS Institute of Information TechnologyPage 110
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Fig12.2
4-bit universal shift register
PRELAB TASK
Write properties of clear, clock, shift-right , shift-left ,parallel –load of Universal Shift
Register.
LAB TASK
1.
Implement Universal Shift Register on FPGA.
POST LAB TASK
1.
2.
Write HDL (Verilog) structural description for Universal Shift Register.
Simulate the task #1 on Xilenx.
COMSATS Institute of Information TechnologyPage 111
Downloaded by Academic Aids (academicaids9@gmail.com)
lOMoARcPSD|29615521
LAB #02 Boolean Function and Universal Gates Implementation on Kl-31001 Trainer using Gate Ic’s
Critical Analysis/Conclusion
Lab Assessment
Pre Lab
/5
Performance
/5
Results
/5
Viva
/5
Critical Analysis
/5
/25
Instructor Signature and Comments
COMSATS Institute of Information TechnologyPage 112
Downloaded by Academic Aids (academicaids9@gmail.com)