Agilent EEsof EDA
Designing for Signal Integrity with Advanced Design System
Jump the Gigabit-per-Second Barrier
Increasing consumer and business
demand for digital entertainment and information transmission is driving the need
for high-speed systems such
as routers, servers, mass storage system, and PCs. Chip-tochip connections inside these
systems have undergone
an architectural shift from
parallel busses to serializer/
deserializer (SERDES) links.
Such serial links eliminate
parallel bus clock skew and
reduce the number of traces
— advantages that come at
the cost of large increases
in bit rate on the remaining
traces. At data rates greater
than a gigabit per second
and with channel flight times
longer than a bit period, signal
integrity is a major concern.
Under these conditions,
high-speed analog effects,
previously only seen in highfrequency RF and microwave
engineering, can impair the
signal quality and degrade the
bit error rate of the link.
17.5
Clock frequency (GHz)
15.0
12.5
10.0
7.5
Parallel bus
Serial bus
5.0
2.5
0
1998
2000
2002
2004
2006
2008
Year
2010
2012
2014
2016
Projected increase of
clock frequencies
Source: ITRS 2004
Update to the SIA Roadmap
2
These bundles, listed in Table 1, provide
the most complete serial link analysis for
standards such as Infiniband, PCI Express,
RapidIO, DDR, HDMI, and 10 gigabit/s
Ethernet. They allow you to:
n Analyze complete serial links by
co-simulating individual components,
each at its most appropriate level of
abstraction: link-, circuit- or physicallevel.
n Import S-parameter accurately into
transient simulation.
n Perform jitter diagnosis with the
proven EZJIT Plus algorithm used in
Agilent instruments, resulting in
dramatically reduced product design
cycles.
The following sections highlight key
features of the main modules that make
up these bundles.
On-board
On-chip
Agilent EEsof EDA has for years been
proud to offer Advanced Design System
(ADS) as the premier simulator of RF and
microwave effects. RF and microwave
engineers trust ADS to analyze their
circuits and to help them mitigate the
impairments encountered at these
frequencies. Now, through continuous
research and innovation, Agilent EEsof
EDA offers three ADS bundles that put
the applicable simulators, libraries, and
capabilities into the hands of signal
integrity engineers.
ADS Signal Integrity Designer bundles come in different configurations
to meet your design requirements.
The following product configuration matrix illustrates the capabilities in each bundle.
E9010L ADS
E9011L ADS
Signal Integrity
Signal Integrity
Designer
Designer Pro
E8900 ADS Design Environment
n
n
E8901 Data Display
n
n
E5720 Connection Manager
n
n
E8881 Linear Simulator
n
n
E8884 High Frequency SPICE
n
n
E8885 Convolution Simulator
n
n
E8949 IBIS I/O Models
n
n
E8951 Multilayer Interconnect Models
n
n
E8921 Momentum 3D-Planar EM Simulator
n
E8922 Momentum Visualization
n
E8902 Layout
n
E8904 GDSII Translator
n
E8905 DXF Translator
n
E4687 Broadband SPICE Model Generator
n
E8828 Signal Integrity Verification Toolkit
n
E8823 Ptolemy Simulator
E8819 EMDS for ADS 3D EM Simulator
E9012L ADS
Signal Integrity
Designer Premier
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
High Frequency SPICE and Convolution Simulator
dB (Channel_Sparameter_Simulation S(21))
dB (varC”CMP1_FFT_IMP(2;1)freqResp”)
At data rates exceeding a gigabit per
second, the most accurate way to characterize interconnect is by S-parameter
measurements using a multiport vector
network analyzer.
However, these
0
measured data must
-20
first be converted to
a time-domain mod-40
el before circuit- and
link-level metrics
-60
like eye diagrams
or BER channel
-80
performance can be
determined in the
-100
simulator. For electrically short lines
-120
0
2
4
6
8 10 12 14 16 18 20
without serious
Frequency (GHz)
attenuation, lumped
element SPICE
or pole/zero models are adequate, and
Comparison of 10 gigabit/second
indeed Broadband SPICE Model Generator
measured backplane S-parameters
(discussed in detail below) performs such
with “round trip” S-parameters
a conversion. However, for electrically
derived from the model in ADS
long transmission lines or cases with deep
Convolution Simulator.
attenuation, the Convolution Simulator is
faster and more accurate.
3
The Convolution Simulator derives a
time-domain impulse response from the
frequency-domain interconnect models
while applying physical constraints such
as passivity and delay-causality. The
model is then convolved with the digital
input signal to accurately predict link-level
performance. It takes into account effects
such as skin effects, dispersion, and
dielectric losses that are associated with
high frequency transmission lines.
The patented convolution technology in
ADS provides several powerful techniques
for causality correction, delay causality
enforcement, passivity enforcement, and
optimal techniques for frequency response
preservation. The Convolution Simulator
works transparently with High Frequency
SPICE and enables concurrent simulation of non-linear transistor level devices
with models derived from S-parameters.
High Frequency SPICE natively supports
unencrypted HSPICE netlists, and HSPICE
netlists encrypted with the ADS encryption key. An example of the latter is the
Stratix II FPGA transceiver library, available as a no-charge download from Altera.
Decomposition of TDR/TDT measurements
Time Domain Reflectometry (TDR) and
Time Domain Transmission (TDT) are
measurement techniques that characterize a complex channel by sending
an abrupt voltage step down a line and
comparing the incident, transmitted, and
reflected voltage waves. The shape and
polarity of the transmission and reflection
gives information
about the position
2
TDR/TDT response for a
2.5-Gbps differential channel
TDR into channel 1& 1
500
400
60
40
20
0
-20
TDR
Time (nsec)
V2_mrs, mV
600
4
Time (nsec)
500
Broadband SPICE Model Generator
300
100
-100
V4_mrs, mV
V3_mrs, mV
V1_mrs, mV
3
and nature of impedance changes at each
discontinuity. The ADS High Frequency
SPICE and Convolution Simulator combine
to form a highly accurate method for
decomposing the measured TDR/TDT
response into component behavior. By
adjusting the component parameters to fit
the composite response, you can reveal
the cause of the underlying channel
impairments.
10
0
-10
-20
The Broadband SPICE Model Generator provides the capability
to convert measured or simulated S-parameter models to
lumped equivalent or pole zero representations. Lumped equivalent representations can be used with various types of SPICE
simulators. It also gives you the ability to enforce passivity
during broadband SPICE model extractions.
TDT
Time (nsec)
Time (nsec)
Multilayer Interconnect
Models
This library contains up to 40 metal layers
and 80 coupled lines. It offers an alternative trade off in simulation speed versus
accuracy compared with the Momentum
Planar EM simulator. The models run
faster than Momentum, but Momentum is
more accurate. The effects of impedance,
loss, crosstalk, and delay are modeled
with the simplified underlying 2-D electromagnetic field solver associated with
these models.
0
Multilayer Interconnect Models have
advantages over microstrip and stripline
models, including a greater number of
available coupled-line models, the ability
to place them on any specific layer, and
automatic computation of microstrip or
stripline operations.
-20
-40
-60
0
4
8
12
16
Frequency (GHz)
20
Broadband SPICE model overlays
exactly with original S-parameters
for a RambusTM device
Multilayer
interconnect
models
4
Signal Integrity Verification Toolkit
The Signal Integrity Verification Toolkit features powerful jitter analysis capabilities and
provides excellent correlation between simulated and measured
jitter components
and BER measurements. The jitter
algorithm in ADS
is based on and is
verified against the
CLK_onchip, V
CLK_src, V
IBIS I/O models
4
IBIS (I/O Buffer Information Specification) is a public-domain, industry-standard specification modeling input and
outputs of digital circuits. Semiconductor vendors may create IBIS models for
their parts and distribute them for use
2
0
-2
High Frequency SPICE natively supports unencrypted HSPICE netlists, and all SPICE dialects
encrypted with the ADS encryption key. Signal
Integrity Verification Toolkits add support for
HSPICE netlists encrypted with the Synopsys
HSPICE encryption key, through co-simulation
with HSPICE itself.
ADS provides powerful jitter analysis for analyzing
all the random and deterministic jitter components
present in a digital signal. It also provides accurate
BER bathtub plots. The
capability is based on
patented EZJIT Plus
technology, which is
available in Agilent’s
real-time oscilloscopes.
The Eye Diagram front panel in
ADS allows you to calculate eye
diagram parameters using an
interface that is similar to that of
Agilent instruments
6
patented EZJIT Plus algorithm used in Agilent’s
test and measurement instruments.
0
20
40
60
80
100
Comparison of
received on-chip
time-domain
waveform and its
source waveform.
in any IBIS-compatible simulator. IBIS
simulation provides faster simulation as
compared with equivalent-circuit SPICE
models. Using IBIS models, the nonlinear
effects of integrated circuit I/O buffers
can be modeled faster and more precisely,
using vendor-supported information. ADS
presently supports the IBIS
4.2 specification. Agilent
representatives on the EIA
IBIS committees contribute
to and track these evolving
standards, and help keep
Agilent EEsof EDA tools
up-to-date.
IBIS model palette and
schematic showing timedomain simulation of IBIS
models, package traces,
and nonlinear transistor
devices based on ASIC
and S-parameter models.
5
Electromagnetic (EM) Simulators
Agilent EEsof EDA offers two EM simulators in ADS: Momentum and EMDS. These
tools employ the method of moments and
finite element method (FEM) methods,
respectively.
Momentum 3D-planar EM
simulator
Momentum is a 3-D planar electromagnetic (EM) simulator used for accurate
interconnect analysis. It accepts arbitrary
planar design geometries (including multilayer traces and viaas) and accurately
simulates complex
3-D EM effects
including coupling
and parasitics.
Accurate EM
simulation enables
signal integrity
designers to
improve interconnect performance
and increases
confidence that
the manufactured
product will function as simulated.
Trace and via modeling in
ADS Momentum
Momentum RF is a second solver technology within the Momentum EM engine that
reduces simulation time, compared with
Momentum’s regular microwave solver
technology, without sacrificing accuracy.
It is particularly applicable to large and
complex structures.
Electromagnetic/circuit co-simulation
6
with layout components breaks down the
barriers between electrical and physical
analysis domains. The layout component
technology allows ADS users to create
layout components that can be used
in both the physical and the schematic
design views. Once artwork and ports are
defined, the user can generate a layout
component with the click of a button.
Because Momentum is integrated into the
ADS design flow, simulation setup times
are reduced, and design productivity is
increased.
EMDS for ADS 3D EM
simulator
There are many types of components such as
bondwire arcs and dielectric bricks that require
3-D electromagnetic analysis on non-planar
geometries. E9012L ADS Signal Integrity
Designer Premier includes an integrated finite
element analysis tool called EMDS. Designers
can use ADS layout tools or import a layout
from a third-party layout package and simulate
it using either Momentum (based on the
method of moments) or EMDS (based on the
finite element method).
Ptolemy Simulator
The ADS Signal Integrity Designer Premier
includes ADS Ptolemy. This module simulates the link-level digital signal processing (DSP) components used in SERDES
transceivers, such as FIR pre-emphasis
filters, fixed and adaptive equalizers such
as line codecs, feed forward equalizers
(FFEs) and decision feedback equalizers
(DFEs). It’s ideal for serial link simulation because it provides the ability to
co-simulate these DSP components with
the analog and RF components for true
mixed-signal environments with link-,
circuit-, and physical-level abstractions.
The analog/RF components could be linear components such as S-parameters or
nonlinear components such as transistors
and IBIS models. They can be designed in
ADS or imported from a third-party layout
database.
ADS Ptolemy allows integration of
language-based algorithms and intellectual property (IP) into the channel path.
Languages supported natively include
C, C++, SystemC, and Verilog-A. Digital
HDLs (Verilog and VHDL) are supported
by co-simulation with NC-Sim from
Cadence or ModelSim from Mentor
Graphics. Similarly, Agilent Ptolemy
supports co-simulation with MATLAB
from The MathWorks.
ADS provides system components such
as 8B10B coders/decoders, 64B66B coders/decoders, FIR filters, PRBS sources,
FFE and DFE equalizers, oscillators, and
other system components required to
represent a serial link.
2.0
1.5
1.0
0.5
5.0
-0.5
-1.0
-1.5
-2.0
0.0 2.0E3 4.0E3 6.0E3 8.0E3 1.0E4
Output waveform of a DFE
showing the convergence
and adaptive eye opening.
Transmitter
Analog channel
Link-level co-simulation
combines the analog channel
with adaptive equalizers.
Receiver
An ADS simulation of
a 10-Gbps serial link
7
World-class support, training, and services
All Agilent EEsof EDA products are
backed by a world-class team of experienced application and technical support
engineers who are dedicated to providing
the right software, support, and consulting solutions to increase engineering
productivity and long-term success. We
offer worldwide, local-language, technical
support via telephone, fax, e-mail, and the
worldwide web.
In addition, our web-based Agilent EEsof
Knowledge Center is an around-the-clock
resource for comprehensive support
information and downloadable examples
for all our products. It hosts software
updates and has a tracking feature that
makes it easy for you to submit and man-
age support cases and related enhancement requests. The search feature lets
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sort through them by date, popularity, or
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put you in touch with other users, support
engineers, and product developers. And,
you can get training when and where you
want it through e-learning short courses
and technical information sessions.
Every team’s design flow has aspects that
are unique. To save time and get individual attention focused on your application,
take advantage of our consulting solution
services. We offer complete consulting in
signal integrity.
Contact your Agilent EEsof EDA
field sales engineer for more
information or for a free evaluation.
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System to signal integrity challenges, visit:
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For information about Agilent’s ADS Signal Integrity bundles,
visit:
www.agilent.com/find/eesof-si-products.
To request an evaluation of Agilent’s Signal Integrity
solutions, visit:
www.agilent.com/find/eesof-si-demo-software-request.
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Revised: October 24, 2007
Product specifications and descriptions
in this document subject to change
without notice.
© Agilent Technologies, Inc. 2008
Printed in USA, May 14, 2008
5989-8392EN