Design of a 32 – bit
RISC – V Core
(RV32I)
NAVINKUMAR K – ECE - B
19EC1067
Overview
1. Quick Intro and Motivation
2. Proposed Microarchitecture and RV32I ISA
3. Features of the design
4. Design steps (System Verilog)
5. Simulation and Verification
6. Measuring the Performance
7. Adding more features and Superscalar Architecture Proposal
8. Conclusion
Why do we
need RISC – V
Architecture?
Developed at UC, Berkeley
Open – source ISA
One for all
Incorporates
lessons from
previous decades of
processor design
Modular ISA
Optional extensions
for 64 – bit and
even 128 – bit
Flexible and no
forced
implementations
Proposed
Microarchitecture
S L I G HT LY B AS ED ON MI PS 16 PROC ES S OR
R E F EREN CES :
C O M P U T E R O R G A N I Z AT I O N A N D D E S I G N T H E H A R D W A R E S O F T W A R E
I N T E R FA C E [ R I S C - V E D I T I O N ] , D AV I D A . PAT T E R S O N , J O H N L . H E N N E S SY
D I G I TA L D E S I G N A N D C O M P U T E R A R C H I T E C T U R E , R I S C - V E D I T I O N , 1 S T E D I T I O N , S A R A H L .
H A R R I S , D AV I D H A R R I S
Proposed Microarchitecture (diagram created using Draw.io software)
RV32I ISA
Need this for decoder design!
Types of Instructions
Immediate Extender unit uses this table
Features
Based on RV32I Core
Supports 27 instructions of the total 37 instructions
Basic Integer Processing (Add/Sub, Logical, Shift Operations)
Datapath – Controller Design
5 – stage Pipeline design
Complete Hazard Handling (Data Hazards and Control Hazards)
Modular and highly extensible
Design Steps
SYSTEM VERILOG USED AS THE HDL
Load Word First
lw x1, 2(x7)
[x7 + 2] = x1
Store Word
sw x1, 9(x5)
x1 = [x5+9]
R - type
and x1, x2, x3
5 - stage Pipelined Datapath
Control Unit (Split into two modules)
Main
Decoder
Main Decoder
Control
Unit
ALU
Decoder
•For determining the type of
instruction
ALU Decoder
•Determines the operation to
be performed by the ALU
Hazard
Handling
Occurs when an instruction
depends on the results of the
previous instruction which is not
yet completed.
Data Hazard
1. Data Hazards
1. Forwarding
2. Stalling ( for load word )
2. Control Hazards
1. Flushing
Solution
Stalling for
load word
hazard
Since the result of load instr. not
available till the end of Memory
Access Stage, we stall the next
instructions by cycle.
Load word hazard
When result appears in Write Back
Stage, we forward it to the
execution stage.
Solution
Control Hazards
We flush the following two instructions whenever the branch is taken. Flush decode and execute stage.
Design steps summary
Implement Load Word Instruction first
Then Store Word Instruction
Modify datapath and decoder to include R - type
Add branch and store instructions (MUX for PC)
Debug and Verify
Pipeline the data path and the controller
Design Hazard Unit
Debug and verify
Simulation and
Verification
TOOLS USED: INTEL QUARTUS PRIME LITE, VS CODE
Performance
Measurement
CRITICAL PATH, MAX. FREQUENCY, AVERAGE CPI
Critical Path
Performance
Measurement
Future Goals
More Pipeline stages
Implement superscalar architecture
Cache memory
Branch Predictor
Thank You