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Clientthe person/institution funding the product
HexA numerical notation using base 16
How to convert Binary to Hex?Make it the capacity of a byte (8 bits long), split it into 2, then use the table for conversion. 
How to convert Hex into Binary?Each Hex number seperately, find each letter/number equivalent on the table, put them together
How to convert Decimal into BinaryDivide by two, note 1 for each odd number and note 0 for each even number. from bottom to top put together the string of binary.  
How to convert Decimal into HexConvert to binary, then turn the binary into byte form and break it in half
<div><div><div>&nbsp;</div></div></div><div>What is true color?</div>Maximizing the 24 slots of hex bits available
"Represent 78 (base 10) in its equivalent (base 16) format
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"11001 (base 2) into decimal
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"(11010110) base 2 -&gt; hexadecimal
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"1001101 (base 2) -&gt; (base 16)
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"Convert 75 (base 10) into hexadecimal
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Lossy CompressionFiles will lose quality when it is compressed
Run Length Encoding (RLE)A method of compression that looks for repeating patterns and encodes them into one item of data of a specific length
Processor SpeedMillions instructions per second (MIPS)
Convert (89) Base 10 to its equivalent Base 2 representation<div>01011001</div>
Convert 101101 to its equivalent BASE 16 representation4D
DRAM constantly leaks, so it requires constantrefreshing
The secondary memory and CPU are connected. True or False?False
Define Virtual Memory"It hides the complexities of functions. It's the process of moving out idle applications from 1⁰&nbsp;to the 2⁰&nbsp;(temporarily) to make space for incoming applications. It's returned to primary memory as needed and stored in units called ""pages"""
Memory LeakWhen an application is quit but the allocated memory is still being used
Types of bandwidthPeak theoretical bandwidth and sustained memory bandwidth
Batch processingPrograms are batched together then executed as a group
MultiprogrammingRun/access multiple cores. Two or more programs may be loaded in the main memory
Multi-threadingA program is written in threads that can be executed in parallel
Benefits of Multi-threadingFaster<br>Effecient in relation to using a single cpu/single core system
What does core mean?CPU or system
Multi-processingComputer system has more than one core, so run across multiple cores
Negatives of multi-threadingThreads can't be dependent on the same resource - leads to deadlock
DeadlockWhen two or more processes are blocked, needing to access shared resources in a specific order.&nbsp;
Multi-accessAllows for multiple users to use the same client [disk partition -&gt; uses authentication methods to identify users]
MAC AddressStanding for Media Access Control Address, it's a unqiue 12-character alphanumeric attribute that is used to identify individual electronic devices on a network. It's built in and cannot be removed (anymore)
What is the O/S responsible for, with regards to the IP and MAC&nbsp;it's responsible for the IP and MAC addressing related to the client, whenever a connection/session is established
ASCIIA character set which involves all Latin letters
UnicodeAn extension of ASCII that adds other languages support
What does Unicode use to extend it's predecessor?It combines different letters to create new, longer ones. Goes to UTF-8, UTF-16, UTF-32
ROMNon-volatile primary memory
Burst TimeCPU time occupied by process without waiting for input/output
Run TimeThe time taken, alongside fetching/waiting and executing
Three states of a job in the CPUWait -&gt; Ready -&gt; Execute
Two types of compression algorithmslossy compression and lossless compression
SpoolSequence of print jobs
Task Scheduling Algorithms- First come first serve<br>- Shortest job first<br>- Round robin<br>- Multi-Level Feedback Queue<br>- Multi-Level Queue
Round RobinCPU allocates / runs every job in a predetermined time slice, so basically&nbsp;splits the work of all the available into the same portions of tasks and does it at the same time. Ex. 4ms for task 1, even if it's too much or not enough time.&nbsp;
"Multi-Level Queue [<span style=""color: rgb(255, 255, 255);"">Without&nbsp;Feedback]</span>"- Assigned priority and dependencies<br>- Children rely on parents to execute their tasks&nbsp;<br>- Because this version has no feedback, it will run without giving errors and can give indecipherable outputs
"<span style=""color: rgb(255, 255, 255);"">Polling</span>"Processor continuously (ie preset frequency) checks the periphreal devices on their status
"<span style=""color: rgb(255, 255, 255);"">Interuppt</span>"When the periphreal device issues an error/interrupt signal to the processor to signify change in status
"<span style=""color: rgb(255, 255, 255);"">Benefit&nbsp;and&nbsp;negative&nbsp;of&nbsp;polling</span>"Resource intensive but optimal behavior
"<span style=""color: rgb(255, 255, 255);"">Benefit&nbsp;and&nbsp;negative&nbsp;of&nbsp;interuppt</span>"Less optimal cause of Latency, but not resource intensive
"<span style=""color: rgb(255, 255, 255);"">Peak&nbsp;theoretical&nbsp;b/w</span>"achieved only under ideal conditions:<br>- no heat<br>- no obstruction<br>- no virtual memories<br>- no interrupts
"<span style=""color: rgb(255, 255, 255);"">Sustained&nbsp;memory&nbsp;bandwidth</span>"Average bandwidth achieved across extraneous / all confounding variables when the CPU runs.&nbsp;
"<span style=""color: rgb(255, 255, 255);"">Excessive&nbsp;swapping?</span>"Fragmentation
"<span style=""color: rgb(255, 255, 255);"">Excessive&nbsp;paging?</span>"thrashing
"<span style=""color: rgb(255, 255, 255);"">Memory&nbsp;segmentation</span>"<div>occurs in place of paging, when there isn’t a preset block. Storage is dynamic but excessive swapping can lead to fragmentation. Also leads to cons such as:&nbsp;</div><div><ul><li><div>Physical wear and tear</div></li><li><div>Less predictability</div></li><li><div>Non-contiguous</div></li></ul></div>
"<span style=""color: rgb(255, 255, 255);"">Paging&nbsp;[in&nbsp;virtual&nbsp;memory]</span>"<div>The transfer of data between primary and secondary memory, done in specific amounts at a time (pages, ex:- 20mB).&nbsp;</div>
"<span style=""color: rgb(255, 255, 255);"">Cache</span>"Holds the information from the RAM that is most actively used and accessed most frequently. Most relevant types of cache rn are L1 and L2.&nbsp;<br><br>L1 is placed on the CPU and L2 is placed between the 1⁰&nbsp;and 2⁰
"<span style=""color: rgb(255, 255, 255);"">Compaction</span>"&nbsp;a process where the memory manager rearranges the memory space to create larger blocks of contiguous memory. Excessive compaction can lead to checkerboaring
"<span style=""color: rgb(255, 255, 255);"">Where&nbsp;is&nbsp;the&nbsp;MAC&nbsp;address&nbsp;found?</span>"The 12-digit hexadecimal code is found on a network interface card.&nbsp;
"<span style=""color: rgb(255, 255, 255);"">Purpose&nbsp;of&nbsp;MAC&nbsp;address&nbsp;and&nbsp;NIC</span>"NIC is responsible for the client connection to the WAN&nbsp;
"<span style=""color: rgb(255, 255, 255);"">D-RAM</span>"Dynamic RAM:<br><ul><li><div>Cheaper</div></li><li><div>Requires constant refreshing to keep data useable</div></li><li><div>Data leaks</div></li><li><div>Memory capacity &gt;&gt;</div></li><li><div>HL [DDR, data is transferred at the rise and fall of the clock]</div></li></ul>
"<span style=""color: rgb(255, 255, 255);"">S-RAM</span>"Static RAM:<br><ul><li><div>Does not leak</div></li><li><div>Super fast</div></li><li><div>Very expensive (Needs more transistors per byte)</div></li><li><div>Used usually for cache [which stores more frequently used applications]</div></li><ul><li><div>L1 &lt;- inside CPU</div></li><li><div>L2 &lt;- between CPU and primary memory</div></li></ul></ul>
"<span style=""color: rgb(255, 255, 255);"">Define&nbsp;CPU</span>"<div>The part of the computer that performs instructions based on input and output</div>
"<span style=""color: rgb(255, 255, 255);"">Parts&nbsp;of&nbsp;the&nbsp;CPU</span>"ACC<br>ALU<br>CU<br>CIR<br>MDR<br>MDB<br>MAR<br>MAB<br>RAM<br>
"<span style=""color: rgb(255, 255, 255);"">Differences&nbsp;between&nbsp;ROM&nbsp;and&nbsp;RAM</span>"ROM cannot be written to, RAM can<br>ROM holds the Basic [Input/Output] System, RAM holds the programs running and data used<br>ROM is much smaller than RAM<br>ROM is non-volatile, RAM is volatile
"<span style=""color: rgb(255, 255, 255);"">ALU</span>"<div>&nbsp;Arithmetic Logic Unit, used for handling arithmetic operations and basic input/output logic operations&nbsp;</div>
"<span style=""color: rgb(255, 255, 255);"">CU</span>"<div>Control Unit, it’s what retrieves the instructions from the 1⁰ and handles its execution&nbsp;</div>
"<span style=""color: rgb(255, 255, 255);"">Fetch&nbsp;</span>""<li>Program Counter (PC) sends address of the next instruction to Memory Address Register</li>
<li>Memory Address Bus (MAB) sends this address to the RAM</li>
<li>The memory unit uses the address to locate the instruction in RAM.</li><div></div><div></div>
<li>The instruction is fetched from RAM and placed on the Memory Data Bus (MDB).</li>
<li>The MDR captures the fetched instruction.</li>"
"<span style=""color: rgb(255, 255, 255);"">Decode</span>"The Instruction goes from the MDR to the CIR&nbsp;<br>CU decodes the instruction, sees whether or not it can pass&nbsp;<br>If it's passable, CU sends a decoded version to the ALU
"<span style=""color: rgb(255, 255, 255);"">Execute</span>"ALU performs arithmetic or logical operation as instructed<br>The latest result is stored in the accumulator
"<span style=""color: rgb(255, 255, 255);"">CIR</span>"Current Instruction Register: Stores the instruction currently being decoded.
"<span style=""color: rgb(255, 255, 255);"">MDR</span>"Memory Data Register: Holds the data fetched fom during the cycle
"<span style=""color: rgb(255, 255, 255);"">MAR</span>"Memory Address Register: Stores the memory address from which data will be fetched
Broad Types of Secondary Storage?Direct access [HDD/SSID] and Sequential access
What is Direct Access 2⁰?Data can be retrieved with indexed values
What is sequential access [secondary memory]Data can only be retrieved by reading all data that was sequentially stored up until that point&nbsp;