Microelectronic Engineering 149 (2016) 145–152
Contents lists available at ScienceDirect
Microelectronic Engineering
journal homepage: www.elsevier.com/locate/mee
Accelerated publication
Measurement-based electrical characterization of through silicon vias
and transmission lines for 3D integration
Xin Sun a, Runiu Fang a, Yunhui Zhu a, Xiao Zhong a, Yuan Bian a, Yong Guan a, Min Miao b,
Jing Chen a, Yufeng Jin c,a,⁎
a
b
c
National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Institute of Microelectronics, Peking University, Beijing 100871, China
Information Microsystem Institute, Beijing Information Science and Technology University, Beijing 100101, China
Peking University Shenzhen Graduate School, Shenzhen 518055, China
a r t i c l e
i n f o
Article history:
Received 2 February 2015
Received in revised form 3 September 2015
Accepted 19 October 2015
Available online 20 October 2015
Keywords:
3D integration
Through silicon via (TSV)
Transmission line
Electrical measurement
RF characterization
a b s t r a c t
Measurement-based electrical characterization of through silicon via (TSV) and redistribution layer (RDL) is of
great importance for both fabrication process and system design of 3D integration. This paper presents the electrical measurements and analysis of TSV and double-sided RDL test structures, from DC to high frequency up to
40 GHz. TSV shows great dependence of DC resistance and leakage current on fabrication process. An inverse
V-shaped C–V curve is presented between adjacent TSVs in N-type silicon substrate, from − 10 V to 10 V. In
the high frequency characterization, two methods are proposed and applied to extract resistance and inductance
of a single grounded TSV. Individual transmission loss of TSV, RDLs on top and bottom surface of silicon substrate
are calculated, and corresponding circuit parameters thereof are extracted to characterize their electrical properties precisely.
© 2015 Elsevier B.V. All rights reserved.
1. Introduction
With increasing demands for smaller, multi-functional electronic
devices, 3D integration with through silicon via (TSV) has attracted
substantial attention and has been already on the way to commercialization. It provides vertical interconnects with high integrated density,
greatly reduced interconnect length, low power consumption, heterogeneous integration, high system speed and small form factor [1–4].
Many 3D integration architectures have been proposed to address
different applications, including MEMS, CMOS image sensor (CIS),
stacked memories, and so on. Nevertheless with these sophisticated
3D integration technique, TSV and redistribution layer (RDL) remain
the key components for signal transmission. According to the functionality requirements, a wide range of different signals (digital, analog, RF
etc) exist in the electrical system. It is mandatory to thoroughly investigate the electrical behavior of TSV and redistribution layers, both at DC
and RF/microwave frequencies.
So far, electrical modeling and simulation of TSV have been done
in lots of previous works. Several equivalent circuit models have been
proposed for TSV, and analytical expressions of its RLCG parameters
were derived. Kim et.al [5] proposed an equivalent circuit model for
TSVs arranged in a ground-signal configuration. The values of RLCG
⁎ Corresponding author at: Peking University Shenzhen Graduate School, Shenzhen
518055, China.
E-mail address: yfjin@pku.edu.cn (Y. Jin).
http://dx.doi.org/10.1016/j.mee.2015.10.010
0167-9317/© 2015 Elsevier B.V. All rights reserved.
parameters were tied to the geometrical and physical parameters of
TSV based on two-conductor transmission line theory. Salah et al. [6]
used a π-type equivalent circuit model for a single TSV inside grounded
silicon substrate, and the dimensional analysis method was used to
derive the expressions of RLCG parameters. Liu et al. [7] applied
magneto-quasi-static theory and developed a rigorous resistanceinductance model of TSV, considering the skin effect and proximity
effect of TSV at high frequency. Impact of physical parameters of TSV
on its transmission performance were also widely studied, such as TSV
height, diameter, pitch, liner thickness, cross-section shape, substrate
resistivity, etc. [8–11]. Fundamental design rules can be drawn based
on these parametric analyses. DC resistance, leakage current and C–V
measurement of TSV have been widely used for process evaluation in
previous works [12–15]. Gu et al. [16] evaluated the loss and crosstalk
properties of RDL transmission lines on silicon substrate. A TSV–RDLbump test vehicle was measured up to 20 GHz in [5], and the measured
S parameters agreed well with the ones calculated from the equivalent
circuit model. Ndip et al. [17] extracted the inductance and capacitance
of GSG–TSV from single-port open and short TSV test vehicles, in the
100 MHz to 40 GHz frequency range. Dual-port TSV chain structures
were measured in [18], and RLCG parameters of TSV were extracted
based on empirical formulas and 3D full wave electromagnetic simulations. Four-port test vehicle with two grounded TSVs were applied in
[19]. Coupling capacitance and conductance were extracted. In the
above-mentioned studies, some only dealt with experimental results
without sufficient analysis. As measurement analysis is of great concern
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X. Sun et al. / Microelectronic Engineering 149 (2016) 145–152
dependent properties of TSV's resistance and inductance. Accuracy
is improved with a new de-embedding method. Another test vehicle
with GSG–TSV and RDL transmission lines is measured to show the
signal integrity of the interconnect path for 3D integration. The contributions of TSV, RDL transmission line, and test pad to the total transmission loss of the test vehicle are calculated respectively, and RLCG
parameters of TSV and RDL transmission line are extracted and analyzed for design recommendations.
2. TSV–RDL structure description
Fig. 1. SEM cross section of the fabricated structures with TSV and metal lines on both sides
of the silicon substrate.
to both fabrication process and system design, there is still room for
improvements in the studies of measurement-based characterization
of TSV and RDL.
In this paper, electrical measurement and analysis of TSV and RDL
structures are carried out, from DC to high frequency up to 40 GHz.
Test structures are designed and fabricated based on an in-house fabrication process [20–21]. DC resistance, leakage current, and C–V curves
are measured to evaluate the basic properties of TSV and RDLs. A test
vehicle with a grounded TSV is applied to study the frequency-
Several test structures are fabricated to analyze the electrical
properties of TSV and RDLs, which consist of TSVs and RDLs on both
top and bottom surface of silicon substrate. Fig. 1 is the scanning electron microscope (SEM) image of the fabricated TSV and double-sided
RDL structures. TSVs are etched with DRIE (deep reactive ion etching)
equipment and filled with electroplated copper. The fabricated TSVs
show a tapered cross-section, with 17.6 μm in diameter and approximately 99 μm in depth. TSVs are isolated with SiO2 from Si substrate.
The SiO2 liner is no thicker than 0.5 μm due to the difficulty of high
aspect ratio deposition. As shown in Fig. 1, copper RDLs on the top
and bottom surface of the silicon substrate are electroplated with a
thickness of 6.8 μm and 5.8 μm respectively. RDLs on the top side
are lined with a 9.2 μm thick BCB (benzocyclobutene) layer from Si
substrate, and bottom RDLs are deposited on a SiO2 layer, which is
less than 2 μm thick. N-type silicon substrate is thinned to 87.6 μm,
of which the average bulk resistivity is 3.1 Ω cm by four-point probe
measurement.
Fig. 2. Four-point Kelvin structure for TSV resistance measurement, (a) 3D model, (b) SEM image in top view, (c) distribution of measured single TSV resistance, the inset shows resistance
distribution below 200 mΩ.
X. Sun et al. / Microelectronic Engineering 149 (2016) 145–152
Fig. 3. Resistance of daisy chains with different TSV number.
3. DC analysis of TSV and RDL
In this section, resistance, leakage current and C–V curves are measured to emphasize the DC/low frequency properties of TSV and RDL.
Several 3 μm-thick, 500 μm-long BCB lined metal lines are used for
resistance measurement of RDLs, which are fabricated on the top surface of silicon substrate, with line width of 10 μm, 20 μm and 30 μm
respectively. The calculated sheet resistance is 8.87 mΩ/□, and the calculated conductivity of copper is about 3.6 × 107 S/m, lower than the
theoretical value of 5.8 × 107 S/m. Lithography resolution, BCB shrinkage, surface roughness of metal lines may all contribute to the fluctuations of RDL resistance.
DC resistance of a single TSV is evaluated with four-point Kelvin
structures, as show in Fig. 2(a). Electric current flows through test
pads marked as I + and I −, and voltage between test pads V + and
V − is recorded, so that the accurate resistance of the centered TSV
is measured. Fig. 2(b) shows the surface SEM image of the Kelvin
test structure. Cumulative distribution of single TSV resistance in
Fig. 2(c) shows that, TSV resistance gets a relatively wide distribution, ranging from 4.3 mΩ to 7 Ω, with over 75% lying between
4.3 mΩ to 200 mΩ, as in the inset curve. Contact resistance between
TSV and RDL may be the major cause of wide spreading of resistance.
Besides, straight-line daisy chain with maximum 42 TSVs, and two
serpentine daisy chains with 54 and 108 TSVs are also measured,
which consist of TSVs, RDLs on top and bottom surface of Si substrate.
147
The pitch between adjacent TSVs in line or in array is 50 μm. Fig. 3
shows the resistance of daisy chains as a function of TSV number,
which shows fine connectivity between TSV and RDLs. The calculated
slope of curve segment in Fig. 3 indicates that, the resistance of TSV
and surface RDLs in series is 14 mΩ for straight-line daisy chain, and
33 mΩ for serpentine ones. Dense TSV distribution leads to higher
resistance.
Interdigital comb structure of top metal lines is designed and fabricated for leakage current test, measured with voltage varying from 0 V
to 50 V. Each electrode has seven 700 μm-long RDL lines in parallel.
The width and space of top RDL lines are 20 μm/30 μm. Leakage current
between top RDLs is less than 3 pA up to 50 V, indicating great insulation
of metal lines.
Open-ended TSV pair is fabricated for leakage current measurement,
as graphed in Fig. 4(a). Two adjacent TSVs are of 30 μm in pitch with
each connected by test pad. It is observed from Fig. 4(b) that the leakage
current between TSVs is tens of nA below 2 V, and reaches 150 nA up to
30 V. Leakage current between the top metal pad pair stays below 1 pA
up to 30 V. Top metal lines shows pretty good insulation properties,
while TSV dominates the leakage current performance. As mentioned
above, the sidewall SiO2 liner of TSV is no thicker than 0.5 μm, causing
a large leakage current as voltage increases. Isolation of sidewall liner
is still of great importance for the electrical reliability of TSV.
To investigate the MOS capacitance effect of TSV, TSV pairs similar to
Fig. 4(a) but with pitch of 40 μm/50 μm between TSVs are fabricated and
measured from −10 V to 10 V at 5 MHz. A sharp inverse V-shaped C–V
curve is formed, as shown in Fig. 5. The peak capacitance value is around
0 V, which is ten times larger than that near ±10 V. The capacitance between metal pads is very small and is neglected here. As TSVs are buried
in a low-resistivity N-type silicon substrate with thin SiO2 liner around,
this coupling structure with two adjacent TSVs is similar to a twoterminal partially-depleted SOI MOS capacitor, a Metal-InsulatorSemiconductor-Insulator-Metal (MISIM) structure. As the applied voltage varies, the semiconductor surface around one of these two TSVs
changes from inversion mode to accumulation mode, and the other
operates reversely [22].
4. High frequency analysis of TSV and RDL transmission lines
Regarding high frequency and high speed applications of 3D integration, high frequency measurement and analysis of TSV and RDL are also
necessary. In this section, scattering parameters of RDL and TSV–RDL
chain structures are measured with microwave probe station and vector
network analyzer up to 40 GHz. High frequency transmission performances of TSV and double-sided RDLs are investigated, and their electrical parameters are also extracted and analyzed.
Fig. 4. Leakage current test of TSV pair, (a) SEM image of TSV pair for leakage current test in top view, (b) current–voltage curves of TSV pair up to 30 V, compared with that of pad pair
without TSV.
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Fig. 5. Capacitance-voltage curves of TSV pair with pitches of 40 μm and 50 μm.
4.1. Resistance and inductance extraction of single TSV
The dual-port GSG (Ground-Signal-Ground) structure in Fig. 6 is fabricated to extract the resistance (noted as RTSV) and inductance (noted
as LTSV) of a single TSV. The peripheral 36 TSVs connect the backside
ground plane and the ground ring on the top surface, while the centered
TSV connects the backside ground plane and a topside metal line in the
middle. Unlike DC measurement, high frequency characterization can
capture the frequency-dependent properties of TSV. Two equivalent
models are applied for this dual-port test structure, T-model based on
Z parameter, and cascaded model in terms of ABCD matrix, shown in
Fig. 7(a) and (b) respectively.
For the T-model in Fig. 7(a), RTSV and LTSV can be extracted from
the real and imaginary part of Z3 component respectively [23]. In this
T-model extraction method, the dual-port structure in Fig. 6 is considered as a lumped circuit, which neglects distributed parasitic
parameters of metal lines connecting TSV. To improve the accuracy
of RTSV/LTSV extraction, the cascaded model in Fig. 7(b) is proposed
here. An additional “THRU” structure similar to Fig. 6 but without
the centered TSV is used to de-embed the parasitic parameters of
metal lines. As shown in Fig. 7(b), both metal lines noted as ‘TL’
and the centered TSV are represented by distributed ABCD parameters.
The ABCD matrix of TSV can be solved with the “THRU” which consists
of only two TL metal lines. Using the cascaded model, the shunt admittance of TSV only includes RTSV and LTSV in series, in terms of ABCD
matrix [24].
The extracted resistance and inductance of the centered TSV are
illustrated in Fig. 8(a) and (b). It is shown that, the resistance (RTSV)
and inductance (LTSV) extracted from the T-model with Z parameters
Fig. 7. Equivalent models for resistance and inductance extraction of single TSV in Fig. 6,
(a) T-shaped model with Z parameter, (b) cascaded model with ABCD parameter.
are higher than that from the cascaded model, especially as the frequency increases. Both RTSV and LTSV are frequency-dependent due
to skin effect [17]. Based on the cascaded model extraction method,
RTSV is about 1 Ω, and LTSV 46 pH at 40 GHz. Comparison with simulation results are also illustrated in these two figures. The extracted
RTSV is higher than the simulated one, because RTSV has a strong variation with electrodeposition quality of TSV, tapered shape of TSV, contact
resistance between TSV and RDL, and so on. As LTSV is correlated with
fewer variables, only the shape and size of TSV, it matches better with
the simulation results.
4.2. High frequency characterization of TSV–RDL path
Critical signal path used in 3D integration may consist of RDLs on the
top and bottom surface of silicon substrate, and TSV. It is of great significance to evaluate the performance of a typical TSV–RDL signal path, and
to find out the dominant part of the transmission loss.
Aiming at this issue, test structures shown in Fig. 9 are fabricated and
measured, including two transmission line structures noted as TL1, TL2,
and two TSV–RDL chain structures noted as DUT1 and DUT2. Dimensions of these test structures are listed in Fig. 9(b). TL1 and TL2 consists
of CPW-type top RDL lines with two test pads on the ends, and the CPW
line of TL2 is two times as long as the one of TL1. DUT1 and DUT2 has the
similar configuration including test pads, top RDLs, GSG–TSV sets
(50 μm TSV–TSV pitch) and bottom RDLs. The backside RDLs of DUT2
are also two times as long as the ones of DUT1.
Fig. 6. Dual-port TSV structure for extraction of TSV resistance and inductance, (a) 3D model, (b) SEM image in top view.
X. Sun et al. / Microelectronic Engineering 149 (2016) 145–152
149
Fig. 8. Extracted resistance and inductance of single TSV with test structures in Fig. 6, dark line for simulation results, red line for T model extraction method, and blue line for cascaded
model extraction method, (a) resistance, (b) inductance. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
Fig. 9. TSV test structures in ground-signal-ground (GSG) type, TL1 and TL2 denote 200 μm-long and 400 μm-long GSG metal lines on the top side of silicon substrate, DUT1 and DUT2
denote chain structures of TSV and metal lines with 200 μm-long and 400 μm-long backside metal lines, (a) 3D model, (b) SEM image in top view.
All of the four structures are schematically divided into small transmission segments, noted as TL (top RDL line, 200 μm long), BL (Bottom
RDL line, 200 μm long), PAD and TSV (GSG–TSV set), as shown in Fig. 10.
Then those four test structures can be represented by these transmission segments cascading in terms of ABCD matrices, so that the transmission parameters of these segments can be obtained by matrix
operations [25–26].
Fig. 11(a) and (b) shows the measured S11 and S21 parameters of
TSV–RDL test structures in Fig. 9, along with calculated S11 and S21 parameters of test pad, top RDL line (TL), bottom RDL line (TL) and GSG–
TSV set. It is observed that, structure DUT2 in Fig. 9 shows large insertion
loss, up to −7.7 dB at 40 GHz, while the loss of structure TL2 with only
top RDLs is much lower, −2.2 dB at 40 GHz. Curves of PAD covers the
slight loss caused by probe contact, discontinuity, impedance mismatch,
and so on. Top transmission line (TL) benefits from the 9 μm thick BCB
liner, with S21 magnitude of just − 0.54 dB at 40 GHz. As for bottom
transmission line (BL), thin SiO2 liner helps to attenuate S21 magnitude
to −0.96 dB at 40 GHz. Comparing with PAD, TL, BL segments, GSG–TSV
shows much larger loss in 0–40 GHz range, −1.89 dB at 40 GHz, and a
steep drop of S21 magnitude below 1.5 GHz.
Generally, it is indicated that TSV dominates the transmission loss of
TSV–RDL signal path. Low-resistivity (3.1 Ω cm) silicon substrate and
very thin sidewall SiO2 liner could be the causes of TSV's large loss. To
validate this conclusion, RLCG parameters (resistance, inductance,
capacitance, and conductance) of TSV are extracted from the calculated
ABCD matrix of GSG–TSV structure. Both π-model and T-model are
applied as the equivalent circuit model of GSG–TSV, as shown in
Fig. 12(a) and (b). Then conversion from ABCD parameters to Y parameters is carried out for π-model, and conversion to Z parameters for
T-model [27]. RLCG parameters of circuit models in Fig. 12, can be
extracted from Y parameters and Z parameters of GSG–TSV, respectively.
Fig. 13(a) and (b) illustrate the extracted RLCG values of GSG–TSV,
of which ‘π’ is short for π-model in Fig. 12(a), and ‘T’ for T-model in
Fig. 12(b). Except for the slight deviation of resistance values, RLCG
parameters derived from π-model and T-model are almost identical.
Because of skin effect, the resistance of TSV increases with frequency,
and inductance decreases with frequency. Comparing with single TSV
structure in Fig. 6, GSG configuration leads to more obvious proximity
effect between signal TSV and grounded TSV, which results in higher
series resistance values. Mutual inductance between signal TSV and
grounded TSV helps to reduce the total inductance of GSG–TSV model.
Fig. 10. Decomposition diagram of the four test structures shown in Fig. 9, each structure
consists of test pad (PAD), 200 μm-long topside metal line (TL), 200 μm-long bottom metal
line (BL), and/or GSG–TSV (TSV) segments. Brackets [] denote the ABCD parameters of
corresponding transmission segment.
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X. Sun et al. / Microelectronic Engineering 149 (2016) 145–152
Fig. 11. S parameter of TSV test structures and transmission segments (test pad, top/bottom metal lines and GSG–TSV set). (a) S11 magnitude, (b) S21 magnitude.
The inductance values of single TSV and GSG–TSV are approximately 46
pH and 27 pH above 5 GHz respectively.
Back to the concerns of low-resistive Si substrate and SiO2 liner, from
Fig. 13(b), it is shown that, extracted capacitance of GSG–TSV excesses
400 fF below 1.5 GHz, causing a sharp increase of transmission loss in
lower frequency range as shown in Fig. 11(b). As frequency increases,
capacitance value tends to steady around 25 fF, while the conductance
of TSV rises to 8–10 mS, which equals a shunt resistor of 100 Ω or so,
and dominates the transmission loss of GSG–TSV in a broad frequency
range above 5 GHz.
Distributed RLCG parameters of top and bottom RDL transmission
lines are also graphed in Fig. 14 (a)–(d), with black lines for top RDL,
and blue lines for bottom RDL [28]. Telegrapher's equation model is
applied and illustrated in these figures. As above-mentioned, both top
RDL and bottom RDL transmission lines are CPW-type. The width of signal line in the middle is 28 μm, and the gap between signal line and GND
line aside is 22 μm. Top RDL lines are about 1 μm thicker than RDL lines
on the backside of Si substrate, as shown in Fig. 1, so that the series
resistances of top RDL are lower than the ones of bottom RDL, and resistance curves in Fig. 14(a) are expected, increasing with frequency.
Fig. 14(b) shows that inductance is relatively constant over frequency,
but presents a rapid drop below 1.5 GHz. The inductance of top RDL
transmission line is higher than that of the bottom RDL, due to the
thicker metal as well.
Benefiting from the 9 μm thick BCB liner, top RDL transmission
line gets shunt capacitance of only 0.12 pF/mm over frequency. As for
the bottom RDL transmission line with thin SiO2 liner, the capacitance
is much larger at low frequency, and decreases as frequency rises, as
shown in Fig. 14(c). In Fig. 14(d), it can be seen that, top RDL transmission line exhibits a slow increase of conductance over frequency, while
the conductance of bottom RDL transmission line increase rapidly
below 20 GHz, and goes flat beyond 20 GHz.
With these analyses, it is shown that thicker insulation liner for TSV
and RDL helps decrease the frequency dependent loss, and a highresistivity silicon substrate is recommended for better high frequency
performance.
MOS capacitance effect of TSV, the measured capacitance between
two adjacent TSVs shows a sharp inverse V-shaped curve under bias
voltage from −10 V to 10 V. Peak capacitance value is around 0 V, and
is ten times larger than that near ± 10 V. Mechanism of this MISIM
structure will be further studied in the future. As for the high frequency
characterization up to 40 GHz, two methods are presented to extract
resistance and inductance of a single grounded TSV. A “THRU” structure
is used to improve the accuracy of this extraction. Four ground-signalground (GSG) type TSV–RDL chain structures are measured, and calculations are operated to make clear the contributions of GSG–TSV, pad,
RDL transmission lines to the transmission loss of those TSV-RDL test
structures. It is found that TSV dominates the transmission loss of
three-dimensional TSV–RDL signal path. RLCG parameters of both
GSG–TSV and RDLs are extracted and analyzed. Thicker insulation
layer for TSV and RDLs, and high-resistivity silicon substrate are recommended for better high frequency performance of TSV-RDL signal path.
Acknowledgments
The work presented is funded by Major State Basic Research
Development Program of China (Project No. 2015CB0572), the Importation and Development of High-Caliber Talents Project of Beijing
Municipal Institutions (Great Wall Scholar, No. CIT&TCD20150320),
5. Conclusions
In this paper, electrical measurement of TSV and RDL test structures
are carried out and analyzed, from DC to high frequency up to 40 GHz.
The measured sheet resistance of 3 μm-thick RDLs on the silicon substrate is 8.87 mΩ/□, and great insulation is observed between metal
lines with less than 3 pA leakage current up to 50 V. The measured DC
resistance of a single TSV shows a wide distribution, ranging from
4.3 mΩ to 7 Ω, requiring process optimization of TSV in the future.
Resistance measurement results of daisy chains show good electrical
connectivity between TSVs and RDLs. Leakage current between two
adjacent TSVs reaches 150 nA up to 30 V without breakdown. Due to
Fig. 12. Equivalent Circuit model for GSG–TSV set, (a) π-model, (b) T-model.
X. Sun et al. / Microelectronic Engineering 149 (2016) 145–152
151
Fig. 13. Extracted electrical parameters of GSG–TSV with circuit models in Fig. 12, (a) resistance and inductance, (b) capacitance and conductance.
Fig. 14. Extracted electrical parameters per millimeter of metal lines on top and bottom sides of silicon substrate, (a) resistance, (b) inductance, (c) capacitance, (d) conductance.
National Science and Technology Major Project of China (Project
No. 2009ZX02038), and National Natural Science Foundation of China
(Project No.61176102). The authors would also like to thank Huawei
Technologies for supporting this research.
References
[1] J.U. Knickerbocker, P.S. Andry, E. Colgan, B. Dang, T. Dickson, X. Gu, C. Haymes, C.
Jahnes, Y. Liu, J. Maria, R.J. Polastre, C.K. Tsang, L. Turlapati, B.C. Webb, L. Wiggins,
S.L. Wright, 2.5D and 3D technology challenges and test vehicle demonstrations,
Proceeding of IEEE conference on Electronic Components and Technology Conference (ECTC) 2012, pp. 1068–1076.
[2] H. John, Lau, evolution, challenge, and outlook of TSV, 3D IC integration and 3d
silicon integration, Proceeding of International Symposium on Advanced Packaging
Materials (APM) 2011, pp. 462–488.
[3] P. Garrou, C. Bower, P. Ramm, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Wiley-VCH, New York, 2008.
[4] S. Pozder, R. Chatterjee, A. Jain, Z. Huang, R.E. Jones, E. Acosta, Progress of 3D integration technologies and 3D interconnects, IEEE International Interconnect Technology
Conference 2007, pp. 213–215.
[5] J. Kim, J.S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M.S.
Suh, K.Y. Byun, J. Kim, High-frequency scalable electrical model and analysis of
a through silicon via (TSV), IEEE Trans. Compon. Packag. Manuf. Technol. 1 (2)
(2011) 181–195.
[6] K. Salah, A. El Rouby, H. Ragai, K. Amin, Y. Ismail, Compact lumped element model
for TSV in 3D-ICs, Proceeding of IEEE International Symposium on Circuits and Systems (ISCAS) 2011, pp. 2321–2324.
[7] E.X. Liu, E.P. Li, W.B. Ewe, H.M. Lee, T.G. Lim, S. Gao, Compact wideband equivalentcircuit model for electrical modeling of through-silicon via, IEEE Trans. Microwave
Theory Tech. 59 (6) (2011) 1454–1460.
[8] S.P. Jun, R. Chunghyun, K. Joungho, Electrical characterization of trough silicon via
(TSV) depending on structural and material parameters based on 3D full wave
simulation, Proceeding of International Conference on Electronic Materials and
Packaging(EMAP) 2007, pp. 1–6.
[9] I. Savidis, S.M. Alam, A. Jain, S. Pozder, R.E. Jones, R. Chatterjee, Electrical modeling
and characterization of through-silicon vias (TSVs) for 3-D integrated circuits,
Microelectron. J. 41 (1) (2010) 9–16.
152
X. Sun et al. / Microelectronic Engineering 149 (2016) 145–152
[10] Y. Liang, L. Ye, Closed-form expressions for the resistance and the inductance of
different profiles of through-silicon vias, IEEE Electron Device Lett. 32 (3) (2011)
393–395.
[11] A.E. Engin, S.R. Narasimhan, Modeling of crosstalk in through silicon vias, IEEE Trans.
Electromagn. Compat. 55 (1) (2013) 149–158.
[12] P.S. Andry, C. Tsang, E. Sprogis, C. Patel, S.L. Wright, B.C. Webb, L.P. Buchwalter, D.
Manzer, R. Horton, R. Polastre, J. Knickerbocker, A CMOS-compatible process for
fabricating electrical through-vias in silicon, Proceeding of IEEE conference on
Electronic Components and Technology Conference (ECTC) 2006, pp. 831–837.
[13] J.-C. Souriau, L. Castagne, J.-L. Liotard, K. Inal, J. Mazuir, F. Le Texier, G. Fresquet, M.
Varvara, N. Launay, B. Dubois, T. Malia, 3D multi-stacking of thin dies based on
TSV and micro-inserts interconnections, Proceeding of IEEE conference on Electronic Components and Technology Conference (ECTC) 2012, pp. 1047–1053.
[14] G. Katti, A. Mercha, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Stucchi, M.
Rakowski, I. Debusschere, P. Soussan, W. Dehaene, K. De Meyer, Y. Travaly, E.
Beyne, S. Biesemans, B. Swinnen, 3D Stacked ICs Using Cu TSVs and Die to
Wafer Hybrid Collective Bonding, International Electron Devices Meeting
(IEDM), 2009.
[15] S. Sage, P. John, S. Dobritz, J. Bornge, J. Vitiello, M. Bottcher, Investigation
of different methods for isolation in through silicon via for 3D integration,
Microelectron. Eng. 107 (2013) 61–64.
[16] G. Xiaoxiong, L. Turlapati, B. Dang, C.K. Tsang, P.S. Andry, T.O. Dickson, M.P. Beakes,
J.U. Knickerbocker, D.J. Friedman, High-density silicon carrier transmission line
design for chip-to-chip interconnects, Proceeding of IEEE Conference on Electrical
Performance of Electronic Packaging and Systems (EPEPS) 2011, pp. 27–30.
[17] I. Ndip, K. Zoschke, K. Lobbicke, M.J. Wolf, S. Guttowski, H. Reichl, K.D. Lang, H.
Henke, Analytical, numerical-, and measurement-based methods for extracting
the electrical parameters of through silicon vias (TSVs), IEEE Trans. Compon. Packag.
Manuf. Technol. 4 (3) (2014) 504–515.
[18] L. Cadix, C. Bermond, C. Fuchs, A. Farcy, P. Leduc, L. Dicioccio, M. Assous, M.
Rousseau, F. Lorut, L.L. CHapelon, B. Flechet, N. Sillon, P. Ancey, RF characterization
[19]
[20]
[21]
[22]
[23]
[24]
[25]
[26]
[27]
[28]
and modelling of high density through silicon vias for 3D chip stacking, Microelectron.
Eng. 87 (2010) 491–495.
E. Eid, T. Lacrevaz, C. Bermond, S. Capraro, J. Roullard, B. Flechet, L. Cadix, A. Farcy, P.
Ancey, F. Calmon, O. Valorge, P. Leduc, Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking, in, Microelectron. Eng. 88
(2011) 729–733.
Y. Zhu, S. Ma, X. Sun, R. Fang, X. Zhong, Y. Bian, M. Chen, J. Chen, M. Miao, W. Lu, Y.
Jin, Development and characterization of a through-multilayer TSV integrated SRAM
module, Proceeding of IEEE conference on Electronic Components and Technology
Conference (ECTC) 2013, pp. 885–890.
Y. Zhu, S. Ma, X. Sun, J. Chen, M. Miao, Y. Jin, Numerical modeling and experimental verification of through silicon via (TSV) filling in presence of additives,
Microelectron. Eng. 117 (2014) 8–12.
C. Cheng-Hao, K. Li-Min, Y.-C. Hu, H. Wen-Chun, K. Cheng-Ta, C. Kuan-Neng, Sealing
bump with bottom-up Cu TSV plating fabrication in 3-D integration scheme, IEEE
Electron Device Lett. 34 (5) (2013) 671–673.
J.H. Wu, J. Scholvin, J.A. Del Alamo, A through-wafer interconnect in silicon for RFICs,
IEEE Trans. Electron Devices 51 (11) (2004) 1765–1771.
K.C. Gupta, R. Garg, R. Chadha, Computer-Aided Design of Microwave Circuits,
Artech House, Dedham, 1981.
B. Qing-Hong, N. Li, K. Bunsen, H. Asada, K. Matsushita, K. Okada, A. Matsuzawa,
Evaluation of a multi-line de-embedding technique for millimeter-wave CMOS
circuit design, Proceeding of Asia-Pacific Microwave Conference (APMC) 2010,
pp. 1901–1904.
C. Hsiu-Ying, H. Jiun-Kai, K. Chin-Wei, S. Liu, W. Chung-Yu, A novel transmission-line
deembedding technique for RF device characterization, IEEE Trans. Electron Devices
56 (12) (2009) 3160–3167.
N. Kinayman, M.I. Aksun, Modern Microwave Circuits, Artech House, Norwood,
2005.
W.R. Eisenstadt, Y. Eo, S-parameter-based IC interconnect transmission line characterization, IEEE Trans. Compon. Hybrids Manuf. Technol. 15 (4) (1992) 483–490.