UNIT 6
Combination Logic Circuit
6.1 Introduction:
A combinational circuit consists of input variables, logic gates, and output variables. The logic gates
accept signals from the inputs and generates to the output. Both input and output data are represented by
binary signals i.e. They exist in two possible values logic-1 and logic-0.
Each input variable to a combinational circuit may have one or two wires. One wire available
may represent either in normal form (unprimed) or in complement form (prime) with inverter for each
literal not available input wire. On the other hand, input variable may appear in two wires with both
normal and complement form to input of the circuit.
The design of combinational logic circuits starts from verbal outline of the problem and ends in a
logic circuit diagram, or a set of Boolean functions. The procedure involves following steps:
1. The problem is stated.
2. The number of available input variables and required output variable is determined.
3. The input and output variables are assigned symbols.
4. The truth table defines the required relationship between input and output.
5. The simplified Boolean function for each output is obtained.
6. The logic diagram is drawn.
6.2 Karnaugh Map or K-Map
The complexity of digital logic gates that implement a Boolean function is directly related to algebraic
expression, represented in truth table in different forms. Map method provides a simple, straight forward
procedure for minimizing Boolean functions with either a pictorial form of truth table or an extension of
Venn diagram. This method was first proposed by Veitch(1) and slightly modified by Karnaugh(2), also
known as “Veitch diagram” or the “Karnaugh Map”.
 The k-map is a diagram made up of grid of squares.
 Each square represents one minterm.
 The minterms are ordered according to Gray code (only one variable changes between adjacent
squares).
 Squares on edges are considered adjacent to squares on opposite edges.
 Karnaugh maps become awkward to use with more than 4 variables.
By recognizing various patterns, the user can derive alternative algebraic expression for same functions,
selecting the simplest one with minimum number of literals.
Two variable maps
For n-variable k-map 2n cells are required. Therefore for two variables k-map; 22=4 squares, one for each
minterm, as shown in Figure will be required. There are four minterms for a Boolean function with two
variables.
AB 0
1
A B B’
B
00
01
A’B’ A’B
A’
10
11
AB’
AB
A
Fig: Two-variable map
Three variable map
To construct 3-variable k-map 23=8 cells are required. Therefore, a three-variable map consists of eight
squares, as shown in Figure. There are eight minterms for three binary variables.
A BC 00
01
11
10
AB C 0
1
00
000
001
011
010
000
001
100
101
111
110
010
011
110
111
100
101
Fig: Three-variable k-map
Four variable K-Map
To construct 4-variable k-map 24=16 cells are required. Therefore, a four-variable map consists of sixteen
squares, as shown in Figure. There are sixteen minterms for four binary variables.
AB CD 00
01
11
10
00
0000 0001 0011 0010
01
11
10
0100
0101
0111
0110
1100
1101
1111
1110
1000
1001
1011
1010
Example: Plot the Boolean Expression:
Y=A’BC’D’+AB’CD’+A’BCD’+ABC’D
Y= 0100 + 1010 + 0110 + 1101
m4
m10
m6
m13
Y=∑m (4,6,10,13)
AB CD 00
01
11
10
0000
0001
0011
0010
00
01
0100
0101
0111
0110
11
1100
1101
1111
1110
10
1000
1001
1011
1010
Other way to fill.
AB CD C’D’ C’D
1
CD
CD’
1
1
1
6.2.2 Pairs, Quads, and Octets
We can group 1’s on Karnaugh map by following rules, enclosing adjacent cells containing 1’s. The goal is
to maximize the size of groups and minimize number of groups. Adjacent cells which have 1’s can be
grouped together in 2’s power i.e.
21- 2 adjacent cells can be grouped (pair)
22- 4 adjacent cells can be grouped (quad)
23- 8 adjacent cells can be grouped (octets)
Rules to be followed or K-map simplification
1. Groups do not include any cells containing a zero.
2. Groups may be horizontal or vertical, but not diagonal.
3. Groups must contain 1,2,4,8, or 2n cells.
4. Each group should be large as possible (i.e. gives minimal literals, that requires less gates).
Example1: pair grouping.
AB CD CD CD
CD
AB
1
AB
1
1
1
AB
1
1
1
1
1
1
A’B’
=BD
= B’D’
1
Example3: octet grouping.
AB CD C’D’ C’D
CD
AB’C
CD’
1
AB
AB
BCD
Hence final expression is:
F= A’C’D+ BCD+ AB’C
1
Example2: quad grouping.
AB CD C’D’ C’D
CD
AB
=(A’B’+A’B)C’D’
=A’(B’+B).C’D’
=A’C’D
1
AB
AB
CD
Hence final expression is:
F= BD+B’D’
CD’
1
1
1
1
1
1
1
1
1
1
1
1
C
D
Hence final expression is:
F= C+D
6.3 Analysis o SOP and POS
The arbitrary logic unction can be expressed in the following form:
I. Sum of Product (SoP)
II. Product of Sum (PoS)
Product term: the AND function is referred to as a product. The variable in a product term can appear
either in complemented form or in uncomplemeted (normal) form. For example AB’C or ABC is a
product form.
Sum term: The OR unction is generally used to refer as sum. Or e.g; A+B+C’ is a sum term.
Note:
For POS
Normal form - 1
Unnormal form - 0
Terms used- minterm (e.g. a’.b.c)
For SOP
0
1
maxterm (e.g. a’+b+c)
6.3.1 Sum of Products (SoP)
The logical sum of two or more product terms is called a “Sum of Product” expression. It is basically
an OR operation o AND operational variables such as:
F=A’B+B’C+A’BC.
The expression above has three sum of two and three variables. SOP can have the term A’B’C’
but not ABC.
6.3.1.1 AND/OR implementation of a SoP expression
It simply requires ORing the outputs of two or more AND gates. For expression AB+BCD+A, the
output X of the OR gates equals to SAP expression.
A
B
B
C
D
A
C
X=AB+BCD+AC
6.3.1.2 NAND/NAND implementation of a SOP expression
NAND gates can be used to implement SOP expression. By using only NAND gates, an
AND/OR function can be accomplished.
A
B
B
C
D
A
C
X=AB+BCD+AC
Fig: NAND/NAND implementation of AND/OR.
6.3.2 Conversion of general expression to SOP form.
Any logic expression can be changed into SOP form by applying Boolean algebra techniques.
e.g. A(B+CD)=AB+ACD (using distributive law)
The standard SOP form
It is one in which all the variables in domain (Boolean expression with set of variables) appear in each
product term in the expression. It is important in constructing truth tables.
SOP form
Total number combinations = 2n, number of variables (n)
There are two ways to express function in Boolean algebra i.e. SOP form (minterms-m) and POS (max
terms-M) form. SOP form is written when the function is high (1).
Minterms - m0
m1
m2
m3
m4
m5
m6
m7
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
0
0
1
0
1
1
1
1
F(A,B,C) = m2+m4+m5+m6+m7
= ∑m(2,4,5,6,7)
F = ABC+ABC+ABC+ABC+ABC
(standard/canonical form- since it is written directly from
the truth table)
Also, we can use laws of Boolean algebra to find minimal SOP form.
6.3.4 Products of Sum (PoS)
The logical product of two or more sums is called “Product of Sum” expression. It is basically an
AND operation of OR operated variables. Such as F=(A’+B).(B’+C).(A’+B+C)
A POS expression can contain a single variable term as in A(A+B+C)(B+C+D). In POS expression, a
single over bar cannot extend over more than one variable.
6.3.4.1 Implementation of a POS expression
It simply requires ANDing the outputs two or more OR gates. For expression (A+B)(B+C+D)(A+C). The
output X of the AND gate equals to POS expression.
A
B
A
B
C
A
C
X=(A+B)(A+B+C)(A+C)
The standard PoS form
It is one in which all the variables in the domain appears in each sum term in the expression. Any non
standard PoS expression (simply PoS) can be converted to standard form using Boolean algebra. PoS
form is used (written) when the function is low.
Maxterms - M0
M1
M2
M3
M4
M5
M6
M7
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
0
0
1
0
1
1
1
1
F = (A+B+C).(A+B+C).(A+B+C)
(Standard/Canonical POS form with maxterms)
In SOP form: F=A.B.C+A.BC+A.B.C
Complementing both sides, we get.
( F)= (A.B.C+A.B.C+A.B.C)
= (A.B.C)’.(A.B.C)’.(A.B.C)’
F = (A+B+C).(A+B+C).(A+B+C)
In standard POS form, each maxterm will have all the variables in normal or complemented form.
Boolean algebra can be used to reduce standard/canonical PoS form to minimal PoS form.
F=(A+B+C)(A+B+C)(A+B+C)
Assuming A+B as X, we get
F=(X+C.C).(A+B+C)
F=(A+B)(A+B+C)
F=A+B(B+C)
Y=A+B.B+BC
Y =A+BC
Y=(A+B)(A+C) – minimal SoP form
6.3.5 Don’t Care Conditions
In a map, 0’s and 1’s are entered corresponding to input variables that make function equal to 1or 0. The
maps are simplified using either 1’s or 0’s , the cells which do not contain 1 are assumed to contain 0 and
vice-versa. This is not always true since there are cases in which certain combinations of input variables
do not occur. This condition is known as don’t care condition and can be represented as K-map as a X
mark in the corresponding cell.
The X mark in a cell may be assumed to be a 1 or a 0 depending upon which one leads to a
simpler expression. For example, BCD code conversion of 0 to 16 decimal values, there are six invalid
combinations: 1010, 1011, 1100, 1101, 1110, and 1111 never occurs in application, hence can be treated
as “Don’t care” terms with respect to their effect on output. When grouping the 1’s, the X can be treated
as 1’s to make larger grouping.
Inputs
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Output
Y
0
0
0
0
0
0
0
1
1
1
X
X
X
X
X
X
CD 00
AB
00
01
11
10
1
01
11
10
X
X
X
X
1
1
X
X
Without don’care- Y=ABCD+ABC
With don’t care- Y=A+BCD
Don’t care
6.3.6 Simplification of Quine McClusky method
The map method of simplification is convenient till 4 to 5 variables in number, since excessive number of
squares prevents reasonable selection of adjacent squares.
Quine McClusky method overcomes this problem. It is specific step by step procedure that is
guaranteed to produce a simplified standard form expression for a function. It can be applied to problems
with many variables and is suitable for machine computation.
The tabulation method was first formulated by Quine and later improved by McKlusky. It is
formal tabular method for applying Boolean Distributive Law to various terms to find minimum sum of
products by eliminating literals that appear in two terms as complements. The tabular method of
simplification consists of two parts:
a) First is to write function in standard minterm (Sop) form.
X=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD
b) Arrange minterms according to number of 1’s in each minterm.
6.4 Hazards and hazards cover
Simplification technique gives minimal expressions for logic equation. Simplified equations can be
realized using minimum hardware. But to overcome some practical problems, in certain cases we may
prefer to include more terms in the simplified equation. Practical logic circuits do not generate outputs
instantaneously. There is finite propagation delay that gives rise to hazards.
Hazard covers are additional terms in a logic equation that prevents hazards. For combinational
logic circuit hazard may go unnoticed but in sequential logic circuit it may cause major malfunction.
Types of Hazards
Static hazard: it exist if an output signal is suppose to remain at a particular logic value when an input
variable changes it’s value, but instead the signal undergoes momentary changes in it’s value.
Static -1 Hazard
This type of hazard occurs when y= A+A’ type of situation appears for a logic circuit for certain
combination of other inputs and A makes a transition 1 0. An A+A’ condition should always generate
logic 1 at the output, i.e. static-1.
A
A’
Y=A+A’
1
0
1+0=1
0
1
0+1=1
Consider a simple logic circuit as shown:
A
A’
1 0
The not gate takes finite time to become logic 1 following 1 0 transition of the input A. the OR gate
output goes to logic 0 for a small duration which is unwanted.
A
A’
Y=A+A’
1
0
1+0=1
0
0
0+0=0
0
1
0+1=1
The width of this logic 0 output is in nanoseconds and is called a glitch as shown in the figure.
1
A0
1
A
T1
T1=NOT gate delay
0
T2=OR gate delay
Y1
0
T2
Tpd
Static-1 hazard cover
Consider an example Y=AC+BC’. Corresponding logic circuit is as shown:
A
C
Y
B
Consider input A=1, B=1 and C makes a transition 1 0. The output has a glitch and hence the circuit has
static-1 hazard.
Consider the K-map simplification
A BC 00
01
11
10
00
1
1
C+C’
1
B’C
1
Additional term AB
The additional term AB ensures Y=1 for A=1 and B=1and A 1 0 transition at C does not affect the
output. The circuit free from static-1 hazard is as shown below:
A
C
Y
B
Fig: static-1 hazard free circuit.
Static -0 Hazard
This type of hazard occurs when y= A.A’ type of situation appears for a logic circuit for certain
combination of other inputs and A makes a transition 0 1. An A.A’ condition should always generate
logic 0 at the output, i.e. static-0.
A
0
1
A’
1
0
Y=A.A’
0.1=0
1.0=0
Consider a simple logic circuit as shown:
A
Y
A’
The NOT gate takes finite time to become logic 0 following 0 1 transition at the input A. The AND gate
output goes to logic 1 for a small duration which is unwanted.
A
A’
Y=A.A’
0
1
0.1=0
1
1
1.1=1
1
0
1.0=0
The width of this logic 1 output is in nanoseconds and is called a glitch as shown in the figure.
T1
T1- NOT gate delay
T2- AND gate delay
T2
tpd
Static-0 hazard cover
Consider an example Y= (B+C).(A+C’). Corresponding logic circuit is as shown:
A
C
Y
B
Consider input A=0, B=0 and C makes a transition 0 1. The output has a glitch and hence the circuit has
static-0 hazard.
A BC 00
01
11
10
000 0
0
0
1
Y= (B+C) (A+C’) (A+B)
0
1
1
1
1
The additional term A+B ensures Y=0 for A=0, B=0 and C 0 1 transition at C does not affect the output.
The circuit free from static-0 hazard is as shown below:
A
B
C
Fig: static-0 hazard free circuit.
6.5 HDL implementation models
The three common HDLs are Verilog, VHDL, and SystemC. Of these, SystemC is the newest. The
HDLs will allow fast design and better verification. In most of the industries, Verilog and VHDL are
common. Verilog, one of the main Hardware Description Language standardized as IEEE 1364 is used
for designing all types of circuits. It consists of modules and the language allows Behavioral, Dataflow
and Structural Description.
Generally, HDL structure consist a textual description involving many inputs, outputs, signals
operators, components, multiple architectures, and comments. Concurrent and sequential way of
programming style is possible in HDL. Each and every HDL uses a different structure and design method.
The examples shown below using VHDL and Verilog will help to get an overall idea about HDL structure
and design.
VHDL: AND GATE EXAMPLE
 Using Data Flow Modeling: Data Flow Modeling in VHDL shows the flow of the data from input to
output. In the AND gate example, first the library definitions are given. Then the entity
declaration. Entity or the architectural body of the AND gate includes the inputs ‘a’, ‘b’, output ‘c’
and the entity name ‘AND1’.Here the data type of the input and output is bit type which
represents 0 and 1 values. Generally in VHDL data types are classified as scalar, composite,
access, standard logic and file types.The words in color are the generally known as reserved
words in VHDL. After the entity description, the architecture is defined, which involves the design
of the gate. ‘<=’ represents the assignment operator. In this ‘and’ is the logical operator
representing the function. The relational, logical, adding, miscellaneous, sign and multiplying are
generally the operators present in VHDL.

Figure 1: VHDL Data Flow Model of AND Gate
Using Structural Modeling: Structural Modeling in VHDL helps to model any circuit by specifying
the components used in them. The model will clearly define the interconnections also. Here
each component in the circuit is modeled as an entity. In the structural AND gate example, after
defining the library and the entity, the component is defined. After the ‘begin’ statement in the
architecture, the function of the component in the circuit is defined using the inputs, signals and
outputs. This model allows a hierarchical design.

Figure 2: VHDL Structural Model of AND Gate
Using Behavioral Modelling: It uses constructs similar to C language.In this model, we can use
if-else, for loops, while statements and case statements too.
Figure 3: VHDL Behavioral Model of AND Gate
Verilog: OR GATE EXAMPLE
 Using Data Flow Modeling: Instead of using the assignment operator, it uses the continuous
assignment statement with the keyword ‘assign’. Verilog generally defines each circuit using a
module. The module will generally involve the name of the design, its inputs and outputs and
functionality. In the OR Gate example ‘orgate’ is the module name. In Verilog we generally use
wires and registers to define the variables.Here the OR function is represented by using the
operator ‘|’.Generally, Verilog involves arithmetic, logical, relational, equality, bitwise, reduction,
shift, concatenation, replication and conditional operators.


Figure 4: Verilog Data Flow Model of OR gate
Using Structural Modeling: In this model, the component represents another design module.
Figure 5: Verilog Structural Model of OR Gate
Using Behavioral Modeling: In Verilog, this model is exactly similar to C.Here we use always
block were the statements are written.Reg is used to declare the variable.
Figure 6: Verilog Behavioral Model of OR Gate