Computer Architecture
Lecture 3. MIPS Instructions #3
(Chapter 2. Instructions: Language of the Computer)
Prof. Kon-Woo Kwon
Computer Engineering
Hongik University
Data Transfer Instructions
• CPU has a limited number of registers inside
▪ There are many data in your program, much more than
registers inside CPU can accommodate
• Examples: int a, b, c;
int dummy [100];
▪ In MIPS, there are 32 general-purpose registers inside the CPU
▪ So, CPU is able to keep only a small amount of data in registers
on the fly
• Thus, MIPS (and all other CPUs) must provide
instructions that transfer data between memory and
registers
▪ Such instructions are called data transfer instructions
▪ To access data in memory, the data transfer instruction should
supply the memory address
2
Memory Operands
• To apply arithmetic operations
▪ Load values from memory into registers
▪ Store result from register to memory
• Memory is byte addressed
▪ 1 = 1byte (8-bit)
• Words are aligned in memory
▪ Address must be a multiple of 4
• MIPS is Big Endian
▪ Most-significant byte at least address of a word
▪ c.f. Little Endian: least-significant byte at least
address
3
Memory addressing
1byte (8-bit)
001001102 = 0x36
0x1000
0x1001
0x1002
….
4
Word Alignment
1byte (8-bit)
001001102 = 0x36
0x1000
0x1004
0x1008
0x100C
0x1010
• Address must be a multiple of 4 for…
▪ lw (load word) and sw (store word) instructions
5
Endianness
What happens if store this 4-byte value to address 0x1000 ?
1234567816 = 1×
167+ 2×
166 +3×
165…
0x1000
0x1001
0x1002
0x1003
12
34
56
78
Big Endian : MIPS, SPARC
78
56
34
12
Little Endian : x86, RISC-V
6
Endianness
• If you always store / load 4 bytes at a time at 4-byte
aligned addresses, endianness does not matter
• It matters when you read in smaller sizes.
0x1000
12
34
56
78
Big Endian: read 2 bytes at 0x1000 → 0x1234
78
56
34
12
Little Endian: read 2 bytes at 0x1000 → 0x5678
7
Memory Operand Example 1
• C code:
g = h + A[8];
▪ g in $s1, h in $s2, base address of A in $s3
Base address of A: 0x1000
0x1020 = 0x1000 + 4×8
0x1004
A[0]
A[1]
0x1008
A[2]
A[8]
8
Memory Operand Example 1
• C code:
g = h + A[8];
▪ g in $s1, h in $s2, base address of A in $s3
• Compiled MIPS code:
▪ Index 8 requires offset of 32
• 4 bytes per word
offset
base register
lw $t0, 32($s3)
add $s1, $s2, $t0
# load word
9
Memory Operand Example 2
• C code:
A[12] = h + A[8];
▪ h in $s2, base address of A in $s3
• Compiled MIPS code:
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 48($s3)
# load word
# store word
10
Immediate Operands
• Many times a program will use a constant
▪ Ex) Incrementing an index to point to the next element of an array
• Adding the constant 4 to register $s3 (using lw and add),
lw $t0, AddrConstant4($s1) # $t0 = constant 4
add $s3, $s3, $t0
# $s3 = $s3 + $t0
• Alternative: constant data specified in an instruction
addi $s3, $s3, 4
◼ Make the common case fast
◼ Allow instructions to contain immediate operands
• No subtract immediate instruction
▪ Just use a negative constant
addi $s2, $s1, -1
11
I-format
• R-format instructions have all 3 operands in registers
• In I-format instructions, one operand can be stored in
instruction itself
▪ They are called immediates because they are immediately
available from the instructions
• They do not require a register or memory access
▪ 16-bit immediate field in MIPS instructions limits values to
the range of (-215 ~ +215–1) since it uses 2’s complement
opcode
rs
rt
immediate
◼ Good design demands good compromises
◼ Three instruction formats
12
I format
Revisiting 2’s Complement Number
• In hardware design of computer arithmetic, the 2’s
complement number provides a convenient and simple way to
do addition and subtraction of unsigned and signed numbers
• Given an n-bit number N in binary, the 2’s complement of N is
defined as
2n – N for N ≠ 0
0 for N = 0
▪ Example:
• With a 4-bit, 3 is 4’b0011 and 2’s complement of 3: 24 -3 = 4’b1101
• A fast way to get a 2s complement number is to flip all the
bits and add 1
13
Number System Comparison with N-bit
Number System
Range
Unsigned
[0, 2N-1]
Sign/Magnitude
[-(2N-1-1), 2N-1-1]
2’s Complement
[-2N-1, 2N-1-1]
• Thus, 16-bit can represent a range of
▪ Unsigned: [ 0 ~ +(216-1)] = [ 0 ~ +65535]
▪ Sign/Magnitude: [-(216-1-1) ~ +(216-1-1)] =[-32767 ~ +32767]
▪ 2’s complement: [-216-1 ~ +216-1-1] =[-32768 ~ +32767]
14
addi
• I format instruction
addi
rt, rs, imm
• Example:
addi $t0, $s3, -12
#$t0 = $s3 + (-12)
Name
opcode
8
binary
hexadecimal
rs
rt
19
immediate
8
-12
001000
10011
01000 11111 11111
110100
001000
10011
01000 11111 11111
110100
0x2268 FFF4
15
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31
lw
• lw reads a word (32-bit) from memory and loads into a register
• I format Instruction
lw
rt, address
• Example:
lw
$t0, 24($s3)
# load (read) word from memory
# $t0 <= [$s3 + 24]
Name
opcode
35
rs
rt
19
immediate
8
24
MIPS architect defines the opcode
binary
hexadecimal
100011
10011
01000 00000 00000
011000
100011
10011
01000 00000 00000
011000
0x8E68 0018
16
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31
lw example
lw
$t0, 24($s3)
#load (read) word from memory
# $t0 <= [$s3 + 24]
Main Memory (2GB)
0x7FFFFFFF
Assume that $s3 has 0x0000_0094
$s3 + 2410 = 0x0000_00ac
0001 1000 // 24 = 0x18
+ . . . 1001 0100 // $s3 = 0x94
$t0
. . . 1010 1100 = 0x000_000ac
$s3
0xAABBCCDD
0x000000af
0x000000ae
0x000000ad
0x000000ac
0x00000094
0x000000ac
Address Bus
CPU
Data Bus
17
0x00000003
0x00000002
0x00000001
0x00000000
Byte address
in hex
lw (Cont)
•
lw is an I format instruction
opcode
rs
rt
immediate
• The memory address (32 bit address) is formed by adding the
contents of the base address register to the offset
▪ In lw $t0, 24($s3), the base is $s3 and the offset is 24
▪ The immediate specified in an instruction is a 16-bit 2’s complement
number in the range [-32768, 32767]
Main Memory
base + 32767
base
base + (-32768)
18
sw
• sw stores (writes) a word (32-bit) from a register to main memory
• I format instruction
sw rt, address
• Example:
sw $t2, 8($s3) # store(write) word to memory
# [$s3 + 8] <= $t2
Name
opcode
43
rs
rt
19
immediate
10
8
MIPS architect defines the opcode
binary
hexadecimal
101011
10011
01010 00000 00000
001000
101011
10011
01010 00000 00000
001000
0xAE6A 0008
19
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31