(CAT-1 MATERIALS)
19L604 – EMBEDDED SYSTEMS AND IOT
3104
INTRODUCTION: Characteristics of Embedded Systems(4-6), Design Challenges(8-9), Design
Flow(437-443), Specifications and Modeling(437-443), Design Model (437-443),, Product Design
Life Cycle(Introduction Chapter & Chapter 1),
Wired & Wireless Commn. Protocols: I2C (406-410), SPI, CAN(422-425), BLUETOOTH (HC05
Module), WIFI (Node MCU), Ethernet(411-413). (Note: Refer the respective datasheets & in
addition refer the following notes attached for communication Protocols) (10+3)
ARCHITECTURE OF ARM CORTEX-M4 MICROCONTROLLER: General Purpose I/O,
System Clock, Watch-Dog-Timer, Micro DMA, Low Power Modes, Interrupts. (Datasheet: P.No. 46
to 67)
(10+3)
Text & Reference Books:
1. Computers & Components by Wayne Wolf
2. Embedded System Design by Arnald Berger
1
2
3
4
5
Desing flow,
6
7
8
9
10
11
12
13
SERIAL COMMUNICATION
AND
NETWORK TOPOLOGY
TABLE OF CONTENS
CHAPTER NO
CONTENTS
PAGE NO.
1
INTRODUCTION TO
COMMUNICATION PROTOCOLS
9
2
NETWORKING TOPOLOGIES
18
2
BLUETOOTH
24
3
WIFI
33
4
SPI
41
5
CAN
47
6
I2C
54
7
ETHERNET
79
14
INTRODUCTION TO COMMUNICATION PROTOCOLS
COMMUNICATION:
The imparting or exchanging of information by speaking, writing or using other medium or
by means of sending or receiving information such as telephone lines or computers. The basic components
of an electronic communication system include a transmitter, a receiver, a communication medium or
channel and noise. Information is transmitted into the system in analog or digital form, it is then processed
and decoded by the receiver.
Example: Satellite communications
In communication synchronization is mandatory to transmit and receive the data. If there is no
synchronization means, there will be no proper communication.
Figure 1.1 : Communication Model
WHY COMMUNICATION?
We communicate for a variety of reasons. We use communication to share information, ask
questions, express wants and needs, develop social enquiries, etc…
SERIAL COMMUNICATION
In telecommunication and data transmission, serial communication is the process of sending data one
bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to
parallel communication, where several bits are sent as a whole, on a link with several parallel channels.
SYNCHRONIZATION
But even though all the components may be available, communication may still not take place
effectively. This can be due to 2 reasons:• Receiver may not be able to receive transmitted data as it could be full.
• Receiver may not know that data has been transmitted.
Therefore, before communication takes place there must be mutual understanding between transmitter and
receiver which is known as synchronization or handshaking. This is essential in communication.
Synchronization can be done using two ways, they are
1. Clock based Synchronization
2. Baud rate based Synchronization
15
Synchronous and Asynchronous are different from Synchronization. Synchronous and Asynchronous way
of communication are two different ways to achieve communication.
One example of synchronization is the behavioral flow of DB – 9 connector used in UART
communication.
Figure 1.2 : COM Port 1 9-PIN D-Type Connector
DB9 is a commonly known connector used in Serial Asynchronous Data Transmission that are
designed to work with the EIA/TIA 232 serial interface standard. RS-232 (Recommended Standard 232) is
the standard for establishing serial data transfer between DTE (Data Terminal Equipment) and DCE (Data
Circuit-terminating Equipment). A DB9 connector has 9 pins arranged in two rows as shown in figure 1.2
having 5 pins in top row and remaining 4 pins in the bottom. It is also known as COM port and is used to
interface device with data rate less than 20kbps. DB9 connector supports full-duplex data transfer.
Figure 1.3 : Pin Description
16
DB9 connectors were commonly used for serial peripheral devices like keyboards, mouse, joysticks,
etc. Also they are used on DB9 cable assemblies for data connectivity.
Figure 1.4 : Synchronization Signals
Double synchronization occurs in the above example. Hence this is also called as Handshake. Thus by
synchronization, we can guarantee that data will be transmitted and received successfully.
CLOCK based Synchronization:
•
•
•
It provides the exact same time to all clocks in the system as shown in figure 1.5.
It consists of a “master clock” and a “slave clocks”.
The master clock communicates with all the slave clocks in the system to provide with an accurate
time source.
•
The purpose is to make sure that all the clocks in the system show the exact same time.
• The data to be transmitted has start bit and stop bit. Start bit goes from high to low and stop bit goes
from low to high.
• Once the negative falling edge of the clock pulse sent by the transmitter is recognized by the
receiver, the receiver will acknowledge and transmitter can send the data.
• The main problem in using the clock based synchronization is that when this is used for long distance
communication there may be distortion in the clock pulse due to some unavoidable losses of the
conducting material.
• So the receiver may not be able to receive the clock pulse properly.
Examples: Inter Integrated circuit, Serial Peripheral Interface.
Figure 1.5: Tx & Rx Synchronization through Clock Pulse
17
BAUD RATE based Synchronization:
Baud rate represents the number of times per second a signal (changing from zero to one
or one to zero) or symbol (the connection's voltage, frequency or phase) in a communications channel
changes state or varies. For example, a 2,400 baud rate means the channel is changing states up to 2,400
times per second. This method of synchronization is followed in off-board communication. The baud rate of
the transmitter and receiver must be same for proper data transmission, if not the device with higher baud
rate must be reduced to the baud rate as same as the other device has, then only the proper communication
will take place. Standardized connectors are needed to connect the transmitter and receiver.
Examples: Universal Serial Bus, UART, Ethernet, Controller Area Network(CAN).
Why off-board / board-to-board communication don’t use clock signal for
communication?
•
•
Preserving the edge will be difficult for long distance wired communication. Because clock will
transfer from transmitter to receiver, the receiver will detect the edge. But here that clock signal
may converted to sine signal and edge can’t be detected. So communication can’t happen.
First place the data bits on transmission line and receiver will wait for detecting falling edge and
when it detects falling edge it will get data bit from the transmission line.
SUMMARY
Table 1.1: Features of Clock based & Baud Rate based Synchronization
CLOCK
BAUD RATE
On Board (with in board)
Off Board (between 2 boards)
Communication between IC’s
Communication between boards
No need for connectors
Standardized cable or connector are needed
Eg: IIC (I2C), SPI
Eg: USB, Ethernet, UART, VGA, CAN
MODES OF COMMUNICATION
•
•
•
Simplex
Half duplex
Full duplex
SIMPLEX:
In Simplex mode, the communication is unidirectional, as on a one-way. Only one of the two devices on a
link can transmit, the other can only receive. The simplex mode can use the entire capacity of the channel to
send data in one direction.
Example: FM radio, TV receiver.
18
Figure 1.6 : Simplex Communication
HALF DUPLEX:
In half-duplex mode, each station can both transmit and receive, but not at the same time. When one device
is sending, the other can only receive, and vice versa. The half-duplex mode is used in cases where there is
no need for communication in both direction at the same time. The entire capacity of the channel can be
utilized for each direction.
Example: Walkie- talkie in which message is sent one at a time and messages are sent in both the
directions.
Figure 1.7 : Half-Duplex Communication
FULL DUPLEX:
In full-duplex mode, both stations can transmit and receive simultaneously. In full-duplex mode, signals
going in one direction share the capacity of the link with signals going in other direction, this sharing can
occur in two ways:
• Either the link must contain two physically separate transmission paths, one for sending and other for
receiving.
• Or the capacity is divided between signals travelling in both directions.
Full-duplex mode is used when communication in both direction is required all the time. The capacity of the
channel, however must be divided between the two directions.
Examples: Telephone Network in which there is communication between two persons by a
telephone line, through which both can talk and listen at the same time.
19
Figure 1.8 : Full Duplex Communication
Comparison for the three types of communication channel:
Table 1.2: Comparison of Simplex, Half-Duplex & Full-Duplex Communication
BASIS FOR
COMPARISON
SIMPLEX
HALF DUPLEX
FULL DUPLEX
Direction of
communication
Communicational is
Unidirectional.
Communication is
two directional but
one at the time.
Communication is
two directional and
done
simultaneously.
Send/Receive
A sender can send
data but can’t
receive it.
A sender can send
as well as receive
the data but one at
the time.
A sender can send
as well as receive
the data
simultaneously.
Performance
The half and full
duplex yields better
performance than
the simplex.
The full duplex
mode yields higher
performance than
the half duplex.
It has Better
performance. It
doubles the
utilization of the
bandwidth.
Example
FM Radio,
Keyboards,
Monitors.
Walkie- Talkies
Telephone
POINT TO POINT COMMUNICATION:
It refers to a communications connection between two communication end points or nodes.
EXAMPLE: Telephone call, in which one telephone is connected with one other, and what is
said by one caller can only be heard by the other.
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UART
Figure 1.9
UART follows the full duplex method of communication since it uses different buffers for
transmission and reception that means transmission and reception can be done simultaneously as shown in
figure 1.8. UARTs transmit data asynchronously, which means there is no clock signal to synchronize the
output of bits from the transmitting UART to the sampling of bits by the receiving UART. Instead of a clock
signal, the transmitting UART adds start and stop bits to the data packet being transferred. These bits define
the beginning and end of the data packet so the receiving UART knows when to start reading the bits.
When the receiving UART detects a start bit, it starts to read the incoming bits at a specific frequency
known as the baud rate. Baud rate is a measure of the speed of data transfer, expressed in bits per second
(bps). Both UARTs must operate at about the same baud rate. The baud rate between the transmitting and
receiving UARTs can only differ by about 10% before the timing of bits gets too far off.
Figure 1.10 : UART Communication Signals
SPI
SPI (Serial Peripheral Interface) follows full-duplex method of communication. The tansmitter which
sends the data is known as master and the receiver which receives the data is known as slave. If the master is
ready to send the data it sends the clock pulse to another SPI after acknowledging the will be transmitted
through MOSI(Master Out Slave Out). Similarly the data can be transmitted from slave to master using
MISO(Mater In Slave Out) as shown in figure 1.11. So at the same time both transmision and reception is
done, hence SPI is a full duplex serial communication protocol.
Figure 1.11 : SPI Communication Signals
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USB
A Universal Serial Bus (USB) is a common interface that enables communication between devices
and a host controller such as a personal computer (PC). It connects peripheral devices such as digital
cameras, mice, keyboards, printers, scanners, media devices, external hard drives and flash drives.
USB(Universal Serial Bus) follows half duplex method and baud rate based synchronization .
Figure 1.12 :USB Communication Signals
Unlike the other protocals USB has Vcc and GND using this any one of the connected can be fed by
the another device and also It uses differential logic to tansfer the data D+ transfers the data as it is and Dtransfers the data inverted version of the data as shown in figure 1.12. If any external factors like noise affect
the data both data will be distorted, but by using the CMMR cocept the noise will be reduced and it doesnot
affect the data since both the data are inversion to each other.
CAN
Figure 1.13 : CAN Communication Signals
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As shown in figure 1.13, CAN (Controller Area Network) follows half duplex method of
communication at the same time both transmision and reception can’t be caried out and also it uses
differential logic to transfer the data explained as same as in the USB.
Ethernet
Ethernet follows full-duplex method and uses differential logic to tansfer the data.
Ethernet is most widely used LAN Technology, which is defined under IEEE standards 802.3. The reason
behind its wide usability is Ethernet is easy to understand, implement, maintain and allows low-cost network
implementation. Also, Ethernet offers flexibility in terms of topologies which are allowed. Ethernet operates
in two layers of the OSI model, Physical Layer, and Data Link Layer. For Ethernet, the protocol data unit is
Frame since we mainly deal with DLL. In order to handle collision, the Access control mechanism used in
Ethernet is CSMA/CD.
Figure 1.14 : Ethernet Communication Signals
DIFFERENTIAL LOGIC:
1.
2.
3.
4.
5.
6.
7.
Data what we send may be affected due to the external noise.
So differential logic were introduced.
Same data is send in both +ve and –ve logics.
But, the effects of noise will be same in both +ve and -ve pins.
Thus it will gets rejected.
Only the signals with opposite logic will be taken as information while others will get rejected.
In this way it rejects 99.99% noises occurs in the network.
CMRR:
1. CMRR uses differential logics.
2. It has the ability to reject the common mode signals.
3. Some of the serial communication protocol which use differential logic are:
• Controller Area Network (CAN)
• Ethernet
• USB
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NETWORKING TOPOLOGY:
Geometric representation of how the computers are connected to each other is known as topology.
There are 5 types of topologies, they are:
•
•
•
•
•
STAR TOPOLOGY
BUS TOPOLOGY
RING TOPOLOGY
TREE TOPOLOGY
MESH TOPOLOGY
STAR TOPOLOGY:
•
•
•
Here, each device is connected to a central device called hub.
Each device communicates via hub.
If one device wants to send the data to other device, first it has to send data to the hub and then then
the hub transmits that data to the desired device.
Figure 1.15 : Star Topology
Advantages of this topology:
•
•
If N devices are connected to each other in star topology, then the number of cables required to
connect them is N. So, it is easy to set up.
Each device require only 1 port i.e. to connect to the hub.
Problems with this topology:
•
•
•
If the concentrator (hub) on which the whole topology relies fails, the whole system will crash down.
Cost of installation is high.
Performance is based on the single concentrator i.e. hub.
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BUS TOPOLOGY:
•
•
In this, there is a main cable. Each device is connected to the main cable through the drop lines.
A device called Tap which connects the drop line to the main cable.
Figure 1.16 : Bus Topology
Advantages of Bus topology:
•
If N devices are connected to each other in bus topology, then the number of cables required to connect
them is known as backbone cable and N drop lines are required.
• Cost of the cable is less as compared to other topology, but it is used to build small networks.
Problems with Bus topology:
•
•
If the common cable fails, then the whole system will crash down.
If the network traffic is heavy, it increases collisions in the network. To avoid this, various protocols are
used in MAC layer known as Pure Aloha, Slotted Aloha, and CSMA/CD etc.
RING TOPOLOGY:
•
•
•
Each device is connected with the two devices on either side of it.
There are two point to point links a device has with the devices on the either side of it.
Thus, it forms a ring like structure.
The following operations takes place in ring topology:
• One station is known as monitor station which takes all the responsibility to perform the operations.
• To transmit the data, station has to hold the token. After the transmission is done, the token is to be
released for other stations to use.
• When no station is transmitting the data, then the token will circulate in the ring.
• There are two types of token release techniques: Early token release releases the token just after the
transmitting the data and Delay token release releases the token after the acknowledgement is
received from the receiver.
25
Figure 1.17 : Ring Topology
Advantages of Ring topology:
•
•
The possibility of collision is minimum in this type of topology.
Cheap to install and expand.
Problems with Ring topology:
•
•
Troubleshooting is difficult in this topology.
Addition of stations in between or removal of stations can disturb the whole topology
TREE TOPOLOGY:
• Here, the connected elements are arranged like a branch of tree.
• Tree topologies are frequently used to organize the computers in a corporate network, or the
information in a database.
26
Figure 1.18 : Tree Topology
MESH TOPOLOGY:
•
•
Here, each device is connected to every other device on the network through a dedicated point -topoint link.
Each device is connected to n-1 devices of the network, where n is the total devices.
Figure 1.19 : Mesh Topology
Advantages of Mesh topology:
•
•
It is robust.
Fault is diagnosed easily. Data is reliable because data is transferred among the devices through
dedicated channels or links.
• Provides security and privacy.
27
Problems with Mesh topology:
•
•
•
Installation and configuration is difficult.
Cost of cables are high as bulk wiring is required, hence suitable for less number of devices.
Cost of maintenance is high.
TOPOLOGY FOLLOWED BY THE VARIOUS WIRED AND WIRELESS
COMMUNICATION
Table 1.3: Communication Protocols with its associated topologies
SNo Wired / Wireless Communication
Topology
1
UART
No Topology
2
CAN
Bus Topology
3
IIC
Bus Topology
4
Ethernet
Star Topology
5
USB
Tree Topology
6
SPI
Star/ Ring Toplogy
7
All Wireless Communication
Mesh Topology
COMMUNICATION MODES
Table 1.4: Communication Model Table
SNo
Examples
Simplex
Half Duplex
Full Duplex
1
FM Radio Receiver
2
Walkie- Talkie
✓
3
IIC
✓
4
USB
✓
5
CAN
✓
6
UART
✓
7
SPI
✓
8
Ethernet
✓
✓
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OVERIEW
Table 1.5: Wired and Wireless Communication Protocol Comparison Table
29
BLUETOOTH:
1. BLUETOOTH
Bluetooth was originally designed to exchange a lot of data at close range in continuous, streaming data
applications. The devices are able to both send and receive data at the same time. This is perfect for many
common consumer products, such as computer headsets, where the two devices are close together.
Fig 2.1 : Bluetooth Symbol
Bluetooth is a wireless technology standard used for exchanging data between fixed and mobile devices over
short distances using short-wavelength UHF radio waves in the industrial, scientific and medical radio
bands, from 2.400 to 2.485 GHz, and building personal area networks (PANs). It was originally conceived
as a wireless alternative to RS-232 data cables.
Example: Bluetooth mouse.
Fig 2.2 : Bluetooth Mouse
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Range depends on surroundings, radio performance and antennas
There are many factors affecting Bluetooth range, typically:
•
•
•
•
The output power of the transmitter
The sensitivity of the receiver
Physical obstacles in the transmission path
The antennas
While the radio performance and antennas are pretty static for a given Bluetooth device, the surroundings
can vary a lot. Outdoors, in an open field, you can get a range of up to a hundred meters. But that is a rare
situation. Indoors, obstacles like concrete walls will attenuate the radio signal and the effective range will be
drastically reduced. In normal use, ten meters is a good guide to what can be achieved between two
Bluetooth devices indoors.
2. BLUETOOTH LOW ENERGY:
When Bluetooth low energy (BLE, formerly called Bluetooth Smart) hit the market in 2011, the key
advantage over earlier versions was lower power consumption over the same range, but with lower
bandwidth. It’s intended for devices that only need to exchange small amounts of data periodically,
extending battery life by months or even years.
How to improve Bluetooth range with networking
We can connect Bluetooth devices to multiple distributed gateways connected to the internet. The Bluetooth
devices can communicate with each other, and with online services, via these gateways. This is an ideal
solution if the devices are spread over a large geographical area. Each hub can usually only handle a few
directly connected devices, which is another limitation of Bluetooth. We are likely to run into a situation
where we want to handle hundreds or even thousands of Bluetooth devices in a relatively small area, such as
an office building. For this we need to use a Mesh Network to connect the gateway and the local Bluetooth
devices.
STACK
Stack is a set of codes which are already available for the user.
Example: Bluetooth stack.
The IEEE standardized Bluetooth as IEEE 802.15.1.
Industry Scientific Medical Band is a frequency spectrum(ISM), for which it is not needed to pay for use.
Frequency of ++
ISM Band is 2.4 GHz.
Network Architecture has a layered architecture of ICP/IP architecture. They are,
•
Physical layer
•
Data link layer
•
Network layer
31
•
Transport layer
•
Session layer
•
Presentation layer
•
Application layer.
LAYERS EXPLANATION:
The Bluetooth UART service allows another device such as a smartphone to exchange any data it wants to
with the micro: bit, in small chunks which are intended to be joined together. UART stands for Universal
Asynchronous Receiver Transmitter and is one way in which serial data communications can be performed,
usually between two devices connected by a physical, wired connection. The Bluetooth UART service
emulates the behaviour of a physical UART system and allows the exchange of a maximum of 20 bytes of
data at a time in either direction.
3. HC05 BLUETOOTH MODULE:
HC-05 module is an easy to use Bluetooth SPP (Serial Port Protocol) module, designed for transparent
wireless serial connection setup. Serial port Bluetooth module is fully qualified Bluetooth V2.0+EDR
(Enhanced Data Rate) 3Mbps Modulation with complete 2.4GHz radio transceiver and baseband. It uses
CSR Blue core 04-External single chip Bluetooth system with CMOS technology and with AFH (Adaptive
Frequency Hopping Feature). It has the footprint as small as 12.7mmx27mm. Hope it will simplify your
overall design/development cycle.
SPECIFICATIONS:
Hardware features:
• Typical -80dBm sensitivity
• Up to +4dBm RF transmit power
• Low Power 1.8V Operation ,1.8 to 3.6V I/O
• PIO control
• UART interface with programmable baud rate
• With integrated antenna
• With edge connector
Software features:
• Default Baud rate: 38400, Data bits:8, Stop bit:1,Parity:No parity, Supported baud rate:
9600,19200,38400,57600,115200,230400,460800.
• Given a rising pulse in PIO0, device will be disconnected.
• Status instruction port PIO1: low-disconnected, high-connected;
• PIO10 and PIO11 can be connected to red and blue led separately. When master and slave are paired,
red and blue led blinks 1time/2s in interval, while disconnected only blue led blinks 2times/s.
• Auto-connect to the last device on power as default.
• Permit pairing device to connect as default.
• Auto-pairing PINCODE:”0000” as default
• Auto-reconnect in 30 min when disconnected as a result of beyond the range of connection.
32
4. BLOCK DIAGRAM:
DEVICE 1
MICROCONTROLLER
DEVICE 2
RXDHCO5
TXD
TXD
BLUTOOTH
MODULE
RXD
MOBILE
Fig 2.3 : Communicating Mobile Phone with 8051 Microcontroller
5. APPLICATION:
BLUETOOTH TERMINAL HC 05:
Simple HC-05 / HC-06 Terminal for Sending and Monitoring data for embedded system
- One-of-a-kind App that gives us compatibility with all microcontrollers. All we need is a HC-05 serial
adapter connection with serial ports of the controllers.
- Control any Micro-controller that uses a Bluetooth Module HC 05 or HC 06 through our smart phone.
- This app can send and receive commands via Bluetooth so we can debug our hardware problems easily.
FEATURES:
•
The app displays all the paired devices and throws an error when correct Bluetooth device is not
connected.
Fig 2.4 : Bluetooth Terminal App in Mobile Phone
•
The screen when the connected to HC 05
33
Fig 2.5. Device is connected to HC 05
•
HC 05 terminal app settings
- Keep Screen on/off option.
- Remove Ads and get uninterrupted access with an Ad - free version of Bluetooth Terminal.
Fig 2.6. App settings
•
Customise the number of buttons and font size.
34
Fig 2.7. Button and font size setting
•
Facilitates to customise the buttons and send data as hexadecimal or ASCII.
Fig 2.8. Data type settings
- By default, Received data in ASCII format and It can be changed from top MENU.
- By default, Data sent in ASCII format and It can be changed from long pressing of particular Button.
- By default, \r\n will be sent on every sending data and It can be changed from long pressing of particular
Button.
35
5.1 CIRCUIT DIAGRAM:
Fig 2.9. Circuit diagram of Interfacing HC 05 with 8051
Fig 2.10 Connection of led to indicate reception of data via Bluetooth
CODE FOR TRANSMITTING:
#include<reg51.h>
Voidmain()
{
SCON=0x50; //mode 1, 8 bit data,1 start bit,1 stop bit
TMOD=0x20; // timer 1 mode 2(8 bit auto reload)
TH1=0xFD; //9600 baud rate
TL1=0xFD; //9600 baud rate
TR1=1; start the timer
while(1)
{
SBUF='A'; //character to be transmitted is copied to SBUF
while(!TI); // wait until transmit interrupt flag is set
TI=0; //clear transmit interrupt flag
SBUF=0x0D; //carriage return
while(!TI);
TI=0;
36
SBUF=0x0A; // new line
while(!TI);
TI=0;
}
}
DESCRIPTION:
In the above code, character A is being transmitted. The transmitted data can be viewed using
Bluetooth terminal HC 05 mobile app. We can also transmit a string.
OUTPUT:
Fig 2.11. Transmitted character is viewed in the app
CODE FOR RECEIVING:
#include<reg51.h>
void main()
{
SCON = 0X50;
TMOD = 0X20;
TH1 = 0XFD;
TL1 = 0XFD;
TR1 = 1;
while(1)
{
SBUF = 'T';
while(!TI);
TI = 0;
while(!RI);
P0 = SBUF;
RI = 0;
37
}
}
DESCRIPTION:
In the above code, character T is being transmitted. The transmitted data can be viewed by
establishing connection of led to indicate reception of data via Bluetooth
ADVANTAGES OF BLUETOOTH:
•
It avoids interference from other wireless devices.
•
It has lower power consumption.
•
It is easily upgradeable.
•
It has range better than Infrared communication.
•
The Bluetooth is used for voice and data transfer
DISADVANTAGES OF BLUETOOTH:
•
slow data speeds
•
poor data security
•
shortened battery life.
APPLICATIONS:
•
Bluetooth Tethering.
•
Transfer Files between Two Devices.
•
Play Multiplayer Games Over Bluetooth.
•
Connect Different Devices.
•
Control Home Security Gadgets.
•
Bluetooth and Cars.
38
WI-FI
INTRODUCTION
Nowadays Technology is moving towards INTERNET OF THINGS (IOT).
IOT can be defined as,’ It is Anything that can be controlled/Monitored from Anywhere at
Anytime’. The Module which can be used to connect to Internet is ESP8266. This modue
allows user to connect to Internet by means of AT-COMMANDS. Local WIFI network can
generated by creating Hotspot using Mobile Phones.
Fig 3.1
OBJECTIVE
To Monitor/Control a sensor/Switch anywhere at anytime.
PROBLEMS
To monitor/control a sensor/Switch we require a Microcontrollor. But ESP8266
is a wifi module but not a MicroControllor.
SOLUTION
ESP8266 + MCU will meet the above Requirement.
39
ESP8266 Wi-Fi module:
The ESP8266 Wi-Fi Module is a self-contained SOC with integrated TCP/IP protocol
stack that can give any microcontroller access to your Wi-Fi network. The ESP8266 is
capable of either hosting an application or offloading all Wi-Fi networking functions from
another application processor. Each ESP8266 module comes pre-programmed with an AT
command set firmware, meaning, you can simply hook this up to your Arduino device and
get about as much Wi-Fi-ability as a Wi-Fi Shield offers (and that's just out of the box)! The
ESP8266 module is an extremely cost effective board with a huge, and ever growing,
community.
Fig 3.2 : ESP 8266 Module
CP2102:
The CP2102 USB to UART Bridge provides a complete plug and play interface
solution that includes royalty-free drivers. The CP210x USB to UART Bridge Virtual COM
Port (VCP) drivers are required for device operation as a Virtual COM Port to facilitate host
communication with CP210x products. These devices can also interface to a host using
the direct access driver.
Fig 3.3 : CP2102 USB to UART Bridge
ARDUINO IDE:
• It supports Arduino boards.
• CP212x device driver is downloaded, so that NodeMCU can be used.
• D type connector- COM port.
• COM1 is Physical COM port.
• COM3 is Virtual COM port.
40
• In Arduino IDE, board must be set as NodeMCU1.0(ESP-12E Module) and port
must be set as COM3(some Virtual COM port).
•
There is no connection between NodeMCU and COM3.Port COM3 is set
because of the CP2102 device driver.
.NodeMCU:
NodeMCU is an open source IoT platform. It includes firmware which runs on
the ESP8266 Wi-Fi SoC from Espressif Systems, and hardware which is based on the ESP12 module. The term "NodeMCU" by default refers to the firmware rather than the
development kits. The firmware uses the Lua scripting language.Power supply is given
through USB.
Fig 3.4
NodeMCU is an open source IoT platform. It includes firmware which runs on the
ESP8266 Wi-Fi SoC from Espressif Systems, and hardware which is based on the ESP-12
module.
The term "NodeMCU" by default refers to the firmware rather than the development kits.
The firmware uses the Lua scripting language. It is based on the eLua project, and built on
the Espressif Non-OS SDK for ESP8266. It uses many open source projects, such as luacjson and SPIFFS.
Features:
• Wi-Fi Module – ESP-12E module similar to ESP-12 module but with 6 extra GPIOs.
41
• USB – micro USB port for power, programming and debugging; Power – 5V via
micro USB port
• Dimensions – 49 x 24.5 x 13mm
• NodeMCU Dev Kit has Arduino like Analog (i.e. A0) and Digital (D0-D8) pins on its
board.
• Headers – 2x 2.54mm 15-pin header with access to GPIOs, SPI, UART, ADC, and
power pinsMisc – Reset and Flash buttons. It supports serial communication protocols
i.e. UART, SPI, I2C etc. With the help of such serial protocols we can connect it with
serial devices like I2C enabled LCD display, Magnetometer HMC5883, MPU-6050
Gyro meter + Accelerometer, RTC chips, GPS modules, touch screen displays, SD
cards etc.
PIN DETAILS:
Table 3.1
I/O index
ESP8266 pin
0 [*]
GPIO16
1
GPIO5
2
GPIO4
3
GPIO0
4
GPIO2
5
GPIO14
6
GPIO12
7
GPIO13
8
GPIO15
9
GPIO3
10
GPIO1
11
GPIO9
12
GPIO10
D0 (GPIO16) can only be used for GPIO read/write. It does not support opendrain/interrupt/PWM/I²C or 1-Wire.While writing the GPIO code for Node MCU, we cannot
address them with actual GPIO pins numbers. There are different I/O index numbers
assigned to each GPIO pin which is used for GPIO addressing. The following table consists
of the GPIO pin with its index number.
42
CHALLENGES FACED
Writing code for WiFi is a quite difficult task.
SOLUTION
Using WiFi Stack to code NodeMCU.
PROGRAMMING NODEMCU
To code NodeMCU, Arduino environment is used. Usual Arduino Boards
dosent have onboard WiFi. To configure Arduino environment to program NodeMCU we
should patch up Arduino Environment with patch given by ESP8266 Community. To do that
following steps has to be followed.
STEPS TO BE FOLLOWED FOR PATCHING ARDUINO IDE
• First Open Arduino IDE.
• In files Go to preferences or press CTRL + comma.
• Now
paste
this
link
on
Additional
Board
Manager.(‘http://arduino.esp8266.com/stable/package_esp8266com_index.json’)
• Now go to tools → Boards → Board Manager.
• Scroll to the end and install ESP8266 community Boards v.2.4.0
• Once installation is done NodeMCU is ready to be programmed.
WAYS TO PROGRAM NODEMCU
• Through Arduino IDE by creating a WebPage using HTML.
• Through Arduino IDE by using BLYNK APP.
BY CREATING WEBPAGE
The Arduino code used to Switch LED over a WebServer is given Below.
#include <ESP8266WiFi.h>
#define LED D0
const char* ssid = "Kandy";
const char* password = "12345678";
unsigned char status_led=0;
43
WiFiServer server(80);
void setup() {
Serial.begin(115200);
pinMode(LED, OUTPUT);
Serial.println();
Serial.println();
Serial.print("Connecting to ");
Serial.println(ssid);
WiFi.begin(ssid, password);
while (WiFi.status() != WL_CONNECTED )
{
delay(500);
Serial.print(".");
}
Serial.println("");
Serial.println("WiFi connected");
server.begin();
Serial.println("Server started");
Serial.println(WiFi.localIP());
}
void loop() {
WiFiClient client = server.available();
if (!client) {
return;
}
Serial.println("new client");
44
while(!client.available())
{
delay(1);
}
String req = client.readStringUntil('\r');
Serial.println(req);
client.flush();
if (req.indexOf("/ledoff") != -1)
{
status_led=0;
digitalWrite(LED,HIGH);
Serial.println("LED OFF");
}
else if(req.indexOf("/ledon") != -1)
{
status_led=1;
digitalWrite(LED,LOW);
Serial.println("LED ON");
}
String web = "HTTP/1.1 200 OK\r\nContent-Type: text/html\r\n\r\n";
web += "<html>\r\n";
web += "<body>\r\n";
web += "<h1> MONITORING AND CONTROL USING WIFI</h1>\r\n";
web += "<p>\r\n";
45
if(status_led==1)
web += "LED ON\r\n";
else
web += "LED OFF\r\n";
web += "</p>\r\n";
web += "</p>\r\n";
web += "<a href=\"/ledon\">\r\n";
web += "<button>LED ON</button >\r\n";
web += "</a>\r\n";
web += "</p>\r\n";
web += "<a href=\"/ledoff\">\r\n";
web += "<button>LED OFF</button >\r\n";
web += "</a>\r\n";
web += "</body>\r\n";
web += "</html>\r\n";
client.print(web);
}
RESULT
Thus performance and applications of Nodemcu has been studied.
46
SPI PROTOCOL
INTRODUCTION:
There are various microcontroller communication interfaces in the market today to tackle almost any
conceivable communication task. The types of interfaces available, can be classified into two basic
categories. They are
•
•
Synchronous Interfaces
Asynchronous Interfaces
Synchronous interfaces are characterized by the presence of a dedicated receive/transmit clock signal. A
‘Master’ device usually outputs a clock signal that is received by all ‘Slave’ devices to receive and transmit
data in sync. Examples of synchronous interfaces are: SPI (Serial Peripheral Interface), Microwire, I2C
(Inter Integrated Circuit), USART (Universal Synchronous & Asynchronous Receiver Transmitter).
SPI:
A Serial Peripheral Interface is an interface that enables the serial (one bit at a time) exchange of data
between two devices, one called a master and the other called a slave. An SPI operates in full duplex mode.
This means that the data can be transferred in both directions at the same time. The SPI is most often
employed in systems for communication between the CPU and peripheral devices. It is also possible to
connect two microprocessors by means of SPI.
SPI is a serial communication protocol used for serial communication over short distance (few centimetres)
between individual Integrated Circuits. It uses 3 wires for full duplex communication i.e.,
•
MOSI - Master Out Slave In
•
MISO - Master In Slave Out
•
SCLK - Serial Clock
•
SS - Slave Select
Addressing is done with Chip Select signal that is also from master side. It is used when data is to be sent to
small number of devices since each slave requires individual CS (Chip Select) wire. CS is used by master to
select which slave will receive or transmit data.
Typical applications include:
• Secure Digital cards.
• Liquid crystal displays.
SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The
master device originates the frame for reading and writing. Multiple slave-devices are supported through
selection with individual slave select (SS), sometimes called chip select (CS), lines. Sometimes SPI is called
a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. The SPI may be accurately
described as a synchronous serial interface, but it is different from the Synchronous Serial Interface (SSI)
protocol, which is also a four-wire synchronous serial communication protocol.
The SSI protocol employs differential signaling and provides only a single simplex communication channel.
SPI is one master and multi slave communication. Serial Peripheral Interface (SPI) is an interface bus
commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors,
and SD cards. It uses separate clock and data lines, along with a select line to choose the device you wish to
talk to.
47
The SPI bus specifies four logic signals:
•
•
•
•
SCLK: Serial Clock (output from master)
MOSI: Master Output Slave Input, or Master Out Slave In (data output from master)
MISO: Master Input Slave Output, or Master In Slave Out (data output from slave)
SS: Slave Select (often active low, output from master)
SERIAL CLOCK:
•
SCLK: SCK
MASTER OUTPUT→ SLAVE INPUT (MOSI):
•
SIMO, MTSR - correspond to MOSI on both master and slave devices, connects to each other
•
SDI, DI, DIN, SI - on slave devices; connects to MOSI on master, or to below connections
•
SDO, DO, DOUT, SO - on master devices; connects to MOSI on slave, or to above connections
MASTER INPUT ← SLAVE OUTPUT (MISO):
•
SOMI, MRST - correspond to MISO on both master and slave devices, connects to each other
•
SDO, DO, DOUT, SO - on slave devices; connects to MISO on master, or to below connections
•
SDI, DI, DIN, SI - on master devices; connects to MISO on slave, or to above connections
SLAVE SELECT:
•
SS: S̅S̅, SSEL, CS, C̅S̅, CE, nSS, /SS, SS#
In other words,
•
MOSI (or SDO on a master) connects to MOSI (or SDI on a slave).
•
MISO (or SDI on a master) connects to MISO (or SDO on a slave).
Slave Select is the same functionality as chip-select and is used instead of an addressing concept.
Pin names are always capitalized as in Slave Select, Serial Clock, and Master Output Slave Input.
SPI is used to talk to a variety of peripherals, such as
•
•
•
•
•
•
•
•
Sensors: temperature, pressure, ADC, touchscreens, video game controllers
Control devices: audio codecs, digital potentiometers, DAC
Camera lenses: Canon EF lens mount
Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11, handheld video games
Memory: flash and EEPROM
Real-time clocks
LCD, sometimes even for managing image data
Any MMC or SD card
48
For high-performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to
sensors, or for flash memory used to bootstrap if they are SRAM-based.
Although there are some similarities between the SPI bus and the JTAG protocol, they are not
interchangeable. The SPI bus is intended for high speed, on board initialization of device peripherals, while
the JTAG protocol is intended to provide reliable test access to the I/O pins from an off board controller
with less precise signal delay and skew parameters.
While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold
violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles.
Consequently, the JTAG interface is not intended to support extremely high data rates.
SGPIO is essentially another application stack for SPI designed for particular backplane management
activities. SGPIO uses 3-bit messages.
One unique benefit of SPI is the fact that data can be transferred without interruption. Any number of bits
can be sent or received in a continuous stream. With I2C and UART, data is sent in packets, limited to a
specific number of bits. Start and stop conditions define the beginning and end of each packet, so the data is
interrupted during transmission.
SPI is a common communication protocol used by many different devices.
For example, to the use of SPI to communicate with microcontrollers.
•
•
•
SD card modules,
RFID card reader modules,
2.4 GHz wireless transmitter/receivers.
MASTER/SLAVE:
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When
the master generates a clock and selects a slave device, data may be transferred in either or both directions
simultaneously. In fact, as far as SPI is concerned, data are always transferred in both directions. It is up to
the master and slave devices to know whether a received byte is meaningful or not. So, a device must
discard the received byte in a "transmit only" frame or generate a dummy byte for a "receive only" frame.
Fig 5.1
SPI specifies four signals: clock (SCLK); master data output, slave data input (MOSI); master data input,
slave data output (MISO); and slave select (CSS). Figure shows these signals in a single-slave configuration.
SCLK is generated by the master and input to all slaves. MOSI carries data from master to slave. MISO
carries data from slave back to master. A slave device is selected when the master asserts its CSS signal.
If multiple slave devices exist, the master generates a separate slave select signal for each slave.
49
Fig 5.2
The master generates slave select signals using general-purpose discrete input/output pins or other logic.
This consists of old-fashioned bit banging and can be pretty sensitive. You have to time it relative to the
other signals and ensure, for example, that you don't toggle a select line in the middle of a frame.
While SPI doesn't describe a specific way to implement multi-master systems, some SPI devices support
additional signals that make such implementations possible. However, it's complicated and usually
unnecessary, so it's not often done.
A pair of parameters called clock polarity (CPOL) and clock phase (CPHA) determine the edges of the clock
signal on which the data are driven and sampled. Each of the two parameters has two possible states, which
allows for four possible combinations, all of which are incompatible with one another. So, a master/slave
pair must use the same parameter pair values to communicate. If multiple slaves are used that are fixed in
different configurations, the master will have to reconfigure itself each time it needs to communicate with a
different slave.
SPI does not have an acknowledgement mechanism to confirm receipt of data. In fact, without a
communication protocol, the SPI master has no knowledge of whether a slave even exists. SPI also offers no
flow control. If you need hardware flow control, you might need to do something outside of SPI.
Slaves can be thought of as input/output devices of the master. SPI does not specify a particular higher-level
protocol for master-slave dialog. In some applications, a higher-level protocol is not needed and only raw
data are exchanged. An example of this is an interface to a simple codec. In other applications, a higherlevel protocol, such as a command-response protocol, may be necessary. Note that the master must initiate
the frames for both its command and the slave's response.
Both SPI and I2C offer good support for communication with low-speed devices, but SPI is better suited to
applications in which devices transfer data streams.
SPI's full duplex communication capability and data rates (ranging up to several megabits per second) make
it, in most cases, extremely simple and efficient for single master, single slave applications. On the other
hand, it can be troublesome to implement. for more than one slave, due to its lack of built-in addressing; and
the complexity only grows as the number of slaves increases.
Far from being just a dumb "byte port," SPI is often an elegant solution for modest communication needs. It
can also serve as a platform on which to create higher-level protocols.
50
DAISY CHAIN:
A single active-low SS (or active-low CS) signal controls all the slaves' active-low CS inputs; all slaves
receive the same clock signal. Only the first slave in the chain (SLAVE 1) receives the command data
directly from the microcontroller. Every other slave in the network receives its DIN data from the DOUT
output of the preceding slave in the chain.
For daisy-chaining to work successfully, the slave must be able to input a command at DIN during a given
command-cycle (defined by the number of clock pulses required to clock in one command), and output the
same command at DOUT during the subsequent command-cycle. Stated simply, there is a DIN-to-DOUT
delay of one command-cycle. The slave must, moreover, only execute the command written to it on the
rising edge of active-low CS. This means that as long as active-low CS remains low, the slave ignores the
command and outputs it at DOUT on the following command-cycle. If active-low CS goes high after a given
command-cycle, all slaves execute the commands just written to their respective DIN inputs. If active-low
CS goes high, data is not output at DOUT. This process makes it possible for every slave in the chain to
execute a different command. As long as these daisy-chain requirements are satisfied, the microcontroller
only needs three signals (active-low SS, SCK, and MOSI) to control all the slaves in the network.
ACCOMPLISHMENT OF DAISY CHAIN:
In a daisy-chained system, SLAVE 1 receives data directly from the microcontroller. This data is clocked
into SLAVE 1's internal shift register. As long as active-low CS (or active-low SS) remains low, this data
propagates through to SLAVE 1's DOUT output. DOUT of SLAVE 1 goes into DIN of SLAVE 2, so the
data is clocked into SLAVE 2's internal shift register as the data appears on SLAVE 1's DOUT output. Just
as SLAVE 2 receives its data from SLAVE 1, the microcontroller can simultaneously send another
command to SLAVE 1. This new command overwrites the previous data in SLAVE 1's shift register. As
long as active-low CS remains low, the data propagates through the entire daisy-chain until each of the slave
devices has received its appropriate command. The command loaded into each slave's shift register executes
on the rising edge of active-low CS.
Fig 5.3.
ADVANTAGES:
•
No start and stop bits, so the data can be streamed continuously without interruption
•
No complicated slave addressing system like I2C
•
Higher data transfer rate than I2C (almost twice as fast)
•
Separate MISO and MOSI lines, so data can be sent and received at the same time
51
DISADVANTAGES:
•
Uses four wires (I2C and UARTs use two)
•
No acknowledgement that the data has been successfully received (I2C has this)
•
No form of error checking like the parity bit in UART
•
Only allows for a single master
Any communication protocol where devices share a clock signal is known as synchronous. SPI is a
synchronous communication protocol. There are also asynchronous methods that don’t use a clock signal.
For example, in UART communication, both sides are set to a pre-configured baud rate that dictates the
speed and timing of data transmission.
52
CAN
What is CAN?
o The CAN Bus is an automotive bus developed by Robert Bosch in 1986, CAN is a serial bus
protocol to connect individual systems and sensors as an alternative to conventional multi-wire
looms.
o One of the first automotive control networks developed for convenience.
o A Controller Area Network (CAN bus) is a robust vehicle bus standard designed to
allow microcontrollers and devices to communicate with each others' applications without a host
computer.
o It is a message-based protocol, designed originally for multiplex electrical wiring within automobiles
to save on copper, but can also be used in many other contexts. For each device the data in a frame is
transmitted sequentially but in such a way that if more than one device transmits at the same time the
highest priority device is able to continue while the others back off. Frames are received by all
devices, including by the transmitting device.
CONVENTIONAL SYSTEM
CAN
FIG 6.1: CAN
BRIEF:
It is a serial bus network of microcontrollers that connects devices, sensors and actuators in a system
or sub-system for real time control applications.
There is no addressing scheme used in controller area networks, as in the sense of conventional
addressing in networks (such as Ethernet).
53
Messages are broadcast to all the nodes in the network using an identifier unique to the network. Based on
the identifier, the individual nodes decide whether or not to process the message and also determine the
priority of the message in terms of competition for bus access.
FIG 6.2: CAN
This method allows for uninterrupted transmission when a collision is detected, unlike Ethernets that will
stop transmission upon collision detection. CAN network is basically CSMA/CA
CAN bus is a twisted pair with states CANH and CANL
Twisted pair, two conductors (forward and return) are twisted together for the purpose of cancelling EMI.
In a twisted pair, two conductors of a single wire are twisted together in order to carry equal and opposite
signals so the destination detects the difference between the two, which is known as differential mode
transmission.
FIG 6.3: CAN
ARCHITECTURE:
CAN is a multi-master serial bus standard for connecting Electronic Control Units (ECUs) also known as
nodes. (Automotive electronics is a major application domain.) Two or more nodes are required on the CAN
network to communicate. The complexity of the node can range from a simple I/O device up to an
54
embedded computer with a CAN interface and sophisticated software. The node may also be a gateway
allowing a general purpose computer (such as a laptop) to communicate over a USB or Ethernet port to the
devices on a CAN network.
All nodes are connected to each other through a two wire bus. The wires are a twisted pair with a 120 Ω
(nominal) characteristic impedance.
Two signals, CAN high (CANH) and CAN low (CANL) are either driven to a "dominant" state with CANH
> CANL, or not driven and pulled by passive resistors to a "recessive" state with CANH ≤ CANL. A 0 data
bit is encoded as a dominant state, while a 1 data bit is encoded as a recessive state, so a wired-AND
convention is produced, giving nodes with lower ID numbers priority on the bus.
TYPES:
ISO 11898-2:
It is also called high-speed CAN (bit speeds up to 1 Mbit/s on CAN, 5 Mbit/s on CAN-FD), uses a linear
bus terminated at each end with 120 Ω resistors.
High-speed CAN signaling drives the CANH wire towards 5 V and the CANL wire towards 0 V when any
device is transmitting a dominant (0), while if no device is transmitting a dominant, the terminating resistors
passively return the two wires to the recessive (1) state with a nominal differential voltage of 0 V.
(Receivers consider any differential voltage of less than 0.5 V to be recessive.) The dominant differential
voltage is a nominal 2 V. The dominant common mode voltage (CANH+CANL)/2 must be within 1.5 to
3.5 V of common, while the recessive common mode voltage must be within ±12 of common.
FIG 6.4: High-Speed CAN Network. ISO 11898-2
55
FIG 6.5: High-Speed CAN Signaling. ISO 11898-2
ISO 11898-3:
It is also called low-speed or fault-tolerant CAN (up to 125 Kbps), uses a linear bus, star bus or multiple star
buses connected by a linear bus and is terminated at each node by a fraction of the overall termination
resistance. The overall termination resistance should be close to, but not less than, 100 Ω.
Low-speed fault-tolerant CAN signaling operates similarly to high-speed CAN, but with larger voltage
swings. The dominant state is transmitted by driving CANH towards the device power supply voltage (5 V
or 3.3 V), and CANL towards 0 V when transmitting a dominant (0), while the termination resistors pull the
bus to a recessive state with CANH at 0 V and CANL at 5 V.
FIG 6.6: Low-Speed Fault-Tolerant CAN Network. ISO 11898-3
56
FIG 6.7: Low-Speed CAN Signaling. ISO 11898-3
CAN – LAYERS:
CAN has further sub divided into different layers,
o Object layer
o Transfer layer
o Physical layer
These two layers comprise all services and functions of data link layer in OSI model they work for:
o
o
o
Finding which messages are to be transmitted.
Decide which message received by the transfer layer are actually to be used.
Providing interface to application layer
FIG 6.8: CAN LAYER
57
FIG 6.9: CAN LAYER
PHYSICAL LAYER:
CAN is one of the most robust network technologies, especially if we are using a line-topology with very
short stubs and a twisted-pair of cable.
A twisted-pair copper cable with common ground usually realizes the physical transmission. Of course, all
connected nodes need to support the same data-rate and the same bit-timing settings.
FIG 6.10: PHYSICAL LAYER OF CAN
58
ISO 11898, at terminal node, it will be 120 ohm together, and if it is a stub node (node in between), then
terminal resistors shall be 2.6Kohm to maintain the bus impedance between 50 ohm to 60 ohm.
OBJECT AND TRANSFER LAYER:
MESSAGE FILTERING - Filtering the required data so that the other message identifiers are ignored
easily at the door step
FIFO HANDLING- Messages will be stored in FIFO in the receive order and the same will be sent to
application either in the order or based on priority.
ERROR HANDLING - There are different type of errors recorded during operation.
ACKNOWLEDGEMENT – Response to the messages received from different ECU via bus
BIT STUFFING FOR CRC - Is the insertion of non information bits into data
MESSAGE FRAMING- Transmit message framing.
CAN SIGNAL STRUCTURE:
CAN data has two states,
Recessive, CANH-CANL
0.5V
Dominant CANH-CANL
0.9V
FIG 6.11: CAN SIGNAL STRUCTURE
CAN bus is basically a differential pair, difference between CANH and CANL constitutes the voltage levels
of each state. At idle bath carry 2.5V which is recessive.
When data is transmitted, CANH goes to 3.75V and CANL drops to 1.25V, thereby generating a 2.5V
differential between the lines, which is dominant.
ARBITRATION:
The message arbitration (the process in which two or more CAN controllers agree on who is to use the bus)
is of great importance for the really available bandwidth for data transmission.
59
Any CAN controller may start a transmission when it has detected an idle bus. This may result in two or
more controllers starting a message (almost) at the same time. The conflict is resolved in the following way.
The transmitting nodes monitor the bus while they are sending. If a node detects a dominant level when it is
sending a recessive level itself, it will immediately quit the arbitration process and become a receiver
instead. The arbitration is performed over the whole Arbitration Field and when that field has been sent,
exactly one transmitter is left on the bus. This node continues the transmission as if nothing had happened.
The other potential transmitters will try to retransmit their messages when the bus becomes available next
time. No time is lost in the arbitration process.
An important condition for this bit-wise arbitration to succeed is that no two nodes may transmit the same
Arbitration Field. There is one exception to this rule: if the message contains no data, then any node may
transmit that message.
Since the bus is wired-and and a Dominant bit is logically 0, it follows that the message with the numerically
lowest Arbitration Field will win the arbitration.
The main rules of bus arbitration are:
•
•
•
•
Bit wise arbitration across the Arbitration Field
Zero Bit = Dominant Bus Level,
One Bit = Recessive Bus Level,
Dominant bit overrides recessive bit
The CAN bus level will be dominant in case any number of nodes in the network output a dominant level.
The CAN bus level will only be recessive when all nodes in the network output a recessive level. An
equivalent from some electronics basics will explain the relationship between node output and the resulting
bus level as shown in picture 6.12
FIG 6.12: CAN EXAMPLE
60
This example uses three nodes in a CAN network, in this case represented by three transistors in opencollector configuration (“Wired And”). The bus level will be at low level (dominant) in case any number of
transistors in the network output a dominant level. The bus level will only be at high level (recessive) when
all transistors in the network output a recessive level.
FIG 6.13: WIRED AND LOGIC
• Bus is considered idle, i.e. free for access, after end of the completely transmitted message followed
by the Intermission Field.
• Node that transmits message with lowest message ID, i.e. highest priority, wins the arbitration and
continues to transmit. Competing nodes switch to receiving mode (listening mode).
• Nodes that lost arbitration will start a new arbitration as soon as the bus is free for access (idle)
again. Thus CAN provides a non-destructive bus arbitration.
• Picture 6.14 demonstrates the interaction between a CAN node, trying to access the bus, and the
actual CAN bus.
61
FIG 6.14: ARBITRATION PROCESS FLOW CHART
1. The CAN node (CAN controller) waits for the end of the intermission field (refer to Chapter 4 Message Frame Architecture).
2. As soon as the bus is being detected as idle, the CAN node signals an SOF (Start of Frame) by
putting a dominant (low) level onto the bus. Every other node in the network, that did not request
bus access, will immediately switch to a receiving mode.
3. The CAN controller sends the first/next message ID bit (Message IDs can be 11 or 29 bit long, the
most significant bit – MSB will be sent first).
4. The CAN controller compares its output signal with the actual bus level (at the end of each bit
cycle).
5. The node will lose the arbitration, in case it did send a recessive level (high) and detects a dominant
(low) bus level. Consequently the node will switch into receiving mode.
6. An error condition exists when the node detects a recessive level on the bus after it did output a
dominant level. This is a clear violation of the CAN standard and the node will send an error frame
to the bus.
7. If the node has finished sending all arbitration bits (message ID plus RTR) without loosing the bus
arbitration, it will transmit the rest of the message. At this time all other CAN nodes in the network
will have switched to receiving mode.
Another example of CAN bus arbitration is shown in Fig 6.15
1. Each ECU will place the data on the bus
2. Each ECU will receive the same data back for confirmation.
3. Dominant (0) will get high priority than recessive (1).
62
4. If the ECU is not receiving the same bit back that it sends, it lost the choice and wait for another
opportunity.
5. If ECU wins in the arbitration, place the data on the bus.
6. Same will be repeated continuously
FIG 6.15: CAN ARBITRATION
CAN FEATURES:
•
•
•
•
•
•
•
•
•
Multiple masters are allowed in the BUS
Inherent priority levels for messages
Bus arbitration by message priority
Error detection and recovery at multiple levels
Synchronization of data timing across nodes with separate clock sources
Bidirectional communications across a single pair of twisted cables
Increased immunity to noise
Wide common-mode range allowing differences in ground potential between nodes
Configuration flexibility
63
CAN DATA FORMAT:
CAN data has four different frame type,
•
Data frame: Carries data from a transmitter to the receivers.
•
Remote frame: It is transmitted by the unit to request for a transmission of the data frame with the
same identifier.
•
Error frame: Transmitted by any unit on detecting the a bus error
•
Overload frame: It is to provide a additional delay between preceding and succeeding data or remote
frame.
FIG 6.16: CAN DATA FORMAT
CAN DATA AND REMOTE FRAME:
FIG 6.17: CAN DATA AND REMOTE FRAME
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It contains,
• Arbitration
-
•
•
•
•
Identifier (address of each data)
Remote Transmission Request (Requesting re transmission)
Extended Identifier
DLC (Data Length Code)
CRC field
Acknowledgement
End of frame
Eliminate data
bits, then frame
becomes
control frame
FIG 6.18: CAN CONTROL FRAME
ERROR DETECTION MECHANISMS
The CAN protocol defines no less than five different ways of detecting errors. Two of these works at the
bit level, and the other three at the message level.
1. Bit Monitoring.
2. Bit Stuffing.
3. Frame Check.
4. Acknowledgement Check.
5. Cyclic Redundancy Check.
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BIT MONITORING
Each transmitter on the CAN bus monitors (i.e. reads back) the transmitted signal level. If the bit level
actually read differs from the one transmitted, a Bit Error is signalled. (No bit error is raised during the
arbitration process.)
BIT STUFFING
When five consecutive bits of the same level have been transmitted by a node, it will add a sixth bit of
the opposite level to the outgoing bit stream. The receivers will remove this extra bit. This is done to
avoid excessive DC components on the bus, but it also gives the receivers an extra opportunity to detect
errors: if more than five consecutive bits of the same level occurs on the bus, a Stuff Error is signalled.
FRAME CHECK
Some parts of the CAN message have a fixed format, i.e. the standard defines exactly what levels must
occur and when. (Those parts are the CRC Delimiter, ACK Delimiter, End of Frame, and also the
Intermission, but there are some extra special error checking rules for that.) If a CAN controller detects
an invalid value in one of these fixed fields, a Form Error is signalled.
ACKNOWLEDGEMENT CHECK
All nodes on the bus that correctly receives a message (regardless of their being “interested” of its
contents or not) are expected to send a dominant level in the so-called Acknowledgement Slot in the
message. The transmitter will transmit a recessive level here. If the transmitter can’t detect a dominant
level in the ACK slot, an Acknowledgement Error is signalled.
CYCLIC REDUNDANCY CHECK
Each message features a 15-bit Cyclic Redundancy Checksum (CRC), and any node that detects a
different CRC in the message than what it has calculated itself will signal a CRC Error.
ERROR CONFINEMENT MECHANISMS
Every CAN controller along a bus will try to detect the errors outlined above within each message. If an
error is found, the discovering node will transmit an Error Flag, thus destroying the bus traffic. The other
nodes will detect the error caused by the Error Flag (if they haven’t already detected the original error)
and take appropriate action, i.e. discard the current message.
Each node maintains two error counters: the Transmit Error Counter and the Receive Error Counter.
There are several rules governing how these counters are incremented and/or decremented. In essence, a
transmitter detecting a fault increments its Transmit Error Counter faster than the listening nodes will
increment their Receive Error Counter. This is because there is a good chance that it is the transmitter
who is at fault!
A node starts out in Error Active mode. When any one of the two Error Counters raises above 127, the
node will enter a state known as Error Passive and when the Transmit Error Counter raises above 255,
the node will enter the Bus Off state.
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•
An Error Active node will transmit Active Error Flags when it detects errors.
•
An Error Passive node will transmit Passive Error Flags when it detects errors.
•
A node which is Bus Off will not transmit anything on the bus at all.
The rules for increasing and decreasing the error counters are somewhat complex, but the principle is
simple: transmit errors give 8 error points, and receive errors give 1 error point. Correctly transmitted
and/or
received
messages
causes
the
counter(s)
to
decrease.
Example (slightly simplified): Let’s assume that node A on a bus has a bad day. Whenever A tries to
transmit a message, it fails (for whatever reason). Each time this happens, it increases its Transmit Error
Counter by 8 and transmits an Active Error Flag. Then it will attempt to retransmit the message.. and the
same thing happens.
When the Transmit Error Counter raises above 127 (i.e. after 16 attempts), node A goes Error Passive.
The difference is that it will now transmit Passive Error Flags on the bus. A Passive Error Flag
comprises 6 recessive bits, and will not destroy other bus traffic – so the other nodes will not hear A
complaining about bus errors. However, A continues to increase its Transmit Error Counter. When it
raises above 255, node A finally gives in and goes Bus Off.
What does the other nodes think about node A? – For every active error flag that A transmitted, the other
nodes will increase their Receive Error Counters by 1. By the time that A goes Bus Off, the other nodes
will have a count in their Receive Error Counters that is well below the limit for Error Passive, i.e. 127.
This count will decrease by one for every correctly received message. However, node A will stay bus
off.
Most CAN controllers will provide status bits (and corresponding interrupts) for two states:
•
“Error Warning” – one or both error counters are above 96
•
Bus Off, as described above.
Some controllers also provide a bit for the Error Passive state. A few controllers also provide direct
access to the error counters.
The CAN controller’s habit of automatically retransmitting messages when errors have occurred can be
annoying at times. There is at least one controller on the market (the SJA1000 from Philips) that allows
for full manual control of the error handling.
BUS FAILURE MODES
The ISO 11898 standard enumerates several failure modes of the CAN bus cable:
1. CAN_H interrupted
2. CAN_L interrupted
3. CAN_H shorted to battery voltage
4. CAN_L shorted to ground
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5. CAN_H shorted to ground
6. CAN_L shorted to battery voltage
7. CAN_L shorted to CAN_H wire
8. CAN_H and CAN_L interrupted at the same location
9. Loss of connection to termination network
For failures 1-6 and 9, it is “recommended” that the bus survives with a reduced S/N ratio, and in case of
failure 8, that the resulting subsystem survives. For failure 7, it is “optional” to survive with a reduced
S/N ratio.
In practice, a CAN system using 82C250-type transceivers will not survive failures 1-7, and may or may
not survive failures 8-9.
There are “fault-tolerant” drivers, like the TJA1053, that can handle all failures though. Normally you
pay for this fault tolerance with a restricted maximum speed; for the TJA1053 it is 125 kbit/s.
ADVANTAGES
•
It allows 1Mbps data rate. CAN FD (flexible data rate) version supports more than this speed i.e.
supports 2+Mbps. CAN FD will support more bandwidth which is eight times more than
standard CAN bus.
•
It is used to reduce wiring in various automotive applications. Due to less complex interface, it is
widely used across various industries.
•
It saves overall cost and time due to less and simple wiring as well as use of flash programming.
•
Standard CAN protocol supports 8 bytes while CAN FD protocol supports 64 bytes in the data
field part.
•
Supports auto retransmission of lost messages.
•
It works in various electrical environments without any issues.
•
The protocol supports different error detection capabilities such as bit error, ack error, form error,
CRC error and stuff error.
DISADVANTAGES
•
Though maximum number of nodes are not specified for the network. It supports upto 64 nodes
due to electrical loading.
•
It supports maximum length of 40 meters.
•
It is likely to have undesirable interactions between nodes.
•
It incurs more expenditure for software development and maintenance.
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•
CAN driver must produce at least 1.5V across typical 60 Ohm.
•
Network should be wired in topology which limits stubs as much as possible.
•
In order to reduce signal integrity issues such as reflections CAN bus should be properly
terminated at both the ends with resistors.
•
Node removal requires use of termination resistors of 120 Ohm value at appropriate places on the
CAN bus.
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I2C PROTOCOL
I2C (Inter-Integrated Circuit), is multi-master, multi-slave, packet switched, single-ended, serial
computer bus, synchronous invented by Philips in 1982. It is widely used for attaching lower-speed
peripheral ICs to processors and microcontrollers in short-distance, intra-board communication.
FIG 7.1: I2C CONNECTION
The I2C is a serial bus protocol consisting of two signal lines such as SCL and SDL lines which are used to
communicate with the devices. The SCL stands for a ‘serial clock line’ and this signal is always driven by
the ‘master device’. The SDL stands for the ‘serial data line’, and this signal is driven by either the master or
the I2C peripherals. Both these SCL and SDL lines are in open-drain state when there is no transfer between
I2C peripherals.
Many slave devices are interfaced to the microcontroller with the help of the I2C bus through I2C level
shifter IC for transferring the information between them. The I2C protocol used to connect a maximum of
128 devices that are all connected to communicate with the SCL and SDL lines of the master unit as well as
the slave devices. It supports Multimaster communication, which means two masters are used to
communicate the external devices.
I2C TERMINOLOGY
- TRANSMITTER
This is the device that transmits data to the bus.
- RECEIVER
This is the device that receives data from the bus.
- MASTER
This is the device that generates clock, starts communication, sends I2C commands and stops
communication.
- SLAVE
This is the device that listens to the bus and is addressed by the master.
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- MULTI-MASTER
I2C can have more than one master and each can send commands.
- ARBITRATION
A process to determine which of the masters on the bus can use it when more masters need to
use the bus.
- SYNCHRONIZATION
A process to synchronize clocks of two or more devices.
- BUS SIGNALS
Both signals (SCL and SDA) are bidirectional. They are connected via resistors to a positive
power supply voltage. This means that when the bus is free, both lines are high. All devices on the
bus must have open-collector or open-drain pins. Activating the line means pulling it down (wired
AND). The number of the devices on a single bus is almost unlimited – the only requirement is that
the bus capacitance does not exceed 400 pF. Because logical 1 level depends on the supply voltage,
there is no standard bus voltage.
- SERIAL DATA TRANSFER
For each clock pulse one bit of data is transferred. The SDA signal can only change when the
SCL signal is low – when the clock is high the data should be stable.
FIG 7.2: SERIAL DATA TRANSFER
- START AND STOP CONDITION
Each I2C command initiated by master device starts with a START condition and ends with a STOP
condition. For both conditions SCL has to be high. A high to low transition of SDA is considered as START
and a low to high transition as STOP.
After the Start condition the bus is considered as busy and can be used by another master only after a Stop
condition is detected. After the Start condition the master can generate a repeated Start. This is equivalent to
a normal Start and is usually followed by the slave I2C address.
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Microcontrollers that have dedicated I2C hardware can easily detect bus changes and behave also as I2C
slave devices. However, if the I2C communication is implemented in software, the bus signals must be
sampled at least two times per clock cycle in order to detect necessary changes.
FIG 7.3: I2C START AND STOP CONDITION
SYNCHRONIZATION
Each master must generate its own clock signal and the data can change only when the clock is low. For
successful bus arbitration a synchronized clock is needed. Once a master pulls the clock low it stays low
until all masters put the clock into high state. Similarly, the clock is in the high state until the first master
pulls it low. This way by observing the SCL signal, master devices can synchronize their clocks.
ARBITRATION
For normal data transfer on the I2C bus only one master can be active. If for some reason two masters
initiate I2C command at the same time, the arbitration procedure determines which master wins and can
continue with the command. Arbitration is performed on the SDA signal while the SCL signal is high. Each
master checks if the SDA signal on the bus corresponds to the generated SDA signal. If the SDA signal on
the bus is low but it should be high, then this master has lost arbitration. Master I2C device that has lost
arbitration can generate SCL pulses until the byte ends and must then release the bus and go into slave
mode. The arbitration procedure can continue until all the data is transferred. This means that in multimaster system each I2C master must monitor the I2C bus for collisions and act accordingly.
CLOCK SYNCHRONIZATION AND HANDSHAKING
Slave devices that need some time to process received byte or are not ready yet to send the next byte, can
pull the clock low to signal to the master that it should wait. Once the clock is released the master can
proceed with the next byte.
I2C DATA TRANSFER
Data on the I2C bus is transferred in 8-bit packets (bytes). There is no limitation on the number of bytes,
however, each byte must be followed by an Acknowledge bit. This bit signals whether the device is ready to
proceed with the next byte. For all data bits including the Acknowledge bit, the master must generate clock
pulses. If the slave device does not acknowledges transfer this means that there is no more data or the device
is not ready for the transfer yet. The master device must either generate Stop or Repeated Start condition.
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FIG 7.4: I2C DATA TRANSFER
Each master must generate its own clock signal and the data can change only when the clock is low. For
successful bus arbitration a synchronized clock is needed. Once a master pulls the clock low it stays low
until all masters put the clock into high state. Similarly, the clock is in the high state until the first master
pulls it low. This way by observing the SCL signal, master devices can synchronize their clocks.
FIG 7.5: I2C DATA TRANSFER
I2C DATA TRANSFER RATES:
The I2C protocol operates three modes such as: fast mode, high-speed mode and standard mode wherein the
standard mode data speed ranges 0Hz to 100Hz, and the fast mode data can transfer with 0Hz to 400 KHz
speed and the high-speed mode with 10 KHz to 100KHz. The 9-bit data is sent for each transfer wherein 8bits are sent by the transmitter MSB to LSB, and the 9th bit is an acknowledgement bit sent by the receiver.
FAST MODE
In the FAST mode, the physical bus parameters are not altered. The protocol, bus levels, capacitive load etc.
remain unchanged. However, the data rate has been increased to 400 Kbit/s and a constraint has been set on
the level of noise that can be present in the system. To accomplish this task, a number of changes have been
made to the I2C bus timing.
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Since all CBUS activities have been cancelled, there is no compatibility anymore with CBUS timing. The
development of ICs with CBUS interface has long been stopped. The existing CBUS IC's are discontinued.
Furthermore, the CBUS devices cannot handle these higher clock rates.
The input of the FAST mode devices all include Schmitt triggers to suppress noise. The output buffers
include slope control for the falling edges of the SDA and SCL signals. If the power supply of a FAST mode
device is switched off, the bus pins must be floating so that they do not obstruct the bus.
The pull-up resistor must be adapted. For loads up to 200 pF, a resistor is sufficient. For loads between
200pF and 400pF, a current source (active pull-up) is preferred.
HIGH-SPEED MODE
•
•
•
•
•
•
•
•
-
The high-speed variant of the I2C bus allows communication up to 3.4 Mbit per second.
Both, master and slave device must be highspeed-enabled in order to benefit from this increase.
High-speed IC devices are downward compatible allowing for mixed bus systems.
In order to shorten signal rise time HS mode master devices have a combination of an open-drain
pull-down and current-source pull-up circuit on the SCL output.
HS IC masters can actually source current to the bus which is referred to as boosting.
This current source is enabled only (!) during HS operation and just for one master.
HS mode master devices generate a serial clock signal with a HIGH to LOW ratio of 1 to 2.
HS mode master devices can have a built-in bridge to separate lower speed devices from the bus
during HS transfer. The main purpose of such bridge is to reduce the capacitive load on the bus and
to avoid conflicts caused by low speed devices.
TRANSMISSION FORMAT
A high-speed transmission starts up in full-speed mode, i.e. at max. 400 kbit.
FIG 7.6: TRANSMISSION FORMAT IN I2C
•
•
•
•
•
•
•
•
•
•
•
•
Start condition is sent
8 bit ‘master code’ is sent at 400 kbit max
Master code is ‘not acknowledged’
Active master switches to high-speed communication
The ‘master code’ is a reserved value. 8 of them are available
Arbitration and clock synchronisation only take place during master code transmission, not during
HS transfer
The current-source circuit is enabled after the transmission of the master code
The active master sends out a repeated start condition followed by the address of the desired slave
This address is acked (positive acknowledgment) or nacked (negative acknowledgment)
Transmission continues in the known manner
The current source circuit is disabled after each repeated start condition and after each ack or nack to
give slaves a chance to stretch the clock
It is re-enabled once SCL has been released by all devices
74
•
All devices return to fast mode operation after a stop condition is sent
STANDARD MODE
Standard mode of I2C bus uses transfer rates up to 100 kbit/s and 7-bit addressing. Such I2C interface is
used by many hundred I2C-compatible devices from many manufacturers since its introduction in the 80s.
I2C COMMUNICATION
The I2C bus protocol is most commonly used in master and slave communication wherein the master is
called “microcontroller”, and the slave is called other devices such as ADC, EEPROM, DAC and similar
devices in the embedded system. The number of slave devices is connected to the master device with the
help of the I2C bus, wherein each slave consists of a unique address to communicate it. The following steps
are used to communicate the master device to the slave:
Step1: First, the master device issues a start condition to inform all the slave devices so that they listen on
the serial data line.
Step2: The master device sends the address of the target slave device which is compared with all the slave
devices’ addresses as connected to the SCL and SDL lines. If anyone address matches, that device is
selected, and the remaining all devices are disconnected from the SCL and SDL lines.
Step3: The slave device with a matched address received from the master, responds with an
acknowledgement to the master thereafter communication is established between both the master and slave
devices on the data bus.
Step4: Both the master and slave receive and transmit the data depending on whether the communication is
read or write.
Step5: Then, the master can transmit 8-bit of data to the receiver which replies with a 1-bit
acknowledgement.
I2C MESSSAGE FORMAT:
FIG 7.7: I2C MESSAGE FORMAT
With I2C, data is transferred in messages. Messages are broken up into frames of data. Each message has an
address frame that contains the binary address of the slave, and one or more data frames that contain the data
75
being transmitted. The message also includes start and stop conditions, read/write bits, and ACK/NACK bits
between each data frame
The address frame is always the first frame after the start bit in a new message. The master sends the address
of the slave it wants to communicate with to every slave connected to it. Each slave then compares the
address sent from the master to its own address. If the address matches, it sends a low voltage ACK bit back
to the master. If the address doesn’t match, the slave does nothing and the SDA line remains high.
COMMUNICATION WITH 7-BIT I2C ADDRESSES
FIG 7.8: 7 BIT I2C COMMUNICATION
Each slave device on the bus should have a unique 7-bit address. The communication starts with the Start
condition, followed by the 7-bit slave address and the data direction bit. If this bit is 0 then the master will
write to the slave device. Otherwise, if the data direction bit is 1, the master will read from slave device.
After the slave address and the data direction is sent, the master can continue with reading or writing. The
communication is ended with the Stop condition which also signals that the I2C bus is free. If the master
needs to communicate with other slaves it can generate a repeated start with another slave address without
generation Stop condition. All the bytes are transferred with the MSB bit shifted first.
If the master only writes to the slave device then the data transfer direction is not changed.
FIG 7.9: 7 BIT I2C COMMUNICATION
If the master only needs to read from the slave device then it simply sends the I2C address with the R/W bit
set to read. After this the master device starts reading the data.
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FIG 7.10: 7 BIT I2C COMMUNICATION
Sometimes the master needs to write some data and then read from the slave device. In such cases it must
first write to the slave device, change the data transfer direction and then read the device. This means
sending the I2C address with the R/W bit set to write and then sending some additional data like register
address. After writing is finished the master device generates repeated start condition and sends the I2C
address with the R/W bit set to read. After this the data transfer direction is changed and the master device
starts reading the data.
FIG 7.11: 7 BIT I2C COMMUNICATION
7-BIT I2C ADDRESSING
A slave address may contain a fixed and a programmable part. Some slave devices have few bits of the I2C
address dependent on the level of address pins. This way it is possible to have on the same I2C bus more
than one I2C device with the same fixed part of I2C address.
FIG 7.12: 7 BIT I2C ADDRESSING
The allocation of I2C addresses is administered by the I2C bus committee which takes care for the
allocations. Two groups of 8 I2C addresses are reserved for future uses and one address is used for 10-bit
I2C addressing.
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FIG 7.13: 7 BIT I2C ADDRESSING
The general call address is used to address all devices on the slave bus. If any slave device doesn’t need to
respond to such call or general call is not supported by the slave device, the call must be ignored. If the
device supports general call and wants to receive the data it must acknowledge the address and read the data
as a slave receiver.
START BYTE
If microcontroller has I2C hardware and the microcontroller acts as a slave then the software needs to do
nothing to check the bus state. The I2C hardware will detect Start condition, receive the I2C address and
interrupt the software if necessary. However, if the I2C interface is implemented by the software, the
microcontroller has to sample SDA line at least twice per clock pulse in order to detect changes. To simplify
detection of I2C commands on the bus in such cases, a special I2C address called Start byte is used. Such
start byte (0000 0001) is followed by an acknowledge pulse (for interface compatibility reasons). This
combination holds the SDA line low for 7 clock pulses and allows simple detection of active I2C bus with
lower sampling frequency.
FIG 7.14: I2C START BYTE
EXTENSION OF THE I2C SPECIFICATIONS
Standard mode of I2C bus uses transfer rates up to 100 kbit/s and 7-bit addressing. Such I2C interface is
used by many hundred I2C-compatible devices from many manufacturers since its introduction in the 80s.
However, with the advance of the technology, needs for higher transfer rates and larger address space
emerged. There are cases where large amount of data needs to be transferred. Many complex embedded
boards contain a large number of different I2C devices. In some cases it is very hard to avoid address
collisions since 7 bits for I2C addresses allow only 127 different addresses where only 112 can actually be
78
used. Some I2C devices on the board, despite address pins, have the same address. This resulted in few
upgrades to the standard-mode I2C specifications:
Fast Mode – supports transfer rates up to 400 kbit/s
• High-speed mode (Hs-mode) – supports transfer rates up to 3.4 Mbit/s
• 10-bit addressing – supports up to 1024 I2C addresses
There can by any combination of the devices on the bus regardless of the supported speed and addressing.
Fast mode devices are downward-compatible and can work with slower I2C controllers. However, most
modern I2C controllers support all speeds and addressing modes.
•
High-speed mode uses signals called SCLH and SDAH to emphasize the higher speed. These signals are
usually separated from standard SDA and SCL lines. High-speed mode introduces also few differences (or
improvements) in the specifications:
•
•
•
•
Improved data and clock line output drivers
Schmitt trigger and spike suppression circuits on data and clock inputs
Clock synchronization and arbitration is not used
Clock signal has 1 to 2 high/low ratio
10-BIT I2C ADDRESSING
10-bit addressing can be used together with 7-bit addressing since a special 7-bit address (1111 0XX) is used
to signal 10-bit I2C address. When a master wants to address a slave device using 10-bit addressing, it
generates a start condition, then it sends 5 bits signaling 10-bit addressing (1111 0), followed by the first two
bits of the I2C address and then the standard read/write bit.
FIG 7.15: I2C 10 BIT ADDRESSING
If the master will write data to the slave device it must send the remaining 8 bits of slave address as the
second byte.
If the master will read data from the slave device it must send the complete 10-bit address (two bytes) as for
writing, then a repeated start is sent followed by the first address byte with read/write bit set to high to signal
reading. After this procedure the data can be read from the slave device.
FIG 7.16: I2C 10 BIT ADDRESSING
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USING I2C TO CONTROL 7 SEGMENT DISPLAY
PCF8574 Remote 8-Bit I/O Expander for I2C Bus:
This 8-bit input/output (I/O) expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 6-V
VCC operation. The PCF8574 device provides general-purpose remote I/O expansion for most
microcontroller families by way of the I2C interface [serial clock (SCL), serial data (SDA)]. The device
features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high current drive
capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without
the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source
to VCC is active.
FIG 7.17: PCF8574 BLOCK DIAGRAM
INTERFACE SERIAL EEPROM 24LC512 TO LPC2148 MICROCHIP:
•
•
•
•
•
LPC2148 supports two fast I2C-buses (I2C0 & I2C1).
I2C bus interface that may be configured as Master, Slave or Master/Slave.
Supports programmable clock to allow adjustment of multiple data speed: standard (100 kbps), fast
(400 kbps) and high speed (3.4 Mbps).
Supports bi-directional data transfer between master and slave.
I2C protocol is useful where many devices connected on the bus. This helps to reduce the cost and
complexity of circuit as more devices allowed to communicate through same bus.
80
•
The I2C bus may be used for test and diagnostic purposes.
I2C REGISTER MAP:
FIG 7.18: I2C REGISTER MAP
TIMING DIAGRAM:
FIG 7.19: TRANSMISSION FORMAT IN I2C
1. Data transfer is initiated with a start bit signalled by SDA being pulled low while SCL stays high.
2. SCL is pulled low, and SDA sets the first data bit level while keeping SCL low.
3. The data are sampled (received) when SCL rises for the first bit . For a bit to be valid, SDA must not
change between a rising edge of SCL and the subsequent falling edge.
4. This process repeats, SDA transitioning while SCL is low, and the data being read while SCL is high
81
5. The final bit is followed by a clock pulse, during which SDA is pulled low in preparation for
the stop bit.
6. A stop bit is signalled when SCL rises, followed by SDA rising.
PROCEDURE:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interfacing seven segment display with I2C and LPC2148 can be implemented using keil IDE. The
following are steps involved in interfacing:
To create a new project, select Project New project and enter the project name.
To select the device, right click on the Target and select LPC2148 from the list of devices under
devices tab.
In output tab, click the ‘create hex file’ option and in linker tab select the target memory.
Click OK to add the startup files.
Click File-New to create a new file which opens an empty editor window where source code is
entered. Save the file with appropriate extension.
In the project workspace, right click source group and select ‘add existing file to source group’ and
add the previously created file to the project.
Select Project-Build Target. Any errors present will be displayed on the output window. Once the
errors are rectified, target will be built.
Select Debug-Start/stop debug to compile the program. Run the program from which the output can
be viewed in the ports and registers.
For programming the controller, Flash magic is used. Select the device from drop down list.
Set the baud rate and COM port and specific clock frequency.
Check the erase blocks used by firmware check box.
Select the hex file of the project using the browse button. Click Start.
The status of programming will be displayed in the bottom right corner.
Turn on the LPC2148 kit and press the reset button. Once the program is loaded into the
microcontroller, the output can be observed in the seven segment displays.
PROGRAM:
#include<lpc214x.h>
#include<stdio.h>
#define DESIRED_BAUDRATE 19200
#define CRYSTAL_FREQUENCY_IN_HZ 12000000
#define PCLK CRYSTAL_FREQUENCY_IN_HZ
// since VPBDIV=0x01
#define DIVISOR (PCLK/(16*DESIRED_BAUDRATE))
int i,temp,Temp1,addr;
unsigned char i2c_data[] = {0x00,0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67};
static void delay(void )
{
volatile inti,j;
for (i=0;i<55;i++)
for (j=0;j<550;j++);
}
static void delay1(void )
{
volatile inti,j;
for (i=0;i<1100;i++)
for (j=0;j<1500;j++);
}
void i2c_write(char a,char add)
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{
//START CONDITION
I2C0CONSET=0x60; //0x60 change
flag.
delay();
delay();
temp=I2C0STAT;
while(temp!=0x08)
temp=I2C0STAT;
//SLAVE ADDRESS
I2C0DAT=add;
I2C0CONCLR=0x28;
temp=I2C0STAT;
delay();
while(temp!=0x18)
{
temp=I2C0STAT;
delay();
}
//Data Write
I2C0DAT=a;
I2C0CONCLR=0x08;
temp=I2C0STAT;
while(temp!=0x28)
{
temp=I2C0STAT;//& 0x28;
delay();
}
//STOP CONDITION
I2C0CONSET=0x10;
I2C0CONCLR=0x8;
delay1();
}
void main()
{
int ii;
PINSEL0=0x00000055 ;
VPBDIV=0x01 ;
I2C0CONCLR=0x6C; //clear I2C0CONCLR register
I2C0CONSET=0x40; //Enable I2C.
I2C0SCLH=110;
I2C0SCLL=90;
while(1)
{
for(ii=0;ii<=10;ii++)
i2c_write(i2c_data[ii],0x70);
for(ii=0;ii<=10;ii++)
i2c_write(i2c_data[ii],0x72);
for(ii=0;ii<=10;ii++)
i2c_write(i2c_data[ii],0x74);
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//start I2C data transmission when set STA
for(ii=0;ii<=10;ii++)
i2c_write(i2c_data[ii],0x76);
for(ii=0;ii<=10;ii++)
i2c_write(i2c_data[ii],0x78);
for(ii=0;ii<=10;ii++)
i2c_write(i2c_data[ii],0x7A);
}
}
OUTPUT:
The first seven segment display in the LPC2148 microcontroller display the digits 0-9 and turns off. Then
the second seven segment display displays the digits 0-9. Likewise, the four seven segment displays in the
kit display the digits 0-9 one after the other.
ADVANTAGES:
•
•
•
•
Maintains low pin/signal count even with numerous devices on the bus
Adapts to the needs of different slave devices
Readily supports multiple masters
Incorporates ack/nack functionality for improved error handling
DISADVANTAGES:
•
•
•
Increases the complexity of firmware or low-level hardware
Imposes protocol overhead that reduces throughput
Requires pull-up resistors, which:
• Limit clock speed
• Consume valuable pcb real estate in extremely space-constrained systems
• Increase power dissipation
84
ETHERNET
Ethernet is a way of connecting computers together in a local area network or LAN. It has been the most
widely used method of linking computers together in LANs since the 1990s. The basic idea of its design is
that multiple computers have access to it and can send data at any time.
Robert Metcalfe invented Ethernet technology. Ethernet was originally standardized as IEEE 802.3 with a
data transmission rate of 10 Mb/s
FIG 8.1: ETHERNET CABLE
IS ETHERNET A PROTOCOL?
Ethernet is a link layer protocol in the TCP/IP stack, describing how networked devices can format data for
transmission to other network devices on the same network segment, and how to put that data out on the
network connection.
EVOLUTION:
Ethernet has evolved to include higher bandwidth, improved medium access control methods, and different
physical media. The coaxial cable was replaced with point-to-point links connected by Ethernet
repeaters or switches. Ethernet stations communicate by sending each other data packets: blocks of data
individually sent and delivered. As with other IEEE 802 LANs, adapters come programmed with globally
unique 48-bit MAC address so that each Ethernet station has a unique address. The MAC addresses are used
to specify both the destination and the source of each data packet. Ethernet establishes link-level
connections, which can be defined using both the destination and source addresses. On reception of a
transmission, the receiver uses the destination address to determine whether the transmission is relevant to
the station or should be ignored. A network interface normally does not accept packets addressed to other
Ethernet stations.
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An EtherType field in each frame is used by the operating system on the receiving station to select the
appropriate protocol module (e.g., an Internet Protocol version such as IPv4). Ethernet frames are said to
be self-identifying, because of the EtherType field. Self-identifying frames make it possible to intermix
multiple protocols on the same physical network and allow a single computer to use multiple protocols
together. Despite the evolution of Ethernet technology, all generations of Ethernet (excluding early
experimental versions) use the same frame formats. Mixed-speed networks can be built using Ethernet
switches and repeaters supporting the desired Ethernet variants.
Due to the ubiquity of Ethernet, the ever-decreasing cost of the hardware needed to support it, and the
reduced panel space needed by twisted pair Ethernet, most manufacturers now build Ethernet interfaces
directly into PC motherboards, eliminating the need for installation of a separate network card.
SHARED MEDIA:
Original Ethernet's shared coaxial cable (the shared medium) traversed a building or campus to every
attached machine. A scheme known as carrier sense multiple access with collision detection (CSMA/CD)
governed the way the computers shared the channel. This scheme was simpler than competing Token Ring
or Token Bus technologies. Computers are connected to an Attachment Unit Interface (AUI) transceiver,
which is in turn connected to the cable (with thin Ethernet the transceiver is integrated into the network
adapter). While a simple passive wire is highly reliable for small networks, it is not reliable for large
extended networks, where damage to the wire in a single place, or a single bad connector, can make the
whole Ethernet segment unusable. Through the first half of the 1980s, Ethernet's 10BASE5 implementation
used a coaxial cable 0.375 inches (9.5 mm) in diameter, later called "thick Ethernet" or "thicknet". Its
successor, 10BASE2, called "thin Ethernet" or "thinnet", used the RG-58 coaxial cable. The emphasis was
on making installation of the cable easier and less costly.
Since all communication happens on the same wire, any information sent by one computer is received by all,
even if that information is intended for just one destination.The network interface card interrupts the
CPU only when applicable packets are received: the card ignores information not addressed to it. Use of a
single cable also means that the data bandwidth is shared, such that, for example, available data bandwidth
to each device is halved when two stations are simultaneously active.
A collision happens when two stations attempt to transmit at the same time. They corrupt transmitted data
and require stations to re-transmit. The lost data and re-transmission reduces throughput. In the worst case,
where multiple active hosts connected with maximum allowed cable length attempt to transmit many short
frames, excessive collisions can reduce throughput dramatically. However, a Xerox report in 1980 studied
performance of an existing Ethernet installation under both normal and artificially generated heavy load.
The report claimed that 98% throughput on the LAN was observed. This is in contrast with token
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passing LANs (Token Ring, Token Bus), all of which suffer throughput degradation as each new node
comes into the LAN, due to token waits. This report was controversial, as modeling showed that collisionbased networks theoretically became unstable under loads as low as 37% of nominal capacity. Many early
researchers failed to understand these results. Performance on real networks is significantly better.
In a modern Ethernet, the stations do not all share one channel through a shared cable or a simple repeater
hub; instead, each station communicates with a switch, which in turn forwards that traffic to the destination
station. In this topology, collisions are only possible if station and switch attempt to communicate with each
other at the same time, and collisions are limited to this link. Furthermore, the 10BASE-T standard
introduced a full duplex mode of operation which became common with Fast Ethernet and the de facto
standard with Gigabit Ethernet. In full duplex, switch and station can send and receive simultaneously, and
therefore modern Ethernets are completely collision-free.
ETHERNET FRAME FORMAT:
FIG 8.2 ETHERNET FRAME FORMAT
WIRED ETHERNET NETWORK:
The Ethernet technology mainly works with the fiber optic cables that connect devices within a distance of
10 km. The Ethernet supports 10 Mbps. A computer network interface card (NIC) is installed in each
computer, and is assigned to a unique address. An Ethernet cable runs from each NIC to the central switch
or hub. The switch and hub act as a relay though they have significant differences in the manner in which
they handle network traffic – receiving and directing packets of data across the LAN. Thus, Ethernet
networking creates a communications system that allows sharing of data and resources including printers,
fax machines and scanners.
87
FIG 8.3 WIRED ETHERNET COMMUNICATION
WIRELESS ETHERNET:
FIG 8.4 WIRELESS ETHERNET COMMUNICATION.
Ethernet networks can also be wireless. Rather than using Ethernet cable to connect the computers, wireless
NICs use radio waves for two-way communication with a wireless switch or hub. It consists of Ethernet
ports, wireless NICs, switches and hubs. Wireless network technology can be more flexible to use, but also
require extra care in configuring security.
88
TYPES OF ETHERNET NETWORKS:
There are several types of Ethernet networks, such as Fast Ethernet, Gigabit Ethernet, and Switch Ethernet.
A network is a group of two or more computer systems connected together.
1. Fast Ethernet:
The fast Ethernet is a type of Ethernet network that can transfer data at a rate of 100 Mbps using a twistedpair cable or a fiber-optic cable. The older 10 Mbps Ethernet is still used, but such networks do not provide
necessary bandwidth for some network-based video applications. Fast Ethernet is based on the proven
CSMA/CD Media Access Control (MAC) protocol, and uses existing 10BaseT cabling. Data can move from
10 Mbps to 100 Mbps without any protocol translation or changes to the application and networking
software.
FIG 8.5 TWISTED PAIR CABLE
2. Gigabit Ethernet:
The Gigabit Ethernet is a type of Ethernet network capable of transferring data at a rate of 1000 Mbps
based on a twisted-pair or fiber optic cable, and it is very popular. The type of twisted-pair cables that
support Gigabit Ethernet is Cat 5e cable, where all the four pairs of twisted wires of the cable are used to
achieve high data transfer rates. The 10 Gigabit Ethernet is a latest generation Ethernet capable of
transferring data at a rate of 10 Gbps using twisted-pair or fiber optic cable.
FIG 8.6 OPTICAL FIBRE CABLE
89
3. SWITCH ETHERNET
Multiple network devices in a LAN require network equipment such as a network switch or hub. When
using a network switch, a regular network cable is used instead of a crossover cable. The crossover cable
consists of a transmission pair at one end and a receiving pair at the other end.
The main function of a network switch is to forward data from one device to another device on the same
network. Thus a network switch performs this task efficiently as the data is transferred from one device to
another without affecting other devices on the same network.
FIG 8.7 SWITCH ETHERNET
The network switch normally supports different data transfer rates. The most common data transfer rates
include 10 Mbps – 100 Mbps for fast Ethernet, and 1000 Mbps – 10 Gbps for the latest Ethernet.
Switch Ethernet uses star topology, which is organized around a switch. The switch in a network uses a
filtering and switching mechanism similar to the one used by the gateways, in which these techniques have
been in use for a long time.
4. 10 GIGABIT ETHERNET:
10 Gigabit Ethernet is the fastest and most recent of the Ethernet standards. IEEE 802.3ae defines a version
of Ethernet with a nominal rate of 10Gbits/s that makes it 10 times faster than Gigabit Ethernet.
Unlike other Ethernet systems, 10 Gigabit Ethernet is based entirely on the use of optical fiber connections.
This developing standard is moving away from a LAN design that broadcasts to all nodes, toward a system
which includes some elements of wide area routing. As it is still very new, which of the standards will gain
commercial acceptance has yet to be determined.
ALTERNATE TECHNOLOGIES OF ETHERNET:
The Ethernet supports different types of networks or topologies such a bus topology, ring topology, star
topology, tree topology, and so on. These topologies can be used for transferring and receiving data using
different types of cables like coax, twisted pair, fiber optic, etc.
90
Alternate technologies of Ethernet include the “Token Ring” protocol designed by IBM, and the robust
Asynchronous Transfer Mode (ATM) technology. ATM allows devices to be connected over very long
distances to create WANs (Wide Area Networks) that behave like LANs. However, for an inexpensive
network located in a single building, Ethernet is a well-established standard with a solid record, boasting
over three decades of providing reliable networking environments.
DIFFERENT TYPES OF ETHERNET CABLES:
Different variants of Ethernet technologies are designated according to the type and diameter of the cables
used as given below:
⚫
10Base2: The cable used is a thin coaxial cable: thin Ethernet.
⚫
10Base5: The cable used is a thick coaxial cable: thick Ethernet.
⚫
10Base-T: The cable used is a twisted-pair (T means twisted pair) and the speed achieved is around 10
Mbps.
⚫
100Base-FX: Makes it possible to achieve a speed of 100 Mbps by using multimode fiber optic (F
stands for Fiber).
⚫
100Base-TX: Similar to 10Base-T, but with a speed 10 times greater (100 Mbps).
⚫
1000Base-T: Uses a double-twisted pair of category 5 cables and allows a speed up to one Gigabit per
second.
⚫
1000Base-SX: Based on multimode fiber optic uses a short wavelength signal (S stands for short) of
850 nanometers (770 to 860 nm).
⚫
1000Base-LX: Based on multimode fiber optic uses a long wavelength signal (L stands for long) of
1350 nm (1270 to 1355 nm). Ethernet is a widely used network technology because the cost of such a
network is not very high.
CATEGORIES FOR ETHERNET CABLES:
A variety of different cables are available for Ethernet and other telecommunications and networking
applications. These network cables that are described by their different categories, e.g. Cat 5 cables, Cat-6
cables, etc., which are often recognized by the TIA (telecommunications Industries Association) and they
are summarized below:
⚫
Cat-1: This is not recognized by the TIA/EIA. It is the form of wiring that is used for standard telephone
(POTS) wiring, or for ISDN.
⚫
Cat-2: This is not recognized by the TIA/EIA. It was the form of wiring that was used for 4Mbit/s token
ring networks.
91
⚫
Cat-3: This cable is defined in TIA/EIA-568-B. It is used for data networks employing frequencies up to
16 MHz. It was popular for use with 10 Mbps Ethernet networks (100Base-T), but has now been
superseded by Cat-5 cable.
⚫
Cat-4: This cable is not recognized by the TIA/EIA. However it can be used for networks carrying
frequencies up to 20 MHz. It was often used on 16Mbps token ring networks.
⚫
Cat-5: This is not recognized by the TIA/EIA. This is the network cable that is widely used for 100BaseT and 1000Base-T networks as it provides performance to allow data at 100 Mbps and slightly more (125
MHz for 1000Base-T) Ethernet. The Cat 5 cable superseded the Cat 3 version and for a number of years
it became the standard for Ethernet cabling. Cat 5 cable is now obsolete and therefore it is not
recommended for new installations. Cat 5 cable uses twisted pairs to prevent internal crosstalk, XT and
also crosstalk to external wires, AXT. Though not standardized, the Cat 5 cable normally uses 1.5 - 2
twists per centimeter.
⚫
Cat-5e: This form of cable is recognised by the TIA/EIA and is defined in TIA/EIA-568, being last
revised in 2001. It has a slightly higher frequency specification that Cat-5 cable as the performance
extends up to 125 Mbps.Cat-5e can be used for 100Base-T and 1000Base-t (Gigabit Ethernet). Cat 5e
standard for Cat 5 enhanced and it is a form of Cat 5 cable manufactured to higher specifications
although physically the same as Cat 5. It is tested to a higher specification to ensure it can perform at the
higher data speeds. The twisted pairs within the network cables tend to have the same level of twisting as
the Cat 5 cables.
⚫
Cat-6: This cable is defined in TIA/EIA-568-B provides a significant improvement in performance over
Cat5 and Cat 5e. During manufacture Cat 6 cables are more tightly wound than either Cat 5 or Cat 5e and
they often have an outer foil or braided shielding. The shielding protects the twisted pairs of wires inside
the Ethernet cable, helping to prevent crosstalk and noise interference. Cat-6 cables can technically
support speeds up to 10 Gbps, but can only do so for up to 55 metres - even so this makes them relatively
long Ethernet cables. The Cat 6 Ethernet cables generally have 2+ twists per cm and some may include a
nylon spline to reduce crosstalk, although this is not actually required by the standard.
⚫
Cat-6a: The “a” in Cat 6a stands for “Augmented” and the standard was revised in 2008. The Cat 6a
cables are able to support twice the maximum bandwidth, and are capable of maintaining higher
transmission speeds over longer network cable lengths. Cat 6a cables utilise shielded which is sufficient
to all but eliminate crosstalk. However this makes them less flexible than Cat 6 cable.
⚫
Cat-7: This is an informal number for ISO/IEC 11801 Class F cabling. It comprises four individually
shielded pairs inside an overall shield. It is aimed at applications where transmission of frequencies up to
600 Mbps is required.
⚫
Cat-8: These cables are still in development, but will be released in the foreseeable future to provide
further improvements in speed and general performance.
92
TABLE 8.1 CATEGORIES OF ETHERNET CABLES
TOP FEATURES OF ETHERNET CONTROLLER:
• Includes 1st round “hop” to a Tier 1 provider
• Provides wholesale pricing for all types of businesses
• Connects directly to the carrier’s backbone
• Offers Service Level Agreements with every connection
• Provides low-cost bandwidth
• Provides higher rates of data transfer
• Offers ‘Plug and Play’ provisioning
ADVANTAGES OF ETHERNET:
• To form an Ethernet, we do not need much cost. It is relatively inexpensive. It is costless as compare
to other systems of connecting computers.
• In Ethernet, all the node have the same privileges. It does not follow client-server architecture.
• It does not require any switches or hubs
• Maintenance and administration are simple.
• The cable used to connect systems in ethernet is robust to noise.
• As it is robust to the noise, the quality of the data transfer does not degrade. The data transfer quality
is good.
• With a Gigabit network, users can transfer data with the speed of 1-100Gbps.
DISADVANTAGES OF ETHERNET:
93
• It offers a nondeterministic service.
• It does not hold good for real-time applications as it requires deterministic service.
• As the network cannot set priority for the packets, it is not suitable for a client-server architecture.
• In an interactive application, data is very small and need quick data transfer. In ethernet, there is a
limit of the minimum size of the frame to 46B. The result of that, it is not a good choice for
interactive applications.
• If you are using it for interactive applications, you have to feed dummy data to make the frame size
46B which is mandatory.
• Not suitable for traffic-intensive applications. If the traffic on the Ethernet increases, the efficiency
of the Ethernet goes down.
• It provides connectionless communication over the network.
• After receiving a packet, the receiver doesn’t send any acknowledge.
• If there is any problem in ethernet, it is difficult to troubleshoot what cable or node in the network
causing an actual problem.
94
REFERENCES
1) http://mathworld.wolfram.com/Topology.html
2) http://www.circuitbasics.com/basics-uart-communication/
3) https://searchnetworking.techtarget.com/definition/Ethernet
4) https://www.techopedia.com/definition/2320/universal-serial-bus-usb
5) https://techterms.com/definition/p2p
6) https://study.com/academy/lesson/modes-of-communication.html
7) https://www.setra.com/blog/what-is-baud-rate-and-what-cable-length-is-required-1
8) http://www.circuitbasics.com/basics-of-the-i2c-communication-protocol/
9) https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi/all
10) https://www.elprocus.com/what-is-a-communication-system-and-its-basic-elements/
11) https://www.geeksforgeeks.org/transmission-modes-computer-networks/
12) https://www.comparitech.com/net-admin/network-topologies-advantages-disadvantages/
13) https://www.elprocus.com/common-mode-rejection-ratio-cmrr-operational-amplifier/
14) https://www.electronics-notes.com/articles/connectivity/usb-universal-serial-bus/basics-tutorial.php
15) https://www.beyondlogic.org/usbnutshell/usb1.shtml
16) http://www.usbmadesimple.co.uk/ums_6.html
17) https://www.electronicshub.org/basics-serial-peripheral-interface-spi/
18) https://i2c.info/i2c-bus-specification
19) http://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2cbus/general-introduction/enhanced-i2c-fast-mode.html
20) http://ww1.microchip.com/downloads/en/AppNotes/I2C-Master-Mode-30003191A.pdf
21) https://www.mikroe.com/ebooks/programming-dspic-microcontrollers-in-pascal/operating-modesof-i2c-module
22) http://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2cbus/general-introduction/high-speed-i2c-hs-mode.html
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