New Approach For Full Chip
Electrical Reliability
Verification
Frank Feng
Circuit Verification Methodologist
Calibre D2S
May, 2017
Use Static Rule to Regulate Dynamic Behavior :

We live in a dynamic world/society, but we intend to make our
lives rich/smooth/safe by rule regulations

Silicon chip is operated under a dynamic environment, but we
intend to make our chip working as designed with good reliability
by rule checking

The rule checking is a static approach, however, it is a real
practical way to verify full chip design reliability, especially for
design in advanced technology (28 nm, 16 nm, 10 nm, 7 nm, etc.)
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Status of Chip Design Reliability Verification :
Consider Methodology, Tool, and Foundry Support
Reliability Design
Issue
ESD
Chip
Dynamic

Latch-up
EOS

TDDB
Cell/Transistor
Cell/Transistor
Static
Dynamic
?


?


?


?


Analog Logic Driven
Layout Design
Static

?
IR Drop


EM




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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Manual Check, Marker, or Using Less Accurate
Design Data are General ESD/Latch-up Design Practices, but they are un-reliable
Manual placed marker layer is not a desired
method
It is interconnect resistance along ESD path
wanted by designer
IO Cell
Power Cell
VDD
Input
Pad
Core Circuit
VSS
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
IO Cell
Comprehensive ESD Design Verification Can be
Achieved by Calibre PERC in Automation :
Power Pads
ESD Path
Resistance
Power
Clamping
Circuit
IO ESD
Circuit
DVDD
AVDD
Core Circuit
IO PAD
CDM ESD
Circuit
ESD Path
Current
Density
P2P Effective
Resistance
DVSS
AVSS
Ground Pads
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Comprehensive Latch-up Design Verification Can
be Achieved by Calibre PERC in Automation :
Spacing <= #um
N+ STRAP
R<#ohm
P+ STRAP
N+ OD
required
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
P+ OD
R<#ohm
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Comparison Between Automatic And Manual ESD
Design Verification Methodology :
Items
Calibre PERC
Marker Layer
Eye Ball
Rules Coverage
over 90%
under 30%
under 10%
False Error
no
many
always
Tool Integration
topology, LVS, DRC, Rextraction
DRC +
manual
marker
manual
examining
Tool Quality
sign-off level
dependence
no quality
Programmable
fully
partially
never
Run Time
~ hours
hours ~ days
~ days
Human Error
never
sometimes
always
User Usage
automatically
semi-auto
manually
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Logic Driven Layout Check Flow :
PERC LDL P2P/CD
PERC LDL DRC
Layout GDS/OASIS
Layout GDS/OASIS
Layout
Netlist Extraction
Layout
Netlist Extraction
Topology
Pin Pairs Selection
Topology Devices /
Nets Selection
Probe Points
Generation
+
R Extraction
Generate
Selected Devices / Nets
Geometrical Shapes
Static Simulation
↓
Generate Result DFMDB
Execute DRC Operations
↓
Generate Result DFMDB
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Netlist Traverse Integrates Layout DRC, LVS, PEX,
and Spice Simulation to Provide Functions of :

Programmable Topological Checking, Pattern Recognition,
and Voltage Propagation

Logical Driven Layout P2P Effective Resistance Check

Logical Drive Layout Current Density Check

Logical Driven Layout DRC Check
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Topology Checking for Verification of IO/PG ESD
Protection Scheme :
Power Pads
IO ESD Circuit
Power Pads
Core
Circuit
Trigger
CKT
IO PAD
Ground Pads
10
Power
Clamp
HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Ground Pads
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Topology Checking for Verification of Cross Power
Domain CDM Protection Scheme :
VDD1
VDD2
Core Circuit 1
Core Circuit 2
Power
Clamp
Power
Clamp
VSS2
VSS1
VSS (Common Ground)
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
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PERC-LDL P2P :
For Verification of Reff Along ESD Paths and Across Different Voltage Domains to Ensure ESD Paths
will Provide Protection as Designed
Power Pads
VDD1
IO PAD
Core
Circuit
VDD2
Core
Circuit 1
Core
Circuit 2
VSS1
Ground Pads
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
VSS2
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Calibre PERC Catches Violations Matched With
Real Silicon Failures :
Over Threshold Current Density Burn Weak
Interconnect Area
No CDM Protection On Cross Power Domain
Net, Receiver Gate Is Damaged
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Real User Comment for Calibre PERC :
Automatic, Efficient, and Accurate
Items
Eye Ball
Calibre PERC
Rules Coverage
under 10%
over 90%
0.3 hour execution
+ 1.5 hour layout extraction
+ 1.5 hour current density check
+ 2.5 hour P2P resistance check
Time Consumed
3 man day
(24 hours)
Tool Integration
Manual Examination
Topology, LVS, DRC, P2P, CD
Repetition
Effort doubled
Small overhead
Human Error
Prone
immune
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
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Calibre PERC is Qualified by TSMC for
Un-Checkable ESD/LATCH-UP Rules in DRM :
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Run Summary of ESD Path Reff Measurements For
a N10 Design ~ 1 cm^2 / Multi-Billion Devices
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Perform Electrical Over Stress Checking without
Dynamic Simulation by Calibre PERC Voltage Propagation

EOS has caused integrated circuit failures, regardless of the semiconductor manufacturer

The result of an EOS event can range from degradation to the IC up to catastrophic damage where the IC is
permanently non-functional
Identify
design
3.6
1.8
1.8
Label
voltages
Propagate
voltages
Catch static
violations
0
Debug
using RVE
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
An Useful Static Voltage Propagation to Handle General MultiPower Domains Chip Needs :
A Methodology to Assist Voltage Shift
VCC_3P3
VCORE_2P5
Nch_thinOx
VOUT_2P5
Net-A
VCORE_1P8
Nch_thinOx
VOUT_1P8
LOGICS
Net-B
Core
Net-D
Net-C
VCORE_1P2
VCORE_1P2
Power Management
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Nch_thinOx
A Few Techniques Are Used To Shift Voltage in
Propagating Voltage into Internal Circuitry :

User provides specific nets to assist voltage shift

User provides specific cells or cell placements to assist voltage shift

User provides specific circuit patterns to assist voltage shift
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Voltage Dependent DRC is a Feasible Verification Methodology for
Interconnect TDDB :
is Provided for 20 nm+ Technology by Foundry

The thin dielectric between different node for interconnect metal
wires is under substantial electrical stress, and is prone to
breakdown over time

In Foundry DRC tech file, spacing criteria is raised when net is
applied by higher than core voltage. The spacing criteria is further
regulated into different levels depending on delta-voltage range
between the nets

Foundry has provided text annotation methodology to facilitate
voltage dependent DRC checks
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
To Achieve Voltage Dependent DRC Checking :
Static Voltage Propagation + Voltage Shift Methodology + Text Annotated DRC
Export high voltage nets with {maxV #} {minV #}
annotation
VCC_3P3
3.3
1.2
VCORE_2P5
2.5
Nch_thinOx
VOUT_2P5
Net-A
VCORE_1P8
1.8
3.3
VOUT_1P8
1.2
LOGICS
Net-B
Nch_thinOx
Core
Net-D
1.2
Net-C
VCORE_1P2
Power Management
VCORE_1P2
2.5
1.2
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
Nch_thinOx
A New EDA Tool Platform Can Handle Wide Scope
Of Reliability Verifications :
m3
Calibre PERC
EOS
Avoid Chip Failures
Voltage Aware DRC
Realize Area Savings
 Verification Beyond Traditional DRC, LVS, ERC, and PEX
 Rule Base Approach Align With Foundry Design Rule
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HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017
dummy
Analog Design Matching Pair
Multi-Power Domains
Validate SoC / AMS Design Intent
ESD
dummy
m2
m2
m1
m1
dummy
dummy
IO ESD / PG Clamp Verification
m4
www.mentor.com/perc
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