DIGITAL INTEGRATED CIRCUITS
Exercise 1 –DC Analysis on MOSFET & FinFET
Submitted by:
Edet Bijoy Kumaradhas
Student ID: 0884021
International College of Semiconductor Technology
National Chiao Tung University, Taiwan
 Select one FinFET model and one Buck CMOS Model
o Models selected (http://ptm.asu.edu/)
 7nm FinFET (nFET and pFET)
 32nm Bulk CMOS (nMOS and pMOS)
 Simulation of DC Characteristics in HSPICE
o Vgs – Ids of N-FinFET and NMOS (in one figure)
The netlist files used to simulate this exercise are nfetdc_1.sp
and nmosdc_new.sp.
The plot of Vgs – Ids is plotted in Fig. 1a and Fig. 1b in linear and log
scale respectively. Where is Fig. 1a, the blue color curve corresponds
to NFinFET and yellow color curve corresponds to NMOS. Whereas in
Fig. 1b, the green color curve corresponds to NFinFET and red color
curve corresponds to NMOS.
From both the figure the slope of the curves clearly shows that
FinFET possess better sub threshold slope.
International College of Semiconductor Technology
National Chiao Tung University, Taiwan
Fig. 1a Vgs – Ids (Linear Scale)
Fig. 1b Vgs – Ids (Log Scale)
International College of Semiconductor Technology
National Chiao Tung University, Taiwan
Vgs – Ids of P-FinFET and PMOS (in one figure)
The netlist files used to simulate this exercise are pfet_new.sp
and pmosdc_new.sp.
The plot of Vgs – Ids is plotted in Fig. 2a and Fig. 2b in linear and log
scale respectively. Where is Fig. 2a and 2b, the green color curve
corresponds to PFinFET and yellow color curve corresponds to
PMOS.
From both the figure the slope of the curves clearly shows that
FinFET possess better sub threshold slope.
Fig. 2a Vgs – Ids (Linear Scale)
International College of Semiconductor Technology
National Chiao Tung University, Taiwan
Fig. 2b Vgs – Ids (Log Scale)
International College of Semiconductor Technology
National Chiao Tung University, Taiwan
o Vds – Ids of N-FinFET
The Vds – Ids of N-FinFET is shown in Fig. 3. The netlist files
used to simulate this exercise is nfetdc_1.sp.
The simulation is run for Vds varies from 0 to 1V with a step size of
0.1 for the vales different values of Vgs, say 0.0V, 0.2V, 0.4V, 0.6V,
0.8V, 1.0V (the order in the graph is from bottom to top)
Fig. 3 Vds – Ids of N-FinFET
International College of Semiconductor Technology
National Chiao Tung University, Taiwan
o Vds – Ids of NMOS
The Vds – Ids of NMOS is shown in Fig. 4. The netlist files used
to simulate this exercise is nmosdc_new.sp.
The simulation is run for Vds varies from 0 to 1V with a step
size of 0.1 for the vales different values of Vgs, say 0.0V, 0.2V,
0.4V, 0.6V, 0.8V, 1.0V (the order in the graph is from bottom to
top)
Fig. 4 Vds – Ids of N-MOS
International College of Semiconductor Technology
National Chiao Tung University, Taiwan