ICT114
Timed Online Assignment – July Semester 2021
Computer Architecture
Wednesday, 17 November 2021
1:00 pm – 3:30 pm
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Time allowed: 2.5 hours
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INSTRUCTIONS TO STUDENTS:
1. This Timed Online Assignment (TOA) contains FOUR (4) questions and comprises
TEN (10) pages (including cover page).
2. You must answer ALL questions.
3. If you have any queries about a question, or believe there is an error in the question,
briefly explain your understanding and assumptions about that question before
attempting it.
4. You MUST submit your answers via Canvas (similar to TMA submission) at the
end time of this TOA (as stated on this cover page). The 15 minutes grace period as
shown on Canvas is strictly meant for technical issues encountered during
submission. Thereafter, you will not be able to submit your answers and you will be
considered as having withdrawn from the course. No appeal will be allowed.
5. You are to include the following particulars in your submission: TOA Course Code,
Your Name, and SUSS PI No. Name your submission file as
TOACourseCode_FullName_StudentPI. Use underscore and NOT Space. Example:
TOAXYZ_RaphaelLee_T1923161 (omit D/O, S/O).
6. Your submission should consist of only one file and must not exceed 500MB in size.
The file must be a Microsoft Word file saved in .doc or .docx format. All answers are
to be typed. Flowcharts and graphs may be scanned or photographed and embedded
in the Word file provided it does not exceed the file size limit of 500MB.
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
Page 1 of 10
7. You are required to sketch a diagram in some of the questions, if you are unable to
include them into the word document, you may upload them as pdf.
Please ensure that the total file size including word document does not exceed 500
MB and rename your pdf with the following naming convention:
CourseCode_FullName_StudentPI_PDF1
All uploaded hand written sketches and diagrams must be clear, readable and
complete. Marks will not be awarded for un-readable or incomplete images.
8. E114 instruction set summary (Appendix 1) and a partial ASCII codes table
(Appendix 2) are attached.
9. To prevent plagiarism and collusion, your submission will be reviewed by Turnitin.
The Turnitin report will only be made available to the marker and you will not be
able to view it.
10. The University takes plagiarism and collusion seriously, and your Turnitin report will
be examined thoroughly as part of the marking process.
____________________________________________________________________________________
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
Page 2 of 10
Answer all questions. (Total 100 marks)
Question 1
Analyse and explain the various number representations and answer the following
questions.
(a)
A processor uses 16-bit sign-magnitude representation to represent integers, what
is the range of decimal values it can represent? Show your working.
(2 marks)
(b)
An 8-bit microprocessor has an 8-bit wide memory. Given A = 7410 and B = 5810.
(c)
(i)
Determine the ASCII character if it has a value of 7410. Show your
working.
(2 marks)
(ii)
Express -A and -B in 8-bit sign-magnitude representation. Show your
working.
(2 marks)
(iii)
Show how the processor computes the arithmetic operation B - A in 2’s
complement arithmetic. Convert the result to decimal and show it is equal
to -16. Show your working.
(4 marks)
(iv)
Show how the processor computes the logic operation
(NOT(A) AND B) OR (NOT(B) AND A). Express the result in
hexadecimal. Show your working.
(6 marks)
(v)
Examine the values of A, B and the result of the operation in Question
1(b)(iv). Explain and deduce the logic operation equivalent to the logic
operation (NOT(A) AND B) OR (NOT(B) AND A).
(3 marks)
This microprocessor uses the specifications shown in Figure Q1(c) for 32-bit
floating-point number representation. If the representation in hexadecimal
number is C1E0 0000, determine the decimal value of the representation. Show
your working.
Figure Q1(c)
(6 marks)
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
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Question 2
(a)
(b)
For the following computer applications, recognize the features of various types
of computer systems and discuss whether a supercomputer, mainframe, midrange
computer or workstation would be the most appropriate computer to be used.
Give reasons for each of your choices.
(i)
A computer to be used at National Aeronautics and Space Administration
(NASA) for launching space shuttles and space exploration purposes.
(ii)
A computer for a small start-up company with Twenty (20) employees
who will access this computer remotely for applications, files and printer
sharing.
(iii)
A computer for a large international bank in the United States of America.
The computer handles high-frequency trading and need to react
instantaneously to changes in financial markets. Furthermore, it also
processes enormous volumes of transactions,
(iv)
A computer to be used by a busy sales executive who needs to access the
Internet, prepare reports and create spreadsheets.
(8 marks)
Instruction format, word size, and clock rate are some of the key CPU design
features.
(i)
Discuss the advantages and disadvantages of increasing word size.
(6 marks)
(ii)
Discuss the characteristics of the CPU and the primary storage that need
to be balanced to achieve maximum system performance.
(4 marks)
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
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(c)
Figure Q2(c) shows a computer with a Princeton Institute for Advanced Studies
(IAS) structure.
Figure Q2(c)
Demonstrate and describe the process that the processor must undertake to
WRITE a value to main memory. In your description, you must list and make
reference to the Memory Address Register (MAR), Memory Buffer Register
(MBR), address bus, data bus and control bus. For the control bus, line(s) that
is/are activated during the operation should be included.
(7 marks)
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
Page 5 of 10
Question 3
This question is based on the EASY68K simulated processor. Assume the contents of all
data and address registers are equal to zero before the start of the program. All numbers
are in hexadecimal.
Demonstrate how instructions of the program are executed by using the E114 Processor
Instruction Set of the EASY68K simulator.
The incomplete main program shown in Figure Q3 reads an array of twelve 8-bit signed
integers. If the integer value in the array is positive or zero, it does nothing to the value.
If the integer value is negative, it then calls a subroutine. The subroutine left shift the
contents of the register that holds the negative value by 2 places.
The main program starts at address 200016 and the subroutine at address 250016. The array
starts at address 300016.
Figure Q3
Note: The above code contains an instruction Logical Shift Right (LSR), which will right
shift the contents of the register D1 by 2 places.
(a)
Determine the missing items <<1>> to <<5>> to create the complete program.
(10 marks)
(b)
The main program includes a loop. Which register is being used as a loop counter?
(2 marks)
(c)
Explain the function of register A2.
(2 marks)
(d)
Explain the function of the instruction LSR #$02, D1.
(2 marks)
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
Page 6 of 10
(e)
Identify the addressing mode used in each of the following instructions:
(i)
(ii)
(iii)
MOVE.L A1, A2
MOVE.B (A1)+, D1
LSR
#$02, D1
(3 marks)
(f)
The initial contents of the memory are shown in Figure Q3(f). Give the
address(es) and the contents of the memory that is(are) changed by the program.
Figure Q3(f)
(6 marks)
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
Page 7 of 10
Question 4
(a)
A computer system has a 20-bit address bus and can address an 8-bit wide
memory. The memory contains:
16 Kbytes of system ROM
128 Kbytes of user RAM and
16 Kbytes of video RAM
The system ROM, user RAM and video RAM form a contiguous block of
memory starting at address 0. The rest of the address range after video RAM is
not used.
Draw the memory map for the computer system. Indicate the starting and ending
addresses in hexadecimal for each block of memory and any unused space. Show
how the memory addresses are obtained.
(12 marks)
(b)
Discuss the steps taken by the processor when the I/O module of an external
device sends an interrupt request signal to the processor.
(5 marks)
(c)
Explain how a cache improve performance when reading data from and writing
data to a storage device.
(8 marks)
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
Page 8 of 10
Appendix 1
Operation
Move
MOVE <EA1>,<EA2>
E114 Processor Instruction Set Summary
NZ
BWL
Description
**
XXX
move data
Arithmetic
ADD <EA1>, An or Dn
SUB <EA1>, An or Dn
**
**
XXX
XXX
add binary
subtract binary
Logical
AND <EA3>, Dn
NOP <EA3>, Dn
OR
<EA3>, Dn
NOT Dn
**
-**
**
XXX
logical AND
no operation
logical OR
logical NOT
XXX
XXX
Remarks
Control
BRA <Label>
BSR <Label>
BNE <Label>
BMI <Label>
BPL <Label>
JMP <Label>
RTS
STOP #$2700
---*
**---
branch always
branch subroutine
branch not equal
branch on negative
branch on positive
jump always
return from subroutine
stop
- flag not affected , * flag affected
<EA1> = Dn, An, (An), (An)+, $<data>, #$<data>
<EA2> = same as <EA1> except #$<data>
<EA3> = Dn, #<data>
An:
Address register A0 to A7
Dn:
Data register D0 to D7
(An) :
Content of address whose address is in An
(An)+:
Similar to (An) but after instruction An=An+1 for.B, An+2 for .W and An+4 for .L
$nnnn:
16-bit Hexadecimal address
$nnnnnnnn:
32-bit Hexadecimal address
#$nn:
8-bit immediate Hexadecimal data
#$nnnn:
16-bit immediate Hexadecimal data
#$nnnnnnnn:
32-bit immediate Hexadecimal data
T121 Stack operation
MOVE.L Dn,-(A7)
- Push operation: Dn data store on the stack. A7-4 =A7 after operation
MOVE.L (A7)+,Dn
Pop operation: Stack data is put back to Dn. A7+4 =A7 after operation
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
Page 9 of 10
Char
Binary
Appendix 2 Partial ASCII Table
Hex
Char
Binary
Hex
Char
Binary
Hex
00100000
20
A
01000001
41
a
01100001
61
!
00100001
21
B
01000010
42
b
01100010
62
"
00100010
22
C
01000011
43
c
01100011
63
#
00100011
23
D
01000100
44
d
01100100
64
$
00100100
24
E
01000101
45
e
01100101
65
%
00100101
25
F
01000110
46
f
01100110
66
&
00100110
26
G
01000111
47
g
01100111
67
‘
00100111
27
H
01001000
48
h
01101000
68
(
00101000
28
I
01001001
49
i
01101001
69
)
00101001
29
J
01001010
4A
j
01101010
6A
*
00101010
2A
K
01001011
4B
k
01101011
6B
+
00101011
2B
L
01001100
4C
l
01101100
6C
,
00101100
2C
M
01001101
4D
m
01101101
6D
-
00101101
2D
N
01001110
4E
n
01101110
6E
.
00101110
2E
O
01001111
4F
o
01101111
6F
/
00101111
2F
P
01010000
50
p
01110000
70
0
00110000
30
Q
01010001
51
q
01110001
71
1
00110001
31
R
01010010
52
r
01110010
72
2
00110010
32
S
01010011
53
s
01110011
73
3
00110011
33
T
01010100
54
t
01110100
74
4
00110100
34
U
01010101
55
u
01110101
75
5
00110101
35
V
01010110
56
v
01110110
76
6
00110110
36
W
01010111
57
w
01110111
77
7
00110111
37
X
01011000
58
x
01111000
78
8
00111000
38
Y
01011001
59
y
01111001
79
9
00111001
39
Z
01011010
5A
z
01111010
7A
----- END OF PAPER -----
ICT114 Copyright © 2021 Singapore University of Social Sciences (SUSS)
TOA – July Semester 2021
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