EE315B
VLSI Data Conversion Circuits
- Autumn 2011 Katelijn Vleugels
Stanford University
Table of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Introduction
Sampling, Quantization, Reconstruction
Spectral Performance Metrics
Nyquist Rate DACs
Sampling Circuits
Voltage Comparators
Flash and Folding ADCs
Pipeline ADCs
Bit-at-a-Time ADCs, Time Interleaving
Oversampling ADCs
Oversampling DACs
Limits on ADC Power Dissipation
Data Converter Testing
Introduction
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 1
1
Motivation (1)
This course
Analog
Media and
Transducers
Signal
Conditioning
A/D
Digital
Processing
Signal
g
Conditioning
D/A
Sensors, Actuators,
Antennas, Storage Media, ...
B. Murmann
EE315B - Chapter 1
2
Motivation (2)
•
Benefits of digital signal processing
– Reduced sensitivity
y to "analog"
g noise
– Enhanced functionality and flexibility
– Amenable to automated design & test
– Direct benefit from the scaling of VLSI technology
– "Arbitrary" precision
•
Issues
– Data converters are difficult to design
• Especially due to ever-increasing performance requirements
– Data converters often present a performance bottleneck
• Speed, resolution or power dissipation of the A/D or D/A
converter can limit overall system performance
EE315B - Chapter 1
B. Murmann
3
Data Converter Applications (1)
•
Consumer electronics
– Audio,
Audio TV
TV, Video
– Digital Cameras
– Automotive control
– Appliances
– Toys
•
Communications
– Mobile Phones
– Personal
P
lD
Data
t A
Assistants
i t t
– Wireless Transceivers
– Routers, Modems
B. Murmann
EE315B - Chapter 1
4
Data Converter Applications (2)
•
Computing
p
g and Control
– Storage media
– Sound Cards
– Data acquisition cards
•
Instrumentation
– Lab bench equipment
– Semiconductor test equipment
– Scientific equipment
– Medical equipment
EE315B - Chapter 1
B. Murmann
5
A/D Converter Application Space
24
22
DVD
Audio
20
1kW
Res
solution [bits
s]
18
1W
16
Audio
14
12
DSL
1mW
10
8
GSM Base
GSM Rx
Motor
Controls
Video
Ultrasound
DTV
DVC
Teleph.
Dig. Scope
HDD
6
4
1µW
Wireline Interface
2
1kHz
B. Murmann
10kHz
100kHz
1MHz
10MHz
Bandwidth
EE315B - Chapter 1
100MHz
1GHz
10GHz
6
Example 1
[Poulton, ISSCC 2003]
•
High performance digital
oscilloscopes rely on extremely
high performance ADCs
•
Example
– 20 GSample/s, 8-bit ADC
– 10 W Power dissipation
B. Murmann
EE315B - Chapter 1
7
Example 2
•
A typical cell phone contains:
– 4 Rx ADCs
Dual Standard, I/Q
– 4 Tx DACs
Audio, Tx/Rx power
– 3 Auxiliary ADCs
control, Battery
– 8 Auxiliary DACs
charge
control display
control,
display, ...
•
A total of 19 data converters!
B. Murmann
EE315B - Chapter 1
8
Example 3
[Mehta, ISSCC2005]
•
Low-cost, single chip solutions require embedded data
conversion
•
Example: 802.11g Wireless LAN chip
– 2x 11-bit DAC, 176 MSamples/s
– 2x 9
9-bit
bit ADC,
ADC 80 MSamples/s
EE315B - Chapter 1
B. Murmann
9
Survey Data (ISSCC & VLSI 1997-2008)
10
10
P/fs [Joules]
10
10
10
http://www.stanford.edu/~murmann/adcsurvey.html
-6
-7
-8
-9
FOM 
P
fs  2ENOB
10
10
fJ
conv-step
-10
ENOB 
10
 100
-11
Flash
Pipeline
SAR
Sigma-Delta
Other
-12
-13
20
B. Murmann
30
40
50
60
70
SNDR [dB]
80
90
EE315B - Chapter 1
100
SNDR[ dB ]  1.76
6.02
110
10
ADC Energy Trend
Slope ~0.5x/2.1years
log(P//f s [pJ])
6
4
2
0
2008
2006
2004
2002
2000
1998
Year
•
20
40
60
80
100
120
SNDR [dB]
Reduction of ~30x
30x over past 10 years (!)
B. Murmann
EE315B - Chapter 1
B. Murmann
B
Murmann, "A/D
A/D Converter Trends:
Power Dissipation, Scaling and
Digitally Assisted Architectures," Proc.
IEEE Custom Integrated Circuits
Conference (CICC), pp. 105-112,
Sept.
p 2008.
11
Course Objective
•
Acquire a thorough understanding of the basic principles and
challenges in data converter design
– Focus on concepts that are unlikely to expire within the next
decade
– Preparation
p
for further study
y of state-of-the-art "fine-tuned"
realizations
•
Strategy
– Acquire breadth via a complete system walkthrough and a
survey of existing architectures
– Acquire depth through a midterm project that entails design
and thorough characterization of a specific circuit example in
modern technology
B. Murmann
EE315B - Chapter 1
12
Staff and Website
•
Teaching assistants
– See web
•
Administrative support
– Ann Guerra, CIS 207
•
Lecture videos are provided on the web, but please come to
class to keep the discussion intercative
•
Web
W
b page: http://ccnet.stanford.edu/ee315b
htt //
t t f d d / 315b
– Check regularly, especially the "bulletin board" section
– Only enrolled students can register for ccnet access
• We synchronize the ccnet database with axess.stanford.edu
manually, ~ once per day during first week of instruction
EE315B - Chapter 1
B. Murmann
13
Preparation
•
Course prerequisites
– EE214 or equivalent
• Device physics and models
• Transistor level analog circuits, elementary gain stages
• Frequency response,
response feedback,
feedback noise
– Prior exposure to Spice, Matlab
– Basic signals and systems
– Probablity
•
Please talk to me if you are not sure if you have the required
background
g
B. Murmann
EE315B - Chapter 1
14
Analog Circuit Sequence
Fundamentals for upperlevel undergraduates and
entry-level graduate
students
Analysis and design
techniques for highhigh
performance circuits in
advanced Technologies
Design of application
and functionfunction specific
mixed-signal/RF
building blocks
EE314 —
RF Integrated
Circuit Design
EE114 —
Fundamentals of
Analog Integrated
Circuit Design
EE214 —
Advanced Analog
Integrated Circuit
Design
EE315A — VLSI
Signal
Conditioning
Circuits
EE315B — VLSI
Data Conversion
Circuits
B. Murmann
EE315B - Chapter 1
15
Assignments
•
Homework: (20%)
( %)
– Handed out on Tue, due following Tue after lecture (1 pm)
– Lowest HW score is dropped in final grade calculation
•
Midterm Project: (40%)
– Transistor level design and simulation of a data converter
sub-block (no layout)
– Prepare a project report in the format and style of an IEEE
journal paper
•
Final Exam (40%)
B. Murmann
EE315B - Chapter 1
16
Honor Code
•
Please remember yyou are bound by
y the honor code
– I will trust you not to cheat
– I will try not to tempt you
•
But if you are found cheating it is very serious
– There is a formal hearing
– You can be thrown out of Stanford
•
Save yourself and me a huge hassle and be honest
•
For more info
– http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/
honorcode.pdf
B. Murmann
EE315B - Chapter 1
17
Tools and Technology
•
Primary tools
– Cadence Virtuoso Schematic Editor
– Cadence Virtuoso Analog Design Environment
– Cadence SpectreRF simulator
– You can use your own tools/setups “at own risk“
•
Getting started
– Read tutorials and setup info provided in the CAD section of the
course website
•
EE315A/B Technology
– 0.18-m CMOS
– BSIM3v3 models p
provided under /usr/class/ee315b/models
B. Murmann
EE315B - Chapter 1
18
Reference Books
•
Gustavsson, Wikner, Tan, CMOS Data Converters for
Communications, Kluwer, 2000.
•
A. Rodríguez-Vázquez, F. Medeiro, and E. Janssens, CMOS
Telecom Data Converters,, Kluwer Academic Publishers,, 2003.
•
B. Razavi, Data Conversion System Design, IEEE Press, 1995.
•
R. Schreier, G. Temes, Understanding Delta-Sigma Data
Converters, Wiley-IEEE Press, 2004.
•
R. v. d. Plassche, CMOS Integrated Analog-to-Digital and
Digital-to-Analog
Digital
to Analog Converters, 2nd ed., Kluwer, 2003.
•
J. G. Proakis, D. G. Manolakis, Digital Signal Processing,
Prentice Hall, 1995.
EE315B - Chapter 1
B. Murmann
19
Course Topics
•
Id l sampling,
Ideal
li
reconstruction
t ti and
d quantization
ti ti
•
Sampling circuits
•
Voltage comparators
•
Nyquist-rate ADCs and DACs
•
Oversampled ADCs and DACs
•
Data converter performance trends and limits
•
Data converter testing
B. Murmann
EE315B - Chapter 1
20
Sampling, Quantization, Reconstruction
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
EE315B - Chapter 2
B. Murmann
1
The Data Conversion Problem
•
Real world signals
g
– Continuous time, continuous amplitude
•
Digital abstraction
– Discrete
Di
t time,
ti
discrete
di
t amplitude
lit d
•
Two problems
– How to discretize in time and amplitude
• A/D conversion
– How to "undescretize" in time and amplitude
• D/A conversion
B. Murmann
EE315B - Chapter 2
2
Overview
•
We'll fist look at these building blocks from a functional, "black
box" perspective
– Refine later and look at implementations
p
B. Murmann
EE315B - Chapter 2
3
Uniform Sampling and Quantization
•
Most common way of performing A/D
conversion
– Sample signal uniformly in time
– Quantize signal uniformly in
amplitude
lit d
•
Key questions
– How fast do we need to sample?
• Must avoid "aliasing“
– How much "noise" is added due
to amplitude quantization?
B. Murmann
EE315B - Chapter 2
4
Aliasing Example (1)
Am
mplitude
fs 
1
 1000kHz
Ts
fsig  101kHz
kH
Time


f
v sig  n   cos  2  in  n 
fs


v sig  t   cos  2  fin  t 
t  n  Ts 
n
fs
101


 cos  2 
n
1000 

EE315B - Chapter 2
B. Murmann
5
Aliasing Example (2)
Am
mplitude
fs 
1
 1000kHz
Ts
fsig  899kHz
Time

899
101


 899
 


v sig  n   cos  2 
 n   cos  2  
 1  n   cos  2 
n
1000
1000
1000



 



B. Murmann
EE315B - Chapter 2
6
Aliasing Example (3)
Am
mplitude
fs 
1
 1000kHz
Ts
fsig  1101kHz
Time

1101 
101

 1101  


v sig  n   cos  2 
 n   cos  2  
 1  n   cos  2 
n
1000 
1000 

1000  


B. Murmann
EE315B - Chapter 2
7
Consequence
•
The frequencies fsig and N·fs ± fsig (N integer), are
indistinguishable in the discrete time domain
B. Murmann
EE315B - Chapter 2
8
Sampling Theorem
•
In order to prevent aliasing, we need
fsig ,max 
fs
2
•
The sampling rate fs=2·fsig,max is called the Nyquist rate
•
Two possibilities
– Sample fast enough to cover all spectral components
components,
including "parasitic" ones outside band of interest
– Limit fsig,max through filtering
B. Murmann
EE315B - Chapter 2
9
Brick Wall Anti-Alias Filter
B. Murmann
EE315B - Chapter 2
10
Practical Anti-Alias Filter
Desired
Signal
Parasitic
Tone
Attenuation
Continuous
Time
0
B
fs/2
0
B/fs
0.5
fs-B
fs
...
f
Discrete
Time
•
f/fs
Need to sample faster than Nyquist rate to get good attenuation
– "Oversampling"
"O
li "
B. Murmann
EE315B - Chapter 2
11
How much Oversampling?
[v.d. Plassche, p.41]
Alias
Rejection
Filter Order
fs/fsig,max
•
Can tradeoff sampling speed against filter order
•
In high speed converters, making fs/fsig,max>10 is usually
impossible or too costly
– Means that we need fairly high order filters
B. Murmann
EE315B - Chapter 2
12
Classes of Sampling
•
Nyquist-rate sampling (fs > 2·fsig,max)
– Nyquist data converters
– In practice always slightly oversampled
•
Oversampling (fs >> 2·fsig,max)
– Oversampled data converters
– Anti-alias filtering is often trivial
– Oversampling also helps reduce "quantization noise"
• More later
•
Undersampling, subsampling (fs < 2·fsig,max)
– Exploit aliasing to mix RF/IF signals down to baseband
– See e.g. Pekau & Haslett, JSSC 11/2005
B. Murmann
EE315B - Chapter 2
13
Subsampling
•
Aliasing is "non-destructive"
non destructive if signal is band limited around some
carrier frequency
•
Downfolding of noise is a severe issue in practical subsampling mixers
– Typically achieve noise figure no better than 20 dB (!)
B. Murmann
EE315B - Chapter 2
14
Quantization of an Analog Signal
Vq ((quantized ou
utput)
Transfer Function
Slope=1
Slope
1
•
Quantization step 
•
Quantization
Q
ti ti error has
h
sawtooth shape
– Bounded by –/2, +/2
•
Ideally
– Infinite input range and
infinite number of
quantization levels
•
In practice
– Finite input range and
fi it number
finite
b off
quantization levels
– Output is a digital word
(not an analog voltage)

eq (quantiz
zation error)
x (input)
Error eq=q-x
+/2
-/2
x (input)
B. Murmann
EE315B - Chapter 2
15
Conceptual Model of a Quantizer
•
Encoding block determines how quantized levels are mapped
into digital codes
•
Note that this model is not meant to represent an actual
hardware implementation
– Its
ts pu
purpose
pose is
s to sshow
o tthat
at qua
quantization
t at o a
and
de
encoding
cod g a
are
e
conceptually separate operations
– Changing the encoding of a quantizer has no interesting
implications
p
on its function or p
performance
B. Murmann
EE315B - Chapter 2
16
Digital Outpu
ut
Encoding Example for a B-Bit Quantizer
•
111
110
101
100
011
010
001
000

eq (quan
ntization erro
or)
Analog Input
Example: B=3
– 23=8 distinct output
p codes
– Diagram on the left shows
"straight-binary encoding"
– See e.g. Analog Devices "MT009: Data Converter Codes" for
other encoding schemes
• http://www.analog.com/en/content/0
,2886,760%255F788%255F91285,
00.html
+/2
•
-/2 •
FSR
x ((input)
p )
B. Murmann
Quantization error grows out of
bounds beyond code boundaries
We define the full scale range
(FSR) as the maximum input range
that satisfies |eq|  /2
– Implies that FSR=2B·
EE315B - Chapter 2
17
Nomenclature
•
Overloading - Occurs when an input outside
the FSR is applied
•
Transition level – Input value at the
transition between two codes. By standard
convention, the transition level T(k) lies
between codes k-1 and k
•
Code width – The difference between
adjacent transition levels. By standard
convention, the code width W(k)=T(k+1)-T(k)
– Note that the code width of the first and
last code (000 and 111 on previous slide)
is undefined
•
LSB size (or width) – synonymous with
code width 
B. Murmann
EE315B - Chapter 2
[IEEE Standard 1241-2000]
18
Implementation Specific Technicalities
•
So far, we avoided specifying the absolute location of the code
range with respect to "zero" input
•
The zero input location depends on the particular
implementation of the quantizer
– Bipolar input
input, mid
mid-rise
rise or mid
mid-tread
tread quantizer
– Unipolar input
•
The next slide shows the case with
– Bipolar input
• The quantizer accepts positive and negative inputs
– Represents the common case of a differential circuit
– Mid-rise characteristic
• The center of the transfer function (zero), coincides with a
transition level
EE315B - Chapter 2
B. Murmann
19
Digital O
Output
Bipolar Mid-Rise Quantizer
111
110
101
100
00
011
010
001
000
Analog Input
-FSR/2
FSR/2
•
0
+FSR/2
Nothing new here…
B. Murmann
EE315B - Chapter 2
20
Bipolar Mid-Tread Quantizer
In theory, less sensitive to infinitesimal disturbance around zero
– In practice, offsets larger than /2 (due to device mismatch)
often
ft make
k thi
this argumentt irrelevant
i l
t
•
Asymmetric full-scale range, unless we use odd number of codes
Digital Ou
utput
•
111
110
101
100
011
010
001
000
Analog Input
FSR/2 + /2
0 FSR/2 - /2
EE315B - Chapter 2
B. Murmann
21
Unipolar Quantizer
Usually define origin where first code and straight line fit intersect
– Otherwise, there would be a systematic offset
•
Usable range is reduced by /2 below zero
Digital Ou
utput
•
111
110
101
100
011
010
001
000
0
B. Murmann
Analog Input
FSR - /2
EE315B - Chapter 2
22
Effect of Quantization Error on Signal
•
Two aspects
– How much noise power does quantization add to samples?
– How is this noise power distributed in frequency?
•
Quantization error is a deterministic function of the signal
– Should be able answer above questions using a
deterministic analysis
– But, unfortunately, such an analysis strongly depends on the
chosen signal and can be very complex
•
Strategy
– Build basic intuition using
g simple
p deterministic signals
g
– Next, abandon idea of deterministic representation and
revert to a "general" statistical model (to be used with
caution!))
EE315B - Chapter 2
B. Murmann
23
Ramp Input
•
Applying a ramp signal (periodic sawtooth) at the input of the
quantizer gives the following time domain waveform for eq
0.6
eq(tt) []
0.4
0.2
0
-0.2
-0.4
0
50
100
Time [arbitrary units]
150
•
What is the average power of this waveform?
•
Integrate over one period
T/2
eq2
B. Murmann
1

eq2 ( t )dt
T T/ 2
eq ( t ) 

t
T
EE315B - Chapter 2
 eq2 
2
12
24
Sine Wave Input
1
1
V
V
0.8
q
0.6
0.4
0.4
0.2
0.2
eq(t) []
0.6
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0
•
02
0.2
0.4
0
4
06
0.6
Time [arbitrary units]
08
0.8
-1
0
1
02
0.2
04
0.4
06
0.6
Time [arbitrary units]
08
0.8
1
Integration is not straightforward…
EE315B - Chapter 2
B. Murmann
25
Quantization Error Histogram
•
•
Sinusoidal input signal with fsig=101Hz, sampled at fs=1000Hz
8-bit quantizer
q
Mean=0.000LSB, Var=1.034LSB2/12
120
100
80
Count
[Volts]
0.8
in
60
40
20
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0 0.1 0.2 0.3 0.4 0.5 0.6
eq/
•
Distribution is "almost" uniform
•
Can approximate average power by integrating uniform
distribution
B. Murmann
EE315B - Chapter 2
26
Statistical Model of Quantization Error
•
Assumption: eq(x) has a uniform probability density
•
This approximation holds reasonably well in practice when
– Signal spans large number of quantization steps
– Signal is "sufficiently active"
– Quantizer
Q
ti
does
d
nott overload
l d
 / 2
Mean
eq 

 / 2
 / 2
Variance
eq2


 / 2
eq

deq  0
eq 2
2
deq 

12
EE315B - Chapter 2
B. Murmann
27
Reality Check (1)
•
Input sequence consists of 1000 samples drawn from Gaussian
distribution, 4=FSR
Mean=-0.004LSB, Var=1.038LSB2/12
150
C
Count
100
50
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1
•
0 0.1 0.2 0.3 0.4 0.5 0.6
eq/
Error power close to that of uniform approximation
B. Murmann
EE315B - Chapter 2
28
Reality Check (2)
•
Another sine wave example, but now fsig/fs=100/1000
•
What's going on here?
Mean=-0.000LSB, Var=0.629LSB2/12
500
Count
400
300
200
100
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0 0.1 0.2 0.3 0.4 0.5 0.6
eq/
EE315B - Chapter 2
B. Murmann
29
Amp
plitude
Analysis (1)
fsig/fs=100/1000
Time
•
Sampled signal is repetitive and has only a few distinct values
– This also means that the quantizer generates only a few
distinct values of eq; not a uniform distribution
B. Murmann
EE315B - Chapter 2
30
Analysis (2)


f
v sig  n   cos  2  in  n 
fs 

•
Signal repeats every m samples, where m is the smallest
integer that satisfies
m
•
fin
i  integer
fs
m
101
 integer
g
1000
 m  1000
m
100
 integer
1000
 m  10
This means that eq(n) has at best 10 distinct values, even if we
take many more samples
EE315B - Chapter 2
B. Murmann
31
Signal-to-Quantization-Noise Ratio
•
Assuming uniform distribution of eq and a full-scale sinusoidal
input,
p we have
SQNR 
B. Murmann
Psig
Pqnoise

1  2B  


2  2 

12
2
2
 1.5
1 5  22B  6.02B
6 02B  1.76
1 76 dB
B (Number of Bits)
SQNR
8
50 dB
12
74 dB
16
98 dB
20
122 dB
EE315B - Chapter 2
32
Quantization Noise Spectrum (1)
•
How is the quantization noise power distributed in frequency?
– First think about applying a sine wave to a quantizer, without
sampling (output is continuous time)
+ many more harmonics
[Y Tsividis,
[Y.
Tsividis ICASSP 2004]
•
Quantization results in an "infinite" number of harmonics
B. Murmann
EE315B - Chapter 2
33
Quantization Noise Spectrum (2)
•
Now sample the signal at the output
– All harmonics (an "infinite" number of them) will alias into
band from 0 to fs/2
– Quantization noise spectrum becomes "white"
[Y. Tsividis, ICASSP 2004]
•
Interchanging sampling and quantization won’t change this
situation
B. Murmann
EE315B - Chapter 2
34
Quantization Noise Spectrum (3)
•
Can show that the quantization noise power is indeed
distributed (approximately) uniformly in frequency
– Again,
Again this is provided that the quantization error is
"sufficiently random"
2 2

12 fs
•
References
– W. R. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., pp. 446-72,
July 1948.
– B.
B Widrow,
Widrow "A
A study of rough amplitude quantization by means of Nyquist
sampling theory," IRE Trans. Circuit Theory, vol. CT-3, pp. 266-76, 1956.
– A. Sripad and D. A. Snyder, "A necessary and sufficient condition for
quantization errors to be uniform and white," IEEE Trans. Acoustics, Speech,
and
d Si
Signall P
Processing,
i
pp. 442
442-448,
448 O
Octt 1977
1977.
B. Murmann
EE315B - Chapter 2
35
Recap
B. Murmann
EE315B - Chapter 2
36
Ideal DAC
•
Essentially a digitally controlled voltage, current or charge source
– Example
p below is for unipolar
p
DAC
•
Ideal DAC does not introduce quantization error!
B. Murmann
EE315B - Chapter 2
37
The Reconstruction Problem
•
As long as we sample fast
enough,
g , x(n)
( ) contains all
information about x(t)
– fs > 2·fsig,max
•
H
How
tto reconstruct
t t x(t)
(t) from
f
x(n)?
( )?
•
Ideal interpolation formula
x(( t ) 


n 
g( t ) 
•
B. Murmann
x(( n )  g(( t  nT
Ts )
sin( fs t )
fs t
Very hard to build an analog
circuit that does this…
EE315B - Chapter 2
38
Zero-Order Hold Reconstruction
•
The most practical way of
reconstructing
g the continuous
time signal is to simply "hold" the
discrete time values
– Either for full p
period Ts or a
fraction thereof
– Other schemes exist, e.g.
“partial-order
p
hold”
• See [Jha, TCAS II, 11/2008]
B. Murmann
•
What does this do to the signal
spectrum?
•
We'll analyze this in two steps
– First look at infinitely narrow
reconstruction pulses
EE315B - Chapter 2
39
Dirac Pulses
•
xd(t) is zero between pulses
– Note that x(n) is undefined at
these times
xd ( t )  x( t ) 
•

n 
( t  nTs )
Multiplication in time means
convolution
l ti iin ffrequency
– Resulting spectrum
Xd ( f ) 
B. Murmann

EE315B - Chapter 2
1
Ts


n 
X f  
Ts 
n  

40
Spectrum
•
Spectrum of Dirac signal contains replicas of Vin(f) at integer
multiples
p
of the sampling
p g frequency
q
y
B. Murmann
EE315B - Chapter 2
41
Finite Hold Pulse
•
Consider the general case with a
rectangular pulse 0 < Tp  Ts
•
The time domain signal on the left
follows from convolving the Dirac
sequence with a rectangular unit pulse
•
Spectrum follows from multiplication with
Fourier transform of the pulse
Hp (f )  Tp
Xp (f ) 
sin( fTp )
fTp
Tp sin(( fTp )
Ts
fTp
e
e
 jfTp
 jfTp


n 
X f  
Ts 
n  

Amplitude Envelope
B. Murmann
EE315B - Chapter 2
42
Envelope with Hold Pulse Tp=Ts
1
09
0.9
0.8
0.7
fTp
Ts
abs(H(f))
Tp sin( fTp )
0.6
0.5
04
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5
2
2.5
3
f/fs
f/f
s
EE315B - Chapter 2
B. Murmann
43
Envelope with Hold Pulse Tp=0.5·Ts
1
09
0.9
0.8
Tp=Ts
0.7
Ts
fTp
abs(H(f))
Tp sin( fTp )
0.6
0.5
04
0.4
Tp=0.5·Ts
0.3
0.2
0.1
0
0
0.5
1
1.5
f/fs
2
2.5
3
f/fs
B. Murmann
EE315B - Chapter 2
44
Example
1
Spectrum of
Continuous Time
Pulse Train (Arbitrary
Example)
05
0.5
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
2
2.5
3
1
ZOH Transfer
Function
("Sinc Distortion")
0.5
0
1
ZOH output,
Spectrum of
Staircase
Approximation
original spectrum
0.5
0
0
0.5
1
1.5
f/fs
EE315B - Chapter 2
B. Murmann
45
Reconstruction Filter
1
09
0.9
0.7
Spectrum
Also called
smoothing
hi filter
fil
•
Same situation
as with anti-alias
filter
– A brick wall
filter would be
nice
– Oversampling
helps
p reduce
filter order
Filter
0.8
0.6
0.5
04
0.4
0.3
0.2
0.1
0
•
0
0.5
1
1.5
2
2.5
3
f/fs
B. Murmann
EE315B - Chapter 2
46
Summary
•
Must obey sampling theorem fs > 2·fsig,max,
– Usuallyy dictates anti-aliasing
g filter
•
If sampling theorem is met, continuous time signal can be
recovered from discrete time sequence without loss of
information
•
A zero order hold in conjunction with a smoothing filter is the
most common way to reconstruct
– May need to add pre- or post-emphasis to cancel droop due
to sinc envelope
•
Oversampling helps reduce order of anti-aliasing
anti aliasing and
reconstruction filters
B. Murmann
EE315B - Chapter 2
47
Static Nonidealities
•
Static deviations of transfer characteristics from ideality
– Offset
– Gain error
– Differential Nonlinearity (DNL)
– Integral Nonlinearity (INL)
•
Useful references
– Analog Devices MT-010: The Importance of Data Converter
Static Specifications
• http://www.analog.com/en/content/0,2886,761%255F795%255F91286,00.html
http://www analog com/en/content/0 2886 761%255F795%255F91286 00 html
– "Understanding Data Converters," Texas Instruments
Application Report LAA013, 1995.
• http://focus.ti.com/lit/an/slaa013/slaa013.pdf
p
p
B. Murmann
EE315B - Chapter 2
48
Offset and Gain Error
•
Conceptually simple, but lots of (uninteresting) subtleties in how
exactly these errors should be defined
– Unipolar versus bipolar, endpoint versus midpoint
specification
– Definition in p
presence of nonlinearities
•
General idea (neglecting staircase nature of transfer functions):
OUT
OUT
Ideal
Ideal
With
offset
With gain
error
IN
IN
EE315B - Chapter 2
B. Murmann
49
ADC Offset and Gain Error
•
Definitions based on bottom and top endpoints of transfer characteristic
– ½ LSB before first transition and ½ LSB after last transition
– Offset is the deviation of bottom endpoint from its ideal location
– Gain error is the deviation of top endpoint from its ideal location with
offset removed
•
Both quantities are measured in LSB or as percentage of full-scale range
Gain Error
Dout
Dout
Ideal
Vin
Ideal
Vin
Offset
B. Murmann
EE315B - Chapter 2
50
DAC Offset and Gain Error
•
Same idea, except that endpoints are directly defined by analog
output
p values at minimum and maximum digital
g
input
p
•
Also note that errors are specified along the vertical axis
B. Murmann
EE315B - Chapter 2
51
Comments on Offset and Gain Errors
•
Definitions on the previous slides are the ones typically used in industry
– IEEE Standard suggest somewhat more sophisticated definitions
based on least square curve fitting
• Technically more suitable metric when the transfer characteristics are
significantly non-uniform or nonlinear
•
Generally, it is non-trivial
Generally
non trivial to build a converter with very good gain/offset
specifications
– Nevertheless, since gain and offset affect all codes uniformly, these
errors tend to be easy
y to correct
• E.g. using a digital pre- or post-processing operation
– Also, many applications are insensitive to a certain level of gain and
offset errors
• E.g. audio signals, communication-type signals, ...
•
More interesting aspect: linearity
– DNL and INL
B. Murmann
EE315B - Chapter 2
52
Differential Nonlinearity (DNL)
•
In an ideal world,, all ADC codes would have equal
q
width;; all
DAC output increments would have same size
•
DNL(k) is a vector that quantifies for each code k the deviation
of this width from the "average"
average width (step size)
•
DNL(k) is a measure of uniformity, it does not depend on gain
and offset errors
– Scaling and shifting a transfer characteristic does not alter its
uniformity and hence DNL(k)
•
Let's
Let
s look at an example
B. Murmann
EE315B - Chapter 2
53
ADC DNL Example (1)
B. Murmann
EE315B - Chapter 2
Code (k)
W [V]
0
undefined
1
1
2
0.5
3
1
4
1.5
5
0
6
15
1.5
7
undefined
54
ADC DNL Example (2)
•
What is the average code width?
– ADC with perfect uniformity would divide the range between
first and last transition into 6 equal pieces
– Hence calculate average code width (i.e. LSB size) as
Wavg 
•
7.5V  2V
 0.9167V
6
N
Now
calculate
l l t DNL(k) ffor each
h code
d k using
i
DNL(k) 
W(k)  Wavgg
Wavg
EE315B - Chapter 2
B. Murmann
55
Result
Code (k)
DNL [LSB]
1
0 09
0.09
2
-0.45
3
0.09
4
0.64
5
-1.00
6
0 64
0.64
•
Positive/negative DNL implies wide/narrow code, respectively
•
DNL = -1
1 LSB iimplies
li missing
i i code
d
•
Impossible to have DNL < -1 LSB for an ADC
– But possible to have DNL > +1 LSB
•
Can show that sum over all DNL(k) is equal to zero
B. Murmann
EE315B - Chapter 2
56
A Typical ADC DNL Plot
[Ahmed, JSSC 12/2005]
•
People speak about DNL often only in terms of min/max number
across all codes
– E.g.
E g DNL = +0
0.63/
63/-0
0.91
91 LSB
•
Might argue in some cases that any code with DNL < -0.9 LSB
is essentially a missing code
– Why ?
B. Murmann
EE315B - Chapter 2
57
Impact of Noise
[W. Kester, "ADC Input Noise: The
Good, The Bad, and The Ugly. Is
No Noise Good Noise?" Analogue
Dialogue, Feb. 2006]
•
In essentially all moderate to high-resolution ADCs, the transition
levels carry noise that is somewhat comparable to the size of an LSB
– Noise "smears
smears out"
out DNL,
DNL can hide missing codes
•
Especially for converters whose input referred (thermal) noise is
larger than an LSB, DNL is a "fairly useless" metric
B. Murmann
EE315B - Chapter 2
58
DAC DNL
•
Same idea applies
– Find output increments for each digital code
– Find increment that divides range into equal steps
– Calculate DNL for each code k using
DNL(k) 
•
St (k)  Step
Step(k)
St avg
Stepavg
One difference between ADC and DAC is that DAC DNL can be
less than -1 LSB
– How ?
B. Murmann
EE315B - Chapter 2
59
Non-Monotonic DAC
DNL(3) 

Step(3)  Stepavg
Stepavg
0.5V  1V
 1.5LSB
1V
•
I a DAC,
In
DAC DNL < -1LSB
1LSB implies
i li non-monotinicity
ti i it
•
How about a non-monotonic ADC?
B. Murmann
EE315B - Chapter 2
60
Non-Monotonic ADC
•
Code 2 has two transition levels  W(2) is ill defined
– DNL is ill-defined!
ill defined!
•
Not a very big issue, because a non-monotonic ADC is usually
not what we'll design for in practice…
B. Murmann
EE315B - Chapter 2
61
Integral Nonlinearity (INL)
•
General idea
– For each "relevant point" of the transfer characteristic,
quantify distance from a straight line drawn through the
endpoints
• An alternative, less common definition uses a least square fit
line as a reference
– Just as with DNL, the INL of a converter is by definition
independent of gain and offset errors
B. Murmann
EE315B - Chapter 2
62
ADC INL Example (1)
•
"Straight line" reference
is uniform staircase
between first and last
transition
•
INL for each code is
INL(k) 
T(k)  Tuniform (k)
Wavg
•
Obviously INL(1) = 0
and INL(7)
( )=0
•
INL(0) is undefined
EE315B - Chapter 2
B. Murmann
63
ADC INL Example (2)
•
Can show that
k 1
INL(k)   DNL(i)
i 1
•
Means that once we computed DNL, we can easily find INL
using a cumulative sum operation on the DNL vector
•
Using DNL values from last lecture, we find
B. Murmann
Code (k)
DNL [LSB]
INL [LSB]
1
0.09
0
2
-0.45
0.09
3
0.09
-0.36
4
0.64
-0.27
5
-1.00
0.36
6
0.64
-0.64
7
undefined
d fi d
0
EE315B - Chapter 2
64
Result
B. Murmann
EE315B - Chapter 2
65
A Typical ADC DNL/INL Plot
[Ishii, Custom
Integrated Circuits
Conference 2005]
Conference,
•
DNL/INL signature often reveals architectural details
– E.g.
E g major transitions
– We'll see more examples in the context of DACs
•
Since INL is a cumulative measure, it turns out to be less
sensitive than DNL to thermal noise "smearing"
B. Murmann
EE315B - Chapter 2
66
DAC INL
•
Same idea applies
– Find ideal output values that lie on a straight line between
endpoints
– Calculate INL for each code k using
INL(k) 
•
Vout (k)  Voutuniform (k)
Stepavg
Interesting property related to DAC INL
– If for all codes |INL| < 0.5 LSB, it
follows that all |DNL| < 1 LSB
– A sufficient
ff
(but
(
not necessary))
condition for monotonicity
B. Murmann
EE315B - Chapter 2
67
Spectral Performance Metrics
Katelijn Vleugels
Stanford University
y
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 3
1
Spectral Performance Metrics
•
Spectral performance metrics follow from looking at converter or
b ildi bl
building
block
k output
t t spectrum
t
•
Basic idea:
– Apply
pp y one or more tones at converter input
p
– Expect same tone(s) at output, all other frequency components
represent non-idealities
•
Important to realize that both static and dynamic errors contribute
to frequency domain non-ideality
– Static: DNL,INL
– Dynamic: glitch impulse, aperture uncertainty, settling time, …
• We’ll look at these later, in the context of specific circuits
B. Murmann
EE315B - Chapter 3
2
Alphabet Soup of Spectral Metrics
•
SNR - Signal-to-noise ratio
•
SNDR (SINAD) - Signal-to-(noise+distortion) ratio
•
ENOB - Effective number of bits
•
DR - Dynamic range
•
SFDR - Spurious free dynamic range
•
THD - Total harmonic distortion
•
ERBW - Effective Resolution Bandwidth
•
IMD - Intermodulation
I t
d l ti distortion
di t ti
•
MTPR - Multi-tone power ratio
B. Murmann
EE315B - Chapter 3
3
DAC Tone Test/Simulation
B. Murmann
EE315B - Chapter 3
4
Typical DAC Output Spectrum
[Hendriks, "Specifying
y g Communications DACs, IEEE Spectrum, July
y 1997]
B. Murmann
EE315B - Chapter 3
5
ADC Tone Test/Simulation
B. Murmann
EE315B - Chapter 3
6
Discrete Fourier Transform Basics
•
DFT takes a block of N time domain samples (spaced Ts=1/fs)
and yyields a set of N frequency
q
y bins
X(k) 
N1
 x(n)e j2kn/N
n0
•
Bin k represents frequency content at k·fs/N [Hz]
•
DFT frequency
q
y resolution
– Proportional to 1/(N·Ts) in [Hz/bin]
– N·Ts is total time spent gathering samples
•
A DFT with N=2integer can be found using a computationally
efficient algorithm
– FFT = Fast Fourier Transform
EE315B - Chapter 3
B. Murmann
7
Matlab Example
clear;
N
50
= 100
100;
fs = 1000;
40
x = cos(2*pi*fx/fs*[0:N-1]);
s = abs(fft(x));
plot(s 'linewidth'
plot(s,
linewidth , 2);
DF
FT Magnitude
e
fx = 100;
30
20
10
0
0
20
40
60
80
100
Bin #
B. Murmann
EE315B - Chapter 3
8
Normalized Plot with Frequency Axis
N
= 100;
fs = 1000;
0
fx = 100;
FS = 1; % full-scale amplitude
s = abs(fft(x));
b (ff ( ))
% remove redundant half of spectrum
s = s(1:end/2);
% normalize magnitudes to dBFS
% dbFS = dB relative to full-scale
s = 20*log10(2*s/N/FS);
DFT M
Magnitude [dB
BFS]
x = FS*cos(2*pi*fx/fs*[0:N-1]);
-50
-100
-150
-200
-250
% frequency vector
-300
f = [0:N/2
[0:N/2-1]/N;
1]/N;
-350
0
plot(f, s, 'linewidth', 2);
0.1
xlabel('Frequency [f/fs]')
0.2
0.3
Frequency [f/fs]
0.4
0.5
ylabel('DFT Magnitude [dBFS]')
EE315B - Chapter 3
B. Murmann
9
Another Example
0
Same as before,, but
now fx=101
•
This doesn't look the
spectrum of a
sinusoid…
•
What's going on?
-10
DFT M
Magnitude [d
dBFS]
•
-20
-30
-40
-50
-60
-70
-80
-90
0
B. Murmann
EE315B - Chapter 3
0.1
0.2
0.3
Frequency [f/fs]
0.4
0.5
10
Spectral Leakage
•
DFT implicitly assumes that
data repeats every N samples
•
A sequence that contains a noninteger number of sine wave
cycles has discontinuities in its
periodic repetition
– Discontinuity looks like a
high frequency signal
component
– Power spreads across
spectrum
•
Two ways
y to deal with this
– Ensure integer number of
periods
– Windowing
EE315B - Chapter 3
B. Murmann
11
Integer Number of Cycles
0
N
= 100
100;
-50
fs = 1000;
fx = fs*cycles/N;
•
Usable test
f
frequencies
i are
limited to a multiple
of fs/N
DFT M
Magnitude [dB
BFS]
cycles = 9;
-100
-150
-200
-250
-300
-350
0
B. Murmann
EE315B - Chapter 3
0.1
0.2
0.3
Frequency [f/fs]
0.4
0.5
12
Windowing
•
Spectral leakage can be attenuated by windowing the time
samples prior to the DFT
•
Windows taper smoothly down to zero at the beginning and the
end of the observation window
•
Time domain samples are multiplied by window coefficients on a
sample-by-sample basis
– Means convolution in frequency
– Sine
Si wave tone
t
and
d other
th spectral
t l components
t smear outt
over several bins
•
Lots of window functions to chose from
– Tradeoff: attenuation versus smearing
•
Example: Hann Window
EE315B - Chapter 3
B. Murmann
13
Hann Window
N=64;
wvtool(hann(N))
Time domain
Frequency domain
50
1
0
Magnitude (dB)
Amplitu
ude
0.8
0.6
0.4
-50
-100
0.2
0
B. Murmann
10
20
30
40
Samples
50
60
-150
0
0.2
0.4
0.6
0.8
Normalized Frequency ( rad/sample)
EE315B - Chapter 3
14
Spectrum with Window
N
0
= 100;
No window
Hann window
f = 1000
fs
1000;
-20
A
= 1;
x = A*cos(2*pi*fx/fs*[0:N-1]);
s
= abs(fft(x));
x1 = x
x.*hann(N);
*hann(N);
s1 = abs(fft(x1));
DFT Magnitude [dBF
FS]
fx = 101;
-40
-60
-80
-100
-120
-140
0
0.1
0.2
0.3
0.4
0.5
f/fs
EE315B - Chapter 3
B. Murmann
15
Integer Cycles versus Windowing
•
Integer number of cycles
– Test signal falls into single DFT bin
– Requires
R
i
careful
f l choice
h i off signal
i
l ffrequency
– Ideal for simulations
– In lab measurements, can lock sampling and signal
f
frequency
generators
t
(PLL)
• "Coherent sampling"
•
Windowing
– No restrictions on signal frequency
– Signal and harmonics distributed over several DFT bins
• Beware of smeared out nonidealities…
– Requires more samples for given accuracy
•
More info
– http://www.maxim-ic.com/appnotes.cfm/appnote
p
pp
pp
_number/1040
B. Murmann
EE315B - Chapter 3
16
Example
•
Now that we've
"calibrated"
calibrated our test
system, let's look at
some spectra that
involve nonidealities
N
= 2048;
cycles = 67;
fs = 1000;
fx = fs*cycles/N;
LSB = 2/2^10;
%generate signal, quantize (mid-tread) and take FFT
•
First look at
quantization noise
introduced by an
ideal quantizer
x = cos(2*pi*fx/fs*[0:N-1]);
x = round(x/LSB)*LSB;
s
= abs(fft(x));
s = s(1:end/2)/N*2;
% calculate SNR
sigbin = 1 + cycles;
noise = [s(1:sigbin-1), s(sigbin+1:end)];
snr = 10*log10( s(sigbin)^2/sum(noise.^2) );
B. Murmann
EE315B - Chapter 3
17
Spectrum with Quantization Noise
2048 point FFT, SNR=61.90dB
0
•
Spectrum looks fairly uniform
•
Signal-to-quantization noise
ratio is given by power in
signal bin, divided by sum of
allll noise
i bi
bins
DFT Ma
agnitude [dB
BFS]
-20
-40
40
-60
-80
-100
100
-120
0
B. Murmann
EE315B - Chapter 3
0.1
0.2
0.3
Frequency [f/fs]
0.4
0.5
18
SQNR
2048 point FFT, SNR=61.90dB

Signal
g
Power
Quantization Noise Power
1  VFS 
2  2 
2
1  VFS 
12  2N 
2

-20
DFT Ma
agnitude [dBF
FS]
SQNR 
0
3 2N
2
2
 6.02  N  1.76 [dB]
 6.02  10  1.76 [[dB]]
-40
40
-60
-80
-100
100
 61.9 dB
-120
0
0.1
0.2
0.3
Frequency [f/fs]
0.4
EE315B - Chapter 3
B. Murmann
0.5
19
FFT Noise Floor
2048 point FFT, SNR=61.90dB
0
 61.9
61 9 dB
dBc  30
30.1
1 dB
 92 dBc
•
Depends on FFT size
•
Plot is “useless”
useless if FFT
size is not specified
-20
DFT Ma
agnitude [dBFS]
 2048 
Nfloor  61.9 dBc  10log 

 2 
-40
40
-60
-80
-100
100
-120
0
B. Murmann
EE315B - Chapter 3
0.1
0.2
0.3
Frequency [f/fs]
0.4
0.5
20
DFT Plot Annotation
•
DFT p
plots are fairly
y meaningless
g
unless yyou clearly
y specifiy
p
y the
underlying conditions
•
Most common annotation
– Specify
S
if how
h
many DFT points
i t were used
d (N)
•
Less common options
– Shift DFT noise floor by
y 10log
g10((N/2)dB
)
– Normalize with respect to bin width in Hz and express noise
as power spectral density
• "Noise
Noise power in 1 Hz bandwidth"
bandwidth
EE315B - Chapter 3
B. Murmann
21
Periodic Quantization Noise
Same as before, but cycles =
64 ((instead of 67))
•
fx = fs64/2048 = fs/32
•
Quantization noise is highly
deterministic and periodic
•
2048 point FFT, SNR=65.09dB
0
-20
For more random and "white"
quantizion noise,, it is best to
q
make N and cycles mutually
prime
– GCD(N,cycles)=1
( , y
)
DFT Ma
agnitude [dB
BFS]
•
-40
-60
-80
-100
-120
0
B. Murmann
EE315B - Chapter 3
0.1
0.2
0.3
Frequency [f/fs]
0.4
0.5
22
Typical ADC Output Spectrum
Fairly uniform noise floor due
to additional electronic noise
•
Harmonics due to
nonlinearities
•
Definition of SNR
SNR 
•
2048 point FFT, SNR=55.99dB
0
-20
Signal Power
Total Noise Power
Total noise power includes all
bins except DC, signal, and
2nd through
th
h 7th harmonic
h
i
– Both quantization noise
and electronic noise affect
SNR
DFT M
Magnitude [d
dBFS]
•
-40
40
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
Frequency [f/fs]
EE315B - Chapter 3
B. Murmann
23
SNDR and ENOB
Definition
SNDR 
•
•
Signal Power
Noise and Distortion Power
Noise and distortion power
includes all bins except DC
and signal
Effective number of bits
ENOB 
B. Murmann
2048 point FFT, SNR=55.9dB, SNDR=47.5dB
0
SNDR(dB) 1.76dB
SNDR(dB)-1.76dB
6.02dB
-20
DFT Magnitude [dBF
FS]
•
-40
-60
-80
-100
-120
0
EE315B - Chapter 3
0.1
0.2
0.3
0.4
Frequency [f/fs]
24
Effective Number of Bits
•
Is a 10-Bit converter with 47.5dB SNDR really a 10-bit
converter?
ENOB 
47.5dB  1.76dB
 7.6
6.02dB
•
We gett ideal
W
id l ENOB only
l ffor zero electronic
l t i noise,
i
perfect
f t
transfer function with zero INL, ...
•
Low electronic noise is costly
y
– Cutting thermal noise down by 2x, can cost 4x in power
dissipation
•
Rule of thumb for good power efficiency: ENOB < B-1
B1
– B is the "number of wires" coming out of the ADC or the so
called "stated resolution"
EE315B - Chapter 3
B. Murmann
25
Survey Data
SNRBits 
SNR(dB)-1.76dB
6.02dB
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on
Selected Areas in Communications, pp. 539-50, April 1999
B. Murmann
EE315B - Chapter 3
26
Dynamic Range
DR 
Maximum Signal Power
 SNRppeak
Minimum Detectable Signal
SNR
(dB)
OVERLOAD
PEAK SNR
FULL SCALE
0dB
DYNAMIC
RANGE
INPUT
Input
Power
AMPLITUDE
[dB]
(dB)
MDS
B. Murmann
EE315B - Chapter 3
27
SFDR
Definition of "Spurious Free
Dynamic Range"
Range
SFDR 
•
Signal Power
Largest Spurious Power
Largest spur is often (but not
necessarily) a harmonic of the
input tone
2048 point FFT, SFDR=48.3dB
0
-20
DFT M
Magnitude [dBFS]
•
-40
40
-60
-80
-100
-120
0
B. Murmann
EE315B - Chapter 3
0.1
0.2
0.3
0.4
Frequency [f/fs]
28
SDR and THD
•
Signal-to-distortion ratio
2048 point FFT, THD=-48.2dB
0
Signal Power
SDR 
Total Distortion Power
•
Total harmonic distortion
THD 
•
Total Distortion Power
1

Signal Power
SDR
By convention, total distortion
power consists of 2nd through 7th
harmonic
DFT M
Magnitude [dB
BFS]
-20
B. Murmann
-60
-80
-100
-120
0
Is there a 6th and 7th harmonic in
the plot to the right?
•
-40
40
0.1
0.2
0.3
0.4
Frequency [f/fs]
EE315B - Chapter 3
29
Lowering the Noise Floor
65536 point FFT, THD=-48.3dB
0
Increasing the FFT size let's
us lower the noise floor and
reveal low level harmonics
-20
DFT M
Magnitude [dBFS]
•
-40
40
-60
-80
-100
-120
0
B. Murmann
EE315B - Chapter 3
0.1
0.2
0.3
0.4
Frequency [f/fs]
30
Aliasing
65536 point FFT, THD=-48.3dB
Harmonics can appear at
"arbitrary" frequencies
due to aliasing
0
-20
DFT Ma
agnitude [dB
BFS]
•
f1 = fx = 0.3125 fs
f2 = 2 f1 = 0.6250 fs  0.3750 fs
f3 = 3 f1 = 0.9375 fs  0.0625 fs
f4 = 4 f1 = 1.2500 fs  0.2500 fs
f5 = 5 f1 = 1.5625 fs  0.4375 fs
-40
40
-60
-80
-100
-120
0
0.1
0.2
0.3
Frequency [f/fs]
EE315B - Chapter 3
B. Murmann
0.4
0.5
31
Intermodulation Distortion
Am
mplitude
f1
f2
SECOND
ORDER
PRODUCTS
f2 - f1
THIRD
ORDER
PRODUCTS
2f1 - f2
2f2 - f1
Frequency
•
f1 + f2
f
IMD is important in multi-channel communication systems
– Third order products are generally difficult to filter out
B. Murmann
EE315B - Chapter 3
32
MTPR
Amplitu
ude [dB]
0
MTPR
-20
-40
-60
-80
-100
-120
120
0.00E+00
4.00E+06
8.00E+06
1.20E+07
1.60E+07
2.00E+07
2.40E+07
2.80E+07
3.20E+07
Frequency(Hz)
Frequency [Hz]
•
Useful metric in multi-tone transmission systems
– E.g. OFDM
B. Murmann
EE315B - Chapter 3
33
Frequency Dependence (1)
•
All of the above discussed metrics generally depend on frequency
– Sampling
p g frequency
q
y and input
p frequency
q
y
[[Analog
g Devices,, AD9203 Datasheet ]
B. Murmann
EE315B - Chapter 3
34
Frequency Dependence (2)
[T
[Texas
Instruments,
I t
t ADS5541 Datasheet
D t h t]
B. Murmann
EE315B - Chapter 3
35
ERBW
•
Defined as the input
p frequency
q
y at which the SNDR of a
converter has dropped by 3dB
– Equivalent to a 0.5-bit loss in ENOB
•
ERBW > fs/2 iis nott uncommon, especially
i ll iin converters
t
designed for sub-sampling applications
B. Murmann
EE315B - Chapter 3
36
Relationship Between INL and SFDR
•
At low input frequencies, finite SFDR is mostly due to INL
•
Quadratic/cubic bow gives rise to second/third order harmonic
•
Rule of thumb: SFDR  20log(2B/INL)
– E.g. 1 LSB INL, 10 bits  SFDR  60dB
Output
Ideal
Quadratic bow
Cubic bow
Input
B. Murmann
EE315B - Chapter 3
37
SNR Degradation due to DNL (1)
[Source: Ion Opris]
•
For an ideal
F
id l quantizer
ti
we assumed
d uniform
if
quatization
ti ti error
over /2
•
Let's add uniform DNL over  0.5 LSB and repeat math...
B. Murmann
EE315B - Chapter 3
38
SNR Degradation due to DNL (2)
•
Integrate triangular pdf

e 2
2
0
•
e  e2
2

 1     de  6


 SNR  6.02  B  1.25 [dB]
3dB
dB
Compare to ideal quantizer
 /2
e2
2
e  
de 

12
 /2
2
•
 SNR  6
6.02
02  B  1
1.76
76 [dB]
Bottom line: non-zero DNL across many codes can easily cost a
few dB in SNR
– "DNL noise"
B. Murmann
EE315B - Chapter 3
39
Nyquist Rate DACs
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 4
1
Overview
•
D/A conversion is typically
yp
y accomplished
p
through
g the division or
multiplication of a reference voltage, current or charge
•
Architectures
– Thermometer
Th
t
– Binary weighted
– Segmented
•
Static performance
– Limited by component matching
•
Dynamic performance
– Limited e.g. by timing errors, "glitches"
B. Murmann
EE315B - Chapter 4
2
Resistor String DAC
VRE F



MSB



LSB
xxxxx
d0
d0
xxxxx
d1
d1
d2
d2
OUT
B. Murmann
•
Simple,
p inherently
y
monotonic
•
Small area up to ~8 bits
•
See e.g. Pelgrom,
JSSC 12/1990
•
Unsuitable for highresolution, high-speed
designs
EE315B - Chapter 4
3
Thermometer DAC Using Switched Currents
•
Advantages
– Monotonicity ensured by
turning on equal-weighted
current sources in succession
– Fast: timing glitches
proportional to step size do not
degrade DNL
•
– Impractical for large B (ie high
resolution)) due to large
g area
taken up by current sources
– Requires large decoder with 2B1 outputs
Binary-to-Thermometer Decoder
B. Murmann
Disadvantages
EE315B - Chapter 4
4
Thermometer DAC Principle
15
Output
0
14
14
13
3
13
3
13
3
12
12
12
12
11
11
11
11
11
10
10
10
10
10
10
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input Code
B. Murmann
EE315B - Chapter 4
5
Binary Weighted DAC
•
Advantages
– Area-efficient
– No decoder needed
•
Disadvantages
– Monotonicity is not guaranteed:
2k-1 source must match sum of
( ) to within 1 LSB to
1-to-2(k-1)
make transition monotonic
– Timing glitches introduce DNL
 MSB transition is “worst case”
B. Murmann
EE315B - Chapter 4
6
Binary Weighted DAC Principle
MSB Transition
Problem
B. Murmann
EE315B - Chapter 4
7
Implementation of Weighted Elements
B. Murmann
EE315B - Chapter 4
8
Segmented DAC
Thermometer
MSB Section
(+ Decoder)
B. Murmann
•
Binary weighted
section with Bb bits
•
Thermometer section
with Bt = B-Bb bits
•
Typically Bt ~ 4…8
•
Reasonably small
decoder
•
Easier to achieve
monotonicity
EE315B - Chapter 4
9
Segmented DAC (2-2)
Transition
Problem Limited
to LSB Section
B. Murmann
EE315B - Chapter 4
10
Static Errors (1)
•
DNL and INL due to unit element mismatch
•
Systematic Errors
– Contact and wiring resistance (IR drop)
– Edge effects in unit element arrays
– Process gradients
– Finite current source output resistance
•
Systematic errors can be mitigated by proper layout and
switching sequence design
– See e.g. [Lin, JSSC 12/98], [Van der Plas, JSSC 12/99]
B. Murmann
EE315B - Chapter 4
11
Mitigating IR Drop
B. Murmann
EE315B - Chapter 4
12
Static Errors (2)
•
In the best possible scenario, we are then limited by “random” errors,
which
hi h are d
due tto material
t i l roughness,
h
randomness
d
iin etching,
t hi
etc.
t
•
The distribution of random errors is usually well approximated by a
Gaussian PDF (central limit theorem)
•
References
– C. Conroy et al., “Statistical Design Techniques for D/A
Converters,” IEEE J. Solid-State Ckts., pp. 1118-28, Aug. 1989.
– P.
P Crippa,
Crippa et al
al., "A
A statistical methodology for the design of highhigh
performance CMOS current-steering digital-to-analog converters,"
IEEE Trans. CAD of ICs and Syst. pp. 377-394, Apr. 2002.
EE315B - Chapter 4
B. Murmann
13
Gaussian Distribution
f(x) 
1
2
e

 x  2
2 2
X
x

04
0.4
f(x)
0.3
0.2
0.1
0
-3
B. Murmann
-2
-1
0
x/X
EE315B - Chapter 4
1
2
3
14
Yield (1)
P  C  X  C  
1
2
C  X
e 2

2  C
 C 
dX  erf 

 2
1
P(-C
C)
P(-X ≤ xX ≤+X)
0.8
0.6
0.4
02
0.2
0
0
0.5
1
1.5
X/
2
2.5
3
C
EE315B - Chapter 4
B. Murmann
15
Yield (2)
C
P(-C  X  C) [%]
C
P(-C  X  C) [%]
0.2000
15.8519
2.2000
97.2193
0.4000
31.0843
2.4000
98.3605
0.6000
45.1494
2.6000
99.0678
0.8000
57.6289
2.8000
99.4890
1.0000
68.2689
3.0000
99.7300
1.2000
76.9861
3.2000
99.8626
1.4000
83.8487
3.4000
99.9326
1 6000
1.6000
89 0401
89.0401
3 6000
3.6000
99 9682
99.9682
1.8000
92.8139
3.8000
99.9855
2.0000
95.4500
4.0000
99.9937
B. Murmann
EE315B - Chapter 4
16
Example
•
Measurements show that the current in a production lot of
current sources follows a Gaussian distribution with  = 0.1 mA
and
d =
 10 mA
A
– What fraction of current sources is within 3% (or 1%) of
the mean?
•
Relative matching ("coefficient of variation")
u 

 I  0.1mA
 stdev   
 1%

 I  10mA
•
Fraction of current sources within 3%
– C = 3  99.73%
•
Fraction of current sources within 1%
– C = 1  68.27%
EE315B - Chapter 4
B. Murmann
17
Mismatch in MOS Current Sources
V1
V2=V1
I1
VB

•
I2
Vt
M1
I  I1  I2  gm Vt  I1
g
I

  m Vt 

I1
I1
M2
1
W
Cox
2
L


Vt 
A Vt
WL
  

A
WL
Example
– W=500m, L=0.2m, gm/ID=10S/A, AVt=5mV-m, A=1%-m
2
2
 S 5mV   1% 
 I   10 


A 10   10 

I
 0.5%2   0.1%2
 0.51%
1
B. Murmann
EE315B - Chapter 4
18
DNL of Thermometer DAC
DNL(k) 
Step(k)  Stepavg
Stepavg
Ik 

1 N
I
N j 1 j
N
1
I
N j 1 j

Ik  I I

I
I
 I 
stdev DNL(k)   stdev    u
 I 
•
Standard deviation of DNL for each code is simply equal to
relative matching (u) of unit elements
•
a pe
Example
– Say we have unit elements with u = 1% and want 99.73% of
all converters to meet the spec
– Which DNL specification value should go into the datasheet?
B. Murmann
EE315B - Chapter 4
19
DNL Yield Example (1)
•
First cut solution
– For 99.73% yield, need C = 3
– DNL = u = 1%
– 3 DNL = 3%
– DNL specification for a yield of 99.73% is 0.03 LSB
• Independent of target resolution (?)
•
Not quite right
– Must keep in mind that a converter will meet specs only if all
codes meet DNL spec, i.e. DNL(k) < DNLspec for all k
– A converter with more codes is less likely to have all codes
meet the specification
– Let's see if this is significant
B. Murmann
EE315B - Chapter 4
20
DNL Yield Example (2)
•
Let's say there are N codes, and assume that all DNL(k) values
are independent, then
– P(all codes meet spec) = P(single code meets spec)N
– P(all codes meet spec)1/N = P(single code meets spec)
•
Lets look at two examples N=63 (6 bits) and N=4095 (12 bits)
– 0.99731/63 = 0.99995708…
– 0.99731/4095 = 0. 99999929929…
•
Can calculate modified confidence intervals using Matlab
– For N=63, C = sqrt(2)*erfinv(0.99731/63) = 4.09
– For N=4095, C = sqrt(2)*erfinv(0.99731/4095) = 4.97
•
Refined
R
fi d result
lt ffor 99
99.97%
97% yield
i ld
– N=63: DNL spec should be 0.0409 LSB
– N=4095: DNL spec should be 0.0497 LSB
B. Murmann
EE315B - Chapter 4
21
DNL Yield Example (3)
•
Getting a more accurate yield estimate for the preceding
example wasn't all that hard
– Unfortunately things won't always be that simple
• E.g. in a segmented DAC, DNL(k) are no longer independent
•
The "typical"
typical DAC designer tends to rely on simulations rather
than trying to formulate "exact" yield equations
– Get rough estimate using simple (often optimistic)
expressions
– Run "Monte Carlo" simulations in Matlab to find actual yield
or to center specs
– Still important to have a qualitative feel for what may cause
discrepancies
B. Murmann
EE315B - Chapter 4
22
INL of Thermometer DAC (1)
INL(k) 
Iout (k)  Iout,uniform (k)
Stepavg
k
 Ij 


j 1
k N
I
N j 1 j
N
1
I
N j 1 j
k
N Ij

j 1
k
k
N
j 1
j k 1
 Ij  
Ij
A N
k
A B
 A N

 A 
 X
var INL(k)   var 
 k   N2 var 
 N2 var  

 A B

 A B
Y
B. Murmann
EE315B - Chapter 4
23
INL of Thermometer DAC (2)
•
For a quotient of random variables
2
2
cov  X,
X Y 
2
 X   
var     X   2X  2Y  2

 X Y 
 Y    Y    X  Y
[Dennis E
E. Blumenfeld
Blumenfeld, Operations Research Calculations Handbook
Handbook, Online:
http://www.engnetbase.com/ejournals/books/book_summary/toc.asp?id=701]
•
After identifying the means (), variances () and covariance
( ) needed in the abo
(cov)
above
e appro
approximation,
imation it follo
follows
s that
k

var INL(k)   k  1   u2
 N
k

INL (k)  u k  1  
 N
B. Murmann
EE315B - Chapter 4
24
INL of Thermometer DAC (3)
INL (k)/
u
6
N=64
N=128
4
2
0
0
20
40
60
80
100
120
140
k
•
St d d deviation
Standard
d i ti off INL iis maximum
i
att mid-scale
id
l (k
(k=N/2)
N/2)
INL  u
•
N N/ 2 1
1
 u N  u 2B
1


2
N  2
2
For a more elaborate derivation of this result see
[Kuboki et al.,
al IEEE Trans.
Trans Circuits & Systems
Systems, 6/1982]
EE315B - Chapter 4
B. Murmann
25
Achievable Resolution
   2 
 

B  log
g2 4  INL    2  2log
g2  INL 



 u 
  u  
•
Example: INL= 0
0.1
1 LSB (at mid
mid-scale
scale code)
B. Murmann
u
B
1%
8.6
0.5%
10.6
0.2%
13.3
0.1%
15.3
EE315B - Chapter 4
26
INL Yield
•
Again, we should ask how many DACs will meet the spec for a
given INL (worst code)
– It turns out that this is a very difficult math problem
•
Two solutions
– Do the math
• G. I. Radulov et al., "Brownian-Bridge-Based Statistical
Analysis of the DAC INL Caused by Current Mismatch," IEEE
TCAS II, pp
pp. 146-150, Feb. 2007.
– Yield simulations
•
Good rule of thumb
– For
F high
hi h ttargett yield
i ld ((>95%),
95%) the
th probability
b bilit off ""allll codes
d
meet INL spec" is very close to "worst code meets INL spec"
EE315B - Chapter 4
B. Murmann
27
DNL/INL of Binary Weighted DAC
•
INL same as for thermometer DAC
– Why?
•
DNL is not same for all codes, but depends on transition
•
Consider worst case: 0111 …  1000 …
– Turning on MSB and turning off all LSBs






2
DNL
 2B 1  1 u2  2B 1 u2  2B  1 u2


 

0111...
•
1000...
8I
4I
2I
I
Example
E
l
– B = 12, u = 1%  DNL = 0.64 LSB
– Much worse than thermometer DAC
B. Murmann
EE315B - Chapter 4
28
DNL (4-bit Example)
15
2  )22
( DNL
D NL //
u
10
5
0
0
2
4
6
8
DAC input code
10
12
14
code
EE315B - Chapter 4
B. Murmann
29
Simulation Example
DNL [in LSB]]
2
1
DNL and INL of 12 Bit converter (from converter decision thresholds)
+0.1
1 LSB,
LSB avg=-9
avg=-9.3e-005,
3e-005 std
std.dev=0.035,
dev=0 035 range=1
range=1.4
4
-1.3
1-13 / +0
0
-1
-2
500
1000
1500
2000
bin
code
2500
3000
3500
4000
INL [in LSB]
2
1
0
-1
B. Murmann
-0.8 / +0.8 LSB, avg=-1.1e-013, std.dev=0.37, range=1.6
500
1000
1500
2000
bin
code
2500
EE315B - Chapter 4
3000
3500
4000
30
Another Random Run
DNL [in L
LSB]
2
1
DNL and INL of 12 Bit converter (from converter decision thresholds)
-0.9 / +0.4 LSB, avg=-7.5e-005, std.dev=0.039, range=1.3
0
-1
500
1000
1500
2000
2500
3000
3500
4000
bin
code
INL [in L
LSB]
2
1
-0.7 / +0.7 LSB, avg=3.3e-014, std.dev=0.33, range=1.3
0
-1
500
1000
1500
2000
2500
3000
3500
4000
bin
code
• Peak DNL not at mid-scale!
– Important to realize that this is just one single statistical
outcome…
EE315B - Chapter 4
B. Murmann
31
Multiple Simulation Runs (100)
Overlay Plot
RMS DNL and INL
[Lin & Bult, JSSC 12/1998]
B. Murmann
EE315B - Chapter 4
32
DNL/INL of Segmented DAC
•
INL
– Same as in thermometer
DAC
•
DNL
– Worst case occurs when
LSB DAC turns off and
one more MSB DAC
element turns on
– Essentially same DNL as
a binary weighted DAC
with Bb+1 bits
Example: B=Bb+Bt=4+4=8
16I
16I
8I
4I
16I
2I
I
EE315B - Chapter 4
B. Murmann
33
Comparison
Thermometer
INL

(worst case)
DNL
(worst case)
Number of
Switched
Elements
B. Murmann
Segmented
Binary
Bi
Weighted
1
u 2B
2
 u
 u 2Bb 1  1
 u 2B  1
2B  1
Bb  2Bt  1
B
EE315B - Chapter 4
34
Example (B=12, u=1%)
INL
DNL
(worst)
(worst)
Number of
Switched
Elements
Thermometer
0.32
0.01
4095
Binary Weighted
0.32
0.64
12
Segmented (Bb=7, Bt=5)
0.32
0.16
38
DAC Architecture
B. Murmann
EE315B - Chapter 4
35
Dynamic DAC Errors (1)
•
Finite settling time and slewing
– Finite RC time constant
– Signal dependent slewing
•
Feedthrough
– Coupling from switch signals to DAC output
– Clock feedthrough
•
Glitches due to timing
g errors
– Current sources won’t switch simultaneously
•
Dynamic DAC errors are generally hard to model!
B. Murmann
EE315B - Chapter 4
36
Dynamic DAC Errors (2)
•
References
– Gustavsson, Chapter 12
– M. Albiol, J.L. Gonzalez, E. Alarcon, "Mismatch and dynamic
modeling of current sources in current-steering CMOS D/A
converters," IEEE TCAS I, pp. 159-169, Jan. 2004
– Doris, van Roermund, Leenaerts, Wide-Bandwidth High
Dynamic Range D/A Converters, Springer 2006.
– T. Chen and G.G.E. Gielen, "The analysis
y
and improvement
p
of a current-steering DAC's dynamic SFDR," IEEE Trans.
Ckts. Syst. I, pp. 3-15, Jan. 2006.
EE315B - Chapter 4
B. Murmann
37
Glitch Impulse (1)
•
DAC output waveform depends on timing
– Consider binary weighted DAC transition 0111…  1000…
ideal
10
Ideal
5
0
1
1.5
2
2.5
3
earlyy
10
LSB early,
LSBs
l MSB llate
t
5
0
1
1.5
2
2.5
3
late
10
LSBs late, MSB early
5
0
B. Murmann
1
15
1.5
2
Time
25
2.5
EE315B - Chapter 4
3
38
Glitch Impulse (2)
•
Worst case glitch impulse (area): t 2B-1
•
LSB area: T
•
Need t 2B-1 << T which implies t << T/2B-1
B. Murmann
fs [MHz]
B
t [ps]
1
12
<< 488
20
16
<< 1.5
1000
10
<< 2
EE315B - Chapter 4
39
Commercial Example
B. Murmann
EE315B - Chapter 4
40
How to minimize dynamic DAC errors?
•
Differential pair switch
•
Retiming
– Latches in (or close to) each current cell
– Latch controlled by global clock to ensure that current cells switch
simultaneously (independent of decoder delays)
•
Make before break
– Ensure uninterrupted current flow, so that tail current source
remains active
•
Low swing driver
– Drive differential pair with low swing to minimize coupling from
control signals to output
•
Cascoded tail current source for high output impedance
– Ensures that overall impedance
p
at output
p nodes is code
independent (necessary for good INL)
B. Murmann
EE315B - Chapter 4
41
Basic Differential Pair Switch
B. Murmann
EE315B - Chapter 4
42
Make-Before-Break Driver
EE315B - Chapter 4
B. Murmann
43
Example Current Cell Implementation
[Barkin & Wooley, JSSC 4/2004]
• Differential pair switch
• Make-before-break driver
• Low swing driver
• Cascoded tail current source
B. Murmann
EE315B - Chapter 4
44
Binary Weighted Charge Redistribution DAC
CP (top plate parasitic)
+
2N–1 C
8C
4C
2C
C
C VOUT
–
VRE F
b1
(msb)
bN–3
bN–2
Vout 
•
bN–1
2B C
2 C  Cp
B
bN
(lsb)
B
Vref 
bi
i
i 1 2
Can redistribute charge onto OTA + feedback capacitor to
mitigate
iti t gain
i error due
d tto Cp
B. Murmann
EE315B - Chapter 4
45
Segmented Charge Redistribution DAC
B. Murmann
EE315B - Chapter 4
46
Serial Charge Redistribution DAC
B. Murmann
EE315B - Chapter 4
47
Implementation Example Segmented DAC
[T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, “An 80-MHz 8bit CMOS D/A Converter,
Converter,” IEEE J. of Solid-State
Solid State Circuits, pp. 983-988,
983 988, Dec. 1986.]
B. Murmann
EE315B - Chapter 4
48
High Performance DAC Examples (1)
100MHz
1GHz
[V d
[Van
den B
Bosch,
h JSSC 3/2001]
B. Murmann
EE315B - Chapter 4
49
High Performance DAC Examples (2)
[[Schafferer,, ISSCC 2004]]
B. Murmann
EE315B - Chapter 4
50
High Performance DAC Examples (3)
[Schafferer, ISSCC 2004]
B. Murmann
EE315B - Chapter 4
51
High Performance DAC Examples (4)
[Lin, ISSCC 2009]
B. Murmann
EE315B - Chapter 4
52
Sample & Hold Circuits
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 5
1
Recap
•
How to build circuits that "sample"?
•
Ideal Dirac sampling is impractical
– Need a switch that opens, closes and acquires signal within
an infinitely small time
•
Practical solution
– "Track and hold"
B. Murmann
EE315B - Chapter 5
2
Outline
•
Elementaryy track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques
– Clock bootstrapping
– Bottom plate sampling
•
Settling
S
ttli and
d noise
i analysis
l i iin charge-redistribution
h
di t ib ti
track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
3
Ideal Track-and-Hold Circuit
B. Murmann
EE315B - Chapter 5
4
Signal Nomenclature
time
Continuous Time Signal
T/H Signal
("Sampled Data Signal")
Clock
Discrete Time Signal
B. Murmann
EE315B - Chapter 5
5
Circuit with MOS Switch
“Pedestal Error”
B. Murmann
EE315B - Chapter 5
6
Nonidealities
•
Non-zero acquisition
q
time / finite bandwidth
•
Thermal noise
•
Aperture uncertainty / clock jitter
•
Signal dependent sampling instant
•
Tracking nonlinearity
•
Hold mode feedthrough
•
Hold mode leakage
•
Charge injection and clock feedthrough
EE315B - Chapter 5
B. Murmann
7
Non-zero Acquisition Time
•
Consider various input
p signal
g
scenarios
1. Input is a sampled data signal, i.e. the
output of another switched capacitor stage
2. Input is a slowly varying continuous time
signal,
s
g a,e
e.g.
g the
e input
pu o
of a
an o
oversampling
e sa p g
ADC
3. Input is a rapidly varying continuous time
signal e
signal,
e.g.
g the input of a Nyquist or sub
subsampling ADC
B. Murmann
EE315B - Chapter 5
8
Non-zero Acquisition Time – Case 1
•
For simplicity, neglect finite rise time of the input signal
•
Consider worst case – the output is required to settle from 0 to
the full-scale voltage of the system (VFS)
First order MOS switch model
  RC

 Vout (t)  VFS 1  e t / 

EE315B - Chapter 5
B. Murmann
9
Non-zero Acquisition Time – Case 1
Ts

 Ts 
2
Vout,err
V
e


,
FS
 2 
 
•
/
  VFS eN
Typically think about settling error in terms of the number of settling
time constants (N) required for ½ LSB settling in a B
B-bit
bit system
 VFS e
N
B. Murmann
N
1 VFS

2 2B

Ts / 2
 ln 2  2B


EE315B - Chapter 5
B
N
6
>4.9
10
>7.6
14
>10.4
18
>13.2
10
Non-zero Acquisition Time – Case 2 & 3
•
Consider a sinusoidal input around “0”, and “0” also as the initial
condition for Vout (for notational simplicity)
Vin (t)  A cos(t  )
Vout ((t))  
A cos(  )
e

t

2 2
1 




initial transient

A cos(t    )
1

2 2 

steady-state response
  atan(()
B. Murmann
EE315B - Chapter 5
11
Non-zero Acquisition Time – Case 2 & 3
•
At t=Ts/2,, the error in the held signal
g
consists of two p
parts
•
Residual error due to initial exponentially decaying initial
transient term
– In
I order
d tto minimize
i i i thi
this error, we need
d tto chose
h
N
appropriately, as calculated for the step input scenario
•
Error due to magnitude attenuation and phase shift in the steady
state term
– This error depends only on the RC time constant and the
input frequency; it cannot be reduced by extending the
length of the track phase
– How significant is the error due to the steady-state term?
B. Murmann
EE315B - Chapter 5
12
Non-zero Acquisition Time – Case 2 & 3
•
As an example, let’s compute the percent amplitude error for the
N values derived previously (½ LSB, B-bit settling to a step)
A
1    
A err 
2
A
 1
A
1
1    
2
1
 1
T /2

1   2fin s
N 

2
1
 1
f 
1   in 
 N fs 
B
N
Aerr (fin = fs/20)
Aerr (fin = fs/2)
6
4.9
0.052%
4.9%
10
76
7.6
0 021%
0.021%
2 1%
2.1%
14
10.4
0.011%
1.1%
18
13.2
0.007%
0.7%
EE315B - Chapter 5
B. Murmann
2
13
Summary – Non-zero Acquisition Time
•
Precise settling to an input step is accomplished within 5…13
RC time constants (depending on precision)
•
Precise tracking of a high-frequency continuous time input
signal tends to impose more stringent requirements
– Number
N b tto remember:
b ~1%
1% attenuation
tt
ti error att N
Nyquist
i t
(fin=fs/2) for N ~10
•
In applications where attenuation is tolerable, the RC time
constant requirements then tend to follow from the distortion
specs
– The larger the attenuation, the larger the instantaneous
voltage drop across the (weakly nonlinear) MOSFET 
undesired harmonics
• More later
B. Murmann
EE315B - Chapter 5
14
Thermal Noise
•
Sample values Vout(n) correspond to instantaneous values of the
track mode noise process
var  Vout (n) 
2
v out,tot
2

1
kT
  4kTR 
df 
1  j2f  RC
C
0
EE315B - Chapter 5
B. Murmann
15
Implications of kT/C Noise
•
Example: suppose we make the kT/C noise equal to the
quantization noise of a B-bit ADC
kT  2

,
C 12

VFS
2B

 2B 
C  12kT 
 V 
 FS 
2
•
For a given B, both C and R (via N on slide 10) are fully determined
•
Example numbers for VFS=1V and fs=100MHz:
B
8
10
12
14
16
18
B. Murmann
C [pF]
0.003
0.052
0.834
13.3
213
3,416
,
EE315B - Chapter 5
R []
246,057
12,582
665
36
1.99
0.11
16
Commercial Example
EE315B - Chapter 5
B. Murmann
17
Aperture Uncertainty
•
In any sampling circuit, electronic noise causes random timing
variations in the actual sampling clock edge
– Adds "noise" to samples, especially if dVin/dt is large
in
•
in
Vin 
dVin
 t
dt
Analysis
– Consider sine wave input signal
– Assume t is random with zero mean and standard deviation t
B. Murmann
EE315B - Chapter 5
18
Analysis
 dV 2

 dV 2 
E Vin2  E  in   t 2   E  in    E t 2
dt 
dt  




 
 
2
 d
1
2
 
 E  A cos  2  fin  t     2t   2  A  fin   2t
dt
2
 

1 2


A




1
2
SNRaperture [dB]  10  log
l 
 20  log
l 


1
 2  fin  t 
  2  A  fin  t 2 
2

•
For an input signal whose power is evenly distributed between
0…fs/2, the above result improves by 4.8 dB
– See e.g.
g [[Da Dalt,, TCAS1,, 9/2002]]
EE315B - Chapter 5
B. Murmann
19
Result
1.E+11
1.E+10
fin [Hz]
1.E+09
t = 0.1ps
1.E+08
t = 1ps
1.E+07
t = 10ps
1.E+06
1.E+05
10
20
30
40
50
60
70
80
90
100
110
120
SNRaperture [dB]
B. Murmann
EE315B - Chapter 5
20
ADC Performance Survey (ISSCC & VLSI 97-10)
Data: http://www.stanford.edu/~murmann/adcsurvey.html
BW [Hz]
B
1.E+11
ISSCC
SSCC 2010
0 0
1.E+10
VLSI 2010
1.E+09
VLSI 1997-2009
1.E+08
Jitter=0.1psrms
ISSCC 1997-2009
Jitter=1psrms
1.E+07
1.E+06
1.E+05
1 E 04
1.E+04
1.E+03
10
20
30
40
50
60
70
80
90
100
110
120
SNDR [dB]
EE315B - Chapter 5
B. Murmann
21
Voltage Dependence of Switch
ID(triode)  Cox
RON
 dI
D(triode)

 dVDS

RON 
•
V 
W
VGS  Vt  DS  VDS

L 
2 
Cox



VDS  0 
1
1

Cox
W
 V  Vt 
L GS
1
W
   Vin  Vt 
L
Two problems
– Transistor turn off is signal dependent, occurs when =Vin+Vt
– RON is modulated by Vin (assuming e.g. =VDD=const.)
B. Murmann
EE315B - Chapter 5
22
Signal Dependent Sampling Instant (1)
()
[Razavi, Data Conversion System Design, p.17]
Tf
•
Must make fall time of sampling clock (Tf) much faster than
maximum dVin/dt
EE315B - Chapter 5
B. Murmann
23
Signal Dependent Sampling Instant (2)
•
Distortion analysis result (see Yu, TCAS II, 2/1999]
HD3 
Amplitude of third harmonic
Amplitude of fundamental

3 A
 
Tf 
8  VCK

•
2
Example: VCK = 1.8V, A = 0.5V, Tf = 100ps, = 2100MHz
2
HD3 
B. Murmann
3  0.5

 2100  106  100  1012   79dB

8  1.8

EE315B - Chapter 5
24
Track Mode Nonlinearity
[Razavi Data Conversion System Design
[Razavi,
Design, p
p.16]
16]
•
Output tracks well when input voltage is low
– Gets distorted when voltage is high due to increase in RON
EE315B - Chapter 5
B. Murmann
25
Analysis
ID  K  VGS  Vt  VDS 
C
K 2
VDS
2
dVout
K
2
 K    Vout  Vt  Vin  Vout    Vin  Vout 
dt
2
•
"All" we need to do is solve the above differential equation…
•
Can use Volterra Series analysis
– General method that allows us to calculate the frequency
domain response of nonlinear circuits with memory
– See e.g. Stanford EE214
•
Luckily someone has already done this for us
– See [Yu, TCAS II, 2/1999]
B. Murmann
EE315B - Chapter 5
26
Result
HD3 
Amplitude of third harmonic
Amplitude of fundamental
2
2

 fin 
1
A
1
A
 

    

4  VGS  Vt 
4  VGS  Vt  fs N
•
VGS is the "quiescent point" value of the gate-source voltage; i.e.
in the zero crossing of the sine input
•
For low distortion
– Make amplitude smaller than VGS-Vt
• Low swing
g  bad for SNR
– Make 1/ much larger than  (input frequency)
• Big switch  may cost lots of power to drive, comes with large
parasitic capacitances
p
p
EE315B - Chapter 5
B. Murmann
27
Numerical Example
•
Parameters
– VDD = VCK = 1.8V
1 8V
– Signal is centered about VDD/2 = 0.9V
– VGS-Vt = 1.8V-0.9V-0.45V = 0.45V
– A = 0.2V
– N = 0.5Ts/ = 10
– fin
i = fs/2
2
HD3 
•
1  0.2  1 

 42dB
4  0.45  2 10
Not all that great…
B. Murmann
EE315B - Chapter 5
28
Hold Mode Feedthrough
[Razavi, Data Conversion System Design, p.17]
CDS
•
Want to make Rout as small as possible
•
Consider using a “T-switch” when holdmode feedthrough is a problem
B. Murmann
EE315B - Chapter 5
29
Hold Mode Leakage
Example:
B. Murmann
EE315B - Chapter 5
30
Gate Leakage Data
A. Annema, et al., “Analog circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits, pp. 132-143, Jan. 2005.
•
•
In 65nm CMOS, gate capacitance droop rate is ~1V/s (!)
Issue is solved with high-k
high k dielectrics in post-65nm
post 65nm technologies
B. Murmann
EE315B - Chapter 5
31
Charge Injection and Clock Feedthrough
“Pedestal Error”
•
Analyze two extreme cases
– Very large Tf (“slow gating”)
– Very small Tf (“fast gating”)
B. Murmann
EE315B - Chapter 5
32
Slow Gating

H
VIN + V T
V IN
t
L
HOLD
O
VO
VIN
ýV
V
t
toff
•
All channel charge has disappeared by toff without introducing
error; it is absorbed by the input source
EE315B - Chapter 5
B. Murmann
33
Slow Gating Model for t > toff
Vout  Vin  Vout
Vout  Vin 

Col
 Vin  Vt  L   Vin 1     Vos
Col  C
Col
Col  C
Vos  
Gain Error
•
Col
 Vt  L 
Col  C
Offset Error
Example: C=1pF, L=0V, Vt=0.45V, W=20m, Col’=0.1fF/m, Col=2fF
  0.2%
B. Murmann
Vos  0.9mV
EE315B - Chapter 5
34
Fast Gating


•
Channel charge
cannot change
instantaneously
•
Resulting surface
potential decays via
charge flow to source
and drain
•
Charge divides
between source and
drain depending on
impedances loading
these nodes
H
VIN + VT
Surface
Potential
t
Qch
S
L
t < to
VO
V IN
S
ýV
V
t > to
t


1
1
Q
1-Q
2 chch
Qch
Q
2 ch
EE315B - Chapter 5
B. Murmann
35
Fast Gating Model for t > toff
Vout  Vin  Vout  Vin 1     Vos
Vout  Vin 
Col
1Q
 H  L   ch
Col  C
2 C
Assuming 50/50
charge split
Qch   WLCox  H  Vin  Vt 

•
1 WLCox
2
C
Vos  
Col
1 WLCox
 H  L  
 H  Vt 
Col  C
2
C
Example: C=1pF,
C 1pF, H-
L=1.8V,
1.8V, Vt=0.45V,
0.45V, W
W=20m,
20m, LCox=2fF/m
2fF/m
Col’=0.1fF/m, Col=2fF
  2%
B. Murmann
Vos  30.6mV
EE315B - Chapter 5
36
Transition Fast/Slow Gating
Fast gating
Slow gating
Fast gating
| |
Slow gating
|Vos|
TtFf
TtfF
•
|| and |Vos| decrease as the fall time of Tf) increases and
approach
pp
the limit case of slow g
gating
g
•
Unfortunately, high-speed switched capacitor circuits tend to
operate in fast gating regime
EE315B - Chapter 5
B. Murmann
37
Speed/Accuracy Trade Off
V 
1 Qch
2 C
1
R
Cox
•
T
1
BW
  s1/ =N1/(RC)
 RC
2fs
2
W
 V  Vt 
L GS

L2
Qch
V
L2
N
fs

BW
Charge
g injection
j
error to speed
p
ratio benefits from shorter
channels and increases in mobility (e.g. due to strain)
B. Murmann
EE315B - Chapter 5
38
Outline
•
Elementaryy track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques
– Clock bootstrapping
– Bottom plate sampling
•
Settling
S
ttli and
d noise
i analysis
l i iin charge-redistribution
h
di t ib ti
track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
39
Improvements
•
Charge
g cancellation
– Try to cancel channel charge by injecting a charge packet
with opposite sign
•
Differential
Diff
ti l sampling
li
– Use a differential circuit to suppress offset
•
CMOS switch
– Try to balance the nonidealities of NMOS device with a
parallel PMOS
B. Murmann
EE315B - Chapter 5
40
Charge Cancellation
Q1  0.5Q
0 5Qch1
h1  Qol1
l1
Q2  Qch2  2Qol2  0.5Qch1  Qol1
Q1  Q2  0
[Eichenberger and Guggenbűhl, JSSC 8/89]
•
Cancellation is never perfect, since channel charge of M1 will not
exactly split 50/50
– E.g.
E g if Rs is very small
small, most of M1’s
M1 s channel charge will flow
toward the input voltage source
•
Not a precision technique, just an attempt to do a partial clean-up
EE315B - Chapter 5
B. Murmann
41
Differential Sampling (1)

VO1
+
VI1
C
CH
VIC 
–
VO2
+
VI2
VID  VI1  VI2
VI1  VI2
2
VOD  VO1  VO2
VOC 
VO1  VO2
2
VO1  1  1  VI1  VOS1
VO2  1  2  VI2  VOS2
C
CH
–
   
   
VOD   1  1 2  VID   1  2  VIC   VOS1  VOS2    1  1 2  VID
2 
2 


 VOS2   1  2 
 VOS2 
V
V
  
   
 1 
VOC   1 2  VID   1  1 2  VIC   OS1
VIC   OS1



2 
2
2 
2
 4 


 


B. Murmann
EE315B - Chapter 5
42
Differential Sampling (2)
•
Assuming good matching between the two half circuits, we have
– Small
S ll residual
id l offset
ff t iin VOD
– Good rejection of coupling noise, supply noise, …
– Small common-mode to differential-mode gain
•
Unfortunately, VOD has essentially same gain error as the basic
single ended half circuit
•
This also
Thi
l means that
th t there
th
will
ill be
b nonlinear
li
terms
t
– Out simplistic analysis assumed that the channel charge is
linearly related to Vin
– This is true only to first order (consider e.g. backgate effect)
• Expect to see nonlinear distortion along with gain error
EE315B - Chapter 5
B. Murmann
43
CMOS Switch

VO
+
VIN

–
•

Qchp  WpLpCox VIN  L  Vtp
CH

Assuming fast gating, 50/50 charge split and WnLn = WpLp
1
1
Qchn  Qchp C
2
Vo  2
 ox
C
C
•
Qchn   WnLnCox  H  VIN  Vtn 

V  Vtp
 
 VIN  H L  tn

2
2





Charges fully cancel e.g. for VIN = (H-L)/2 = VDD/2, and Vtn=|Vtp|,
but there is still signal dependent residual injection
B. Murmann
EE315B - Chapter 5
44
On Resistance of CMOS Switch
•
At least in principle, adding a PMOS can also help with the
problem of signal dependent Ron in track mode
– For increasing VIN, NMOS resistance goes up, PMOS
resistance goes down

VO
+
VIN
–
R
CCH

1
1

W 
W 
nCox    VGSn  Vtn  pCox   VGSp  Vtp
 L n
 L p

EE315B - Chapter 5
B. Murmann
45
Analysis
R
R
R
1
1

W 
W 
nCox    VGSn  Vtn  pCox   VGSp  Vtp
 L n
 L p
1

W 
W 
W  
W 
nCox    VDD  Vtn    nCox    pCox    vin  pCox   Vtp


L
L
 L n




 L p
n
p

1
W 
nCox   VDD  Vtn  Vtp
 L n


if
W 
W 
n    p  
 L n
 L p
•
Independent of Vin  too good to be true!
•
Missing factors
– Body effect
– Short channel effects
B. Murmann

EE315B - Chapter 5
46
Real CMOS Switch
100
VDD = 1.8V
R []
10 m/0.18 m
MN
VDD
Vin
MP
30 m/0.18 m
NMOS
PMOS
NMOS || PMOS
80
60
40
20
0
0
05
0.5
V
1
[V]
15
1.5
•
Design
– Size P/N ratio to minimize change in R over input range
– Size
Si P and
d N simultaneously
i lt
l to
t meett distortion
di t ti specs
•
PMOS brings limited benefit unless the input signal range is
large
g or centered near VDD
B. Murmann
in
EE315B - Chapter 5
47
Outline
•
Elementaryy track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques
– Clock bootstrapping
– Bottom plate sampling
•
Settling
S
ttli and
d noise
i analysis
l i iin charge-redistribution
h
di t ib ti
track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
48
Clock Bootstrapping
+
VDD
-
+
VDD
-
Cboot
Cboot
VGS=VDD=const.
Vin
A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.
•
Phase 1
– Cboot is precharged to VDD
– Sampling switch is off
•
Phase 2
– Sampling switch is on with VGS=VDD=const.
– To first order, both Ron and channel charge are signal
independent
B. Murmann
EE315B - Chapter 5
49
Waveforms
A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.
B. Murmann
EE315B - Chapter 5
50
Circuit Implementation
Switch
A. Abo et al., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-toDigital Converter,” IEEE J. Solid-State Circuits, pp. 599, May 1999
B. Murmann
EE315B - Chapter 5
51
Limitations
•
Efficacy of bootstrap circuit is
reduced
d
db
by
– Body effect
– Parasitic capacitance
between at top plate of C3
R
B. Murmann
Cpar
1


Cpar
Cboot
W  
nCox   
VDD 
Vin  Vtn  Vin  


 
Cboot  Cpar
 L n  Cboot  Cpar
Backgate effect 

EE315B - Chapter 5
52
Performance of Bootstrapped Samplers
•
Bootstrapped “top plate” sampling (as opposed to “bottom plate”
– more later)) tends to work veryy well up
p to ~10bit resolution
•
Example
[Louwsma, JSSC 4/2008]
B. Murmann
EE315B - Chapter 5
53
High-Speed Example without Bootstrap
[[Choi and Abidi, JSSC 12/2001]]
•
For lower resolution applications, it can be OK to drop the
bootstrap
p circuit
B. Murmann
EE315B - Chapter 5
54
Bottom Plate Sampling
•
Used to eliminate input-dependent charge injection error.
•
Basic idea
– Sample signal at the "grounded" side of the capacitor to
achieve signal independent sampling
•
References
– D. J. Allstot and W. C. Black, Jr., “Technological Design
Considerations for Monolithic MOS Switched-Capacitor
Filtering Systems,” Proc. IEEE, pp. 967-986, Aug. 1983.
– K.-L. Lee and R. G. Meyer, “Low-Distortion SwitchedCapacitor Filter Design Techniques,” IEEE J. Solid-State
Circuits, pp. 1103-1113, Dec. 1985.
•
First look at single ended half circuit for simplicity
EE315B - Chapter 5
B. Murmann
55
Bottom Plate Sampling Analysis (1)
•
Turn M2 off "slightly" before M1
– Typically a few hundred ps
delay between falling edges
of e and 
•
During turn off
off, M2 injects charge
Q2 
Q2
1
WLCox  H  Vtn 
2
•
To first order, the charge injected
by M2 is signal independent
•
Voltage across C
VC  Vin 
B. Murmann
EE315B - Chapter 5
Q2
C
56
Bottom Plate Sampling Analysis (2)
Q1 
•
Next, turn off M1
•
M1 will inject signal dependent
charge onto the series
combination of C and the
parasitic capacitance at its
bottom plate (Cpar)
•
Looks like
like, this is not much
different from the conventional
top-plate sampling?
– But wait…
wait
1
WLCox  H  Vin  Vtn 
2
EE315B - Chapter 5
B. Murmann
57
Bottom Plate Sampling Analysis (3)
Q X  CVin  Q2
Charge injected by M2
(Signal independent)
B. Murmann
•
Interesting observation
– Even though
g M1 injects
j
some charge, the total
charge at node X cannot
change!
•
Idea
– Process total charge at
node X instead of looking at
voltage across C
•
The charge can be processed
i ttwo ways
in
– Open-loop
– Closed-loop (charge
redistribution)
EE315B - Chapter 5
58
Open-Loop Charge Processing
Q X  CVin  Q2
1
Vin
2
VX 
M1
C
(no term due to signal
dependent charge!)
Vx
1e
Cpar
1
M2
QX
Q2
C
  Vin

C  Cp
C  Cp C  Cp
1e
2
•
Remaining drawback
– Cpar (and buffer input capacitance) is usually weakly nonlinear
and will introduce some harmonic distortion
B. Murmann
EE315B - Chapter 5
59
Closed-Loop Charge Processing
•
Amplifier forces voltage at node X to “zero”
– Means that charge at node X must redistribute onto
feedback capacitor Cf
B. Murmann
EE315B - Chapter 5
60
Charge Conservation Analysis
Charge at node X during 1:
Q X1  CVin  Q2  0  Cf
Charge at node X during 2:
Q X2  Cf Vout
Q X1  Q x2
Charge Conservation:
CVin  Q2  Cf Vout
 Vout 
•
Q2
C
Vin 
Cf
Cf
Offset term due to signal independent injection from M2 can be
easily removed using a differential architecture
B. Murmann
EE315B - Chapter 5
61
Clock Generation
[A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD
Thesis, UC Berkeley, 1999]
B. Murmann
EE315B - Chapter 5
62
Fully Differential Circuit
EE315B - Chapter 5
B. Murmann
63
Analysis (1)
B. Murmann

Q1m  CVinp  Q
Q2m  CVxm  Cf Vop  Vxm
Q1p  CVinm  Q
Q2p  CVxp  Cf Vom  Vxp
1)
Q1m  Q2m
2)
Q1pp  Q2pp

Vxm  Vxp
EE315B - Chapter 5
Vop  Vom
2


 Voc
64
Analysis (2)
•
Subtracting 1) and 2) yields
Vop  Vom 
•
C
 Vinp  Vinm 
Cf
Adding 1) and 2) yields





C Vinp  Vinm  2Q   C  Cf  Vxp  Vxm  Cf Vop  Vop
Vxc 
•

Cf
Q
C

V oc 
V ic
C  Cf C  Cf
C  Cf
Variations in Vic show up as common mode variations at the
amplifier input
– Need amplifier with good CMRR
B. Murmann
EE315B - Chapter 5
65
T/H with Common Mode Cancellation
S.H. Lewis & P.R. Gray, "A Pipelined 5 MSample/s 9-bit Analog-to-Digital Converter", IEEE
J. Solid-State Circuits, pp. 954-961, Dec. 1987
•
Shorting switch allows to re-distribute only differential charge on
sampling
li capacitors
it
•
Common mode at OPAMP input becomes independent of common
mode at circuit input terminals (IN+/IN-)
•
Original idea: Yen & Gray, JSSC 12/1982
B. Murmann
EE315B - Chapter 5
66
Analysis (1)
During 1
During 2
Cf
Cf
Voc
C
C
Vip
Vfloat
Voc
Vop
C
Cf
•
Vom
Vxm
Vim
i
C
Vxp
Cf
Charge conservation at Vip,Vim and Vfloat
 Vip  Vim   C   Vfloat  Vxp   C   Vfloat  Vxm   C
Vic  Vfloat  Vxc
Vfloat  Vic  Vxc
EE315B - Chapter 5
B. Murmann
67
Analysis (2)
•
Common mode charge conservation at amplifier inputs
 Vic  C  Voc  Cf    Vfloat  Vxc   C   Voc  Vxc   Cf
 Vic  C    Vic  Vxc   Vxc   C  Vxc  Cf
0  Vxc
•
Amplifier input common mode (Vxc) is independent of
– Input
I
t common mode
d (Vic)
– Output common mode (Voc)
B. Murmann
EE315B - Chapter 5
68
Flip-Around T/H
[W. Yang et al., "A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at
Nyquist Input", IEEE J. Solid-State Circuits, pp. 1931-1936, Dec. 2001]
•
Sampling caps are "flipped around" OTA and used as feedback
capacitors during 2
•
Main advantage: improved feedback factor (lower noise, higher speed)
•
Main disadvantage: OTA is subjected to input common mode variations
EE315B - Chapter 5
B. Murmann
69
Sampling Network Design Considerations
1-
1+
1+
1
1-
M1-
M1
M1-
•
M1- switches only needed to
set common mode; M1 is
actual sampling switch
– Make M1 larger than M1-
•
Ideally
y turn off M1- before M1
– In practice, usually OK to
turn off simultaneously
•
In track mode
mode, the total path
resistance is R(M3) plus
bottom plate switch resistance
– Since R(M3) is signal
dependent, make its
resistance small compared
to that of bottom plate
network
[Lin, Kim and Gray, JSSC 4/1991]
1
1
1+
2
B. Murmann
EE315B - Chapter 5
70
Schematic Entry and Layout of M1
•
Use antiparallel devices to implement M1
– Needed in simulation to guarantee circuit symmetry
• E
E.g.
g BSIM model is not necessarily
necessaril perfectl
perfectly ssymmetric
mmetric with
ith
respect to drain/source!
– Needed in layout to ensure symmetry in presence of
drain/source asymmetry due to processing artifacts
B. Murmann
EE315B - Chapter 5
71
What Ultimately Limits Linearity?
•
Track mode nonlinearity due to R=f(Vin)
– Mitigate using clock bootstrapping and proper partitioning of
total path resistance
– Eventually, bootstrapping falls apart high frequencies, due to
parasitics capacitances inside the bootstrap circuit
•
Mismatch in half-circuit charge injection due to R=f(Vin)
– Bottom plate switches in the two half circuits see input
dependent impedance; this creates input dependent charge
injection mismatch
– Bootstrapping helps; ultimately limited by backgate effect
– This effect is often fairly independent of frequency
(somewhat dependent on realization of top plate switch)
•
In high performance designs, can achieve ~80-100dB linearity
up to a few hundreds of MHz
B. Murmann
EE315B - Chapter 5
72
Capacitors
Metal-Insulator-Metal (MIM)
Vertical Parallel Plate (VPP)
[Ng, Trans. Electron Dev., 7/2005]
[Aparicio, JSSC 3/2002]
•
Typically 1-2 fF/m2 (10-20 fF/m2 for advanced structures)
– For 1 fF/m2, a 10 pF capacitor occupies ~100m x 100m
•
Both MIM and VPP capacitors have good electrical properties
– Mostly worry about parasitic caps
– Series and parallel resistances are often not a concern
B. Murmann
EE315B - Chapter 5
73
Plate Parasitics
Symbol
•
Node n1 is usually the "physical"
physical top plate of the capacitor
– Makes nomenclature very confusing, since this plate is
typically used as the "electrical" bottom plate in a sampling
circuit (in the context of "bottom
bottom plate sampling")
sampling )
•
Typical values for a MIM capacitor
– =1%, =10%
B. Murmann
EE315B - Chapter 5
74
Proper Connection of Capacitors
•
“Fat plate” is oriented away from virtual ground nodes to avoid
reduction of feedback factor and reduce potential noise coupling
B. Murmann
EE315B - Chapter 5
75
Outline
•
Elementaryy track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques
– Clock bootstrapping
– Bottom plate sampling
•
Settling
S
ttli and
d noise
i analysis
l i iin charge-redistribution
h
di t ib ti
track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
76
Settling and Noise Analysis
Cf
2
1
Gm
Cs
CL
B. Murmann
EE315B - Chapter 5
77
First Order Amplifier Model
Pi
Piecewise
i linear
li
half-circuit
h lf i it
vx = vxd/2
Cx
vo = -vod/2
in2
 gm v x
for
io  
ID  sign  v x 
B. Murmann
EE315B - Chapter 5
io
ro
gm v x  ID
else
78
Linear Settling (Small Input Step)
0
Vofinal
t=0
-Vistep

v o (t)  Vofinal 1  e t / 
(ignoring feedforward zero)
•
Important parameter: Return factor or "feedback
feedback factor
factor" 

Cf
C f  Cs  C x
EE315B - Chapter 5
B. Murmann
79
Waveform Detail
Static
Error 0
Dynamic
Error d(t)
1
V
Vout
/Vo
o/V
o,ideal
out,ideal
o
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
t/
B. Murmann
EE315B - Chapter 5
80

Static Settling Error
•
Ideal output voltage for t
Vofinal,ideal
ofinal ideal  Vistep 
•
Actual output voltage (from detailed analysis)
Vofinal  Vistep 
•
Cs T0

Cf 1  T0
T0    gmro    avo
Define static settling error
0 
•
Cs
Cf
Vofinal  Vofinal,ideal
Vofinal,ideal
fi l id l
T
1
1
1
 1 T


1
1 T
T
Example: T0=1000  0.1% static settling error
EE315B - Chapter 5
B. Murmann
81
Dynamic Settling Error


t / 
 Vofinal
v o ((t))  Vofinal Vofinal 1  e
dynamic (t) 

 e  t / 
Vofinal
Vofinal
N
B. Murmann
ts
  ln  d 

dynamic
N
1%
4.6
0 1%
0.1%
69
6.9
0.01%
9.2
EE315B - Chapter 5
82
Time Constant

Cf
C f  Cs  C x
R
1
gm
CLtot  CL  1    Cf

1 CLtot

 gm
EE315B - Chapter 5
B. Murmann
83
Transconductor Current
0
Vofinal
t=0
-V
Vistep

v o (t)  Vofinal 1  e t / 
•
During linear settling,
settling the current delivered by the transconductor is
io  CLtot
•

dv o (t)
V
 CLtot ofinal e t / 
dt

Peak current occurs at t=0
io max  CLtot
B. Murmann
Vofinal

EE315B - Chapter 5
84
Slewing
•
The amplifier can deliver a maximum current of ID
– If |io|max > ID, slewing occurs
io max  CLtot
CLtot
Leff
Vofinal
 ID

Vofinal
I
1 CLtot D

 gm

gm
1

ID
Vofinal
•
Example: =0.5, Vofinal=0.5V  gm/ID > 4 S/A will result in slewing
•
Very hard to avoid slewing, unless
− We are willing to bias at very low gm/ID (power inefficient)
− Feedback factor is small (large closed-loop gain, CS/Cf)
− Output voltage swing is small
EE315B - Chapter 5
B. Murmann
85
Output Waveform with Initial Slewing

v o (t)  Voslew  Volin 1  e (t tslew )/ 
v o (t) 
•

ID
t  SR  t
CLtot
C ti
Continuous
d
derivative
i ti iin th
the ttransition
iti slewinglinear
l i li
requires
i
Volin
ID

CLtot

B. Murmann
Volin 
EE315B - Chapter 5
  ID
CLtot
Lt t
86
Dynamic Error with Slewing
t slew   Vofinal  Volin  
Voslew  Vofinal  Volin
•
CLtot
ID
Using the above result, we can now calculate the dynamic error
during the final linear settling portion

 t t slew  / 
v o (t)  Voslew  Volin 1  e 
For t  t slew :



  t t slew  / 
 Vofinal
v o (t)  Vfinal Voslew  Volin 1  e
d (t) 

Vfinal
Vofinal
d (t)  
Volin   t tslew  / 
e
Vofinal
EE315B - Chapter 5
B. Murmann
87
Noise Analysis
Cf
2
1
Cs
Gm
CL
Noise due to switches
B. Murmann
Noise due to amplifier
p
and switches
EE315B - Chapter 5
88
Tracking Phase (1)
•
Variable of interest is total integrated
"noise charge" at node X, qx2
•
Cumbersome to compute using
standard analysis
– Find
d ttransfer
a s e function
u ct o from
o eac
each noise
o se
source (3 resistors) to qx
– Integrate magnitude squared
expressions from zero to infinity and add
•
Much easier
– Use equipartition theorem: each “degree
of freedom” ((e.g.
g energy
gy stored on
capacitor) of a system in thermal
equilibrium holds an average energy of
kT/2
B. Murmann
EE315B - Chapter 5
89
Tracking Phase Noise Charge
•
Energy stored at node X is
1 q2x
1 q2x

2 Ceff 2 Cs  Cf
•
Apply equipartition theorem
1 q2x
1
 kT
2 Cs  Cf 2
q2x  kT  Cs  Cf 
•
B. Murmann
Note that any additional parasitic
capacitance at node X will
increase the sampled noise
charge!
EE315B - Chapter 5
90
Redistribution Phase Noise
4kTRon f
>1 excess noise factor
1
R
Gm
4kTRon1f
•

4kT
f
Gm
In a proper design, Ron1 and Ron2 will be much smaller than
1/Gm, else the switches would significantly affect the dynamics
dynamics,
which would be very wasteful
– It is much easier to design switches with low on-resistance
than an amplifier with very large Gm
EE315B - Chapter 5
B. Murmann
91
Output Referred Noise Comparison
2
•
Ron1 noise referred to vo
C 
2
N1  4kTRon1f   s   H( j)
 Cf 
•
Ron2 noise referred to vo
N2  4kTRon2 f  H( j)
Amplifier noise referred to vo
 C 
4kT
2
Na  
f   1  s   H( j)
Gm
Cf 

2
2
•
2
 Cs 
1

Cf 
Na
 

 1
N1 GmRon1  C 2
s


C
 f
•
2
Na
  Cs 

1
  1
N2 GmRon2 
Cf 
Amplifier noise dominates over noise due to Ron1, Ron2
B. Murmann
EE315B - Chapter 5
92
Total Integrated Amplifier Noise
R
1
Gm
  4kTGm  f
v o2
1
1
   4kT
R
f
R
jCLtot
Lt t
v o2
2

1
R
    4kT
 f 
R
1  jRCLtot
0
2
df  
1 kT
 CLtot
EE315B - Chapter 5
B. Murmann
93
Adding up the Noise Contributions
Cf
2

1
q2x  kT  Cs  Cf 
Cs
Gm
CL
2
v o,1

 Cs  C f

kT

2
C2f
 Cf
q2x
 kT  Cs 
 
1

C
Cf 
f


2
v o,tot

B. Murmann
2
v o,2
 
1 kT
 CLtot
kT  Cs 
1 kT
1
  
Cf 
Cf 
 CLtot
EE315B - Chapter 5
94
Noise in Differential Circuits
•
In differential circuits, the noise power is doubled (because there
are two half circuits contributing to the noise)
•
But, the signal power increases by 4x
– Looks like a 3dB win?
DRsingle
Vˆ 2
 o
kT
C
DRdiff
2Vˆ 


o
2
kT
C
2
2
Vˆ o2
kT
C
•
Yes, there’s a 3dB win in DR, but it comes at twice the power
dissipation (due to two half circuits)
•
Can get the same DR/power in a single ended circuit by
doubling all cap sizes and gm
B. Murmann
EE315B - Chapter 5
95
Summary – Sampling Circuits
•
Three p
predominant implementation
p
styles
y
– Purely passive
– Source follower T/H, up to ~9-10bit accuracy
– Charge redistribution or flip
flip-around
around architecture
•
In a typical, properly designed circuit only the most fundamental
issues are significant
– Jitter, kT/C noise
•
Charge injection is not a problem if properly handled
– E.g.
E g through bottom plate sampling
B. Murmann
96
Outline
•
Elementaryy track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques
– Clock bootstrapping
– Bottom plate sampling
•
Settling
S
ttli and
d noise
i analysis
l i iin charge-redistribution
h
di t ib ti
track-and-hold circuit
•
Noise simulation example
EE315B - Chapter 5
B. Murmann
97
Noise Simulation Example
•
Three ways to simulate noise in switched capacitor circuits
•
Basic .ac/.noise
ac/ noise Spice simulations
– Must simulate noise in each clock phase separately
• Activate 1 switches, run .noise and integrate noise charge at
relevant node over all frequencies and refer to output
• Activate 2 switches, run .noise and integrate noise at output
•
Periodic Steady State Simulation
– E.g. SpectreRF or BDA, "periodic noise analysis“ (PNOISE)
– Allows to simulate noise while switched capacitor circuit is
clocked between 1 and 2
• Noise from all phases is automatically added, all correlation
taken care of
•
Transient Noise
B. Murmann
EE315B - Chapter 5
98
vocss
voc
vdd
I16
C4
500f
I14
p2
2!
p1e!
Example Track and Hold Schematic
p2b!
vdd
voc
vocs
p1e!
I17
p2!
I15
vic
voc
V5
vdc:0
V4
vdc:0
fs = 100MHz
vdd
vdd
C2
500f
C
C8
ccs
I22
C7
cs
Parameters:
Ron = 10Ω (all
( ll switches)
it h )
Cs = Cf = 100fF
CL = 500fF
EE315B - Chapter 5
B. Murmann
99
OTA Simulation Model
Cxp,m 
gm
2fT
in2
   kTg
kT m
f
ro 
avo
gm
ID 
gm
 gm / ID 
Parameters: gm=1mS, avo=1000, =2, gm/ID=10S/A , fT=20GHz
B. Murmann
EE315B - Chapter 5
100
Hold Mode Noise Simulation (.noise)
Calculated value: 248uVrms
EE315B - Chapter 5
B. Murmann
101
Track Mode Noise Simulation (.noise)
*** Compute noise charge and refer charge referred to output via Cf
en vno 0
vcvs vol=( cs*v(x,s) + cf*v(x,f) )/cf‘
.ac dec 100 100 100Gig
.noise v(vno) vdummy
(shown single ended for simplicity)
Calculated value: 413uVrms
B. Murmann
EE315B - Chapter 5
102
PSS Setup
Use “tstab” if your circuit
needs time to get into steady
state (e.g. clock bootstrap
circuits)
Important: set “maxacfreq” to the highest
frequency at which you expect noise to
be significant (10GHz in this example;
see plot on previous slide!)
B. Murmann
EE315B - Chapter 5
103
PSS Waveforms (Clocks)
3.8ns
B. Murmann
EE315B - Chapter 5
104
PNOISE Setup
“Number of sidebands” – typically ~20…200 to handle
noise folding properly. Fast switches  more sidebands
needed. Again, Be sure to set “maxacfrequency” in the
PSS analysis options to a correspondingly large value.
Note: This is not a problem in advanced simulators such
as BDA, which cover an “infinite” number of sidebands
“timedomain” means simulator computes
spectrum of discrete time noise samples
Sampling instant (3.8ns in this example
B. Murmann
EE315B - Chapter 5
105
How Many Sidebands are Needed? (1)
Hold mode noise integral (.noise)
Noise up to 10GHz must
be considered !
 numsidebands =100
100
 macacfreq = 10GHz,
B. Murmann
EE315B - Chapter 5
106
How Many Sidebands are Needed? (2)
Track mode noise integral, (.noise, Ron = 10 Ohms)
Noise up to 1 THz must be
considered !
 numsidebands =10,000?
No! Increase Ron to make
maintain reasonable simulation
time. Keep RonC ~ 10x faster
than amplifier.
EE315B - Chapter 5
B. Murmann
107
PNOISE Result
Sampled Noise
B. Murmann
Noise PSD
EE315B - Chapter 5
108
Comparison
Calculated:
Simulated:
(.noise)
S u ated
Simulated:
(PNOISE)
•
2
v o,1
  413Vrms 
2
2
v o,2
  248Vrms 
2
v o,1
  415Vrms 
2
2
v o,2
  252Vrms 
2
v o,tot
  482Vrms 
2
2
v o,tot
  485Vrms 
2
2
v o,tot
t t   478Vrms 
2
Very good agreement between calculation and both simulation
approaches
B. Murmann
EE315B - Chapter 5
2
109
2
Voltage Comparators
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 6
1
Recap
•
Ultimately, building a quantizer requires circuit elements that
"make decisions"
•
The most widely used "decision
decision circuit"
circuit is a voltage comparator
B. Murmann
EE315B - Chapter 6
2
Ideal Voltage Comparator
•
Function
– Compare
C
th
the iinstantaneous
t t
values
l
off ttwo analog
l voltages
lt
(e.g. an input signal and a reference voltage) and generate a
digital 1 or 0 indicating the polarity of that difference
EE315B - Chapter 6
B. Murmann
3
Preview - Flash ADC
2B-1
Dout
Vin
2B-1 Decision Levels
B. Murmann
EE315B - Chapter 6
4
Design Considerations
•
Accuracy
– Gain (resolution)
– Offset
Off
•
Speed
– Small-signal
g
bandwidth
– Settling time or delay time, slew rate
– Overdrive recovery
•
Power dissipation
•
Input properties
– Sampled data versus continuous time
– Common-mode rejection
– Input capacitance and linearity of input capacitance
– Kickback noise
EE315B - Chapter 6
B. Murmann
5
Gain Requirements
Av
Vin 
VDD
A vo
•
E.g. 12-bit ADC, VDD=1.8V, FSR=0.9V, LSB=0.9V/4096
•
For 1/2 LSB precision, we need
Av 
B. Murmann
1.8V
 16,000  84dB
0.5  0.9V / 4096
EE315B - Chapter 6
6
How to Implement High Gain?
•
Considerations
– Amplification need not be linear
– Amplification need not be continuous in time, if comparator is
used in a sampled data system
• Clock signal will tell comparator when to make a decision
•
Implementation options to be looked at
– Single stage amplification
• E.g.
E g OTA or OpAmp in open loop configuration
– Multi-stage amplification
• E.g. cascade of resistively loaded differential pairs
– Regenerative
R
ti llatch
t h using
i positive
iti ffeedback
db k
• E.g. cross coupled inverters
EE315B - Chapter 6
B. Murmann
7
How about Using an OpAmp or OTA?
fu=10MHz…1GHz
fo 
•
fu
1GHz

 62.5kHz
,
A v 16,000
o 
1
 2.5s
2fo
Way too slow!
B. Murmann
EE315B - Chapter 6
8
Cascade of Open-Loop Amplifiers
For each stage: A 0  gmR 
•
g
u

1
0 
 uu  m  const.
Cgs
0
RC A 0
0 

1
 u
RC A 0
Possible choices for a given, constant overall gain objective
– Lots of stages with low gain
– Onlyy a few stages
g with moderate g
gain
EE315B - Chapter 6
B. Murmann
9
Bandwidth Perspective
•
If we only care about small signal bandwidth, it follows that we
should cascade many low gain stages
– Makes intuitive sense,
sense because each individual stage will
have a very large bandwidth
•
Detailed analysis shows
 N 1 

N 


0N
 Av
01
1
N
2
Av Total gain requirement
01 Bandwidth of single stage realization
0N Bandwidth of N stage realization
1
1500
0 N
01
1000
(Av=10,000)
=10 000)
500
0
B. Murmann
0
5
N
10
EE315B - Chapter 6
15
10
Step Response (1)
•
When the input is a sampled data signal, it is more important to
minimize the delay in response to an input step
Vout (s)  Vin (s)A(s) 
Vistep
s
Av

1  s  u A v1/N
u 

N
1
u
A v  AN
0
i


 
t


t


1/N 
 

1/N N1    A
Vout (t)  Vistep A v  1  e u  A v   u v  
i!


i0






A(t)
()
EE315B - Chapter 6
B. Murmann
11
Step Response (2)
10
Step re
esponse A(t)
8
d(N=3)
(
)
10(1-e-1)
6
4
N=1
N=3
N=5
2
Av*(1-e-1)
0
0
5
10
15
Time t/u
•
d = equivalent settling time constant of N stage realization
– time required for N stage implementation to reach same output
voltage as a single stage realization achieves after 0
•
Th
Three
stage
t
amplifier
lifi wins!
i ! (f
(for Av=10)
10)
B. Murmann
EE315B - Chapter 6
12
Delay versus Number of Stages

A( d )  A v 1  e1

 d
(numerically)
50
Av=10
Av=100
Av=1000
Dellay time d/u
40
30
20
10
0
•
2
4
6
8
10
N (Number of stages)
12
14
Shallow minima!
EE315B - Chapter 6
B. Murmann
13
Optimum Number of Stages
Optimum numbe
er of stages
12
10
Numerical
N
i l resultlt
ln(Av)
8
6
4
2
0 0
10
10
1
2
10
10
Av (Total gain)
3
10
4
10
5
Nopt  ln(A v )
B. Murmann
EE315B - Chapter 6
14
Optimum Gain per Stage
A0,opt (Optimum ga
ain per stage
e)
5
Numerical result
e
45
4.5
4
3.5
3
2.5
2
1.5
1 0
10
Nopt  ln(A v )
10
1
2
10
10
Av (Total gain)
Nopt
e
3
10
 A v  A 0,opt
Nopt
4
10
5
 A 0,opt  e
EE315B - Chapter 6
B. Murmann
15
Cascade of "Integrators" (1)
•
Intuition
– Load resistors (in cascade of open loop amplifiers) shunt
current away from load capacitance; this slows down
amplification
– Drop assumption Av=A0N to see what happens…
•
Analysis

g
v o1  m vin  u v in
sC
s
B. Murmann
EE315B - Chapter 6
v oN 
N
u
sN
vin
16
Cascade of “Integrators” (2)
EE315B - Chapter 6
B. Murmann
17
Cascade of "Integrators" (3)
Vistep N
u
N
s s
Vout ((t))  Vistep  N
u
10
10
8
8
Step response A(t)
Step response A(t)
Vout ((s)) 
6
4
N=1 (with R)
N 1 (i
N=1
(integ)
t )
2
0
0
5
10
6
4
15
0
0
Time t/
Av*(1-e-1)
5
10
15
Time t/
u
B. Murmann
N=3 (with R)
N 3 (i
N=3
(integ)
t )
2
Av*(1-e-1)
tN
N!
u
EE315B - Chapter 6
18
Cascade of "Integrators" (4)
•
Cascade of integrators achieves faster amplification than
cascade of resistively loaded stages
•
Delay time
d  u (N! A( d ))
1/N
•
A( d ) 
Optimum number of stages approximately given by
Nopt  1.1ln  A( d )  0.79
•
Vout ( d )
Vinstep
[Wu, JSSC 12/1988)
Effective gain per stage is still relatively close to e=2.7183…
B. Murmann
EE315B - Chapter 6
19
Latched Comparator (1)
B. Murmann
EE315B - Chapter 6
20
Latched Comparator (2)
t0
setup initial condition
v10  v 20  v d0
t0
enable positive feedback
-
dv1 i1((t)) gm v 2 ((t))


dt
C
C
-
u 
dv 2 i2 (t) gm v1(t)


dt
C
C
C
gm
 v1(t)  v 2 (t)  v d (t)  v d0  et / u
 A(t) 
v d (t)
 et / u
v d0
EE315B - Chapter 6
B. Murmann
21
Comparison
10
Amplificatio
on A(t)
8
6
4
N=3 (with R)
N=3 (integ)
Latch
2
A *(1-e-1)
0
0
v
5
10
15
Time t/
u
•
Latch is much faster than cascade of amplifiers/integrators
B. Murmann
EE315B - Chapter 6
22
Latch "Gain"
B. Murmann
A(d)
d/u
10
23
2.3
100
4.6
1,000
6.9
10,000
9.2
EE315B - Chapter 6
23
"The" Architecture
•
Why bother using pre-amplification (Av)?
– Offset
Off t
• Hard to build latches with offset < 10…100mV
• Use pre-amplification to lower input referred offset
– Common mode rejection
– Attenuate "kickback noise"
– Metastability
B. Murmann
EE315B - Chapter 6
24
Metastability (1)
•
References
– Veendrick, JSSC 4/1980
– Zojer, JSSC 6/1985
•
Consider minimum initial latch input voltage needed to
regenerate to VDD within maximum available time Tmax
Vd0 min 
•
Minimum required pre-amplifier input
Vid0 min 
•
e
VDD
Tmax / u
1 VDD
A v eTmax / u
Probability of seeing a metastable output
P(Error)  P  Vid0  V id0 min
i 
EE315B - Chapter 6
B. Murmann
25
Metastability (2)
•
Assuming a uniform input signal distribution over some range,
we have
PDF
P Error  
V id0min
V id0max
-V
Vid0max
+Vid0max
-Vid0min +Vid0min
•
In a flash ADC, onlyy one out of all comparators
p
can be
metastable. The effective input range Vid0max over which the
signal is distributed is therefore ½ LSB (/2)
 P Error  
B. Murmann
V id0 min
V id0 max
1 VDD
1 VDD

T
/
max u
A
A Tmax / u 2B 1 VDD Tmax / u
 v e
 v e

e

VFS
A v VFS
2
2  2B
EE315B - Chapter 6
26
Metastability (3)
•
Example: 6-bit, 500MHz Flash ADC, Tmax=Ts/2=1ns,
u=1/(2·5GHz)=32ps, Av=3, VFS=0.5VDD
P(Error) 
•
26  1
 2  e1000/32  2  1012
3
Mean time to failure (MTF)
MTF 
1
1
s  1000s  16 minutes


12
P(Error)  fs 2  10
 0.5  109
•
Ideally design for MTF > 1…10 years (not always possible)
•
Can improve MTF by
– Reducing speed (larger Tmax/u)
• Exponential dependence
– Adding pre-amplifier gain
• Linear dependence
B. Murmann
EE315B - Chapter 6
27
Latch: Dynamic Offset
C  C1  C2
•
C1  C2 causes dynamic offset
•
Can show Vos  0.5·C/C·(V(t=0)-VS); VS = inverter switching voltage
– Nikoozadeh & Murmann
Murmann, IEEE TCAS II
II, Dec
Dec. 2006
2006.
•
Example
– 0.5·10fF/100fF·(1V-0.5V)=
(
) 25mV ((!))
B. Murmann
EE315B - Chapter 6
28
CMOS comparators
•
Dominant practical issues in comparator design are often
– Offset
• Latch offset often means must use one or more stages of low gain
pre-amplification
• Preamplifier offset often means must use offset cancellation
techniques
– Overdrive recovery
• Time to recover from large signal and correctly detect small signal
• Typically
T i ll lilimits
it achievable
hi
bl comparator
t speed
d
EE315B - Chapter 6
B. Murmann
29
Input Referred Offset
2VOS  2VOS1 
•
1
A 2v
2VOS2
Example: VOS1=3mV, VOS2=30mV, Av=10
 VOS 
B. Murmann
 3mV 2 
1
10
2
 30mV 2
EE315B - Chapter 6
 4.2mV
30
Amplifier Offset Cancellation (1)
•
In a sampled-data cascade of MOS amplifiers, offset voltages
can be cancelled by storing them on ac-coupling
ac coupling capacitors in
series with the amplifier stages
•
The offset associated with a specific amplifier stage can be
cancelled by storing it in series with either the input or the output
of the stage
– Output Series Cancellation:
• short
h t the
th amplifier
lifi inputs
i
t
• store amplified offset on output coupling capacitors
– Input Series Cancellation:
• close a unity-gain loop around the amplifier
• store offset on input coupling capacitors
EE315B - Chapter 6
B. Murmann
31
Amplifier Offset Cancellation (2)
OUTPUT SERIES
CANCELLATION
INPUT SERIES
CANCELLATION
B. Murmann
EE315B - Chapter 6
32
Output Series Cancellation
2
2
1
1
•
Phase 1: Offset storage, phase 2: Amplify
•
Design considerations
– Must ensure that amplifier does not saturate during phase 1
– Must make C sufficiently large to avoid attenuation and
mitigate
iti t charge
h
injection
i j ti error
EE315B - Chapter 6
B. Murmann
33
Input Series Cancellation
1
2
1
•
Phase 1: Offset storage, phase 2: Amplify
•
In phase 2, input referred offset is Vos/(A+1)
– 4x reduction if A=3
B. Murmann
EE315B - Chapter 6
34
Commercial Example: AD7671
[http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3956]
•
Used in 16-bit, 1 MS/s successive approximation ADC, 0.6 m
CMOS technology
•
Uses cascaded output series offset cancellation
•
Off t <3
Offset
3 mV
V (over
(
process, temperature)
t
t )
B. Murmann
EE315B - Chapter 6
35
Overdrive Recovery (1)
•
Simple linear model of a single-pole amplifier
•
During “reset”, the amplifier settles exponentially to its zero-input
condition with a time constant = RC.
B. Murmann
EE315B - Chapter 6
36
Overdrive Recovery (2)
•
Worst case scenario: maximum input Vm (normalized to ½ LSB)
is followed by minimum input ( ½ LSB)
•
To speed up overdrive recovery
– Use low gain per stage
– Use passive clamps
– Use active restore
EE315B - Chapter 6
B. Murmann
37
Overdrive Recovery (3)
Active Restore
Passive Clamps
B. Murmann
EE315B - Chapter 6
38
Comparator Examples (1)
•
Yukawa, JSSC 6/1985
– Preamplifier followed by interesting latch
– No offset cancellation
– 8 bits, fs = 15MHz
B. Murmann
EE315B - Chapter 6
39
Comparator Examples (2)
•
Purely dynamic "sense amplifier"
– No DC current
B. Murmann
EE315B - Chapter 6
40
Comparator Examples (3)
•
Cho, JSSC 3/1995
– Variation of Yukawa latch used as a dynamic comparator
– No DC power dissipation when  is high
•
M1, M2, M11 and M12 in linear
(triode) region
•
M11, M12 set differential threshold of
comparator
where Vin = Vi1-Vi2 and Vref = VR+-VR-
B. Murmann
EE315B - Chapter 6
41
Comparator Examples (4)
•
Mehr & Dalton, JSSC 7/1999
B. Murmann
EE315B - Chapter 6
42
Comparator Examples (5)
•
Mehr & Dalton, JSSC 7/1999
B. Murmann
EE315B - Chapter 6
43
Comparator Examples (6)
•
Mehr & Singer, JSSC 3/2000
B. Murmann
EE315B - Chapter 6
44
Comparator Examples (7)
•
Wu, JSSC 12/1988
– Instead of pre-amplification, uses latch with offset compensation
B. Murmann
EE315B - Chapter 6
45
Comparator Examples (8)
•
Schinkel, ISSCC 2007: "Double tail sense amplifier"
B. Murmann
EE315B - Chapter 6
46
Selected References (1)
1. R. Poujois and J. Borel, “A Low Drift Fully Integrated MOSFET Operational Amplifier,”
IEEE J. of Solid-State Circuits, pp. 499-503, Aug. 1978.
2 H
2.
H.-S
S. Lee,
Lee D
D. A
A. Hodges and P
P. R
R. Gray
Gray, “A
A Self
Self-Calibrating
Calibrating 15 Bit CMOS A/D
Converter,” IEEE J. of Solid-State Circuits, vol. SC-19, pp. 813-819, Dec. 1984.
3. J. L. McCreary and P. R. Gray, “All-MOS Charge Redistribution Analog-to-Digital
Conversion Techniques — Part I,” IEEE J. of Solid-State Circuits, vol. SC-10, no. 6,
pp. 371-379, Dec. 1975.
4. Y. S. Yee, L. M. Terman and L. G. Heller, “A 1mV MOS Comparator,” IEEE J. of
Solid-State Circuits, vol. SC-13, pp. 294-297, June 1978.
5. A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” IEEE J. of Solid-State
Circuits, vol. SC-20, pp. 775-779, June 1985.
6. B. J. McCarroll, C. G. Sodini, and H.-S. Lee, “A High-Speed CMOS Comparator for
Use in an ADC,” IEEE J. of Solid-State Circuits, vol. 23, pp. 159-165, Feb. 1988.
7. J.-T. Wu and B. A. Wooley, “A 100-MHz Pipelined CMOS Comparator,” IEEE J. SolidState Circuits, vol. 23, pp. 1379-1385, Dec. 1988.
8. B. Razavi and B. A. Wooley, “A 12-b 5-MSample/s Two-Step CMOS A/D Converter,”
IEEE J. Solid-State Circuits, vol. 27, pp. 1667-1678, Dec. 1992.
9. B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution
Comparators,” IEEE J. Solid-State Circuits, vol. 27, pp. 1916-1926, Dec. 1992.
10. T.B. Cho and P.R. Gray, “A 10-b, 20-Msample/s, 35-mW Pipeline A/D Converter,”
IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
B. Murmann
EE315B - Chapter 6
47
Selected References (2)
11. M. Choi and A. A. Abidi, "A 6-b 1.3-GSample/s A/D converter in 0.35-µm CMOS,"
IEEE J. Solid-State Circuits, pp. 1847-1858, Dec. 2001.
12. I. Mehr and D. Dalton, "A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive readchannel applications,"
applications " IEEE J.
J Solid-State
Solid State Circuits,
Circuits pp.
pp 912
912-920,
920 July 1999
1999.
13. I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-MSample/s Nyquist-Rate CMOS ADC,”
IEEE J. Solid-State Circuits, pp. 318-25, March 2000.
14. H. J. M. Veendrick, “The Behavior of Flip-Flops Used as Synchronizers and
Prediction of Their Failure Rate
Rate,” IEEE J.
J Solid-State
Solid State Circuits,
Circuits April 1980
1980.
15. B. Zojer, et al., “A 6-bit/200-MHz full Nyquist A/D converter,” IEEE J. Solid-State
Circuits, vol. SC-20, pp. 780-786, June 1985.
16. K.-L.J. Wong and C.-K.K. Yang, "Offset compensation in comparators with minimum
input-referred supply noise,
noise " IEEE J.
J Solid-State Circuits,
Circuits vol.39,
vol 39 pp
pp. 837-840
837-840, May
2004.
17. A. Graupner, "A Methodology for the Offset-Simulation of Comparators,"
http://www.designers-guide.org/Analysis/comparator.pdf.
18 D
18.
D. Schinkel et al.,
al "A
A Double
Double-Tail
Tail Latch-Type
Latch Type Voltage Sense Amplifier with 18ps
Setup+Hold Time," ISSCC Dig. Techn. Papers, pp. 314-315, 2007.
19. P.P. Nuzzo, et al., "Noise Analysis of Regenerative Comparators for Reconfigurable
ADC Architectures, IEEE Trans. Circuits Syst. I, pp.1441-1454, July 2008.
20 B
20.
B.S.
S Leibowitz,
Leibowitz et al.,
al "Characterization
Characterization of Random Decision Errors in Clocked
Comparators," Proc. IEEE CICC, pp.691-694, Sep. 2008.
B. Murmann
EE315B - Chapter 6
48
Flash and Folding & Interpolating ADCs
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
EE315B - Chapter 7
B. Murmann
1
Nyquist ADC Architectures
•
Nyquist rate
– Word-at-a-time
• Flash ADC
• Instantaneous comparison with 2B-1 reference levels
– Multi-step
• E.g. pipeline ADCs
• Coarse conversion, followed by fine conversion of residuum
– Bit-at-a-time
• E.g. successive approximation ADCs
• Conversion via a binary search algorithm
SPEED
– Level
Level-at-a-time
at a time
• E.g. single or dual slope ADCs
• Input is converted by measuring the time it takes to
charge/discharge
g
g a capacitor
p
from/to input
p voltage
g
B. Murmann
EE315B - Chapter 7
2
ADC Performance Survey (ISSCC & VLSI 97-08)
Data: http://www.stanford.edu/~murmann/adcsurvey.html
10
BW
W [Hz]
10
10
10
Flash
Fl
h
Pipeline
SAR
Sigma-Delta
Other
1psrms Jitter
10
8
6
4
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
EE315B - Chapter 7
B. Murmann
3
Flash ADC
2B-1
Dout
Vin
2B-1
1 Decision Levels
•
Fast
– Speed limited by single comparator plus encoding logic
•
Exponential dependence of power, area and input capacitance
upon number of bits
– Typically use for resolution up to 6 bits
B. Murmann
EE315B - Chapter 7
4
Limiting Error Sources
•
Comparator input
– Offset
– Nonlinear
N li
iinputt capacitance
it
– Kickback noise (disturbs reference)
• All comparators switching simultaneously
•
Timing and comparator output
– “Sparkle codes” caused by bubbles (… 111101000 …)
• E.g. due to clock timing skew
– Metastability
• Analog Devices application note: "Find Those Elusive ADC
Sparkle Codes and Metastable States"
http://www analog com/en/content/0 2886 760%255F788%255F
http://www.analog.com/en/content/0,2886,760%255F788%255F
91218,00.html
B. Murmann
EE315B - Chapter 7
5
Bubbles Due to Timing Errors
K. Uyttenhove, M.S.J. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm
CMOS," Solid-State Circuits, IEEE JSSC, pp. 1115-1122, July 2003.
B. Murmann
EE315B - Chapter 7
6
Bubble Problem
(e.g. due to
timing offset
between two
comparators)
•
Correct output: 1000
1000, actual output: 1110 (!)
B. Murmann
EE315B - Chapter 7
7
Bubble Tolerant Encoder
•
Protects against isolated, single "bubbles"
•
Reference: C. W. Mangelsdorf, “A 400-MHz Flash Converter with Error
C
Correction,”
ti ” IEEE J.
J Solid-State
S lid St t Ckts.,
Ckt pp. 184-191,
184 191 F
Feb.
b 1990
1990.
B. Murmann
EE315B - Chapter 7
8
Alternative (or Additional) Solution
Dedicated T/H at input
drastically reduces
dV/dt at comparator
inputs
Y. Tamba, and K. Yamakido, "A CMOS 6 b 500 MSample/s ADC for a hard disk
drive read channel
channel,“ ISSCC Dig.
Dig Techn.
Techn Papers.
Papers pp.324-325,
pp 324 325 Feb
Feb. 1999
1999.
B. Murmann
EE315B - Chapter 7
9
Metastability
•
Different gates interpret metastable output X differently
•
Correct output: 0111 or 1000, actual output: 1111
B. Murmann
EE315B - Chapter 7
10
Solution 1: Latch Pipelining
•
Use additional latches to create extra gain before generating
decoder signals
•
P
Power
h
hungry and
d area iinefficient
ffi i t
EE315B - Chapter 7
B. Murmann
11
Solution 2: Gray Encoding
Thermometer Code
Gray
Binary
T1
T2
T3
T4
T5
T6
T7
G3
G2
G1
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
G3
B. Murmann
G2
•
Each Ti affects only one Gi
– Avoids disagreement
of interpretation by
multiple
p g
gates
•
Also helps protect against
sparkles
G1
EE315B - Chapter 7
12
Efficient Implementation
•
Reference
– C. Portmann and T. Meng, “Power-Efficient Metastability Error
, IEEE J. Solid-State
Reduction in CMOS Flash A/D Converters,”
Ckts., pp. 1132-40 , Aug. 1996.
EE315B - Chapter 7
B. Murmann
13
Offset
•
Typically want offset of each comparator <1/4LSB
– If we budget half of the input referred offset for the latch, the
other half for the pre
pre-amp,
amp this means pre
pre-amp
amp offset must
be <1/4LSB / sqrt(2)
3VOS  3
•
AVT
1 FSR

WL 4 2 2B
E.g. 6-bit flash ADC, FSR=1V
3
2
AVT
1 1V

 2.8mV
WL 4 2 26
2
V m 
18.4m 2
 3 AVT 
 3  4mV
2
WL  
.
m
W


18
4



 102m



0.18m
 2.8mV 
 2.8mV 
Huge!
B. Murmann
EE315B - Chapter 7
14
Options
•
Simply use large devices
– For each extra bit, need to increase width by 4x, also need
to double number of comparators
– Assuming constant current density, this means each
additional bit costs 8x in power!
•
Offset cancellation
– Tends to cost speed
•
Offset averaging
•
Calibration
B. Murmann
EE315B - Chapter 7
15
Offset Averaging (1)
•
Output of each differential pair is no longer determined by that
pair alone, which results in averaging
R2/R1=1.3
[Kattmann & Barrow, ISSCC 1991]
B. Murmann
EE315B - Chapter 7
16
DNL/
Offset Averaging (2)
[Bult & Buchwald,
Buchwald JSSC 12/1997]
[Scholtens & Vertregt, JSSC 12/2002]
B. Murmann
EE315B - Chapter 7
17
6-bit Flash ADC with Averaging
[Choi & Abidi, JSSC 12/2001]
Averaging networks designed to
reduce input referred offset by 3x
B. Murmann
EE315B - Chapter 7
18
Offset Calibration
S. Sutardja, "360 Mb/s (400 MHz) 1.1 W 0.35μm CMOS PRML read channels with 6
burst 8
8-20×
20× over
over-sampling
sampling digital servo,
servo " ISSCC Dig.
Dig Techn.
Techn Papers
Papers, Feb
Feb. 1999
1999.
B. Murmann
EE315B - Chapter 7
19
Comparator with Integrated Offset DAC
[K.-L.J. Wong and C.-K.K. Yang, "Offset compensation in comparators
with minimum input-referred supply noise," JSSC, May 2004.]
B. Murmann
EE315B - Chapter 7
20
High Performance Flash ADC with Calibration (1)
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006]
B. Murmann
EE315B - Chapter 7
21
High Performance Flash ADC with Calibration (2)
[Park & Flynn,
Flynn "A
A 3.5
3 5 GS/s 5-b
5 b Flash ADC in 90 nm CMOS
CMOS," CICC 2006]
B. Murmann
EE315B - Chapter 7
22
High Performance Flash ADC with Calibration (3)
[Park & Flynn,
Flynn "A
A 3.5
3 5 GS/s 5-b
5 b Flash ADC in 90 nm CMOS
CMOS," CICC 2006]
B. Murmann
EE315B - Chapter 7
23
Reducing Complexity
•
Example: 10-bit flash ADC
– Compared to previous 6-bit example we need to
• Use 16x the number of comparators
• Increase size & power of each comparator by 162 (matching)
– Input capacitance: 1pF·163 = 4096pF (!)
()
– Power: 500mW·163 = 2048W (!)
•
Techniques
– Interpolation
I t
l ti
– Folding
– Folding & Interpolation
– Multi-step conversion, pipelining
B. Murmann
EE315B - Chapter 7
24
Interpolation
•
Idea
– Interpolation between preamp outputs
•
Reduces number of preamps
– Reduced input capacitance
– Reduced area,
area power dissipation
•
Same number of latches
•
Important “side-benefit”
side benefit
– Decreased sensitivity to preamp offset
• Improved DNL
B. Murmann
EE315B - Chapter 7
25
Concept
[van de Plassche, p.118]
B. Murmann
EE315B - Chapter 7
26
Differential Implementation
VA  VB
0
2
B. Murmann
 VA  VB
EE315B - Chapter 7
27
Higher Order Interpolation
• Resistors produce
additional levels
• Define interpolation factor
as ratio ratio of latches
and preamps
• The example shown on
this slide has M=8
[H. Kimura et al, “A 10-b 300-MHz
I t
Interpolated-Parallel
l t d P ll l A/D C
Converter,”
t ”
IEEE J. of Solid-State Circuits, pp.
438-446, April 1993.
B. Murmann
EE315B - Chapter 7
28
Potential Issues with Interpolation
•
Must ensure that "linear range" of adjacent preamplifiers
overlaps
– Sets upper bound on preamp gain
•
Resistor string reduces signal path bandwidth
– Sets upper bound on interpolation factor
factor, typically around 4
•
For interpolation factors >2, amplifier nonlinearity can limit the
precision of zero crossings
– See e.g. [van de Plassche, p.121]
B. Murmann
EE315B - Chapter 7
29
Folding
•
Insight: most of the comparators in a flash ADC are saturated
while only the ones “near” a given input voltage level are
required
i d tto resolve
l a smallll diff
difference.
•
The folding operation maps the input signal into successive
linear segments
segments, in a periodic fashion (“modulo”
( modulo operation):
B. Murmann
EE315B - Chapter 7
30
Folding ADC
MSB
ADC
VIN
Digital
Output
LSB
ADC
Folding Circuit
•
Fast
•
Significantly fewer comparators than flash
•
Nonidealities in folder limit attainable resolution to ~10 bits
B. Murmann
EE315B - Chapter 7
31
Example: 6-bit Folding ADC
•
Coarse ADC determines segment, fine ADC determines level
within segment
•
F ldi ffactor
Folding
t (FF) quantifies
tifi number
b off ffolder
ld output
t t segments
t
B. Murmann
EE315B - Chapter 7
32
Folder Realization
•
Vref1 < Vref2 < … < Vref8
•
For any Vin, only one differential pair is "active", all others are
saturated
B. Murmann
EE315B - Chapter 7
33
Improved Realization
•
Extra differential pair removes DC component in Vout
•
Parameter K controls output common mode
B. Murmann
EE315B - Chapter 7
34
Input-Output Characteristic
B. Murmann
EE315B - Chapter 7
35
Rounding Problem
Useful
Region
B. Murmann
EE315B - Chapter 7
36
Multiple Folds (1)
•
Idea: Use several folders so that any input value falls into
useable "linear"
linear region
B. Murmann
EE315B - Chapter 7
37
Multiple Folds (2)
Hard to line up
with folder
output
Residual
distortion from
folder causes
DNL/INL
B. Murmann
EE315B - Chapter 7
38
Multiple Folds Using Single Threshold (1)
B. Murmann
EE315B - Chapter 7
39
Multiple Folds Using Single Threshold (2)
B. Murmann
EE315B - Chapter 7
•
Initial idea
– Use one folder and 7
comparators in LSB
section
•
Now have
– 8 Folders and 8
comparators (!)
•
Yet another idea
– Use interpolation to
eliminate some of
the folders
40
Interpolation
•
Same idea as discussed in the context of flash ADCs
B. Murmann
EE315B - Chapter 7
41
Interpolation Realization (1)
• Resistive interpolation
B. Murmann
EE315B - Chapter 7
42
Interpolation Realization (2)
• Current interpolation
B. Murmann
EE315B - Chapter 7
43
Complete Folding & Interpolating ADC
•
B. Murmann
EE315B - Chapter 7
6-bit
6
bit Example
– 2 folders
– 4x interpolation
– FF=8
44
State-of-the art Implementation (1)
[Taft et al.,
al JSSC 12/2004]
B. Murmann
EE315B - Chapter 7
45
State-of-the art Implementation (2)
B. Murmann
EE315B - Chapter 7
46
State-of-the art Implementation (3)
B. Murmann
EE315B - Chapter 7
47
State-of-the art Implementation (4)
B. Murmann
EE315B - Chapter 7
48
Folding ADC Problems & Solutions
•
Dynamic problems
– Frequency at the output of a folder is approximately input
frequency times folding factor!
• Finite bandwidth effects can produce zero crossing shifts
– Delay through coarse/fine signal path is not well matched
•
Possible solution
– Add track & hold circuit at ADC input
• This was done in the implementation shown in slides 20-23
•
Static problems
– Offsets in folder transistors can cause DNL, INL
– Interpolation
p
with a factor g
greater 2x can introduce DNL,, INL
due to amplifier nonlinearity
•
Possible solutions
– Averaging,
Averaging calibration
EE315B - Chapter 7
B. Murmann
49
Selected References (1)
Flash ADCs, Offset Averaging
1. K. Kattmann and J. Barrow, "A Technique for Reducing Differential Non-Linearity
Errors in Flash A/D Converters
Converters," ISSCC Digest of Technical Papers
Papers, pp.
pp 170-171
170-171,
Feb. 1991.
2. K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1mm2," IEEE J. of Solid-State Ckts., pp. 1887-1895, Dec. 1997.
3 M.
3.
M Choi and A
A. A
A. Abidi
Abidi, “A
A 6 b 1.3
1 3 Gsample/s A/D converter in 0
0.35m
35m CMOS,
CMOS ” IEEE
J. Solid-State Circuits, pp. 1847–1858, Dec. 2001.
4. C. S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18-m CMOS
Using Averaging Termination,” IEEE J. of Solid-State Ckts., vol. 37, pp. 1599-1609,
Dec 2002
Dec.
2002.
5. X. Jiang, M-C. F. Chang, "A 1-GHz signal bandwidth 6-bit CMOS ADC with powerefficient averaging," IEEE J. of Solid-State Circuits, pp. 532- 535, Feb. 2005.
Folding and Interpolating A/D Converters
6 R.C.
6.
RC T
Taft
ft ett al.,
l "A 1
1.8-V
8V1
1.6-GSample/s
6 GS
l / 8-b
8 b self-calibrating
lf lib ti ffolding
ldi ADC with
ith 7
7.26
26
ENOB at Nyquist frequency," IEEE J. Solid-State Ckts., pp. 2107-2115 Dec. 2004.
7. B. Nauta and A. G. W. Venes, “A 70-MS/s 110-mW 8-b CMOS Folding and
Interpolating A/D Converter,” IEEE J. of Solid-State Circuits, pp. 1302-1308, Dec.
1995
1995.
B. Murmann
EE315B - Chapter 7
50
Selected References (2)
8.
9.
10.
11.
12.
13.
14.
15
15.
16.
M. P. Flynn and B. Sheahan, “A 400-MSample/s, 6-b CMOS Folding and
Interpolating ADC,” IEEE J. of Solid-State Circuits, pp. 1932-1938, Dec. 1998.
H. Pan, M. Segami, M. Choi, J. Cao, F. Hatori and A. Abidi, “A 3.3V, 12b,
50MS
50MSample/s
l / A/D converter
t in
i 0.6mm
06
CMOS with
ith over 80dB SFDR,”
SFDR ” ISSCC Di
Digestt
of Technical Papers, pp. 40-41, Feb. 2000.
M.-J. Choe, B.-S. Song and K. Bacrania, “A 13b 40MSample/s CMOS pipelined
folding ADC with background offset trimming,” ISSCC Digest of Technical Papers,
pp. 36-37,
36 37, Feb. 2000.
G. Hoogzaad and R. Roovers, “A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist
ADC in 0.8 mm2,” IEEE J. Solid-State Circuits, pp. 1796-1802, Dec. 1999.
K. Nagaraj, F. Chen, T. Le and T. R. Viswanathan, “Efficient 6-bit A/D converter using
a 1-bit folding front end,” IEEE J. Solid-State Circuits, pp. 1056-1062, Aug. 1999.
M.-J. Choe and B.-S. Song, “An 8b 100MSample/s CMOS pipelined folding ADC,”
VLSI Symposium Digest of Technical Papers, pp. 81-82, Jun. 1999.
K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1
mm2,” IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997.
P Vorenkamp
P.
V
k
and
d R.
R R
Roovers, “A 12
12-b,
b 60
60-MSample/s
MS
l / cascaded
d d ffolding
ldi and
d
interpolating ADC,” IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, Dec. 1997.
A. G. W. Venes and R. J. van de Plassche, “An 80-MHz, 8-b CMOS folding A/D
converter with distributed track-and-hold preprocessing,” IEEE J. Solid-State Circuits,
vol. 31, pp. 1846-1853,
1846 1853, Dec. 1996.
B. Murmann
EE315B - Chapter 7
51
Selected References (3)
17. M. P. Flynn and D. J. Allstot, “CMOS folding A/D converters with current-mode
interpolation,” IEEE J. Solid-State Circuits, vol. 31, pp. 1248-1257, Dec. 1996.
18. R. Roovers and M. S. J. Steyaert,
y
, “A 175 Ms/s,, 6 b,, 160 mW,, 3.3 V CMOS A/D
converter,” IEEE J. Solid-State Circuits, vol. 31, pp. 938-944, Jul. 1996.
19. W. T. Colleran and A. A. Abidi, “A 10-b, 75-MHz two-stage pipelined bipolar A/D
converter,” IEEE J. Solid-State Circuits, vol. 28, pp. 1187-1199, Dec. 1993.
20. J. van Valburg and R. J. van de Plassche, “An
An 8-b
8 b 650-MHz
650 MHz folding ADC,
ADC,” IEEE J.
Solid-State Circuits, vol. 27, pp. 1662-1666, Dec. 1992.
21. R. J. van de Plassche and P. Baltus, “An 8-bit 100-MHz full-Nyquist analog-to-digital
converter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1334-1344, Dec. 1988.
22 R.
22.
R E
E. JJ. Van de Grift
Grift, I.
I W.
W J.
J M.
M Rutten and M.
M van der Veen,
Veen “An
An 8-bit
8 bit video ADC
incorporating folding and interpolation techniques,” IEEE J. Solid-State Circuits, vol.
SC-22, pp. 944-953, Dec. 1987.
23. R. E. J. van de Grift and R. J. van de Plassche, “A monolithic 8-bit video A/D
converter,” IEEE J. Solid
converter,
Solid-State
State Circuits, vol. SC
SC-19,
19, pp. 374-378,
374 378, Jun. 1984.
24. R.C. Taft, et al., "A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating
ADC with 9.1 ENOB at Nyquist frequency," ISSCC Digest of Technical Papers,
pp.78-79, 79a, Feb. 2009.
B. Murmann
EE315B - Chapter 7
52
Pipeline ADCs
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann and Katelijn Vleugels
B. Murmann
EE315B - Chapter 8
1
Outline
•
General idea of multi-step A/D conversion
•
Pipeline ADC basics
– Ideal block diagram and operation, impact of block
nonidealities
•
Ways to deal with nonidealities
– Redundancy, calibration
•
CMOS implementation details
– Stage scaling, MDAC design
B. Murmann
EE315B - Chapter 8
2
General Concept of Multi-Step Conversion
•
General idea (two-step example)
1. Perform a "coarse" quantization of the input
2. Compute residuum (error) of step 1 conversion using a DAC
and subtractor
3. Digitize computed residuum using a second "fine" quantizer
and
d digitally
di it ll add
dd tto output
t t
B. Murmann
EE315B - Chapter 8
3
Quantizer Model

B. Murmann
EE315B - Chapter 8
1
1 2
LSB  
2
2 2B
4
Analysis
•
Assuming ideal DAC (for now)
+
-
coarse
+
fine
+
•
Dfine=fine - coarse
Vrescoarse
Vin
-
+
Dout=Vin + fine
Dcoarse=Vin + coarse
Output contains only quantization error from fine ADC!
EE315B - Chapter 8
B. Murmann
5
Input to Fine Quantizer (Vres)
1
1 2
 LSB  
2
2 2 Bcoarse
•
Example
– Three decision levels in coarse and fine quantizer
– Aggregate ADC resolution is 4 bits (3+4·3 decision levels)
– Need only 6 comparators, compared to 15 in a 4-bit flash ADC
• Advantage
Ad
t
b
becomes more pronounced
d att hi
higher
h resolutions
l ti
B. Murmann
EE315B - Chapter 8
6
Alternative Illustration
B. Murmann
EE315B - Chapter 8
7
Two-Step ADC Example
B. Razavi and B.A. Wooley, "A 12-b 5-Msample/s two-step CMOS A/D
converter," IEEE JSSC, pp. 1667-1678, Dec. 1992.
B. Murmann
EE315B - Chapter 8
8
Limitations (1)
•
Conversion time is proportional to number of stages employed
– E.g. for a two-step ADC, time required for conversion is
Tconv =2·T
=2 TA/D + TD/A + TSUB
•
Solution
– Introduce a sample and hold operation after subtraction
– Fine ADC has one full clock cycle until new residuum
becomes available
– "Pipelining"
B. Murmann
EE315B - Chapter 8
9
Pipelining – An Old Idea
B. Murmann
EE315B - Chapter 8
10
Limitations (2)
•
Fine ADC(s) must have precision commensurate with overall
target resolution
– E.g. 8-bit converter with 4-bit/4-bit partition; fine 4-bit
decision levels must have "8-bit precision"
•
Solution
– Introduce gain after subtraction
Vin
+
Coarse
ADC
G
-
S/H
Fine
ADC
Dfine
+
DAC
Dout
Dcoarse
B. Murmann
EE315B - Chapter 8
11
Input to Fine Quantizer with Gain
•
No longer need precision comparators
B. Murmann
EE315B - Chapter 8
12
Pipeline ADC Block Diagram
Align & Combine Bits
Dout
Vin
SHA
Stage 1
Stage n-1
Vin1
Stage n
Vres1
G11
G
ADC
DAC
D1
EE315B - Chapter 8
B. Murmann
13
Concurrent Stage Operation
CLK
Align & Combine Bits
Dout
Vin
SHA
St
Stage
1
St
Stage
2
St
Stage
3
ACQUIRE
CONVERT
ACQUIRE
CONVERT
BUFFER
ACQUIRE
CONVERT
ACQUIRE
•
Stages operate on the input signal like a shift register
•
New output data every clock cycle, but each stage introduces ½
clock cycle latency
B. Murmann
EE315B - Chapter 8
14
Data Alignment
Doutt
CLK
CLK
CLK
CLK
Vin
SHA
Stage 1
Stage 2
Stage 3
ACQUIRE
CONVERT
ACQUIRE
CONVERT
BUFFER
ACQUIRE
CONVERT
ACQUIRE
•
Digital shift register aligns sub-conversion results in time
•
g
output
p is taken as weighted
g
sum of stage
g bits
Digital
B. Murmann
EE315B - Chapter 8
15
Latency
[Analog Devices, AD9226 Data Sheet]
B. Murmann
EE315B - Chapter 8
16
Pipeline ADC Characteristics
•
Number of components
p
g
grows linearly
y with resolution
– Unlike flash ADC, where components ~ 2B
•
Pipeline ADC trades latency for conversion speed
– Throughput limited by speed of one stage
• Enables high-speed operation
– Latency can be an issue in some applications
• E.g. in feedback control loops
•
Pipelining only possible with good analog "memory elements"
– Calls for implementation in CMOS using switched
switched-capacitor
capacitor
circuits
B. Murmann
EE315B - Chapter 8
17
Stage Analysis
• Ignore timing/clock delays for simplicity
D  Q(Vin )
B. Murmann
EE315B - Chapter 8
Vres  G  Vin  Vdac 
18
Stage Model with Ideal DAC
D  Vin  q
•
Vres  G  q
Residue
R
id off pipeline
i li stage
t
(Vres) iis equall tto ((-gain)
i ) ti
times subb
ADC quantization error
B. Murmann
EE315B - Chapter 8
19
"Residue Plot" (2-bit Sub-ADC)
{-3/4, -1/4, 1/4, 3/4}
Sub-ADC
Decision
L
Levels
l
B. Murmann
EE315B - Chapter 8
20
Questions
•
How to p
pick stage
g g
gain G for a g
given sub-ADC resolution?
•
Impact and compensation of nonidealities?
– Sub-ADC errors
– Amplifier offset
– Amplifier gain error
– Sub-DAC error
•
Begin to explore these questions using a simple example
– First stage with 2-bit sub-ADC, followed by 2-bit backend
EE315B - Chapter 8
B. Murmann
21
Upper Bound for Stage Gain
Vin

G1
G
Vres


qb
D
Db
q
{-1/2B … 1/2B}
+1
G/2B
Vres
2G/2B
2
-G/2B
-1
-1
1
Dout  Vin 
B. Murmann
qb
G
0
Vin
+1
qb
Grows out of ½ LSB bounds for G>2B
EE315B - Chapter 8
22
Issue with G=2B
Vin
G
41
Vres
qb
D
Db
q
{-1/2B
… 1/2B}
+1
Overrange!
Vres
4
-1
-1
•
0
Vin
+1
qb
Anyy error in sub-ADC decision levels will overload backend ADC and
thereby deteriorate ADC transfer function
B. Murmann
EE315B - Chapter 8
23
Idea #1: G slightly less than 2B
•
Effective stage resolution can be non-integer (R=log2G)
– E.g.
E g R = log23.2
32=1
1.68
68 bits
•
See e.g. [Karanicolas 1993]
B. Murmann
EE315B - Chapter 8
24
Idea #2: G < 2B, but Power of Two
•
Effective stage resolution is an integer
– E.g. R = log22 = 1 = B-1
– Digital
Di it l h
hardware
d
requires
i
only
l a ffew adders,
dd
no need
d tto
implement fractional weights
•
See e.g. [Mehr 2000]
B. Murmann
EE315B - Chapter 8
25
Idea #3: G=2B, Extended Backend Range
• No redundancy in stage with errors
• E
Extra
t decision
d i i llevels
l iin succeeding
di stage
t
used
d tto b
bring
i
residue "back into the box"
•
See e.g.
g [[Opris
p 1998]]
B. Murmann
EE315B - Chapter 8
26
Variant of Idea #2: "1.5-bit stage"
•
S b ADC d
Sub-ADC
decision
i i llevels
l placed
l
d tto minimize
i i i comparator
t countt
•
Can accommodate errors up to ¼
•
B = log2(2+1) = 1.589
1 589 (sub-ADC
(sub ADC resolution)
•
R = log22 = 1 (effective stage resolution)
•
See e.g. [Lewis 1992]
B. Murmann
EE315B - Chapter 8
27
Summary on Sub-ADC Redundancy
•
We can tolerate sub-ADC errors as long as
– The residue stays "inside the box", or
– Another stage downstream returns the residue "into the box"
before it reaches last quantizer
•
This result applies to any stage in an n-stage
n stage pipeline
– Can always decompose pipeline into single stage + backend
ADC
•
In literature, sub-ADC redundancy schemes are often called
"digital correction" – a misnomer in my opinion
•
There is no explicit
p
error correction!
– Sub-ADC errors are absorbed in the same way as their
inherent quantization error
• As long as there is no overranging…
B. Murmann
EE315B - Chapter 8
28
Amplifier Offset
Vos
Vos
Push
Vin
G1
G
Vres
ADC
DAC
Vdac
D
-Vos
•
Amplifier offset can be referred toward stage input and results in
– Global offset
• Usually no problem, unless "absolute ADC accuracy" is required
– Sub-ADC offset
• Easily accommodated through redundancy
B. Murmann
EE315B - Chapter 8
29
Gain Errors
qn
 G 
Dout  Vin  q1  1  1
  ...  n 1
Gd 1 

G

j 1
•
dj
Want to make Gd1 = G1+

B. Murmann
EE315B - Chapter 8
30
Digital Gain Calibration (1)
•
Error in analog gain is not a problem as long as "digital gain
term" is adjusted appropriately
•
Problem
– Need to measure analog gain precisely
•
Example
p
– Digital calibration of a 1-bit first stage with 1-bit redundancy
(R=1, B=2)
•
Note
– Even if all Gdj are perfectly adjusted to reflect the analog gains, the ADC will have nonzero DNL and INL, bounded by 0.5LSB. This can be explained by the fact that the
residue transitions may not correspond to integer multiples of the backend-LSB. This
can cause non-uniformity
if
it iin th
the ADC ttransfer
f ffunction
ti (DNL
(DNL, INL) and
d also
l nonmonotonicity (see [Markus, 2005]).
– In case this cannot be tolerated
•
•
B. Murmann
Add redundant bits to ADC backend (after combining all bits, final result can be truncated back)
Calibrate analog gain terms
EE315B - Chapter 8
31
Digital Gain Calibration (2)
Vres  G  Vin  Vdac 
Db  Vres  qb
B. Murmann
EE315B - Chapter 8
32
Digital Gain Calibration (3)
Step1:
Step2:
1)
Db( 1)  G  Vin  0.25  (qb
2)
Db( 2 )  G  Vin  0.25  (qb
1)
2)
Db( 1)  Db( 2 )  0.5  G  (qb
 (qb
•
Can minimize impact
p
of q
quantization error using
g
– Averaging (thermal noise dither)
– Extra backend resolution
EE315B - Chapter 8
B. Murmann
33
DAC Calibration
Vin
G1
G
Vres
Backend
Logic DAC
ADC
D
(D))
dac(
Force
REG
Doutt
corr(D)
1/Gd
Db
•
Essentially same concept as gain calibration
– Step through DAC codes and use backend to measure errors
•
Store coefficients for each DAC transition in a look-up
look up table
B. Murmann
EE315B - Chapter 8
34
Recursive Stage Calibration
•
First few stages have most stringent accuracy requirements
– Errors of later stages are attenuated by aggregate gain
•
Commonly used algorithm [Karanicolas 1993]
– Take ADC offline
– Measure least significant stage that needs calibration first
– Move to next significant stage and continue toward stage 1
B. Murmann
EE315B - Chapter 8
35
Combining the Bits (1)
•
Example1: Three 2-bit stages, no redundancy
Dout  D1 
B. Murmann
1
1
D2 
D3
4
16
EE315B - Chapter 8
36
Combining the Bits (2)
D1
XX
D2
XX
D3
XX
-----------Dout DDDDDD
•
•
Only bit shifts
No arithmetic circuits needed
EE315B - Chapter 8
B. Murmann
37
Combining the Bits (3)
•
Example2: Three 2-bit stages, one bit redundancy in stages 1
and 2 (6-bit aggregate ADC resolution)
Vin
B1=3
R1=2
B2=3
R2=2
Stage 1
Stage 2
B3=2
Stage 3
“8 Wires“
???
“6 Wires“
Dout[5:0]
B. Murmann
EE315B - Chapter 8
38
Combining the Bits (4)
Dout
1
1
 D1  D2 
D3
4
16
B. Murmann
D1
XXX
XXX
D2
D3
XX
-----------Dout DDDDDD
•
•
Bits overlap
Need adders ((Still,, no
good reason for calling
this "digital correction"...)
EE315B - Chapter 8
39
Combining the Bits (5)
•
For fractional weights
g
((e.g.
g radix <2),
), there is no need to
implement complex multipliers
•
Can still use simple bit shifts; push actual multiplication into lowresolution output
– E.g. a 1x10 bit multiplication needs only one adder…
•
See e.g. [Karanicolas 1993]
B. Murmann
EE315B - Chapter 8
40
Outline
•
Background
– History and state-of the art performance
– General
G
l id
idea off multi-step
lti t A/D conversion
i
•
Pipeline ADC basics
– Ideal block diagram
g
and operation,
p
impact
p
of block
nonidealities
•
Ways to deal with nonidealities
– Redundancy,
Redundancy calibration
•
CMOS implementation details
– Stage scaling, MDAC design
•
Architectural options
– OTA sharing, SHA-less front-end
•
Research topics
EE315B - Chapter 8
B. Murmann
41
Stage Implementation
Flash ADC
"MDAC"
SwitchedS
it h d
Capacitor
Circuit
B. Murmann
EE315B - Chapter 8
42
Generic Circuit
Q
1:
Q  Vin  kCs
2 :
Q  Vres  Cf  Vrefp  mCs  Vrefn   k  m  Cs
  Vres 
kCs
mCs
 k  m  Cs V
Vin 
Vrefp 
refn
Cf
Cf
Cf
 G   Vin  Vdac 
B. Murmann
EE315B - Chapter 8
43
Endless List of Design Parameters
•
Stage resolution, stage scaling factor
•
Stage redundancy
•
Thermal noise/quantization noise ratio
•
OTA architecture
– OTA sharing?
g
•
Switch topologies
•
Comparator architecture
•
F t d SHA vs. SHA
Front-end
SHA-less
l
d
design
i
•
Calibration approach (if needed)
•
Time interleaving?
•
Technology and technology options (e.g. capacitors)
 A very complex optimization problem!
B. Murmann
EE315B - Chapter 8
44
Thermal Noise Considerations
•
Total input referred noise
– Thermal noise + q
quantization noise
– Costly to make thermal noise smaller than quantization noise
•
Example: VFS=1V, 10-bit ADC
– Nquant=LSB2/12=(1V/210)2/12=(280Vrms)2
– Design for total input referred thermal noise ~280Vrms or
larger, if SNR target allows
•
Total input referred thermal noise is the sum of noise in all
stages
– How should we distribute the total thermal noise budget
among the stages?
– Let's look at an example…
B. Murmann
EE315B - Chapter 8
45
Stage Scaling (1)
•
Example: Pipeline using 1-bit (effective) stages (G=2)
•
Total input referred noise power
1

1
1

 ...
Ntot  kT  
 C1 4C2 16C3

B. Murmann
EE315B - Chapter 8
46
Stage Scaling (2)
C1/2
C1
Vin
C2/2
C2
Gm
C3/2
C3
Gm
Gm
1

1
1
Ntot  kT  

 ...
 C1 4C2 16C3

•
•
If we make all caps the same size
size, backend stages contribute
very little noise
Wasteful, because Power ~ Gm ~ C
EE315B - Chapter 8
B. Murmann
47
Stage Scaling (3)
C1/2
C1
Vin
C2/2
C2
Gm
C3/2
C3
Gm
Gm
1

1
1
Ntot  kT  

 ...
 C1 4C2 16C3

•
How about scaling caps down by 22=4x per stage?
– Same amount of noise from every stage
– All stages
t
contribute
t ib t significant
i ifi
t noise
i
– Noise from first few stages must be reduced
– Power ~ Gm ~ C goes up!
B. Murmann
EE315B - Chapter 8
48
Stage Scaling (4)
[Cline 1996]
•
Optimum capacitior scaling lies approximately midway between
these two extremes
EE315B - Chapter 8
B. Murmann
49
Practical Approach to Stage Scaling
•
Start by assuming caps are scaled precisely by stage gain
– E.g. for 1-bit
1 bit effective stages:
C/2
C
Vin
C/4
C/2
Gm
C/8
C/4
Gm
Gm
•
Refine using first pass circuit information & Excel spreadsheet
– Use estimates of OTA power, parasitics, minimum feasible
sampling capacitance etc.
•
Or, buy a circuit optimization tool…
B. Murmann
EE315B - Chapter 8
50
Stage Scaling Examples
[Cli 1996]
[Cline
EE315B - Chapter 8
B. Murmann
51
How Many Bits Per Stage?
•
Low per-stage resolution (e.g. 1-bit effective)
– Need many stages
+ OTAs have small closed loop gain, large feedback factor
• High speed
•
High per-stage resolution (e.g. 3-bit effective)
+ Fewer stages
– O
OTAs can be power
p
hungry,
g y, especially
p
y at high
g speed
p
– Significant loading from flash-ADC
•
Qualitative conclusion
– Use low per-stage resolution for very high speed designs
– Try higher resolution stages when power efficiency is most
important constraint
B. Murmann
EE315B - Chapter 8
52
Power Tradeoff is Fairly Flat!
[Chiu 2004]
 = parasitic cap at output/total
sampling cap in each stage
(junctions, wires, switches, …)
•
ADC p
power varies by
y only
y ~2x across different stage
g resolutions!
EE315B - Chapter 8
B. Murmann
53
Examples
Reference
[Yoshioka, 2007] [Jeon, 2007]
[Loloee 2002]
[Bogner 2006]
Technology
90nm
90nm
0.18um
0.13um
Bits
10
10
12
14
Bits/Stage
1-1-1-1-1-1-1-3
2-2-2-4
1-1-1-1-1-1-1-1-1-1-2
3-3-2-2-4
SNDR [dB]
~56
~54
~65
~64
Speed [MS/s]
80
30
80
100
Power [mW]
13.3
4.7
260
224
mW/MS/s
0.17
0.16
3.25
2.24
•
Low power is possible for a wide range of architectures!
B. Murmann
EE315B - Chapter 8
54
Re-Cap
•
Choosing the "optimum" per-stage resolution and stage scaling
scheme is a non-trivial task
– But – optima are shallow!
•
Quality of transistor level design and optimization is at least as
important
p
((if not more important
p
than)) architectural
optimization…
•
Next, look at circuit design details
– Assume
A
we're
' ttrying
i tto build
b ild a 10
10-bit
bit pipeline
i li
•
•
•
•
Recent technology, feature size ~0.18m or smaller
Moderate to high-speed ~100MS/s
1 bit effective/stage,
1-bit
ff ti / t
using
i "1
"1.5-bit"
5 bit" stage
t
ttopology
l
Dedicated front-end SHA
EE315B - Chapter 8
B. Murmann
55
1.5-Bit Stage Implementation
[Abo 1999] ([Lewis 1992])
•
Cf is used as sampling cap during acquisition phase, as
feedback cap in redistribution phase
– Helps
H l iimprove ffeedback
db k ffactor
t (max.
(
1/3 → max. 1/2)
B. Murmann
EE315B - Chapter 8
56
Residue Plot
[Abo 1999]
B. Murmann
EE315B - Chapter 8
57
Comparators
•
Can tolerate large
g offsets and large
g noise with appropriate
pp p
redundancy
•
Consume negligible power in a good design
– 50-100W
50 100 W or less
l
per comparator
t
•
Lots of implementation options
– Resistive/capacitive
p
reference g
generation
– Different pre-amp/latch topologies
– …
B. Murmann
EE315B - Chapter 8
58
Comparator Examples
Vin
[Chiu 2004]
[M h 2000]
[Mehr
B. Murmann
EE315B - Chapter 8
59
OTA Design Considerations
•
Static amplifier error = 1/(DC Loop Gain)
– E.g. for 0.1% accuracy in first stage of 10-bit ADC, need loop
gain > 60dB
•
Dynamic settling error
– Typically want to settle outputs to ~1/8 LSB accuracy within
1/2 clock
l k cycle
l
•
Thermal noise
– Size capacitors
p
to satisfy
y kT/C noise requirement
q
•
Start by picking an OTA topology that will deliver sufficient gain
– Or think about ways to compensate finite gain error…
•
General references on OTA design
– [Boser 2005], [Murmann, EE315A]
B. Murmann
EE315B - Chapter 8
60
Switches
[Ishii 2005]
•
Make switch RC ~ 10 times
faster than OTA
– Avoids speed degradation
– Minimizes switch noise
contribution
• See e.g. [Schreier 2005]
– Avoids stability issues due to
poles in feedback network
•
Three choices for switches
– Single N or P device
– Transmission gate
– Bootstrapped NMOS
• For high swing nodes that
require
i constant
t t Ron
EE315B - Chapter 8
B. Murmann
61
Front-End SHA
Need constant RON here to
minimize signal dependent
charge
h
iinjection
j ti ffrom S1N, S1P
Minimize
Jitter!
S1P
S1N
[Ishii 2005]
B. Murmann
EE315B - Chapter 8
62
Total Integrated OTA Noise (1)
Cf
N1  1 
g m11  g m31
 2...4
g m1
N2  1 
g m 61
2
g m51
Cs
Cc
1
kT
kT
2
Vod
 2    N1
 2(   N2  1)

Cc
CLtot
Stage 1

Cf
Cf  Cs  Cgs1
Stage 2
ignore in first
cut design
CLtot  CL  1    Cf  Cparasitic
EE315B - Chapter 8
B. Murmann
63
Total Integrated OTA Noise (2)
•
Assuming =1, N1=N2=2
1 kT
kT
2
Vod
4 
6
 Cc
CLtot
•
OTA noise partitioning problem
– How should we split noise between stage1 and stage2
terms?
•
In this design example we'll
we ll use a 2/3
2/3, 1/3 split
– This is yet another design/optimization parameter
•
With this assumption, we have
2
Vod
 18
B. Murmann
kT
CLtot
Cc 
EE315B - Chapter 8
CLtot
3
64
Stage 1 Noise
Cs2
Cs1=C1P+C2P

Cs1 / 2
1

Cs1  Cggs1 3
2
Vod
,1  18
 1C
CLtot  Cs 2   1   s1
 3 2
Vid2 ,1 
kT
Cs 2  Cs1 / 3
18
kT
2 Cs 2  Cs1 / 3
2
EE315B - Chapter 8
B. Murmann
65
SHA Noise

Cs 0
1

Cs 0  Cgs1 2
Cs1
 1C
CLtot  Cs1   1   s 0
 2 2
Cs0
Design choice: Cs0 = Cs1
From sample phase (1)
2
2
Vod
,0  Vid ,0  18
B. Murmann
kT
kT
kT

 16
Cs1  Cs 0 / 4 Cs 0
Cs1
EE315B - Chapter 8
66
Noise Budgeting
•
Total input referred noise budget, assuming VFS,diff=1V
– Nthermal = Nquant=LSB2/12=(1V/210)2/12=(280Vrms)2
•
Reasonable "first cut" partitioning of input referred noise
– SHA → 1/2
– Stage 1 → 1/4
– All remaining stages → 1/4
Vid2 ,0  16
Vid2 ,1 
kT 1
2
  280Vrms   Cs1  1.66 pF
Cs1 2
9
kT
1
2
  280Vrms   Cs 2  0.38 pF
2 Cs 2  Cs1 / 3 4
EE315B - Chapter 8
B. Murmann
67
Capacitor Sizes
•
Cs0
1.66pF
Cs1
1 66 F
1.66pF
Cs2
0.38pF
Cs3
190fF
Cs4
85fF
Cs5
42.fF (minimum)
…
…
Cs10
42.fF (minimum)
/2
/2
/2
Now refine these numbers using simulation and Excel spreadsheet
– Iterate over assumptions/design
p
g choices to optimize
p
design
g
B. Murmann
EE315B - Chapter 8
68
Reality Check
[Honda 2007]
•
Not too far off from a practical design…
EE315B - Chapter 8
B. Murmann
69
Kawahito's Design Charts (1)
(1-bit effective in each stage)
[Kawahito 2006]
(using single-stage OTA model)
B. Murmann
EE315B - Chapter 8
70
Kawahito's Design Charts (2)
[[Kawahito 2006]]
• Consider time-interleaving at high fs
• In theory,
y, plenty
p
y of room for p
power
improvement…
EE315B - Chapter 8
B. Murmann
71
Selected References (1)
•
General
– S. Kawahito, "Low-Power Design of Pipeline A/D Converters," Proc. CICC, pp.
505-512, Sep. 2006.
•
Redundancy & Calibration
– S. H. Lewis et al., "A 10-b 20-Msample/s analog-to-digital converter," IEEE
JSSC, pp. 351-358, Mar. 1992.
– A. N. Karanicolas et al. "A 15-b 1-Msample/s
p
digitally
g y self-calibrated p
pipeline
p
ADC," IEEE J. Of Solid-State Circuits, pp. 1207-1215, Dec. 1993.
– E. G. Soenen et al., "An architecture and an algorithm for fully digital correction
of monolithic pipelined ADCs," IEEE TCAS II, pp. 143-153, Mar. 1995.
– I. E. Opris et al., "A single-ended 12-bit 20 MSample/s self-calibrating pipeline
A/D converter
converter," IEEE JSSC
JSSC, pp
pp. 1898-1903
1898-1903, Dec
Dec. 1998
1998.
– L. Singer et al., "A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120
MHz," ISSCC Dig. Techn. Papers, pp. 38-39, Feb. 2000.
– I. Mehr et al., "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE
JSSC, pp. 318-325, Mar. 2000.
– J. Ming et al., "An 8-bit 80-Msample/s pipelined analog-to-digital converter with
background calibration," IEEE JSSC, pp. 1489-1497, Oct. 2001.
– S.-Y. Chuang et al., "A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined
A/D Converter," IEEE JSSC, pp. 674-683, Jun. 2002.
– J.
J Markus et al
al., "On the monotonicity and linearity of ideal radix
radix-based
based A/D
converters," IEEE Trans. Instr. and Measurement, pp. 2454-2457, Dec. 2005.
B. Murmann
EE315B - Chapter 8
72
Selected References (2)
•
Implementation
– T. Cho, "Low-Power Low-Voltage Analog-to-Digital Conversion Techniques
using Pipelined Architecures, PhD Dissertation, UC Berkeley, 1995,
http://kabuki eecs berkeley edu/ tcho/Thesis1 pdf
http://kabuki.eecs.berkeley.edu/~tcho/Thesis1.pdf.
– L. A. Singer at al., "A 14-bit 10-MHz calibration-free CMOS pipelined A/D
converter," VLSI Circuit Symposium, pp. 94-95, Jun. 1996.
– A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits,"
PhD Dissertation,, UC Berkeley,
y, 1999,,
http://kabuki.eecs.berkeley.edu/~abo/abothesis.pdf.
– D. Kelly et al., "A 3V 340mW 14b 75MSPS CMOS ADC with 85dB SFDR at
Nyquist," ISSCC Dig. Techn. Papers, pp. 134-135, Feb. 2001.
– A. Loloee, et. al, “A 12b 80-MSs Pipelined ADC Core with 190 mW
Consumption from 3 V in 0
0.18-um,
18 um Digital CMOS”
CMOS , Proc.
Proc ESSCIRC
ESSCIRC, pp
pp.
467-469, 2002
– B.-M. Min et al., "A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,"
IEEE JSSC, pp. 2031-2039, Dec. 2003.
– Y. Chiu,, et al.,, "A 14-b 12-MS/s CMOS p
pipeline
p
ADC with over 100-dB
SFDR,” IEEE JSSC, pp. 2139-2151, Dec. 2004.
– S. Limotyrakis et al., "A 150-MS/s 8-b 71-mW CMOS time-interleaved
ADC," IEEE JSSC, pp. 1057-1067, May 2005.
– T. N. Andersen et al., "A Cost-Efficient High-Speed 12-bit Pipeline ADC in
0 18 um Digital CMOS
0.18-um
CMOS," IEEE JSSC
JSSC, pp
pp. 1506
1506-1513,
1513 Jul 2005
2005.
B. Murmann
EE315B - Chapter 8
73
Selected References (3)
– P. Bogner et al., "A 14b 100MS/s digitally self-calibrated pipelined ADC in
0.13um CMOS," ISSCC Dig. Techn. Papers, pp. 832-833, Feb. 2006.
– D. Kurose et al., "55-mW 200-MSPS 10-bit Pipeline ADCs for Wireless
Receivers " IEEE JSSC
Receivers,
JSSC, pp
pp. 1589
1589-1595,
1595 Jul.
Jul 2006
2006.
– S. Bardsley et al., "A 100-dB SFDR 80-MSPS 14-Bit 0.35um BiCMOS
Pipeline ADC," IEEE JSSC, pp. 2144-2153, Sep. 2006.
– A. M. A. Ali et al, "A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With
100 dB SFDR and 50 fs Jitter," IEEE JSSC, pp
pp. 1846-1855, Aug.
g 2006.
– S. K. Gupta, "A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power
Realized by a High Bandwidth Scalable Time-Interleaved Architecture,"
IEEE JSSC, 2650-2657, Dec. 2006.
– M. Yoshioka et al., "A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with
Regulated Overdrive Voltage Biasing
Biasing," ISSCC Dig
Dig. Techn
Techn. Papers
Papers, pp
pp. 452
452453, Feb. 2007.
– Y.-D. Jeon et al., "A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a
Front-End S/H in 90nm CMOS," ISSCC Dig. Techn. Papers, pp. 456-457,
Feb. 2007.
– K.-H. Lee et al., "Calibration-free 14b 70MS/s 0.13um CMOS pipeline A/D
converters based on highmatching 3D symmetric capacitors," Electronics
Letters, pp. 35-36, Mar. 15, 2007.
– K. Honda et al., "A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline
A/D Converter Using Capacitance Coupling Techniques,"
Techniques, IEEE JSSC, pp.
757-765, Apr. 2007.
B. Murmann
EE315B - Chapter 8
74
Selected References (4)
•
Per-Stage Resolution and Stage Scaling
– D. W. Cline, "Noise, Speed, and Power Tradeoffs in Pipelined Analog to
Digital
g
Converters",, PhD Dissertation,, UC Berkeley,
y, November,, 1995,,
http://kabuki.eecs.berkeley.edu/~cline/thesis/thesis.pdf.
– D. W. Cline et al., "A power optimized 13-b 5 MSamples/s pipelined analogto-digital converter in 1.2um CMOS," IEEE JSSC, Mar. 1996
– Y. Chiu,, "High-Performance
g
Pipeline
p
A/D Converter Design
g in Deepp
Submicron CMOS," PhD Dissertation, UC Berkeley, 2004.
– H. Ishii et al., "A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS,"
Proc. CICC, pp. 395-398, Sep. 2005.
•
OTA Design,
Design Noise
– B. E. Boser, "Analog Circuit Design with Submicron Transistors,"
Presentation at IEEE Santa Clara Valley, May 19, 2005,
http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm
– B.
B Murmann
Murmann, EE315A Course Material,
Material http://ccnet.stanford.edu/cgihttp://ccnet stanford edu/cgi
bin/handouts.cgi?cc=ee315a
– R. Schreier et al., "Design-oriented estimation of thermal noise in switchedcapacitor circuits," IEEE TCAS I, pp. 2358-2368, Nov. 2005.
B. Murmann
EE315B - Chapter 8
75
Selected References (5)
•
Capacitor Matching Data
– C. H. Diaz et al., "CMOS technology for MS/RF SoC," IEEE Trans. Electron
Devices, pp. 557-566, Mar. 2003.
– A. Verma et al., "Frequency-Based Measurement of Mismatches Between
Small Capacitors," Proc. CICC, pp. 481-484, Sep. 2006.
•
Reference Generator
– T.
T L.
L Brooks et al
al., "A
A low
low-power
power differential CMOS bandgap reference
reference,"
ISSCC Dig. Techn. Papers, pp. 248-249, Feb. 1994.
•
Research
– B. Murmann et al., "A 12-bit 75-MS/s Pipelined ADC using Open-Loop
R id A
Residue
Amplification,"
lifi ti " IEEE JSSC
JSSC, pp. 2040
2040-2050,
2050 D
Dec. 2003
2003.
– J. Fiorenza et al., "Comparator-Based Switched-Capacitor Circuits for
Scaled CMOS Technologies, " IEEE JSSC, pp. 2658-2668, Dec. 2006.
– E. Iroaga et al. "A 12b, 75MS/s Pipelined ADC Using Incomplete Settling,"
IEEE JSSC
JSSC, pp. 748
748-756,
756 A
Apr. 2007
2007.
– J. Hu, N. Dolev and B. Murmann, "A 9.4-bit, 50-MS/s, 1.44-mW Pipelined
ADC using Dynamic Residue Amplification,“ VLSI Circuits Symposium,
June 2008.
B. Murmann
EE315B - Chapter 8
76
Bit-at-a-Time ADCs
Time Interleaving
Katelijn Vleugels
St f d University
Stanford
U i
it
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 9
1
Cyclic ADC
•
Essentiallyy same as p
pipeline,
p
, but a single
g stage
g is used in a
cyclic fashion for all operations
•
Need many clock cycles per conversion
B. Murmann
EE315B - Chapter 9
2
Implementation Example
1
Vo1
 C 
Vo1   1  5 Vo 2
 C6 
[Erdogan et al. JSSC 12/99]
2
Vo2

Vo 2  Vip  Vref
 CC4
3
EE315B - Chapter 9
B. Murmann
3
Discussion
•
Advantages
– Area efficient
• Typically only one or two switched capacitor stages plus
comparator
– Easy to calibrate
• Need to measure only one coefficient (capacitor ratio)
•
Disadvantages
– Slow
• Need many clock cycles for a single conversion
– Sub-optimal power efficiency
• Cannot scale stages like in a pipeline ADC
• Noise and accuracy requirements decrease from MSB to LSB
cycle, but invested circuit energy per cycle is (usually) constant
B. Murmann
EE315B - Chapter 9
4
Successive Approximation Register ADC
•
Binary search over DAC output
•
High accuracy achievable (16+ Bits)
– Relies on highly accurate comparator
•
Moderate speed (1+ MHz)
EE315B - Chapter 9
B. Murmann
5
Implementation
•
See e.g. [McCreary, JSSC 12/1975]
B
B
C1A  C1B  C
B. Murmann
C2  2C
C3  4C
EE315B - Chapter 9
CB  2B 1C
6
Sampling Phase (5-bit Example)
•
Sample: Sx closes, S1A, S1B, S2,…, S5 connected to Vin
•
Total charge at node Vx after opening Sx
Q  Vin  32C  Vin  Ctotal
B. Murmann
EE315B - Chapter 9
7
Bit5 Test (MSB)

Q  Vin  Ctotal  Vx  Vref   16C  Vx  16C  Cp

Ctotal
1

Vx   Vref  Vin  
2
 Ctotal  Cp
•
Vx<0  Vin>0.5Vref  Bit5=1
•
Vx>0
0  Vin<0.5V
0.5Vref  Bit5
Bit5=0
0
B. Murmann
EE315B - Chapter 9
8
Bit4 Test (Assuming bit5=0)

Q  Vin  Ctotal  Vx  Vref   8C  Vx  24C  Cp

Ctotal
1

Vx   Vref  Vin  
4
 Ctotal  Cp
•
Vx<0  Vin>0.25Vref  Bit4=1
•
Vx>0
0  Vin<0.25V
0.25Vref  Bit4
Bit4=0
0
B. Murmann
EE315B - Chapter 9
9
Limitations
•
Conversion rate typically limited by finite bandwidth of RC
network during sampling and bit-tests
•
For high resolution, the binary weighted capacitor array can
become quite large
– E.g.
g 16-bit resolution,, Ctotal~100pF
p for reasonable kT/C noise
contribution
•
If matching is an issue, an even larger value may be needed
– E.g.
E if matching
t hi di
dictates
t t Cmin=10fF,
10fF then
th 216Cmin=655pF
655 F
•
Commonly used techniques
– Implement
p
"two-stage"
g or "multi-stage"
g capacitor
p
network to
reduce array size [Yee, JSSC 8/79]
– Calibrate capacitor array to obtain precision beyond raw
technology
gy matching
g [[Lee,, JSSC 12/84]]
B. Murmann
EE315B - Chapter 9
10
High Performance Example
B. Murmann
EE315B - Chapter 9
11
Low Power Example
M.D. Scott, B.E. Boser, K.S.J. Pister, "An ultralow-energy ADC for Smart
Dust " IEEE JJ. Solid
Dust,
Solid-State
State Circuits
Circuits, pp
pp. 1123 -1129,
1129 July 2003
2003.
B. Murmann
EE315B - Chapter 9
12
O
Oversampling
li A/D Conversion
C
i
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 10
1
Recap
•
Sampling theorem
fs  2fsig ,max
•
One good reason for sampling faster ("oversampling")
– Can use lower order anti-alias filter
B. Murmann
EE315B - Chapter 10
2
Anti-Alias Filtering
EE315B - Chapter 10
B. Murmann
3
Quantization Noise
Ne(f)
2/12
fB
fs/2
•
Recall that the "noise" introduced by quantizer is evenly
distributed across all frequencies
– Provided that quantization error sequence is "sufficiently
random"
•
Idea: Let's filter out the noise beyond f=fB!
B. Murmann
EE315B - Chapter 10
4
Digital Noise Filter (1)
f B 2

f s / 2 12
•
2
12
Total quantization noise at digital output is reduced proportional
to "oversampling ratio" M=(fs/2)/fB
EE315B - Chapter 10
B. Murmann
5
Digital Noise Filter (2)
•
Increasing M by 2x, means 3-dB reduction in quantization noise
power, and thus 1/2 bit increase in resolution
– "1/2 bit per octave"
•
Is this useful?
•
Reality
R
lit check
h k
– Want 16-bit ADC, fB=1MHz
– Use oversampled 8-bit ADC with digital lowpass filter
– 8-bit increase in resolution necessitates oversampling by 16
octaves
fs  2  fB  M  2  1MHz
MH  216
 131GHz
B. Murmann
EE315B - Chapter 10
6
Noise Shaping Modulators
•
Sample and coarsely quantize the input at a rate well above the
Nyquist rate
•
Shape the spectrum of the quantization noise so as to push
most of its energy outside the signal baseband
•
Out-of-band noise, including quantization noise, is suppressed
by a subsequent digital lowpass filter (ie decimation filter)
•
Output of the digital filter can be resampled at a lower sampling
rate if the filter provides adequate anti-aliasing, as well as noise
suppression
B. Murmann
EE315B - Chapter 10
7
Noise Shaping
•
Idea: "S
Id
"Somehow"
h "b
build
ild an ADC th
thatt h
has mostt off its
it quantization
ti ti
noise at high frequencies
•
Key: Feedback
B. Murmann
EE315B - Chapter 10
8
Noise Shaping Using Feedback (1)
Y  z   E  z   A  z  X  z   A  z Y  z 
 E z
Az
1
 X z
1 A  z 
1 A  z 
 E  z  HE  z   X  z  H X  z 


Noise
Transfer
Function
Signal
Transfer
Function
EE315B - Chapter 10
B. Murmann
9
Noise Shaping Using Feedback (2)
Y z  E z
Az
1
 X z
1 A  z 
1 A  z 






Noise
Transfer
Function
Signal
Transfer
Function
•
Objective
– Want to make STF unity in the signal frequency band
– Want
W t to
t make
k NTF "small"
"
ll" in
i the
th signal
i
l frequency
f
band
b d
•
If the frequency band of interest is around DC (0…fB) we
achieve this byy making
g ||A(z)|
( )| >>1 at low frequencies
q
– Means that NTF is <<1
– Mans that STF  1
B. Murmann
EE315B - Chapter 10
10
Discrete Time Integrator
V  z   z 1U  z   z 1V  z 
v  k   u  k  1  v  k  1
V z
U z
•

z 1
1 z
1

1
z 1
z  e j T
"Infinite gain" at DC (=0, z=1)
EE315B - Chapter 10
B. Murmann
11
First Order “Delta-Sigma” Modulator
-1
-1
1
Y z  E z
 X  z  z  1  E  z  1  z 1  X  z  z 1
1
1
1
1
z 1
z 1

1
•

Output is equal to delayed input plus filtered quantization noise
B. Murmann
EE315B - Chapter 10
12
NTF Frequency Domain Analysis
He ( z )  1  z 1
 e j T / 2  e  j T / 2 
He ( j  )  1  e  j T  2e  j T / 2 


2




 2e
j
T
2

 T
 j sin 
 2


 T
   2 sin 

 2
 j
e

T 
2
 f 
He ( f )  2 sin  fT   2 sin   
 fs 
•
"First order noise Shaping"
•
Quantization noise is attenuated at low frequencies, amplified at
high
g frequencies
q
EE315B - Chapter 10
B. Murmann
13
In-Band Quantization Noise (1)
•
Question: If we had an ideal digital lowpass, what would be the
achieved SQNR as a function of oversampling ratio?
•
Can integrate shaped quantization noise spectrum up to fB and
compare to full-scale signal
Pqnoise 
fB

0

fB

0
 f
2 2 
  2 sin  
12 fs 
 fs
2 2

12 fs
2

  df
 
2
 f 
 2  df
 fs 
3
 2 2  2fB 
 2 2 1






12 3  fs 
12 3 M 3
B. Murmann
EE315B - Chapter 10
14
In-Band Quantization Noise (2)
•
Assuming a full-scale sinusoidal signal, we have

SQNR 
Psig
Pqnoise

2
 B

1  2 1  

2
2

  1.5  2B  1 2  3  M 3

2
2
2
  1





Due to noise
12 3 M 3


shaping &
digital filter
 1.76  6.02B  5.2  30 log( M )
•
dB 
(for large B)
Each 2x increase in M results in 8x SQNR improvement
– 9dB (1.5bits) per octave oversampling
EE315B - Chapter 10
B. Murmann
15
SQNR Improvement
•
Example revisited
– Want 16-bit ADC, fB=1MHz
– Use oversampled 8-bit ADC, first order noise shaping and
(ideal) digital lowpass filter
• SQNR improvement compared to case without oversampling is
-5.2dB+30log(M)
5 2dB+30l (M)
– 8-bit increase in resolution (48dB SQNR improvement)
would necessitate M60
•
N t allll th
Not
thatt b
bad!
d!
B. Murmann
M
SQNR improvement
SQ
po e e t
16
31dB (~5 bits)
256
67dB (~11 bits)
1024
85dB (~14
( 14 bits)
EE315B - Chapter 10
16
DAC Requirements
Y z  E z
Az
1
  X  z   DAC  z  
1 A  z 
1 A  z 
•
DAC error is indistinguishable
g
from signal
g
– Means that DAC must be precise to within target resolution
•
For the previous example, this means that we need an 8-bit
DAC whose
h
output
t t llevels
l h
have 16
16-bit
bit precision…
i i
EE315B - Chapter 10
B. Murmann
17
Solutions
•
Trimming or calibration
– Measure DAC levels during test or at power-up
– Apply
A l correction
ti values
l
tto each
h llevell using
i auxiliary
ili
DAC
•
Dynamic Element Matching Algorithms
– Shuffle DAC unit elements to obtain fairly
y precise
p
"average"
g
output levels
– Two ways
• Data independent shuffling
• Data dependent shuffling
– Data dependent shuffling algorithms allow to push most of
the DAC "noise" outside the signal band
– See
S e.g. [Carley,
[C l
JSSC 4/1989]
4/1989], [G
[Galton,
lt
TCAS II 10/1997]
10/1997],
[Vleugels, JSSC 12/2001]
•
Single bit DAC
B. Murmann
EE315B - Chapter 10
18
Data Independent Shuffling (1)
Carley, L.R., "A noise-shaping coder topology for 15+ bit converters,"
IEEE JSSC, vol.24, no.2, pp.267-273, Apr. 1989.
B. Murmann
EE315B - Chapter 10
19
Data Independent Shuffling (2)
Carley, L.R., "A noise-shaping
coder topology for 15+ bit
converters,"
, IEEE JSSC,, vol.24,,
no.2, pp.267-273, Apr. 1989.
B. Murmann
EE315B - Chapter 10
20
Data Dependent Shuffling (1)
•
•
Select elements such that
each one is used (on
average) the same number
of times
DAC errors quickly sum to
zero; errors are pushed to
high frequencies
R.T. Baird, and T.S. Fiez, "Improved
p
∆Σ
DAC linearity using data weighted
averaging ," IEEE ISCAS, pp.13-16,
May 1995.
B. Murmann
EE315B - Chapter 10
Code 3
Code 4
Code 2
21
Data Dependent Shuffling (2)
B. Murmann
EE315B - Chapter 10
22
Single-Bit DAC
•
A single bit DAC has only two output levels
•
Even if these two levels are imprecise,
imprecise the errors will only affect
gain and offset of the DAC and modulator
– Tolerable in many applications
EE315B - Chapter 10
B. Murmann
23
Modulator with Single-Bit Quantizer (1)
•
Model
1 bit
1-bit
code
•
Expected SQNR (from slide 15 with B=1)
2
SQNR 
Psig
Pqnoise
1  
 
9
2 2
 2  2
 2  M3
  1
2

3
12 3 M
 3.4  30 log( M )
•
dB 
E.g. M=128  SQNR=60dB
B. Murmann
EE315B - Chapter 10
24
Modulator with Single-Bit Quantizer (2)
•
Implementation example
[Schreier, p. 31]
•
Not all that great in terms of achievable SQNR, but sufficient for
some applications
– E.g. digital voltmeter
• See [van de Plassche, pp. 469]
B. Murmann
EE315B - Chapter 10
25
Simulated Response
B. Murmann
EE315B - Chapter 10
26
Spectrum
[Schreier, p. 39]
f/fs
•
Looks like there is some noise shaping, but SQNR=55dB is
lower than the expected 60dB
B. Murmann
EE315B - Chapter 10
27
Amplitude and Frequency Dependence
[Schreier, p. 40]
[M=256]
•
Erratic dependence on amplitude and frequency
– Simple
S
linear model ffails to predict this behavior
•
Issue: Quantization error sequence is not "sufficiently random",
as assumed in the beginning
g
g of this discussion
B. Murmann
EE315B - Chapter 10
28
Quantization Error in 1st Order Modulator
Input x(n)
0.5
0
Qua
antization error e(n)
-0.5
0.5
0
•
200
400
600
800
1000
200
400
600
Sample index n
800
1000
0.5
0
-0.5
05
0
A complicated
complicated, but deterministic function of the input
B. Murmann
EE315B - Chapter 10
29
Aside: Quantizer Gain
•
Another issue is that the gain of the single bit quantizer is illdefined, but we assumed it to be unity in our analysis
•
The actual quantizer gain can be found from simulations, and
then plugged back into the linear model for better agreement
(and stability analysis using root locus, etc.)
•
References
– Schreier, Sections 3.2 and 4.2
– S.
S A
Ardalan,
d l
and
d JJ. P
Paulos,
l
"A
"An analysis
l i off nonlinear
li
b
behavior
h i
in delta - sigma modulators," IEEE TCAS, vol.34, no.6, pp.
593-603, June 1987.
– T.
T Ritoniemi,
Rit i i T
T. K
Karema, and
dH
H. T
Tenhunen,
h
"D
"Design
i off stable
t bl
high order 1-bit sigma-delta modulators," Proc. IEEE ISCAS,
pp. 3267-3270, May 1990.
B. Murmann
EE315B - Chapter 10
30
Tones
•
Since the quantization error is correlated with the input, the
shaped quantization noise contains spurious tones, some of
which lie in the signal band
•
The linear model cannot predict these tones
•
It is generally difficult to predict tonal behavior for arbitrary
inputs, even with a nonlinear model
– Analytical results exist for DC and sine inputs, see e.g.
• R.M. Gray "Spectral analysis of quantization noise in a singleloop sigma
sigma-delta
delta modulator with DC input
input,"" IEEE Trans
Trans.
Comm., pp. 588-599, June 1989.
• R.M. Gray et al., Quantization noise in single-loop sigma-delta
modulation with sinusoidal inputs," IEEE Trans. Comm., pp.
956-968, Sept 1989.
•
Interesting and intuitive to look at DC input as a worst case
B. Murmann
EE315B - Chapter 10
31
DC Input (1)
•
E.g. x(n)=0
– Modulator generates an alternating sequence of 1s and 0s
– Single
Si l ttone att fs/2;
/2 no llow ffrequency componentt
•
E.g. x(n)=0.001/2
– Compared to previous example, only one in 1000 outputs
will change
– Output has period of 1000T, and hence contains a low
frequency, in-band
in band component
B. Murmann
EE315B - Chapter 10
32
DC Input (2)
•
For a DC input, the modulator output consists of discrete tones
("idle tones") with power and frequency given by
  sin  fkT  
Pk  

k


2
x

fk  k  DC  0.5  fs
 

where k is an integer, and r represents the fractional part of r
(r modulo 1)
•
Strongest tones occur for small k, due to reciprocal dependence
•
The plot on the following slide shows the total mean square
error due to in
in-band
band idle tones as a function of DC input (M=16)
(M 16)
B. Murmann
EE315B - Chapter 10
33
MSE due to Idle Tones
X/
B. Murmann
EE315B - Chapter 10
34
Idle Tone Considerations
•
Idle tones are known to be a significant issue in audio applications
– The human ear can detect tones ~20dB below the
thermal/quantization noise floor
•
If idle tones are an issue, there are several options for mitigating their
impact
– Larger
L
oversampling
li ratio
ti
– Multi-bit quantizer and DAC
– Dither
• S
Superimpose
i
a pseudorandom
d
d
signal
i
l att th
the quantizer
ti
iinputt tto ""whiten"
hit "
quantization noise
– See e.g. Chapter 3 of Delta-Sigma Data Converters by Norsworthy, Schreier & Temes.
– Overdesign by making quantization noise much smaller than
electronic noise from integrators
• Noisy integrator(s) help randomize quantization error sequence
– Higher order modulators
• Naturally produce "more random" quantization error sequences
B. Murmann
EE315B - Chapter 10
35
Higher Order Modulators
•
Motivation: better SQNR
Q
for a given
g
oversampling
p g ratio,, p
plus
improved idle tone performance as a side benefit
•
Commonly used architectures
– Single
Si l quantizer
ti
loop
l
with
ith hi
higher
h order
d filt
filtering
i
• Essentially a logical extension to the first order noise shaping
concept discussed previously
– Cascaded,
Cascaded multi-stage
m lti stage mod
modulators
lators
• Contain a separate quantizer in each stage
B. Murmann
EE315B - Chapter 10
36
Higher Order Noise Shaping
•
Lth order noise transfer function

HE ( z )  1  z 1

L
EE315B - Chapter 10
B. Murmann
37
In-Band Quantization Noise
Pqqnoise 
fB

0

fB

0
 f 
2 2 
  2 sin    
12 fs 
 fs  
2 2

12 fs
 f 
  2 
 fs 
 2 2L  2fB 




12 2L  1  fs 
 2  2L  1 


 
12 2L  1  M 
•
2L
df
2L
df
2 L 1
2L 1
For an Lth order modulator, every doubling of M results in an
increase in SQNR of 6L+3dB (L+0
(L+0.5bits)
5bits)
B. Murmann
EE315B - Chapter 10
38
SQNR [d
dB]
SQNR with Single Bit Quantizer
EE315B - Chapter 10
B. Murmann
39
Building a Second-Order Modulator (1)
•
General idea: Start with a first order modulator and replace
p
quantizer by another first order loop
-1
-1
B. Murmann
-1
-1
EE315B - Chapter 10
40
Building a Second-Order Modulator (2)
•
More general structure
-1
-1
a1
a2
-1
-1
b
a a z 2
HX z  1 2
D z

D( z )  1  z 1
B. Murmann

2

1 z 
z 
1
HE

 a2bz 1 1  z 1  a1a2 z 2  1
2
D z
 a  a2  1 and b  2
e.g. for  1
a1  0.5,a2  2 and b  1
EE315B - Chapter 10
41
Boser-Wooley Modulator (1)
(Single-bit)
[Boser & Wooley, JSSC 12/1988]
•
a1=0.5
=0 5 and b=1
b=1, but a2=0.5
=0 5 (instead of 2)
•
Since the integrator is followed by a single-bit quantizer, a2 can
be scaled to reduce swing requirements in second integrator
B. Murmann
EE315B - Chapter 10
42
Boser-Wooley Modulator (2)
EE315B - Chapter 10
B. Murmann
43
Performance of 2nd Order Modulator
[Schreier, p.70]
•
Compared to first
order modulator,
SQNR is in "better"
agreement with
simple linear model
•
Improved idle tone
performance
-20
O
-30
1st order
O
-40
O
O
-50
O
X
O
-60
X
-70
X
-80
2nd order
-90
X
-100
X
-110
-120
X
8
16
32
64
128
256
512
1024
Oversampling Ratio
B. Murmann
EE315B - Chapter 10
44
Single Quantizer Modulators with Order >2
•
Most general (mathematical) filter decomposition
He ( z ) 
L0 ( z ) 
B. Murmann
1
1  L1( z )
Hx ( z ) 
Hx ( z )
He ( z )
L1( z )  1 
L0 ( z )
1  L1( z )
1
He ( z )
VLSI Data Conversion Circuits - Part 9
45
Stability
•
Having more than two integrators in a feedback loop means that
the loop can be unstable (criterion = BIBO)
•
From the diagram of the previous slide, it is clear that the
stability of the loop mostly depends on L1(z), and therefore the
characteristics of the NTF
•
How about the nonlinear transfer characteristic of the quantizer?
– Unfortunately, there is no crisp mathematical result that
would address this question for all possible configurations
– One important, and general aspect of having a nonlinearity
in the loop is that the stability becomes dependent on the
signal (and also L0)!
•
In practice, designers rely on a combination of stability analyses
using the linear model (!), established “heuristics,” and time
d
domain
i simulations
i l ti
off th
the nonlinear
li
model
d l
B. Murmann
EE315B - Chapter 10
46
Stability Heuristics
•
Single-bit
– First order modulator is stable (bounded integrator output)
with arbitrary inputs of less than /2 in magnitude
– Second order modulator is known to be stable with arbitrary
inputs of less than /20 in magnitude, and for "reasonable",
slow varying inputs of magnitude <0.8·/2, integrator outputs
are "likely" to stay within bounds
– Lee's criterion: modulator is "likely" to be stable if
max[He()]<1.5
•
Multi-bit
– A modulator with Nth order differentiation using an N+1 bit
quantizer is stable for arbitrary inputs with amplitude less
than half the quantizer input range (Schreier, p. 104)
– …
B. Murmann
EE315B - Chapter 10
47
Achievable SQNR
•
Diminishing return for order greater 5-6
B. Murmann
EE315B - Chapter 10
48
Topology Example: Single Feedback Loop
He ( z ) 
B. Murmann
1
1  A( z )
Hx ( z ) 
A( z )
 1 in band of interest
1  A( z )
EE315B - Chapter 10
49
Topology Example: CIFB Architecture
[Schreier, p. 115]
•
“Cascade of Integrators with Feedback”
•
All zeros of NTF lie at DC for this structure, i.e. HE(z) = (1-z-1)N
•
Can create complex conjugate zeros by adding feedback paths
around pairs of integrators (cascade of resonators, CRFB
structure)
B. Murmann
EE315B - Chapter 10
50
Typical Design Procedure
•
"Cookbook design"
– See e.g. Delta-Sigma Data Converters, by Norsworthy,
Schreier & Temes, Sections 4.4 and 5.6
– Choose order based on desired SQNR and M
– Design
g NTF using
g filter approximations
pp
((e.g.
g Chebyshev2)
y
)
• Make sure to obey Lee's criterion
– Determine loop-filter transfer function and evaluate
performance and stability
p
y using
g simulations
– Determine implementation-specific coefficients
– Scale coefficients to restrict integrator outputs to stay within
available range (“dynamic
( dynamic range scaling
scaling"))
•
Delta-Sigma Toolbox for MATLAB (by Richard Schreier)
– http://www.mathworks.com/matlabcentral/fileexchange
– Look under "Controls" and find "Delsig" toolbox
B. Murmann
EE315B - Chapter 10
51
"Cookbook" NTF Design Example (1)
% design parameters
L=4;
% order
M 64 % oversampling
M=64;
li
ratio
ti
% stop-band attenuation; reduce if needed to make max(|He(w)|<1.5)
Rstop = 80;
[b,a] = cheby2(L, Rstop, 1/M, 'high');
% normalize to make He(z->inf)=1; needed for realizability
% makes first sample of impulse response of He equal to 1
% makes first sample of impulse response of A equal to 0
% (must have at least one delay around quantizer)
b = b/b(1);
% check Lee's rule; want max(|He(w)|<1.5 )
NTF = filt(b, a, 1)
[mag] = bode(NTF
bode(NTF, pi)
B. Murmann
EE315B - Chapter 10
52
"Cookbook" NTF Design Example (2)
Transfer function:
1 - 3.998 z^-1 + 5.995 z^-2 - 3.998 z^-3 + z^-4
-----------------------------------------------------1 - 3.247 z^-1 + 4.013 z^-2 - 2.231 z^-3 + 0.4699 z^-4
mag = 1.459
0
He [dB
B]
-20
-40
40
-60
-80
-100
B. Murmann
10
-3
-2
10
Frequency [f/f s]
10
-1
EE315B - Chapter 10
53
"Cookbook" NTF Design Example (3)
% Loop filter transfer function
A = inv(NTF) - filt(1,1,1)
Transfer function:
0.7505 z^-1 - 1.982 z^-2 + 1.766 z^-3 - 0.5301 z^-4
--------------------------------------------------1 - 3.998 z^-1 + 5.995 z^-2 - 3.998 z^-3 + z^-4
% Check realizability
a = impulse(A);
a(1)
ans = 0
B. Murmann
EE315B - Chapter 10
54
Commercial Example
EE315B - Chapter 10
B. Murmann
55
Cascaded Modulators
Analog
In
x

y
DELAY
•


–
e
x
+
y
Digital
Di
it l
Out
DIGITAL
DIFFERENCE
Concept
– Cascade of two or more stable (low order) modulators
– Quantization error of each stage is quantized by the
succeeding stages and subtracted in digital domain
B. Murmann
EE315B - Chapter 10
56
Second Order (1-1) Cascade
Y1(z) = z–1X(z) + (1 – z–1)E1(z)
Y2(z) = z–1E1(z) + (1 – z–1)E2(z)
Y(z) = z–1Y1(z) – (1 – z–1)Y2(z)
= z–2X(z) + z–1(1 – z–1)E1(z) – z–1(1 – z–1)E1(z) – (1 – z–1)2E2(z)
Y(z) = z–2X(z) – (1 – z–1)2E2(z)
•
Second order noise shaping using two first order loops!
B. Murmann
EE315B - Chapter 10
57
Properties
•
Order of overall noise shaping is equal to sum of modulator
orders
•
No stability issues
•
Improved idle tone performance
– Input
I
t off second
d stage
t
is
i "noise
" i like"
lik "
– Remaining quantization error from second stage is very
close to white noise
•
Cancellation of first stage quantization noise depends on
matching between analog and digital signal paths
– Hard to suppress
pp
first stage
g q
quantization error by
y more than
40dB
– Mismatch will affect idle tone performance
B. Murmann
EE315B - Chapter 10
58
1-1-1 Cascaded Modulator (MASH)
1
z-1
1
z-1
1
z-1
B. Murmann
EE315B - Chapter 10
59
Mismatch Sensitivity
B. Murmann
EE315B - Chapter 10
60
2-1 Cascade
B. Murmann
EE315B - Chapter 10
61
Mismatch Sensitivity
B. Murmann
EE315B - Chapter 10
62
Circuit Level Considerations
•
Electronic noise
•
Integrator leak
– Finite OTA gain
•
Integrator nonlinearity
– OTA dynamic
d
i settling
ttli error
– OTA slewing
– Capacitor voltage coefficients
•
Comparator hysteresis
– Usually not a problem; simulations show that up to a few %
hysteresis can be tolerated
•
Unwanted mixing effects
– E.g. if Vref contains fs/2, out of band noise will be mixed down
g
band
into signal
B. Murmann
EE315B - Chapter 10
63
Electronic Noise
E.g. 2nd Order Switched Capacitor Modulator
•
Noise from 1st integrator is added directl
directly to the inp
inputt
– Digital filter will reduce this noise by oversampling ratio
•
Noise from 2nd integrator is first-order noise shaped!
– Digital
Di it l filt
filter will
ill remove mostt off thi
this noise
i
•
Especially for high oversampling ratios, only the first one or two integrators
add significant noise
– Qualitatively,
Qualitatively this also holds for other imperfections
imperfections.
B. Murmann
EE315B - Chapter 10
64
Example – Noise from Second Integrator
Can show:
EE315B - Chapter 10
B. Murmann
65
Integrator Analysis (1)
t/Ts
Qs
QI
n-1
Cs·Vi(n-1)
CI·Vo(n-1)
n-1/2
0
CI·V
Vo(n-1/2) = CI·V
Vo(n-1) + Cs·V
Vi(n-1)
n
Cs·Vi(n)
CI·Vo(n) = CI·Vo(n-1) + Cs·Vi(n-1)
n+1/2
…
…
B. Murmann
EE315B - Chapter 10
66
Integrator Analysis (1)
Assuming that Vo is sampled during 1, we have
•
CIVo ( n )  CIVo ( n  1)  CsVi ( n  1)
CIVo ( z )  z 1CIVo ( z )  z 1CsVi ( z )

•
Vo ( z ) Cs z 1

Vi ( z ) CI 1  z 1
Unfortunately, this ideal expression holds only for infinite
amplifier gain
– Let's look at impact of finite gain
EE315B - Chapter 10
B. Murmann
67
Integrator Leak (1)
A
t/Ts
Qs
QI
n-1
Cs·Vi(n-1)
CI·Vo(n-1)·[1+1/A]
n-1/2
Cs·Vo(n-1/2)/A
CI·Vo(n-1/2)·[1+1/A] = CI·Vo(n-1)·[1+1/A] +
Cs·V
Vi(n
(n-1)
1) - Cs·V
Vo(n
(n-1/2)/A
1/2)/A
n
Cs·Vi(n)
CI·Vo(n)·[1+1/A] = CI·Vo(n-1)·[1+1/A] +
Cs·Vi(n-1) - Cs·Vo(n)/A
n+1/2
…
…
B. Murmann
EE315B - Chapter 10
68
Integrator Leak (2)
•
Again, assuming that Vo is sampled during 1, we have
C
 1
 1
CIVo ( z ) 1    z 1CIVo ( z ) 1    z 1CsVi ( z )  s Vo ( z )
A
 A
 A

1  C 
z 1  1  1  s  
A  CI  
Vo ( z ) Cs
g  z 1




Vi ( z ) CI

1 Cs  1
1  1     z 1
z
1 1

A CI 

Vo ( z )  1     z 1Vo ( z )  g  z 1Vi ( z )
•
Finite gain results in "leaky integrator"
– Some fraction of previous output is lost in new cycle
B. Murmann
EE315B - Chapter 10
69
Frequency Domain View
•
Limited gain at low frequencies (→0, z →1)
H0  H( z ) z 1 
•
g
g
 A
1  1    
But noise shaping
p g relies on high
g integrator
g
g
gain at low frequencies…
q
B. Murmann
EE315B - Chapter 10
70
Required DC Gain
[B
[Boser
&W
Wooley,
l
JSSC 12/1988]
•
Good practice to make OTA gain at least a few times larger than
oversampling ratio
B. Murmann
EE315B - Chapter 10
71
State-of-the-art Continuous Time Modulator
[Mitteregger, ISSCC 2006]
•
B. Murmann
4-stage amplifier with
f
feedforward
f
compensation
– Impractical for SC circuits
– Great for CT delta-sigma
modulators
EE315B - Chapter 10
72
Multi-Mode Modulator
[Ouzounov ISSCC 2007]
[Ouzounov,
B. Murmann
•
Delta-sigma
g
ADCs are
more amenable to BW
and DR reconfiguration
– Very hard to
reconfigure
fi
pipelined
i li d
ADCs
•
Great for flexible, multistandard wireless
receivers
EE315B - Chapter 10
73
Decimation Filters
•
References
– J. Candy, "Decimation for Sigma-Delta Modulation," IEEE
Trans Communications,
Trans.
Communications pp.
pp 72
72-76,
76 Jan.
Jan 1986
1986.
– Chapters 1 and 13 of Delta-Sigma Data Converters, by
Norsworthy, Schreier, Temes.
– B.P.
B P Brandt and B
B.A.
A Wooley
Wooley, "A
A low-power,
low power area
area-efficient
efficient
digital filter for decimation and interpolation," IEEE J. SolidState Circuits, pp. 679-687, June 1994.
– E. Hogenauer,
g
, "An economical class of digital
g
filters for
decimation and interpolation," IEEE Trans. Acoustics,
Speech and Signal Processing, pp. 155-162, Apr 1981.
•
j
Objectives
– Remove out-of band quantization noise
– Re-sample at lower frequency
• Ideally
y at Nyquist
yq
rate
B. Murmann
EE315B - Chapter 10
74
Example
Decimation Filter (M = 256)
fS
Analog
Input
11.3
MHz
 Modulator
1-Bit
1
Bit
(2nd-Order)
11.3
MHz
fN
44.1
kHz
Digital
g
Output
(16 Bits)
Quantization
Noise
Signal
Noise
Frequency
•
Frequency
Frequency
Filter must attenuate spectral components around ± N·fN,
– Otherwise theyy will alias onto signal
g
after re-sampling
g
B. Murmann
EE315B - Chapter 10
75
Filter Requirements
•
Pass band 0…20kHz, transition band 20…24.1kHz (f=4.1kHz),
stop band 24.1kHz…5.65MHz
•
A digital FIR filter that meets these requirements would require
more than fs/f = 11.3MHz/4.1kHz  2800 coefficients
– Impractical!
B. Murmann
EE315B - Chapter 10
76
Multi-Step Decimation
•
Key idea: Don’t try to decimate down to fN in one step
– Perform a gradual reduction of sampling rate + some filtering
– E.g.
E T
Two-step
t decimation
d i ti
•
Example: M1=64, fs/M1=176.4kHz
EE315B - Chapter 10
B. Murmann
77
Sinc Filter (1)
•
A popular, low complexity choice for stage 1 is the so-called
sinc-filter
•
From a time domain perspective, this filter simply computes the
average of several samples
y( n ) 
•
Frequency
q
y domain
H( z ) 
•
N
1 1 z
N 1  z 1
1 N 1
 x n  i 
N i 0

f
sin  N
fs
1

H(  ) 
f
N

fs

  j  f  N 1
 e fs
Zeros at multiples of fs/N
– Make N=M1 to attenuate alias components!
B. Murmann
EE315B - Chapter 10
78
Cascade of K Sinc Filters
0
-10
-20
20
-30
-40
-50
K=1
-60
K=2
-70
K=3
-80
90
-90
-100
0 f B fN
fs1
M1
2f s1
M1
Frequency
3f s1
M1
•
Higher order means better rejection
– But also more in-band droop
•
Can show that for Lth order noise shaping,
p g, an ((L+1))th order sinc
filter is the best choice
B. Murmann
EE315B - Chapter 10
79
Sinc Filter Performance
Noise penalty relative to "brick wall" filter
Droop
[N
[Norsworthy,
th p.30]
30]
[Norsworthy, p.31]
•
Only about 0.14 dB increase in baseband noise for decimation
to an intermediate oversampling ratio of 4
•
If droop is undesired, it can be corrected downstream, using a
separate post-emphasis filter
B. Murmann
EE315B - Chapter 10
80
Sinc Filter Performance (2)
•
In addition to suppressing quantization noise, the filter must
attenuate out-of-band signals present at the modulator input
– Worst case freqeuncy is fs/M1-ffB
– E.g. 50dB for sinc3, and intermediate oversampling of 4x
– Any additional desired rejection must come from analog filter
at modulator input
[Norsworthy, p.31]
EE315B - Chapter 10
B. Murmann
81
Sinc Filter Implementation
Numerator Section:
X
1 – z -1
Y
+
X
Y
Delay
Denominator Section:
X
B. Murmann
1
1 – z -1
Y
X
+
Y
Delay
EE315B - Chapter 10
82
Complete Filter Implementation
THIRDORDER
SINC
FILTER
1
IN
11 3
11.3
MHz
20
176.4
176
4
kHz
FIRST
HALFBAND
FILTER
(
(R=18)
)
M 1 = 64
22
88.2
88
2
kHz
SECOND
DROOP
22
16
HALFBAND
CORRECTION
FILTER
FILTER
44.1
44
1
(
(R=110)
)
(
(R=8)
)
kHz
M2 = 2
OUT
44 1
44.1
kHz
M3 = 2
0
Passband Ripple
= ± 0.01 dB
-10
-20
[Brandt & Wooley, JSSC 6/1994]
-30
-40
40
Second
Halfband
Filter
-50
-60
First
Halfband
Filter
Third-Order
Sinc Filter
-70
-80
-90
-100
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (kHz)
EE315B - Chapter 10
B. Murmann
83
Droop Correction
0.6
0.5
0.4
0.3
Droop-Correction
Filter
0.2
First Halfband
Filter
0.1
0.0
-0.1
-0.2
Second
Halfband
Filter
Third-Order
Sinc Filter
-0.3
-0.4
05
-0.5
-0.6
0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (kHz)
B. Murmann
EE315B - Chapter 10
84
Implementation
SINC FILTER
INTEGRATORS
20
20
20
20
20
Addr
Virtual Addr.
Logic
7
7
8
7
Data RAM
PROCESSOR
Addr
(128 x 22)
R/W
Dout
•
Can use serial
C
i l
arithmetic to minimize
hardware area
– Since
Si
output
t t rate
t is
i
usually fairly low
Coefficient/
Control ROM
(256 x 22)
Din
22
22
13
22-Bit Arithmetic Unit (AU)
B. Murmann
43 multiplications and
84 additions per output
sample
 Modulator
Output
20
CLK (11.3 MHz)
Processor
Input
•
Ctrl.
Filter
Output
EE315B - Chapter 10
85
O
Oversampling
li D/A Conversion
C
i
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B – Chapter 11
1
Recap (1)
•
•
•
B. Murmann
Digital signal
Discrete in time
Discrete in amplitude
•
•
•
EE315B - Chapter 2
Analog signal
Continuous in time
Continuous in amplitude
2
Recap (2)
TS
yH (t)
Time
N-Bit Digital lnput Word x(kT)
b1
b2
b3
y(t)
Time
bN
•••
Digital-to-Analog Interface
x*(t)
Zero-Order
H ld
Hold
yH (t) Lowpass y(t) Analog
Filter
Output
EE315B - Chapter 11
B. Murmann
3
Frequency Spectra
Magnitude
Baseband Signal
SpectralImage
Images
Spectral
Bands (Dirac Reconstruction)
||X*(f)|
( )|
0
fS/2
fS
2fS
3fS
0
fS/2
fS
2fS
3fS
0
fS/2
fS
2fS
3fS
|PZ (f)|
|YH (f)|
Frequency
B. Murmann
EE315B - Chapter 11
4
Oversampling D/A Converter
•
Oversampling
g
– relaxes requirements on reconstruction filter
•
Noise shaping
– Encoding
E
di iin single
i l bit code
d ((m=1)
1)
– Relaxes requirements on D/A interface
•
BUT … addition of quantization noise, fortunately most of which
is out-of-band
EE315B - Chapter 11
B. Murmann
5
Oversampling
Magnitude
Spectral
Image
Bands
Spectral
Images
Analog Filter
|X(f)|

fB
fN
2ffN
2
( )
(a)
(M 2) fN (M-1)
(M-2)
(M 1) fN
MffN
M
Analog Filter
|XM (f)|
fB
(b)
fS = M fN
Frequency
•
Oversampling greatly reduces reconstruction filter requirements
•
How to create oversampled DAC input from a Nyquist rate signal?
B. Murmann
EE315B - Chapter 11
6
Interpolation (1)
•
Can increase the sampling rate of a discrete time signal by a
factor of M, by inserting M-1 zero-valued samples between the
actual
t l Nyquist
N
i t rate
t samples
l ("
("zero stuffing")
t ffi ")
– Causes an M-fold periodic repetition of the baseband
spectrum
Image Bands
Spectral Images
Nyquist-rate
yq
Input

fB fS =fN
2 fN
After
Zero
Insertion
(M-2) fN (M-1) fN
M fN

fB
fN
2 fN
(M-2) fN (M-1) fN fS =M fN
EE315B - Chapter 11
B. Murmann
7
Interpolation (2)
•
Why is this a good idea?
•
Can remove images and get wide transition band to play with
– Simple reconstruction filter
– Possibility of noise shaping
• Build
B ild a hi
high
h resolution
l ti DAC using
i a llow resolution
l ti D/A iinterface
t f
Digital
g
M
Lowpass
Filter
fB
fS =M fN
fB
fS =M fN
Interpolator
Output
B. Murmann
EE315B - Chapter 11
8
Example
DIGITAL
Digital
Di
it l 16
Input f
N
Digital
Digital
16
Interpolator M f
N
Noise
ANALOG
Analog
1
Reconstruction
Shaper M fN
Filter
Analog
A
l
Output
1-bit D/A Interface
•
Digital noise shaper is essentially a digital sigma-delta loop
– Shapes "truncation noise" that results from truncating 16-bit
word to a 1-bit output
EE315B - Chapter 11
B. Murmann
9
Spectra
Spectral Images
Digital
Input

fN
IInterpolator
t
l t
Output
N i
Noise
Shaper
Output
2 fN
(M-2) fN (M-1) fN
M fN
B
Baseband
b d Signal
Si
l
Truncation Noise
Quantization
Noise
M fN
M fN
Analog
Output
Frequency
B. Murmann
EE315B - Chapter 11
10
Example
E(z)
X(z)
16 +

–
+

18
z–1
+
+
19

1
z–1
Y(z)
To 1-bit D/A Interface
+
18
Clipper
+

[Su &Wooley, JSSC 12/94]
–
2
Y(z) = z – 2 X(z) + (1 – z –1 ) 2 E(z)
•
Clipper prevents second integrator from overflowing
– Digital "wrap around" would cause large errors
EE315B - Chapter 11
B. Murmann
11
Semi-Digital Reconstruction (1)
Digital
Input 1
DIN
n -Bit Shift Register
z– 1
...
z– 1
z– 1
DIGITAL
a1
...
a2
ANALOG
an

[Su &Wooley, JSSC 12/94]
Analog Output, A OUT
HFIR (z) = a1 z–1 + a2 z–2 + ... + an z–n
•
Attractive alternative to fully analog reconstruction filter
– Build FIR filter with weighted analog outputs
B. Murmann
EE315B - Chapter 11
12
Semi-Digital Reconstruction (2)
Digital
Input
128-Bit Shift Register
DIGITAL
ANALOG
Weighted
Current
Sources
a
1
...
a
2
a 128
Current-to-Voltage
Conversion
I
out
I out
AOUT  z  =
a1z
–1
+ a2z
–2
+ a3 z
–3
Analog
Output
+
+  + anz
–n
DIN  z 
H (z)
•
Li
Linear
if H(
H(z)) iis iindependent
d
d t off DIN(z)
( )
EE315B - Chapter 11
B. Murmann
13
Measurement Results
R
Reconstruction
t ti Filt
Filter
O t t
Output
0
Noise Shaper Output
Analog Output
Power S
Spectrum (dB)
– 20
– 40
– 60
– 80
– 100
– 120
– 140
– 160
1k
10k
100k
1M
Frequency (Hz)
B. Murmann
EE315B - Chapter 11
14
ADC Figures
Fi
off Merit
M it
Limits on ADC Power Dissipation
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
EE315B - Chapter 12
B. Murmann
1
ADC Figures of Merit (1)
•
Objective
j
– Want to compare performance of different ADCs
•
Can use FOM to combine several performance metrics into
one single
i l number
b
•
What are reasonable FOMs for ADCs?
•
How can we use and interpret them?
•
Trends and limits?
•
Reference: B. Murmann, “Limits on ADC Power Dissipation,” in
Analog Circuit Design, by M. Steyaert, A.H.M Roermund, J.H. van
Huijsing (eds.), Springer, 2006.
B. Murmann
EE315B - Chapter 12
2
ADC Figures of Merit (2)
[R. H. Walden, "Analog-to-digital
converter survey and analysis,
analysis " IEEE
Journal on Selected Areas in
Communications, April 1999]
FOM1  fs  2
ENOB
•
This FOM suggests that adding a bit to an ADC is just as hard
as doubling its bandwidth
•
Is this a good assumption?
B. Murmann
EE315B - Chapter 12
3
Survey Data
1bit/Octave
[Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999]
B. Murmann
EE315B - Chapter 12
4
ADC Figures of Merit (3)
[R. H. Walden, "Analog-to-digital
converter survey and analysis,
analysis " IEEE
Journal on Selected Areas in
Communications, April 1999]
f  2ENOB
FOM2  s
Power
•
Sometimes inverse of this metric is used
•
In typical circuits power ~ speed
– FOM2 captures
capt res this tradeoff correctly
correctl
•
How about power vs. ENOB?
– One additional bit = 2x in power?
p
B. Murmann
EE315B - Chapter 12
5
ADC Figures of Merit (4)
•
In a circuit that is limited by
y thermal noise,, each additional bit in
resolution means...
– 6dB SNR, 4x less noise power, 4x bigger C
– Power ~ Gm ~ C increases 4x
•
Even worse: Flash ADC
– Extra bit means 2x number of comparators
– Each of them needs double precision
– Transistor area 4x, Current 4x to maintain current density
– Net result: Power increases 8x
B. Murmann
EE315B - Chapter 12
6
ADC Figures of Merit (5)
•
FOM2 in inappropriate for comparing ADCs that are limited by
matching
g or thermal noise
– Still the most widely used FOM in publications...
•
"Tends to work" because not all power in an ADC is noise
limited
– E.g. Digital power, biasing circuits, etc.
•
To better capture
p
the case of noise limited circuits, one could
use 22ENOB in the numerator of FOM2...
– But how about other (non-noise limited) circuits?
•
My suggestion
– Avoid using a FOM that assumes a fixed relationship
between ENOB and power
B. Murmann
EE315B - Chapter 12
7
ADC Figures of Merit (6)
FOM3 
Power
 "Energy
Energy per Nyquist Sample"
Sample
2  Conversion Bandwidth
•
Compare only
C
l power off ADC
ADCs with
ith approximately
i t l same SNR or
SNDR (ENOB)
•
Useful numbers (~state-of-the-art):
(
)
– 10b (~9 ENOB) ADCs: 0.25...1 mW/MHz
– 12b (~11 ENOB) ADCs: 2...6 mW/MHz
B. Murmann
EE315B - Chapter 12
8
FOM3 (ISSCC & VLSI 1997-2008)
10
10
P/ffs [Joules]
10
10
10
10
10
10
-6
-7
-8
-9
-10
Flash
Pipeline
SAR
D lt Si
Delta-Sigma
Other
100fJ/conv-step
-11
-12
-13
20
30
40
50
60
70
SNDR [dB]
80
90
100
EE315B - Chapter 12
B. Murmann
9
Power Dissipation in Sub-100nm CMOS
10
10
P//fs [Joules]
10
10
10
10
10
10
B. Murmann
-6
-7
7
-8
-9
-10
-11
90nm and below
All
100fJ/conv-step
-12
12
-13
20
30
40
50
60
70
SNDR [dB]
EE315B - Chapter 12
80
90
100
10
Power Dissipation Trend
log(P/f s [pJ])
6
4
2
0
2008
2006
2004
2002
2000
1998
Year
20
40
60
80
100
120
SNDR [dB]
EE315B - Chapter 12
B. Murmann
11
Fundamental Limits
•
Fundamental power limit for a class-B amplifier driving a single
capacitor [Vittoz, ISCAS 1990]
P  8  fsig  CVsig 2
Vn2 
kBT
C
SNR 
2
0.5  Vsig
Vn2
 P  8kBT  SNR  fsig
•
Class-A power limit is  times higher
B. Murmann
EE315B - Chapter 12
12
Switched Capacitor Circuits
2
Sl i
Slewing
Vsig
Linear
Settling
Vsig
3
1
Ts/2
1
2
3
S/H
Class-A
C
EE315B - Chapter 12
B. Murmann
13
Case 1: 100% Slewing
Ibias  C 
Vsig
dV
C
 4  C  Vsig  fsig
dt
Ts / 2
P  2  Vsig  Ibias
2
0.5  Vsig
SNR 
kBT
C
 P  16kBT  SNR  fsig
B. Murmann
EE315B - Chapter 12
14
Case 2: 100% Linear Settling
Ibias
C
bi
dV
dt
C
max
d
dt


V
V 1  e t /    C  sig
i
 sig


max
N
N b off settling
Number
ttli titime constants:
t t
Ts / 2

 P  16  N  kBT  SNR  fsig
•
Much worse
– E.g. N=6.9 for settling to 0.1% precision
EE315B - Chapter 12
B. Murmann
15
Limit Lines
P/(2*BW) [pJ]
1.E+07
ISSCC 1997-2006
1 E+06
1.E+06
ISSCC 2007
1.E+05
Class A
Class B
Slewing
1.E+04
1.E
04
Linear Settling
1.E+03
1.E+02
1.E+01
1.E+00
1.E-01
10
20
30
40
50
60
70
80
90 100 110 120
SNDR [dB]
B. Murmann
EE315B - Chapter 12
16
Discussion
•
Orders of magnitude away from limits
•
Slope
p of limit lines is much steeper
p than fit to experimental
p
data
•
What contributes to these large gaps?
– Must keep in mind that ADCs are not just a single capacitor
circuit…
i it
•
The following analysis factors in practical considerations
– Not fundamental,, but somewhat unavoidable in today's
y
implementations
B. Murmann
EE315B - Chapter 12
17
Design Space Partitioning
•
High SNR
– Complexity ~1 (e.g. first integrator in sigma-delta ADC)
– Limited by thermal noise
•
Moderate SNR
– Complexity ~Bits
Bits (e
(e.g.
g pipelined ADC)
– Partly limited by thermal noise
•
Low SNR
– Complexity ~2Bits (e.g. flash ADC)
– Limited by matching, quantization noise
B. Murmann
EE315B - Chapter 12
18
High SNR SC-Stage (1)
VDD
Vbias
gm2
C
Ibias
Vout
1
Vin
1
2
•
C
gm1
Cg
1'
C
Considerations
– Noise is multiple of kBT/C (nf)
– Swing is only a fraction of VDD ()
– Feedback factor ()
– gm/ID is upper bounded if slewing must be avoided
EE315B - Chapter 12
B. Murmann
19
High SNR SC-Stage (2)
To avoid slewing:
 P  16  N  nf 
•
B. Murmann
g m1
1

Ibias  Vsig
1
 kBT  SNR  fsig



1
 max  1,
g

m1    V
sig
 I
 bias






Graph
p on following
g slide shows result assuming
g
– nf=5, =2/3, =0.5, onset of slewing
EE315B - Chapter 12
20
High SNR SC-Stage (3)
1.E+07
ISSCC 1997-2006
1.E+05
ISSCC 2007
SC Integrator
g
Class B
Class A
1.E+04
Slewing
Linear Settling
P/(2*BW
W) [pJ]
1.E+06
1.E+03
1.E+02
1.E+01
1.E+00
1 E 01
1.E-01
10
20
30
40
50
60
70
80
90 100 110 120
SNDR [dB]
•
Close to experimental data at high SNDR!
EE315B - Chapter 12
B. Murmann
21
Medium SNR
•
Consider two cases
•
Pipeline
p
ADC using
g SC stages
g
– Partially limited by thermal noise
•
Continuous time Gm-C integrator
– Limited by distortion
B. Murmann
EE315B - Chapter 12
22
Pipeline ADC
C
2
C/2
C/4
C/2m
2
2
2
MSB
LSB
•
Theoretical near optimum power scaling
– Scale capacitance by gain of preceding stage
– Stage 1 consumes half of total power
– Adding one bit means power goes up 4x
•
Caveat
– Usually impractical to scale capacitors down to C/2m
EE315B - Chapter 12
B. Murmann
23
Stage Scaling Example
Number of Amplifiers
12
1/4
1/8
1/16
1/32
1/64
1/128
1/128
1/128
1/128
11
1/16
1/32
1/64
1/128
1/128
1/128
1/128
1/128
10
1/64
1/128
1/128
1/128
1/128
1/128
1/128
C
13
1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
1/128
1/128
2 03
2.03
0 54
0.54
0 17
0.17
0 086
0.086
Csingle
1/2
1/8
1/32
1/128
Relative Power
Pipeline/Single SC Stage
(C/Csingle)
4.06
4.32
5.44
11.01
Stage Capacitances
•
Example is simplistic, but in line with state-of-the art
– 10bits ~0
~0.5mW/MSample/s,
5mW/MSample/s 12bits ~2mW/MSample/s
B. Murmann
EE315B - Chapter 12
24
Pipeline ADC Limit Line
1.E+07
P//(2*BW) [pJ]
1 E+06
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
ISSCC 1997-2006
1.E+01
ISSCC 2007
Pipeline
1.E+00
SC Integrator
1.E-01
10
20
30
40
50
60
70
80
90 100 110 120
SNDR [dB]
EE315B - Chapter 12
B. Murmann
25
Gm-C Integrator
VDD
VDD
C
3  v id ,max 
IM3 


32  Vov 
C
iod
vid/2
Ibias
•
cur 
-vid/2
cur 
2
iod ,max
Ibias
v id ,max
Vov

32
IM3
3
Only a small fraction of bias current can be steered into load
– E.g. IM3=60dB, cur=10%
B. Murmann
EE315B - Chapter 12
26
Gm-C Limit Line
1.E+07
P//(2*BW) [pJ]
1 E+06
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
ISSCC 1997-2006
ISSCC 2007
1.E+01
Pipeline
Gm-C Integrator
1.E+00
SC IIntegrator
1.E-01
10
20
30
40
50
60
70
80
90 100 110 120
SNDR [dB]
EE315B - Chapter 12
B. Murmann
27
Low SNR
•
Power of matching limited class-B circuit [Kinget, CICC 1996]
P
•
2
24  Cox  AVT
 fsig
 Vsig ,rms 


 3  Vos 
2
Refined result for flash ADC
ADC, assuming
– Class-A, 1/2 LSB matching with 3-confidence, 2B components, additional
Edyn per clock cycle, partial supply usage ()
1


2
P   12   Cox  AVT
 23B  2  Edyn  2B   fsig



•
Example: =2/3, Cox=15fF/m2, AVt=3mV·m, Edyn=60fJ (~10gates in
0.13m CMOS)
B. Murmann
EE315B - Chapter 12
28
End Result
1.E+07
P//(2*BW) [pJ]
1 E+06
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
ISSCC 1997-2006
ISSCC 2007
Flash
Pipeline
Gm-C Integrator
SC Integrator
1.E+01
1.E+00
1.E-01
10
20
30
40
50
60
70
80
90 100 110 120
SNDR [dB]
B. Murmann
EE315B - Chapter 12
29
Discussion
•
Shown results include only
y minor assumptions
p
about technology
gy
•
Scaling brings some good, some bad news offsetting each other
– Lower VDD, lower Vswing/VDD, …
+ Lower Edyn, higher ft enables moderate/weak inversion
operation with high gm/ID,…
•
Limit lines won't move much,, unless someone hands us a new
disruptive technology
B. Murmann
EE315B - Chapter 12
30
Future Opportunities
•
More intelligent ADCs
– Improved average power dissipation by adapting to
instantaneous speed/resolution requirements
•
"Minimalistic" ADCs using significantly simpler circuits
– Digital compensation of resulting non-idealities
non idealities
– Digital postprocessing is (within limits) "free" in terms of area
and energy
EE315B - Chapter 12
B. Murmann
31
Digital Logic Energy Trend
Mainstream ADC technologies, standard logic library data
ENAND22 [fJ/ga
ate]
10000
1000
0.5
0 35
0.35
0.25
100
0.18
10
0.13
106kT
0.09
1
1997
1999
2001
2003
2005
2007
Year
B. Murmann
EE315B - Chapter 12
32
ADC/Digital Logic Energy Ratio
10,000,000
SNDR=90dB
EAADC/ENANND2
1,000,000
70dB
100,000
50dB
10,000
30dB
1,000
100
1997
1999
2001
2003
2005
2007
Y
Year
EE315B - Chapter 12
B. Murmann
33
Energy Ratio in 2007
•
Interpretation for digitally enhanced ADCs (energy centric)
SNDR
EADC/ENAND2
30
4,679
50
37,432
70
299,479
90
2,396,045
B. Murmann
Additional digital
processing is costly!
Several tens of thousand
gates are "free"
Use as many gates as you
can fit…
EE315B - Chapter 12
34
Digital Logic Gate Density Trend
1,000,000
600 000
600,000
400,000
G
Gates/m
mm2
800,000
200,000
0
350
300
250
200
150
100
50
Technology [nm]
B. Murmann
EE315B - Chapter 12
35
Data Converter Testing
Katelijn Vleugels
Stanford University
Copyright © 2011 by Boris Murmann & Katelijn Vleugels
B. Murmann
EE315B - Chapter 13
1
Just Got Silicon Back...
B. Murmann
•
Now what ?
•
Practical aspects of converter
testing
•
Equipment requirements
•
Pitfalls
EE315B - Chapter 13
2
ADC Test Setup
Evaluation
Board?
Specs?
Signal
Generator
How to g
get
data across?
ADC
Vin
Data
Acquisition
PC
Clock
Generator
Specs?
B. Murmann
EE315B - Chapter 13
3
High-Performance ADC Specs
[W. Yang et al., "A
A 3-V
3 V 340
340-mW
mW
14-b 75-Msample/s CMOS ADC
with 85-dB SFDR at Nyquist
input," IEEE J. of Solid-State
Circuits, Dec. 2001]
•
Your converter will perform even better...
•
Testing a high performance converter may be just as challenging as
designing it!
•
Key to success is to be aware of test setup and equipment limitations
B. Murmann
EE315B - Chapter 13
4
Signal Source
•
Want: SFDR>85dB @ fin=fs/2=37.5MHz
•
Let's see, how about the "value priced" signal generator we
have in the lab...
•
•
•
B. Murmann
f=0...15MHz
Harmonic distortion (f>1MHz):
-35dBc
Need something better...
EE315B - Chapter 13
5
A Better Signal Source
•
OK now we've
OK,
' spentt about
b t $40k,
$40k this
thi should
h ld work
k now... (?)
•
•
•
B. Murmann
f=100kHz...3GHz
Harmonic distortion (f>1MHz):
-30dBc
30dBc !
No way to produce the sine
wave we need without a filter!
EE315B - Chapter 13
6
Filtering Out Harmonics
BP Filter
Amplitude
...
0
•
B. Murmann
fin
2fin
3fin
4fin
...
f
Given HD
Gi
HD=-30dBc,
30dB we need
d a stopband
t b d rejection
j ti > 60dB
to get SFDR>90dB
EE315B - Chapter 13
7
Available Filters
www.tte.com, or
www.allenavionics.com
•
Want to test at many frequencies -> Need to have many
different filters!
B. Murmann
EE315B - Chapter 13
8
Tunable Filter
www.klmicrowave.com
B. Murmann
EE315B - Chapter 13
9
Filter Distortion
•
Beware: The filters themselves also introduce distortion
•
Di t ti is
Distortion
i usually
ll nott specified,
ifi d need
d tto callll manufacturer
f t
•
Often guaranteed: HD<-85dBc,
•
Don'tt trust your filters blindly
Don
blindly...
B. Murmann
EE315B - Chapter 13
10
Clock Generator
•
OK, may be for the clock a "value-priced" signal generator will
suffice...
•
No! The clock signal controls sampling instants – which we
assumed to be precisely equidistant in time (period T)
– See Lecture for a dscussion of aperture uncertainty
•
Typically use sine wave and "square up" with inverter chain
– Jiiter requirements  sine wave specs
Board
Cl k
Clock
Generator
ADC
CLK
50
EE315B - Chapter 13
B. Murmann
11
Phase Noise and Jitter

1 f
 1 

 10L( f )[ Hz ] / 20  

f0 f0
 Hz 
"Cycle to cycle jitter"
[ j
[Hajimiri,
, The Design
g of Low Noise
Oscillators, p.147, Kluwer 1999]
Phase Noise at offset
f from "carrier"
•
Can use the above equation to get a (very rough) jitter estimate
from phase noise spectrum
•
"Value Priced" Signal Generator:
– L(30kHz)=-55dBc/Hz -> fo=15MHz= 230ps rms
•
"$40k" Signal Generator:
– L(30kHz)=-122dBc/Hz -> fo=15MHz= 0.1ps rms  OK!
B. Murmann
EE315B - Chapter 13
12
More on Jitter
•
Once we have a good enough generator, other circuit and test
setup related issues may determine jitter
•
Usually, clock jitter in the single-digit picosecond range can be
prevented by appropriate design techniques
– Separate
p
supplies
pp
– Separate analog and digital clocks
– Short inverter chains between clock source and destination
•
Few, if any, other analog-to-digital conversion non-idealities
have the same symptoms as sampling jitter
– RMS noise proportional to input frequency
– RMS noise proportional to input amplitude
•
So, if sampling clock jitter is limiting your dynamic range, it’s
easy to tell,
tell but may be difficult to fix
fix...
EE315B - Chapter 13
B. Murmann
13
Jitter Estimation
•
Reference
– D.M. Hummels, W. Ahmed, W., F.H. Irons, "Measurement of
random sample time jitter for ADCs," Proc. ISCAS, pp.708-711,
May 1995.
Spectrum of squared sequence
contains
t i a ttone proportional
ti
l tto jitter:
jitt
After removal of harmonics:
B. Murmann
EE315B - Chapter 13
14
Evaluation Board
•
Planning begins with converter pin-out
– Uhps, my clock pin is right next to a digital output...
•
Not "black magic", but weeks of design time and "thinking"
•
Key aspects
– Supply/ground routing
– Bypass capacitors
– Coupling
p g between signals
g
•
Good idea to look at ADC vendor datasheets for example
layouts/schematics/application notes
B. Murmann
EE315B - Chapter 13
15
Vendor Eval Bord Layout
[Analog Devices AD9235 Data Sheet]
B. Murmann
EE315B - Chapter 13
16
One Thing to Remember...
•
A converter does not just have one "input"
– Clock
– Power supply, ground
– Reference voltage
•
For good practices on how to avoid issues see e
e.g.
g
– Analog Devices Application Note 345: "Grounding for Lowand-High-Frequency Circuits"
– Maxim
M i Application
A li ti N
Note
t 729:
729 "Dynamic
"D
i Testing
T ti off Hi
Highh
Speed ADCs, Part 2"
B. Murmann
EE315B - Chapter 13
17
How to Get the Bits Off Chip?
•
"Full swing" CMOS signaling works well for fCLK<100MHz
•
But we want to build faster ADCs...
•
Alternative to CMOS: LVDS – Low Voltage Differential Signaling
•
LVDS vs. CMOS:
– Higher speed, more power efficient at high speed
– Two pins/bit!
Analog Devices Application Note 586: "LVDS
LVDS Data Outputs for High Speed ADCs
ADCs"
B. Murmann
EE315B - Chapter 13
18
LVDS Outputs
Analog Devices Application Note 586: "LVDS Data Outputs for High Speed ADCs"
B. Murmann
EE315B - Chapter 13
19
Data Acquisition
•
Several options:
– Logic
g analyzer
y
with PC interface
– FIFO board, interface to PC DAQ card
– Vendor kit, simple interface to printer port:
[Analog Devices, High-Speed ADC FIFO Evaluation Kit]
B. Murmann
EE315B - Chapter 13
20
Complete Setup
[Maxim Application Note 729: "Dynamic Testing of High-Speed ADCs, Part 2]
EE315B - Chapter 13
B. Murmann
21
Post-Processing
•
LabView (DAQ Software Toolbox), Matlab
– Some vendors provide example source code
– See e
e.g.
g Maxim Application Note 1819: "Selecting
Selecting the Optimum
Test Tones and Test Equipment for Successful High-Speed ADC
Sine Wave Testing"
•
We know how to evaluate spectral
p
metrics
– How about DNL/INL?
•
DAC
– "Trivial",, apply
pp y codes and use "a g
good voltmeter" to measure
outputs
•
ADC
– Need to find "decision levels", i.e. input voltages at all code
boundaries
– One way: Adjust voltage source to find exact code transitions
• "code boundary servo"
– More elegant: Histogram testing
B. Murmann
EE315B - Chapter 13
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Basic Histogram Test Setup
VREF
Ramp VREF
ADC
PC
0
•
DNL follows from total number of occurrences of each code
•
Ramp speed is adjusted to provide e.g. an average of 100
outputs of each ADC code (for 1/100 LSB resolution)
•
Ramps can be quite slow for high resolution ADCs
(65,536 codes)(100 conversions/code)
100 000 conversions/sec
100,000
= 65.6 sec
EE315B - Chapter 13
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Histogram of Ideal 3 Bit ADC
A/D Characteristics [1]
7
ADC characteristics
ideal converter
200
180
6
160
140
120
4
Counts
Digiital Output Code
5
3
100
80
2
60
1
40
20
0
0
-1
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1
2
3
4
5
ADC Input Voltage [1/]
6
7
8
EE315B - Chapter 13
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1
2
3
4
ADC output code
5
6
7
24
Histogram of Sample 3 Bit ADC
A/D Characteristics [3]
200
ADC characteristics
ideal converter
7
180
160
6
140
-0.4
0 4 LSB DNL
120
4
Counts
Digittal Output Code
5
3
100
80
+0.4 LSB INL
2
60
+0.4 LSB DNL
1
40
0
0
20
-1
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1
2
3
4
5
ADC Input Voltage [1/]
6
7
0
8
0
1
2
3
4
5
ADC
C output code
6
7
EE315B - Chapter 13
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DNL from Histogram (1)
140
Step 1
– Remove “over-range bins”
((0 and 7))
120
100
Counts,, End bins removed
d
•
80
60
40
20
0
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EE315B - Chapter 13
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1
2
3
4
5
ADC
C output code
6
7
26
DNL from Histogram (2)
Step 2
– Divide by average count
•
Step 3
– Subtract 1
– Ideal bins have exactly the
average count, which
corresponds to 1 after
normalization
•
0.4
0.3
0.2
DNL = C
Counts / Mean(Coun
nts)
•
Result is DNL
0.1
0
-0.1
-0.2
-0.3
-0.4
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1
2
3
4
5
ADC
C ou
output
pu code
6
7
EE315B - Chapter 13
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INL from Histogram
•
INL is simply running sum of
DNL (see HW)
The DNL information can
also be used directly to
construct the converter
transfer function
– Simply add up all binwidths to find transition
levels
7
6
Reconstrructed Characteristiic
•
5
4
3
2
1
0
-1
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EE315B - Chapter 13
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1
2
3
4
5
ADC Input Voltage
6
7
8
28
DNL and INL of Sample ADC
A/D Characteristics [3]
1.5
DNL [in LSB]
7
6
Digiital Output Code
5
DNL and INL of 3 Bit converter (fromhistogramtesting)
2
ADC characteristics
ideal converter
-0.4
0 4 LSB DNL
avg=-1.9e-017, std.dev=0.25, range=0.8
1
0.5
0
-0.5
-1
1
4
2
3
4
5
6
5
6
bin
3
2
+0.4 LSB INL
1.5
INL [in LSB]
2
+0.4 LSB DNL
1
avg=0.2, std.dev=0.22, range=0.4
1
0.5
0
0
-0.5
-1
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1
2
3
4
5
ADC Input Voltage [1/]
6
7
8
-1
1
2
3
4
bin
EE315B - Chapter 13
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Sinusoidal Inputs
Raw Histogram of ADC Output
250
•
•
•
Precise ramps are hard to
generate
Solution
– Use sinusoidal test signal
Problem
– Ideal histogram is not flat
but has “bath-tub shape”
200
150
100
50
0
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EE315B - Chapter 13
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1000
1500
2000
2500
3000
3500
4000
30
After Correction for Sinusoidal pdf
1.4
x 10
-3
Lineari zed Histogram
1.2
1
0.8
0.6
0.4
0.2
0
0
500
1000
1500
2000
2500
3000
3500
4000
EE315B - Chapter 13
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Resulting DNL and INL
D N L = + 1 .3 / - 1 L S B ,
1 .5
1 m is s i n g c o d e s ( D N L < - 0 . 9 )
DNL [LSB]
1
0 .5
0
- 0 .5
5
-1
0
5 00
1 00 0
1 50 0
2000
c od e
2500
3 00 0
3 50 0
4 00 0
3 00 0
3 50 0
4 00 0
INL = + 1 .7 / -0. 6 9 L S B
2
INL [LSB]
1 .5
1
0 .5
0
- 0 .5
-1
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5 00
1 00 0
1 50 0
2000
c od e
2500
EE315B - Chapter 13
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Correction for Sinusoidal pdf
•
References
– M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic
Testing and Diagnostics of A/D Converters,” IEEE TCAS,
Aug. 1986.
– IEEE Standard 1057
•
Is it necessary to know the exact amplitude and offset of the
sine wave input?
– No!
•
There exists a great deal of confusion about this in the converter
community...
EE315B - Chapter 13
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DNL/INL Code
function [dnl,inl] = dnl_inl_sin(y);
% transition levels
%DNL_INL_SIN
T = -cos(pi*ch/sum(h));
% dnl and inl ADC output
% input y contains the ADC output
% linearized histogram
% vector obtained from quantizing a
hlin = T(2:end) - T(1:end-1);
% sinusoid
% truncate at least first and last
% Boris Murmann, Aug 2002
% bin, more if input did not clip ADC
% Bernhard Boser, Sept 2002
trunc=2;
% histogram boundaries
hlin_trunc = hlin(1+trunc:end-trunc);
minbin=min(y);
maxbin=max(y);
% calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
% histogram
dnl= [0 hlin_trunc/lsb-1];
h = hist(y, minbin:maxbin);
misscodes = length(find(dnl<-0.9));
% cumulative histogram
% calculate inl
ch = cumsum(h);
inl= cumsum(dnl);
inl
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EE315B - Chapter 13
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DNL/INL Code Test
% converter model
B = 6;
% bits
range = 2^(B-1) - 1;
% ideal thresholds
DNL [LSB]
0.5
% thresholds (ideal converter)
th = -range:range;
DNL = +0.7 / -0.71 LSB, 0 missing codes (DNL<-0.9)
1
0
-0.5
th(20) = th(20)+0.7;
th(20)+0 7 % error
-1
-30
fs = 1e6;
C
-10
% try fs/10!
= round(100 * 2^B / (fs / fx));
t = 0:1/fs:C/fx;
x = (range+1) * sin(2*pi*fx.*t);
sin(2*pi*fx *t);
0
code
10
20
30
10
20
30
INL = +0.76 / -0.063 LSB
0.8
0.6
INL [LSB]
fx = 494e3 + pi;
-20
0.4
0.2
0
-0.2
-30
30
-20
20
-10
10
0
code
y = adc(x, th) - 2^(B-1);
hist(y, min(y):max(y));
dnl_inl_sin(y);
B. Murmann
EE315B - Chapter 13
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Limitations of Histogram Testing
•
The histogram test (as any ADC test, of course) characterizes
one particular converter
– Must test many devices to get valid statistics
•
Histogram testing assumes monotonicity
– E.g. “code flips” will not be detected.
•
Dynamic sparkle codes produce only minor DNL/INL errors
– E.g. 123, 123, …, 123, 0, 124, 124, …
– Must look directly at ADC output to detect
•
Noise not detected or improves DNL
– E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
•
Reference
– B. Ginetti and P. Jespers, “Reliability of Code Density Test
for High Resolution ADCs,” Electron. Letters, pp. 2231-2233,
Nov 1991.
Nov.
1991
B. Murmann
EE315B - Chapter 13
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Hiding Problems in the Noise
•
INL looks a lot like there
are 5 missing codes
•
DNL "smeared out" by
noise!
i !
•
Always look at both
DNL/INL
•
INL usually does not lie...
[Source: David Robertson, Analog Devices]
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