Extraction Correlation Between the IC Compiler and StarRC Tools
Prerequisite for Checking Correlation
1. Ensure that the design is completely routed. Do not check correlation for
unrouted or partially routed designs because although the IC Compiler tool
estimates unrouted nets, the StarRC tool does not. If the IC Compiler tool
reports a net as not fully connected, by issuing an RCEX-060 message,
use the verify_zrt_route command to check if it is open.
2. Before you perform StarRC extraction, ensure that the design does not
have many minimum-spacing and minimum-width errors.
3. Ensure that there are no opens or shorts reported in the StarRC run.
Steps for Ensuring Correlation
1. Ensure that the same ITF file is used to generate the TLUPlus and nxtgrd
files and that all the features in the ITF file are supported by both tools.
See the SolvNet article 023179 for information on the support ITF features
in the IC Compiler and StarRC tools.
2. Ensure that both the .nxtgrd and TLUPlus files have been generated using
the same grdgenxo version. To do so, ensure that the grd_ver in the
header portion of the nxtgrd and TLUPlus files match.
3. Generate the TLUPlus files using the recommended StarRC grdgenxo
version that is the same as or earlier than the IC Compiler version.
For example:
o Use StarRC’s grdgenxo version J-2014.06 with IC Compiler version
J-2014.09.
o Do not use StarRC’s grdgenxo version J-2014.12 with IC Compiler
version J-2014.09.
4. Pass the operating temperature information to the StarRC tool by using
the OPERATING_TEMPERATURE command.
o The IC Compiler tool picks up this information automatically from the
operating condition.
5. Ensure that the pin capacitance information is provided to the StarRC tool
o The IC Compiler tool takes the pin capacitance information from
the .db file
o The StarRC tool takes the pin capacitance information from the .db
files present in the LM view
o If LM views are not present, specify the pin capacitance information
in the StarRC tool by using the SKIP_CELL_PORT_PROP_FILE
command.
6. Use the StarRC REDUCTION: TOPOLOGICAL command for pin-to-pin
resistance correlation. The default value is YES. If you are using the
StarRC Simultaneous Multi Corner (SMC) flow, you could also use
REDUCTION: NO_EXTRA_LOOPS command with the
REDUCTION_MAX_DELAY_ERROR setting for timing error control.
7. Disable virtual shield extraction by using the following command:
o set_extraction_options -virtual_shield_extraction false
8. Do not specify the maxIntraCapDistRatio setting in the technology file.
Let the tool use the default value of 8
9. Do not compare to StarRC metal fill emulation. To do so, ensure that
the .itf file does not have FILL-related information. Emulation metal fill is
used in the early stage of the place and route flow and not recommended
for correlation with the StarRC tool.
10. Ensure that the metal fill setting between the IC Compiler and StarRC
tools are consistent. The recommendation is to perform correlation without
metal fill in both tools.
11. Ensure that the following command settings, when used, are consistent in
both tools:
IC Compiler
set_extraction_options \
-max_net_ccap_thres
set_extraction_options \
-max_net_ccap_ratio
set_extraction_options \
-max_net_ccap_avg_ratio
set_extraction_options \
-max_process_scale
StarRC
COUPLING_ABS_THRESHOLD
COUPLING_REL_THRESHOLD
COUPLING_AVG_THRESHOLD
MAGNIFICATION_FACTOR
12. Ensure that the pin resistance extraction setting is consistent between the
two tools. If you use a version of the IC Compiler tool prior to G-2012.06SP2, you need to use the INSTANCE_PORT:SUPERCONDUCTIVE StarRC
command setting. If you use the G-2012.06-SP2 or later version of the IC
Compiler tool, enable pin resistance extraction by using the following
command:
o
set_extraction_options –include_pin_resistance true
For the best resistance correlation between the IC compiler and StarRC tools,
you should use INSTANCE_PORT:SUPERCONDUCTIVE StarRC command
setting
Typical Threshold Settings for Checking Correlation
Process
Technology
Threshold Settings
Changes in Tool Settings
Accuracy
Expectation
(No Metal Fill)
14/16/20 nm
Total Capacitance (ff)
:1
Coupling Capacitance:
Absolute Threshold (ff) : 0.5
Relative Threshold (%) : 0.03
Pin-Pin Resistance (Ohm) : 50
StarRC settings:
MODE: 400
COUPLING_ABS_
THRESHOLD: 5e-16
COUPLING_REL_
THRESHOLD: 0.03
Total Cap:
Mean Error: +- 3%
Standard
Deviation : +/- 5%
IC Compiler settings:
(assuming PF is the
capacitance unit):
28 nm
Total Capacitance (ff)
:1
Coupling Capacitance:
Absolute Threshold (ff) : 0.5
Relative Threshold (%) : 0.03
Pin-Pin Resistance (Ohm) : 3
set_extraction_options \
-max_net_ccap_thres
0.0005 \
-max_net_ccap_ratio 0.03
Resistance:
Mean Error: +/- 3%
Standard
Deviation:3
StarRC settings:
MODE: 400
COUPLING_ABS_
THRESHOLD: 5e-16
COUPLING_REL_
THRESHOLD: 0.03
Total Cap:
Mean Error: +- 3%
Std. Deviation : +/5%
IC Compiler settings:
(assuming PF is the
capacitance unit):
45 nm
Total Capacitance (ff)
:2
Coupling Capacitance:
Absolute Threshold (ff) : 1
Relative Threshold (%) : 0.03
Pin-Pin Resistance (Ohm) : 3
Coupling Cap:
Mean Error: +- 5%
Standard
Deviation : +/- 10%
Coupling Cap:
Mean Error: +- 5%
Standard.
Deviation : +/- 10%
set_extraction_options \
-max_net_ccap_thres
0.0005 \
-max_net_ccap_ratio 0.03
Resistance:
Mean Error: +/- 3%
Standard.
deviation:3
StarRC settings:
MODE: 400
COUPLING_ABS_
THRESHOLD: 1e-15
COUPLING_REL_
THRESHOLD: 0.03
Total Cap:
Mean Error: +- 3%
Standard
Deviation : +/- 5%
IC Compiler settings:
(assuming PF is the
capacitance unit):
Coupling Cap:
Mean Error: +- 5%
Standard
Deviation : +/- 8%
65 nm
Total Capacitance (ff)
:3
Coupling Capacitance:
Absolute Threshold (ff) : 1
Relative Threshold (%) : 0.03
Pin-Pin Resistance (Ohm) : 3
set_extraction_options \
-max_net_ccap_thres 0.001
\
-max_net_ccap_ratio 0.03
Resistance:
Mean Error: +/- 3%
Standard.
Deviation:3
StarRC settings:
MODE: 400
COUPLING_ABS_
THRESHOLD: 1e-15
COUPLING_REL_
THRESHOLD: 0.03
Total Cap:
IC Compiler settings:
(assuming PF is the
capacitance unit):
set_extraction_options \
-max_net_ccap_thres 0.001
\
-max_net_ccap_ratio 0.03
>=
90 nm
Total Capacitance (ff)
:5
Coupling Capacitance:
Absolute Threshold (ff) : 3
Relative Threshold (%) : 0.1
Pin-Pin Resistance (Ohm) : 5
No change in settings for IC
Compiler;
Use MODE: 200 in StarRC
Mean Error : +/-3%
Standard Deviation:
5%
Coupling
capacitance
Mean Error: +/-5%
Standard Deviation
8%
Resistance:
Mean Error: +/- 3%
Standard
Deviation:3
Total capacitance
Mean Error: +/-3%
Std Deviation: 5%
Coupling
capacitance
Mean Error: +/-5%
Standard Deviation:
7%
Resistance:
Mean Error: +/- 3%
Standard
Deviation:3