VHDL
Reference Sheet
by Scott Tippens
Entity
Data Types
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity EntityName is
generic (
SIZE: integer;
SEED: std_logic_vector(7 downto 0)
);
port (
lockCode: in std_logic_vector(SIZE-1 downto 0);
status:
out std_logic_vector(3 downto 0)
);
end EntityName;
Scalar Types
bit
boolean
integer
natural
positive
character
real
severity_level
time
std_logic
Boolean
'1', '0'
True, False
0, 1, 24, -34 (constrain range!)
0 and above (integer subtype)
1 and above (integer subtype)
'a', 'b', '0', '1', '$'
4.3, -23.2, 1.4E6, 12.6E-3
NOTE, ERROR, WARNING
2 ns (ps, ns, us, ms, sec, min, hr)
'0', '1', 'U', 'X', 'Z', 'W', 'L', 'H', '-'
Composite Types
bit_vector
string
std_logic_vector
Architecture
-- All comments begin with two dashes
architecture EntityName_ARCH of EntityName is
constant ACTIVE: std_logic := '1';
type modes_t is (IDLE, RUN, STOP);
signal currentMode: modes_t;
component OtherEntity
generic (
COUNT: integer;
MASK: std_logic_vector(7 downto 0)
);
port (
dataIn: in std_logic;
dataOut: out std_logic_vector(3 downto 0)
);
end component;
begin
DECODER: OtherEntity
generic map (
COUNT => 12,
MASK => X"F3"
)
port map (
dataIn => lockCode(SIZE-1),
dataOut => status
);
end EntityName_ARCH;
Data Flow Statements
signed
unsigned
"10011011", 12, -28
"100011110011", 142, 23
'U'
'X'
'0'
'1'
'Z'
'W'
'L'
'H'
'-'
Signal Attributes
s'event
s'last_value
true if s changed value this cycle
returns value of s prior to event
Array Attributes
a'left
a'right
a'range
a'length
a'reverse_range
leftmost subscript of array
rightmost subscript of array
full range of the array
number of elements in array
full reverse range of the array
when
when
when
when
when
(lampTest='1')
(sel="00")
(sel="01")
(sel="10")
others;
else
else
else
else
PROCESS_NAME: process (reset, clock)
variable counter: integer range 0 to 1024;
begin
if (reset=ACTIVE) then
pulse <= not ACTIVE;
elsif (rising_edge(clock)) then
if (counter=MAX_COUNT) then
pulse <= ACTIVE;
counter := 0;
else
pulse <= not ACTIVE;
counter := counter + 1;
end if;
end if;
end process;
type my_array_t is array (0 to 15) of std_logic;
signal buffer: my_array_t;
buffer(8) <= '1';
case Statement
Record Types
case (myChar) is
when 'a' | 'A' =>
statements;
when 'b' | 'B' =>
statements;
when others =>
statements;
end case;
type test_vector_t is record
writeEn: std_logic;
readEn: std_logic;
dataIn: std_logic_vector(15 downto 0);
end record;
signal myVector: test_vector_t;
myVector <= ('1', '0', X"4FB2");
for Statement
Type Conversion
Equality
Inequality
Less than
Less than or equal
Greater than
Greater than or equal
Predefined Attributes
Note: Within architecture concurrent area only
Process and if/elsif Statement
Uninitialized
Forced Unknown
Forcing 0
Forcing 1
High Impedance
Weak Unknown
Weak 0
Weak 1
Don't Care
Array Types
Relational Operators
for i in 0 to 10 loop
for j in 8 downto 1 loop
statements;
end loop;
end loop;
to_unsigned( I , U'length )
to_integer( U )
)
(U
ed
gn
si
)
std_logic_vector( U )
S
d(
ne
sig
un
Function
unsigned
U
unsigned( V )
to_signed( I, S'length )
integer
I
to_integer( S )
Addition
Subtraction
Modulus
Remainder
Absolute value
Multiplication
Division
Exponentiation
Concatenation
Conditional Signal Assignment
Processes and Functions
Operators: and, or, nand, nor, xor, nxor, not
+
mod
rem
abs
*
/
**
&
with sel select
x <= a when "00",
b when "01",
c when "10",
d when others;
x <= "111"
"000"
"001"
"010"
"100"
"0101101", "10"
"Hello World!"
"10011011", "XZZ10"
std_logic
Logical Operators
Mathematical Operators
Note: Within architecture concurrent area only
Numeric Standard Types
Operators
=
/=
<
<=
>
>=
mode <= apple and (orange or not peach);
Selected Signal Assignment
function rising_edge( signal s: std_logic) return boolean is
constant MAX: integer := 24;
variable mode: std_logic;
begin
return (s'event and s='1' and s'last_value='0');
end function rising_edge;
Package
signed
S
std_logic_vector( S )
std_logic_vector
V
signed( V )
Shift Operations
Recommend concatenation in place of operators.
Allow describing more complex shift operations.
signal myVector: std_logic_vector(15 downto 0);
shiftLeft <= myVector(14 downto 0) & '0';
shiftRight <= '0' & myVector(15 downto 1);
rotateLeft <= myVector(14 downto 0) & myVector(15);
rotateRight <= myVector(0) & myVector(15 downto 1);
Body not required if no functions or procedures.
Body defines functions and procedures.
package physical_io_package is
constant ACTIVE: std_logic := '1';
function to_bcd( a: integer) return std_logic_vector;
component
... -- full port and generic declaration here
end component;
end package physical_io_package;
package body physical_io_package is
constant WIDTH: integer := 4; -- scope only in body
function get_area( length: integer) return integer is
begin
return length * width;
end function get_area;
end package body physical_io_package;
shiftLeft4 <= myVector(11 downto 0) & "0000";
Version 1.0 (2023-05-26)