This article has been accepted for publication in IEEE Transactions on Components, Packaging and Manufacturing Technology. This is the author's version which has not been fully edited
content may change prior to final publication. Citation information: DOI 10.1109/TCPMT.2023.3344328
1
Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
Liquid Metal Interconnects for High Pin Count
Scaling and Socketing Applications
Srikant Nekkanty, Karumbu Meyyappan, Saikat Mondal, Pooya Tadayon
Assembly Test & Technology Development
Intel Corporation, USA
*srikant.nekkanty@intel.com
Abstract— The omnipresent demand for more compute power
along with an increase in memory and high-speed signaling input
–output (HSIO) bandwidth are key drivers behind the exponential
growth in board/second level interconnect (SLI) pin count,
processor package size and thermo-mechanical enabling
complexity. There is also an increasing desire for low-cost
separable interconnect solutions with “late attach” option for
better inventory control and allowing replacement of the processor
packages to enable in-field upgrade/repair and meet reliability,
availability, serviceability (RAS) requirements. Incumbent
interconnect technologies like socketable land grid array (LGA) or
permanently soldered down ball grid array (BGA) come with
inherent limitations that are not scalable and do not meet future
yield, performance, total cost of ownership and system on chip
(SoC) density demands. In this paper, we discuss a novel approach
to overcome these limitations. The proposed solution uses gallium
based liquid metal interconnects that do not require sustained
mechanical load to achieve a stable electrical connection, unlike
LGA, and, hence, decouple pin count scaling from mechanical
loading complexity. In addition, liquid metal interconnects offer
the benefit of reduced lower-level contact resistance (LLCR) with
the elimination of constriction resistance between the conductors
as compared to LGA. In this paper, we discuss the feasibility of
liquid metal interconnects for board/SLI applications, benefits of
the technology to meet future scaling needs.
reduction, as shown in figure 2 based on Intel ® projections, is
limited by Type 3 printed circuit board (PCB) [3]
manufacturing for cost reasons which results in larger form
factor sockets and packages.
Fig 1: Historical server socket pin growth extrapolated out to
the end of the decade.
Index Terms— Liquid metal, gallium, interconnects, sockets
I. INTRODUCTION
There is an ever-growing demand for high performance
compute along with an increase in memory and HSIO for
integrated circuit (IC). This growing demand for total compute
power and memory and I/O bandwidth, especially for data
center server applications, drives exponential growth in
motherboard or second level interconnect (SLI) pin count.
Figure 1 shows the pin count trend for server processors
packages from Intel ® and others [1], [2], plotted as a function
of time and extrapolated out to the future. The trends show that
pin counts for server processor packages are projected to reach
more than 15K pins before the end of this decade. However,
while the server pin count trend is exponential, the board pitch
Fig 2: Server board pitch scaling, based on internal projections,
is limited by Type 3 PCB manufacturing for cost reasons.
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content may change prior to final publication. Citation information: DOI 10.1109/TCPMT.2023.3344328
2
Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
A growing trend of co-packaged solutions is also emerging,
consisting of integration of multi-chip modules to increase
system on chip (SoC) density, such as companion memory,
silicon photonics, etc., to address the need for low power, low
latency, and high bandwidth solutions as shown in figure 3. An
example of such a co-packaged architecture with integrated
multi-photonics modules was recently demonstrated to meet the
computing and communication demands of high-performance
computing (HPC) systems and data centers [4]. In addition, end
users desire low-cost separable interconnect with an ability for
“late attach” and upgrade/repair in field to help them effectively
manage total cost of ownership (TCO).
Also, with the desire to bring SoC modules, such as memory,
closer to compute, there will be a reduced system assembly
yield with an increase in SoC modules if the SoC packages are
permanently soldered down to the board because of compound
yield loss, i.e., if yield of solder attaching one SoC module to
the board is Y (<1), then the compound yield of attaching ‘N’
such SoC modules will be reduced to YN. An example of
compound yield loss is shown with Y=98.5% in figure 5.
However, if each SoC module is attached to the board through
separable interconnects with yield Y, then the compound yield
of N SoC modules will still be Y, since the bad units can easily
be detached (as the interconnects are separable) and replaced by
another SoC. Soldered BGA components do not offer the
flexibility of late attach and require expensive rework process
to be able to replace and service, thus creating a total cost of
ownership challenge for the end-user. The inability to do late
attach has tax and inventory management implications along
the entire supply chain as the attach step often does not take
place in the same geography where the server or client product
is being deployed, putting additional TCO burden on the end
customers. Therefore, separable interconnects are desirable to
avoid system assembly yield loss, make the SoC packages
serviceable and reworkable to enable systems that are reliable,
available, serviceable (RAS).
Fig 3: Multichip module integration to increase SoC density.
The packages made by chip manufacturers currently use two
broad sets of SLI solutions to connect the packages to the
motherboards made by original design manufacturers: ball grid
array (BGA) which provides a soldered connection or socketed
land grid array (LGA) solutions, which provide separable
connections. BGA connects packages to the motherboards
through a high temperature reflow process where a soldered
connection is formed. However, with pin count growth, BGA
package sizes are growing and leading to higher warpage during
surface mount (SMT) process. This leads to process and
reliability challenges as shown in figure 4.
Fig 5: Compound yield loss example with BGA SoC assuming
Y=98.5% attach yield of each SoC. The compound yield of
soldering down (i.e., non-separable interconnects) 24 SoCs to
the board = (0.985)24=~70%. The compound yield attaching 24
SoCs with separable interconnects=98.5%.
Fig 4: Cross sectional illustration of BGA interconnects and the
challenges associated with creating BGA solder joints on a
large package with high warpage.
LGA sockets provide separable interconnects that are
commonly used for SLI applications for modern day compute
devices such as servers and desktops [5], [6]. LGA
interconnects are essentially metal contacts (typically copper
alloy) shaped as cantilever springs that require mechanical
force to connect the packages to the board as shown in figure 6.
A minimum normal mechanical force is needed to ensure stable
electrical continuity as measured by low level contact resistance
(LLCR) [7] between the CPU package pad and LGA contact
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content may change prior to final publication. Citation information: DOI 10.1109/TCPMT.2023.3344328
3
Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
interfaces. Mechanical loading mechanisms must be designed
and implemented to maintain the minimum mechanical force
required over the lifespan of the CPU package and LGA socket
[5], [8]. LLCR of LGA is also significantly higher than BGA
since the LLCR for LGA contacts is driven by the constriction
of current between the contact and package pad conductor
which is a function of the load. Higher LLCR limits the CPU
product performance scaling, increases socket power losses due
to joule heating and presents tradeoff challenges of using a
higher electrically conductive alloy versus reduced contact
mechanical performance [9]. The total mechanical load
required for the CPU package to maintain stable LLCR is
proportional to the pin count, as shown in figure 7. These ranges
of high loads result in complicated loading mechanism designs
[10], [11] to maintain the desired load with larger form factor
packages and drive up TCO, limit board densification to bring
SoC components closer due to spatial mechanical loading keep
out constraints and pose thermo-mechanical performance
limitations and reliability challenges [12], [13]. In summary,
LGA pose performance and pin count scalability challenges for
future demand.
Fig 6: Typical land grid array sockets that exist in the industry
require a minimum sustained mechanical load during device
operation to maintain stable electrical connections between the
package and the board.
Fig 7: Mechanical load historical trends and future projections
of server CPUs sockets predicting >5000N force for 15K pin
count LGA sockets.
The ideal state of an SLI solution should decouple pin count
scaling from mechanical loading complexity, not be a deterrent
for desired board densification to bring SoC components closer
to compute, have low electrical resistance while offering
separability and late attach flexibility for TCO benefits. This
ideal state could be achieved by conductive liquid metals such
as gallium and mercury which are liquid at room temperature.
We postulate that gallium alloy based liquid metal
interconnects, due to the non-toxic nature of gallium, has the
potential to be that interconnect. In the subsequent sections, we
introduce gallium liquid metal interconnects with key
mechanical and electrical characteristics and then show proof
of concept (POC) evaluations that can take advantages of them.
II. NOVEL LIQUID METAL INTERCONNECTS
A. Interconnect Architecture
Gallium based liquid metal (LM) alloys have attracted a wide
range of applications that are well documented in literature;
several applications ranging from soft and stretchable
electronics, e.g., wearable devices, implantable electronics,
microfluidic sensors, antennae, and conformal electrodes have
been widely explored [14]. Gallium alloys as thermal interface
materials for semiconductor devices have also gained traction
in the last few years [15], [16] because of the high thermal
conductivity of gallium alloys. While there is significant
published research and progress on the above-mentioned
applications of gallium based liquid metal alloys, there is dearth
of reported or demonstrated use cases of such alloys for
electrical interconnect applications. Gallium based alloys tend
to stay liquidous at room temperature (ex. melting point of
eGaIn is 15.5° C) with high electrical conductivity (3.4x106
S/m), low viscosity (2 mPa s) [17] and low toxicity and are,
therefore, attractive for interconnect applications., The
liquidous nature along with the high surface tension of the alloy,
however, pose manufacturing and assembly challenges. Our
previous work [18] evaluated different manufacturing
techniques to dispense liquid metal with a lab scale
demonstration of low LLCR that can be used for interconnect
applications. There is insufficient literature information about
the field reliability degradation mechanisms with liquid metal
interconnects. It is known to be highly corrosive to most metals
and has unique failure mechanisms. Our recent work [19]
describe the possible failure mechanisms expected when used
in semiconductor applications. The reference also includes
common reliability stress tests to evaluate the field performance
of the interconnect. Even though the data is the right step in
understanding the field risk, it is still insufficient to establish
new accelerated life prediction models and associated test
requirements.
We envision the architecture involving liquid metal to carry
the following ingredients as shown in figure 8:
1. Gallium based LM alloy. Composition of the alloy can
be altered to reduce the melting temperature to the
desired target.
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4
Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
2.
3.
A patch/carrier/well filled with LM
Conductive array of pins attached to a board or another
device
4. Containment cap which can be optional. Proof of
concept implementations described in the following
sections do not use a containment solution as LM has a
very high surface tension and does not flow like a
traditional liquid. However, some applications may
demand a containment solution like a containment cap
but that is not in the scope of this paper.
While there could be several potential manufacturing and
assembly methods to realize the described LM interconnect
architecture, an example of a typical assembly flow is shown in
figure 9.
(TV) [18] because the resistance contribution is mainly due to
the bulk resistance of the pin. Extended studies were carried out
to demonstrate low resistance interconnects with reduced load
with Intel ® Xeon ® server product-like TV having ~4500 pins.
Package TVs were built with LM attached to packages as
shown in figure 10a with assembly processes described
previously [18] . Pin grid array sockets were made with stamped
metal copper alloy pins and surface mounted on enabling test
boards (ETBs) as shown in figure 10b. Since pins mate with the
liquid metal on package, no external load is needed to establish
stable electrical connection between the board and package. To
demonstrate this, packages were assembled on sockets with no
external load as shown figure 10c. Note that the socket and pins
were designed such that the total package-socket mated
assembly height measured from package pad to ETB pad was
approximately 2 mm as shown in figure 10d.
(a)
(b)
Fig 8: Liquid metal interconnect architecture: (a) before pkg
installation to pin grid array, (b) after installation assembly to
pin grid array. Note: illustration not to scale.
(a)
(b)
(c)
(d)
Fig 10: (a) Package TV with LM, (b) pin grid array socket that
is reflow surface mounted on ETB, (c) package TV assembled
to socket without external load, (d) cross sectional illustration
showing that the package-socket mated assembly stack height
is ~2 mm.
In addition, ~4500 pin LGA sockets with cantilever styled
stamped metal pins, similar to figure 6 in section I, were also
surface mounted on ETBs. ETB layouts and design were
identical to those used for the LM package-socket stack. LGA
package TVs were inserted in the socket with a load of ~1100
N using load mechanisms as shown in figures 11a and b.
Fig 9: Overview of an example assembly flow to realize liquid
metal interconnects.
B. Low load, low resistance with LM interconnects
Liquid metal interconnects can achieve significantly lower
LLCR as reported earlier using 36-pin grid array test vehicles
(a)
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Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
(b)
Fig 11: (a) LGA socket, package TV, and ETB with loading
mechanism in unassembled configuration (b) fully assembled
configuration with mechanical load.
ETBs and package TVs were designed to route daisy chain
connections from the package to the socket and enable 4-wire
LLCR measurement with about 50% of the pins electrically
connected through ~400 daisy chains. Each chain typically
consisted of 6 pins electrically connected alternating between
the board and the package as shown in figure 12.
Fig 12: Package TV with daisy chains (highlighted pads) and a
cross sectional illustration of a six-pin daisy chain layout.
Three boards were assembled for each of the LM and LGA
stacks shown in figures 10 and 11. Resistance from the 1200
measurements is shown in figure 13. As previously
demonstrated with the 36-pin TV [18], resistance with the LM
stack was found to be significantly lower than the LGA socket.
The mean LLCR per pin for LM was about 6mΩ and standard
deviation of 0.4mΩ which are about 3 times lower to LGA
LLCR mean and standard deviation. For reference, a resistance
for BGA connection is also shown in the figure 13 which is a
theoretical assumption of solder ball that is assumed to be
collapsed nominally to ~300 µm.
Fig 13: Room temperature LLCR measurements comparison
of LGA vs LM. Theoretical BGA resistance added for
reference.
Figure 14 shows the contribution of resistance for LGA and
LM interconnects. For an LGA interconnect, the measured
resistance includes the thin long section of the contact. LGA
designs are cantilever mechanical spring which have varying
force based on the warpage of the package. As a result of the
varying force, the contact area between the LGA pad and
contact has a spatial variation which drives a higher resistance
scatter. For an LM interconnect, which is insensitive to load,
the measured resistance is primarily dominated by the bulk
resistance of the pin. In the current implementation, a Cu alloy
pin was used with approximately 5 mΩ bulk resistance, thereby,
driving most of the LM interconnect resistance. The
measurement data presented in figure 13 is measured at room
temperature. However, for real product applications, the
product could be operating at higher temperatures over time in
field resulting in LLCR degradation. Typically, for LGA
contacts, the end of life (EOL) LLCR is 25-35mΩ [12], [20][22]. For LM interconnects, we predict EOL LLCR to be about
12mΩ to account for LLCR increase due to reduced
conductivity at higher operating temperature as well as
resistance degradation with long term reliability based on our
previous work [19]. which shows that temperature change
(room temperature to 110°C) results in resistance increase of 23mΩ. Additionally, resistance change with stress testing was
limited to less than 3mΩ. Therefore, we conservatively assume
EOL resistance to be approximately 6mΩ increase from
beginning of life (BOL) estimates. EOL LLCR predictions for
LM interconnects need to be validated with experimental data
and reliability models which will be the focus of future
research.
In summary, low load, low resistance and separable LM
interconnects were demonstrated with product like form factor
test vehicles.
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6
Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
Fig. 14: Comparison of resistance paths between LGA, LM
and BGA interconnects.
C. High speed signaling characterization of LM interconnect
In the previous section, we demonstrated the low load and
low electrical resistance characteristics of an LM interconnect.
The high-speed signal integrity characterization of LM
interconnects for both differential-ended (DE) signaling and
single-ended (SE) signaling is equally important. To prove the
ability of LM interconnect to support high-speed signaling up
to 64GT/s PAM4 DE and 12.8GT/s SE, insertion loss (IL) and
return loss (RL) targets were set as shown in Table 1 with a
reference impedance of 85 Ω and 50 Ω, respectively, for DE
and SE signals. These targets were set based on the Nyquist
frequency requirement of data rates and budgeting for a
complete channel link consisting of IC package, socket and
motherboard routing.
Table 1: High speed signaling targets for LM interconnects.
Targets
Frequency range
DE IL
>= -1 dB
0-20 GHz
DE RL
SE IL
<= -10 dB
>= -1 dB
0-20 GHz
0-12.8 GHz
SE RL
<= -10 dB
0-12.8 GHz
The socket contact pin geometry was optimized within the 2
mm height physical boundary condition shown in figure 10 to
meet the targets established in Table 1. DE and SE modeling
analyses using ANSYS HFSS were carried out on the packageLM-socket-board stack that included 2 package layers,
dielectric patch containing liquid metal well, socket contact pin
with plastic housing, solder ball, and 2 board layers. Figure 15
and 16 show IL and RL characteristics for the package-LMsocket-board stack for DE and SE, respectively. As seen from
figures 15, and 16 modeling results, LM interconnects can
operate within the desired IL and RL targets.
(a)
(b)
Fig. 15. Differential ended LM socket design performance
based on models for (a) insertion loss, and (b) return loss.
(a)
(b)
Fig. 16. Single ended LM socket design performance based on
models for (a) insertion loss, and (b) return loss.
To further demonstrate LM interconnect viability and
validate high-speed signaling models, a proof of concept 122
pin TV with LM attached to packages, stamped metal pin grid
array sockets and ETBs were designed and fabricated. In this
work experimental metrology and methodology, including deembedding of package and board routing that was described
previously [23] were adopted and followed to establish model
to experimental correlation. Pin grid array sockets were
reflowed surface mounted and packages TVs were assembled
on sockets with no external load as shown figure 17.
(a)
(b)
Fig. 17 (a) 122 pin grid array socket surface mounted on ETB,
(b) package TV assembled to socket without external load for
HSIO experimental measurements.
High speed modeling was done for the TV setup shown in
figure 17 which includes additional micro-via transitions in the
package and board. Test measurements were taken on three
assembled units using N5227A PNA after probing at the test
locations using Gigatest Probe station. Modeled and
experimentally measured IL and RL for both DE and SE
signaling are shown in figure 18, demonstrating good
experimental to model correlation as well as part to part
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Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
variation control.
(a)
(b)
Fig.19: Typical servers with LGA sockets require loading
mechanisms and thick back plates requiring mechanical keep
out volume.
(c)
(d)
Fig. 18. Good HSIO TV experimental to modeling correlation
achieved for (a) Differential ended IL, (b) Differential ended
RL, (c) Single ended IL and (d) Single ended RL.
In conclusion, viability of low load LM interconnects with
low insertion and return loss meeting DE 64GT/s-PAM4 and
SE-12.8GT/s targets were demonstrated through models and
empirical data. Detailed experimental characterization
including near end and far end cross talk as well as exploration
of LM interconnect scaling for higher data rates is not in the
scope of this paper and will be a focus topic of future research.
With validated models, we believe we have line of sight to
extend data rate scaling with new architectures and features.
III. LM INTERCONNECT FOR IC SOCKET APPLICATIONS AND
PROOF OF CONCEPT DEMONSTRATION
Fig 20: LM based IC socket architecture.
POC systems were built using Intel® Xeon® processors with
LM attached to the processors and 4677 pin count sockets to
establish viability of LM interconnects for IC socket
application. Figure 21 shows representative LM integrated
processors and pin grid array sockets like those shown in figure
10 were made and surface mounted on motherboards.
As described in previous sections, we demonstrated that LM
interconnects are capable of low LLCR, high speed signaling,
requiring low load and yet can be separable. These capabilities
allow several potential applications and architectures, some of
which are described in this section. A straightforward use case
application for LM interconnects is a replacement of current
LGA technology for IC sockets. Figure 19 shows a typical
server configuration with LGA sockets which requires loading
mechanisms and backplates to provide stiffness for countering
board deflection. The loading mechanisms and the backplates
consume footprint on the board as well as the overall stack
height. The increase in pin-count demand drive loading
mechanisms requiring larger footprint, thicker backplates, and
complexity and costs which present scalability and device
density challenges to fit within typical server systems. Figure
20 illustrates the IC socket architecture based on liquid metal
interconnects. Note that a retention mechanism is still needed
to retain processor heatsinks as shown in figure 20.
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8
Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
Fig 22: Intel® Xeon® processors systems with LM attached to
the processors used for power-on demonstration. Note:
Processor hidden under heatsinks.
(a)
The reduced resistance path with lower LM socket resistance
is expected to improve power delivery for IC packages to
realize performance uplifts as well as reduced power losses
compared to LGA sockets. Based on the power delivery
analyses for the 4677 pin Xeon ® processor systems with an
assumed max EOL LM socket resistance of 12 mΩ/pin versus
30 mΩ/pin for typical LGA, as mentioned in section II above,
a 6% uplift of maximum input current (ICCmax) can be realized
as shown in figure 23. Also, reduced LM socket resistance
enables a 60% socket power-loss because of lower joule heating
(I2R) or a 60% reduction in the number of power pins. Increased
ICCmax can enable IC performance improvement, provided
platform heatsinks are capable to provide the necessary cooling.
Lower socket power losses enable lower total power
consumption for the same thermally designed current (TDC)
processor which lowers the energy cost, e.g., for server data
centers. Experimental validation of the simulated power
delivery improvements remains a scope of future publications.
(b)
Fig 21: POC Intel ® Xeon ® processors with LM filled patch
attached: (a) Bottom view of the package, (b) Side view X-ray
image.
Xeon® server systems based on two-socket configurations,
shown in figure 22, were successfully powered on with
processors installed in sockets with minimal load along with
heatsink retention assembly. The successful power-on of
Xeon® server systems along with power on for Intel® desktop
processors previously [18], [19] demonstrate viability of LM
interconnects for IC socket applications.
Fig 23: ICCmax increase and socket power loss reduction with
LM interconnects. Values in this chart are normalized with
respect to LGA.
Since LM interconnects require low insertion force to
establish high fidelity electrical connection, LM based sockets
would require significantly lower load compared to LGA
sockets and the total load will be enveloped by the processor
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Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
heatsinks as shown in figure 24. Heatsink loads in figure 24
were based on recommended 138 kPa guidance [24] which is
necessary to ensure optimal thermal performance of the thermal
interface material (TIM) between the heatsink and the IC
integrated heat spreader (IHS) and projected IHS area for future
high pin count packages. Therefore, LM based sockets
decouple future pin-count scaling from load allowing pin count
scaling for future 10K pins and higher pin counts.
.
Fig 25: Motherboard topside mechanical keep out area,
backplate thickness and retention cost reduction with POC
Xeon ® LM. All metrics are normalized against LGA socket.
Fig. 24: LM sockets enable significantly reduced load
(enveloped by processor heatsink loads) and allows decoupling
of pin count scaling from mechanical loads versus LGA.
Retention designs were developed for the POC Xeon form
factors described above with an estimated motherboard keep
out zone (KOZ) reduction of 20%, backplate thickness
reduction of 32%, and 50% cost reduction for an LGA 4677
system as shown in figure 25. The LGA footprint varies by the
product and platform keep outs and usually listed in product
design guides with published values of top side keep out areas
and backplate thickness [24]. Reduced platform mechanical
keep outs enable components such as motherboard voltage
regulators, capacitors, and DIMM connectors to be placed
closer to the IC. Alternatively, it is possible to reduce the ICto-IC spacing to improve platform power delivery and highspeed signaling performance.
The building block demonstration of reduced mechanical
load keep outs along with electrical characteristics for separable
LM interconnects, enables novel architectures and applications
beyond conventional IC sockets to enable increased SoC
density. Examples of novel architectures include integration of
voltage regulator modules (VRM), power delivery components
for both conventional vertical power delivery architectures [25]
with separable LM interconnects or integration of companion
packages such as memory modules or other IC devices such as
photonics IC that would otherwise not be possible or practical
with LGA or BGA interconnects.
IV. CONCLUSIONS AND FUTURE CHALLENGES
In conclusion, the exponential increase in SLI pin count is
driving scalability challenges for incumbent LGA and BGA
interconnects that requires innovation to address scaling. Our
previous work demonstrated LM interconnect feasibility with a
small size 36 pin coupon level evaluations. In this paper, we
expanded on that work through larger Intel® Xeon® product
form factor like experimental test vehicles with the following
demonstrations:
• Ga based LM interconnects are separable unlike BGA
with about 3 times lower electrical resistance compared
to LGA.
• LM interconnects do not require a separate load and is
enveloped by the TIM load requirements for IC package
heatsinks with preliminary data showing line of sight to
scale LM to pin counts >10K pins.
• LM interconnects with low insertion and return loss
meeting DE 64GT/s-PAM4 and SE-12.8GT/s targets
were demonstrated through models and empirical data.
• Xeon® systems were powered on with LM interconnects
showing viability of LM interconnects for IC socket
applications with analyses predicting 60% lower socket
power loss or power pin count reduction due to reduction
in socket electrical resistance compared to LGA.
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© 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
This article has been accepted for publication in IEEE Transactions on Components, Packaging and Manufacturing Technology. This is the author's version which has not been fully edited
content may change prior to final publication. Citation information: DOI 10.1109/TCPMT.2023.3344328
10
Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications
•
Mechanical retention designs with 20% top side
motherboard keep out area reduction, backplate
thickness reduction of 32%, and 50% cost reduction
compared to LGA 4677 sockets.
These technology demonstrations lay a foundation for future
architectures enabling higher SoC density and performance.
While we have demonstrated viability of LM interconnects
through POC vehicles, several challenges exist for high volume
manufacturing and scaling. First of kind tools and
manufacturing systems need to be implemented to transfer lab
scale processes of attaching LM to IC packages to high volume
production. A stable and diverse supply chain of Ga needs to be
established to sustain demand for LM interconnect applications.
Lastly, we expect LM based interconnects to present unique
failure mechanisms compared to existing LGA and BGA
interconnects, thus requiring investigations to comprehend
intrinsic failure mechanisms, develop acceleration models and
qualification methods.
ACKNOWLEDGEMENT
The authors would like to sincerely thank Donald Tran, Jeff
Smalley, Andres Ramirez, Xiao Liu, Jiaqi Wu, Zhichao Zhang,
Leigh Wojewoda, Sugadh Bakare, Weston Roth, Tanner
Kantargis, Wilfredo Acevedo, Rishik Bazaz, and Greg Stone for
design, analyses, experimental data collection support and
valuable architectural discussions.
REFERENCES
[1]
[2]
Heterogenous Integration Roadmap, https://eps.ieee.org/hir, 2021 Edition
P. Wang et al., “CPU Socket Interposer Component Level and
Manufacturability Study and iNEMI 2023 Board Assembly-CPU Socket
Technology Roadmap”, 24th International Conference on Electronic
Packaging technology
[3] IPC-2222B - Sectional Design Standard for Rigid Organic Printed Boards,
2020
[4] R. Mahajan et al., "Co-Packaged Photonics For High Performance
Computing: Status, Challenges And Opportunities," Journal of Lightwave
Technology, vol. 40, no. 2, pp. 379-392, 2022, doi:
10.1109/JLT.2021.3104725.
[5] J. S. Corbin et al. , "Land grid array sockets for server applications," in
IBM Journal of Research and Development, vol. 46, no. 6, pp. 763-778,
Nov. 2002, doi: 10.1147/rd.466.0763.
[6] C. Baldwin et al., “Pentium 4 processor high-volume land-grid-array
technology: Challenges and future trends,” Intel Technol. Journal., vol. 4,
no. 9, pp. 325–336, 2005.
[7] P. Slade, "50 Years of the Holm Conference on Electrical Contacts 1967
- 2016", in Proc. 62nd IEEE Holm Conf. Elect. Contacts, Oct. 2016
[8] Pandey, Vinayak, et al., "Mechanical design and analysis of land grid
array (LGA) sockets.", International Electronic Packaging Technical
Conference and Exhibition. vol. 42002. pp. 1005-1011, July 2005, doi:
10.1115/IPACK2005-73360
[9] J. Chang, et al. "The Challenges of LGA Server Socket Trends.", in
SMTA Pan Pac Symposium, January 2013
[10] P Geng, “Structural Design of LGA Loading Mechanisms for Intel CPU
Stack Retention” ASME Journal of Electronic Packaging. 141, no. 1,
2019, doi: 10.1115/1.4042800.
[11] Torok, John, et al. "Large form factor hybrid LGA interconnects; Recent
applications and technical learning." International Symposium on
Microelectronics. Vol. 2014. No. 1. International Microelectronics
Assembly and Packaging Society, 2014.
[12] R. Martens et al. , "Reliability Study of Low Normal Force LGA
Sockets," in Proc. 58th IEEE Holm Conf. Elect. Contacts, Sep. 2012, doi:
10.1109/HOLM.2012.6336599.
[13] K. Meyyappan et al, "Predicting vibration-induced fretting in land grid
array sockets in simulated field scenarios," in Proc. 62nd IEEE Holm
Conf. Elect. Contacts, Oct. 2016
[14] Lin, Y., Genzer, J. and Dickey, M.D., “Attributes, fabrication, and
applications of gallium‐based liquid metal particles”. Advanced
Science, vol 7, no. 12, 2020, doi: 10.1002/advs.202000192
[15] Gao, Yunxia, and Jing Liu. "Gallium-based thermal interface material
with high compliance and wettability." Applied Physics A, vol. 107, pp
701-708, 2012, doi: 10.1007/s00339-012-6887-5
[16] Hansson, Josef, et al. "Novel nanostructured thermal interface materials:
a review." International Materials Reviews, vol 63, no. 1, pp 22-45, 2018,
doi: 10.1080/09506608.2017.1301014
[17] Liu, Shanliangzi, et al. "Oxide rupture-induced conductivity in liquid
metal nanoparticles by laser and thermal sintering." Nanoscale, vol11,
no. 38, pp. 17615-17629, 2019, doi: 10.1039/C9NR03903A
[18] K. Meyyappan et al., "Liquid Metal Based Low Resistance Interconnect
Technology," in IEEE Transactions on Components, Packaging and
Manufacturing Technology, vol. 13, no. 4, pp. 465-471, 2023, doi:
10.1109/TCPMT.2023.3274743.
[19] K. Meyyappan et al., “Field Risk Evaluation of Liquid Metal
Interconnects in Microelectronics Applications”. (Accepted article)
Advanced
Engineering
Materials,
September
2023,
doi:
10.1002/adem.202300880
[20] https://www.intel.com/Assets/PDF/designguide/302666.pdf
(accessed
Sep. 19, 2023).
[21] https://www.intel.com/content/dam/www/public/us/en/documents/design
-guides/xeon-e7-v2-thermal-guide.pdf (accessed Sep. 19, 2023).
[22] K. Meyyappan et al., “Corrosion Studies on Gold-Plated Electrical
Contacts”, IEEE transactions on Device and Materials Reliability, vol 14,
no. 3, pp. 869-877, 2014, doi: 10.1109/TDMR.2014.2333758.
[23] S. Mondal, et al. “An Improved Methodology for High Frequency Socket
Performance Characterization”, in 31st IEEE Conference on Electrical
Performance of Electronic Packaging and Systems (EPEPS) (pp. 1-3).
IEEE, 2022, doi: 10.1109/EPEPS53828.2022.9947155.
[24] https://www.intel.com/content/dam/www/public/us/en/documents/guides
/xeon-scalable-thermal-guide.pdf (accessed Sep. 19, 2023).
[25] C. Hardy et al., "11.1 A Scalable Heterogeneous Integrated Two-Stage
Vertical
Power-Delivery
Architecture
for
High-Performance
Computing," IEEE International Solid- State Circuits Conference
(ISSCC), pp. 182-184, 2023, doi: 10.1109/ISSCC42615.2023.10067315.
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