Basic Memory Units
The basic memory units which are used by sequential circuits are
• Latch
• Flip Flop
Both Latch and Flip Flops are the fundamental units to store one bit information. They
consists of two inputs and two outputs.
One Input is Set(S) which is used to set the output to 1.
Second Input is Reset(R) to reset the output to 0.
are the two outputs which are complement to each other.
The only difference between Latch and Flip Flop is
Flip Flop is controlled by clock where as latch is not controlled by clock.
13-Feb-24
Dr. Mahaboob Basha Shaik
SR Latch using NOR gates
SR (set-reset) Latch based on two nor gates
Truth Table
13-Feb-24
Dr. Mahaboob Basha Shaik
SR Latch using NAND gates
SR (set-reset) Latch based on two NAND gates
Truth Table
13-Feb-24
Dr. Mahaboob Basha Shaik
Clock
Clock pulse is used by the digital circuits to synchronize all the actions.
When clock is given to latch it becomes flip flop
Clock
Generally the rising edge or falling edge of the clocks are used for actions
13-Feb-24
Dr. Mahaboob Basha Shaik
Clocked SR Flip Flop
Clocked SR changes its state only when clock is rising/falling
Using NOR gates
Using NAND gates
Negative edge triggered
Positive edge triggered
Truth Table
13-Feb-24
Dr. Mahaboob Basha Shaik
D Flip Flop
To overcome the unstable state of SR FF, D FF is developed. The D input is given
Directly to S and through NOT gate to R input. This makes R and S complement to
each other always. So the Q will be always same as D.
Truth Table
13-Feb-24
Dr. Mahaboob Basha Shaik
JK FF
JK FF with extra feed back overcomes the unstable state of SR FF. It is the most
popular flip flop and very widely used. It is almost same as SR FF. But when both
Inputs are high it complements the output.
Truth Table
13-Feb-24
Dr. Mahaboob Basha Shaik
Registers
A collection of flip-flops taken as an entity.
Function:
Holds(Stores) information within a digital system so that it is available to the
logic elements during the computing process.
• Used to perform shifting and other operations on data
• Important part of CPU
 Two basic ways in which information can be written/read
Parallel: All input/output operations are handled simultaneously. Require as
many lines as symbols being transferred.
Serial: Involves the bit by bit transfer of information in a time sequence.
 Four possible ways registers can transfer information:
1. SISO (Serial In and Serial Out)
2. SIPO (Serial In and Parallel Out)
3. PISO (Parallel In and Serial Out)
4. PIPO (Parallel In and Parallel Out)
13-Feb-24
Dr. Mahaboob Basha Shaik
SISO Register
Input(SI) is given to the left most FF. Requires n clock pulses
Output (SO) is taken from the right most FF. Requires n clock pulses
13-Feb-24
Dr. Mahaboob Basha Shaik
SIPO Register
Input(SI) is given to the left most FF. Requires n clock pulses
Output (PO) is taken from all the FFs at a time. Requires only one clock pulse
13-Feb-24
Dr. Mahaboob Basha Shaik
PISO Register
Input(PI) is given to the all the FFs at a time. Requires only one clock pulse.
Output (SO) is taken from right most FF. Requires n clock pulses.
13-Feb-24
Dr. Mahaboob Basha Shaik
PIPO Register
Input(PI) is given to the all the FFs at a time. Requires only one clock pulse.
Output (PO) is taken from all the FFs at a time. Requires only one clock pulse
13-Feb-24
Dr. Mahaboob Basha Shaik
Binary Ripple Counters
13-Feb-24
Dr. Mahaboob Basha Shaik
Asynchronous Counter (4 bit)
Clock is different for each Flip Flop
Main clock is given to FF0
is given as clock to next FF
All the Inputs are tied together and given to 1
13-Feb-24
Dr. Mahaboob Basha Shaik
Synchronous Counter (4 bit)
Clock is same for all Flip Flops
Sequence is controlled through input
T0 is connected to 1 so that Q0 changes its state for each clock pulse
Q0 is connected to T1 so that whenever Q0 is 1, Q1 changes its state
Q0 AND Q1 is connected to T2 so that whenever both Q0 and Q1 are 1, Q2
changes its state.
Q0 AND Q1 AND Q2 is connected to T3 so that whenever all the three Q0, Q1 and
Q2 are 1, Q3 changes its state.
13-Feb-24
Dr. Mahaboob Basha Shaik
Modulo N Counter
Find n such that N<=2n. Where n is the number of Flip Flops
Draw the 2n counter. But counting should be from 0 to N-1 only.
To reset the count after N-1 connect the outputs with value 1 for N to an AND
gate and output of AND gate should be connected to CLR(clear) of the Counter
For Ex
Modulo 10 counter
N=10
To make 10<=2n n is 4
So number of Flip Flops 4
Normal count with 4 Flip Flops is 0 to 15
To reset Counter after 9. In the value of N
(1010) Q3 and Q1 are connected to AND gate
Output of AND gate is given to CLR
13-Feb-24
Dr. Mahaboob Basha Shaik