Pulse Swallow Divider
Mohamed Tohamey
AGENDA:
• TSPC pre scalers with extended operating frequency.
• P Counter & related gates.
• S Counter & related gates.
• Whole divider schematic.
Pre scaler:
Conventional
Implemented
High Frequency and low power:
Implementation:
DFF
Test bench:
Division accuracy
Waveforms:
Min DC vs Amplitude
DC VAlue
Min amplitude
0
800m
100m
700m
200m
600m
300m
500m
400m
400m
500m
300m
600m
200m
700m
100m
P Counter:
Note:
The order of connection is
important.
XNOR gate
AND Gate
Test Bench
S counter:
SR Latch
NOR:
Divider Schematic:
N=2
P=34
S = 2 to 32
Division by 100:
Division by 70:
Division by 75:
References:
• https://pdfs.semanticscholar.org/627d/0a3b1d2664bf4a327fa69cd93
5799e852d0a.pdf
• (2020) Design of CMOS PLLs_ from circuit level to architecture
level_Razavi (1)
• Behzad Razavi - RF Microelectronics (2011, Prentice Hall)
• Different implementation:
https://www.emo.org.tr/ekler/51054713b963049_ek.pdf