Chapter 6
Digital Design and Computer Architecture, RISC-V Edition
David M. Harris and Sarah L. Harris
Chapter 7 <1>
Digital Design and Computer Architecture: RISC-V Edition
Chapter 6 <1>
Harris & Harris © 2020 Elsevier
Chapter 7 :: Microarchitecture
•
•
•
•
•
•
Introduction
Performance Analysis
Single-Cycle Processor
Multicycle Processor
Pipelined Processor
Advanced Microarchitecture
Chapter 7 <2>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Introduction
• Microarchitecture: how to
implement an architecture
in hardware
• Processor:
– Datapath: functional blocks
– Control: control signals
Chapter 7 <3>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Microarchitecture
• Multiple implementations for a single
architecture:
– Single-cycle: Each instruction executes in a
single cycle
– Multicycle: Each instruction is broken up into
series of shorter steps
– Pipelined: Each instruction broken up into series
of steps & multiple instructions execute at once
Chapter 7 <4>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Processor Performance
• Program execution time
Execution Time = (#instructions)(cycles/instruction)(seconds/cycle)
• Definitions:
– CPI: Cycles/instruction
– clock period: seconds/cycle
– IPC: instructions/cycle = IPC
• Challenge is to satisfy constraints of:
– Cost
– Power
– Performance
Chapter 7 <5>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
RISC-V Processor
• Consider subset of RISC-V instructions:
– R-type instructions:
• add, sub, and, or, slt
– I-type instruction:
• lw
– S-type instruction:
• sw
– B-type instructions:
• beq
Chapter 7 <6>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Architectural State Elements
Determines everything about a processor:
– Architectural state:
• 32 registers
• PC
• Memory
Chapter 7 <7>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
RISC-V Architectural State Elements
PCNext
32
CLK
CLK
CLK
PC
32
32
A
RD
Instruction
Memory
5
WE3
A1
RD1
WE
32
32
5
5
32
32
Chapter 7 <8>
A2
RD2
32
32
A3
Register
File
WD3
32
A
RD
Data
Memory
WD
32
R15
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle RISC-V Processor
• Datapath
• Control
Chapter 7 <9>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle RISC-V Processor
• Datapath
• Control
Chapter 7 <10>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
RISC-V Processor
• R-type instructions:
– add, sub, and, or, slt
R-Type
31:25
24:20
funct7
rs2
7 bits
5 bits
19:15
14:12
rs1 funct3
5 bits
3 bits
11:7
6:0
rd
op
5 bits
7 bits
11:7
6:0
rd
op
5 bits
7 bits
11:7
6:0
imm4:0
op
5 bits
7 bits
11:7
6:0
I-Type
• I-type instruction:
– lw
19:15
31:20
imm11:0
rs1 funct3
5 bits
12 bits
14:12
3 bits
S-Type
• S-type instruction:
– sw
31:25
24:20
19:15
14:12
imm11:5
rs2
rs1 funct3
7 bits
5 bits
5 bits
31:25
24:20
19:15
3 bits
B-Type
• B-type instructions:
– beq
Chapter 7 <11>
imm12,10:5 rs2
7 bits
5 bits
14:12
rs1 funct3 imm4:1,11
5 bits
3 bits
5 bits
op
7 bits
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle RISC-V Datapath
CLK
CLK
PCNext
PC
A
RD
Instruction
Memory
Instr
CLK
WE3
A1
WE
RD1
A
A2
RD2
A3
WD3
Register
File
Chapter 7 <12>
RD
Data
Memory
WD
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle RISC-V Processor
• Datapath: start with lw instruction
• Example:
lw t2, -8(s3)
lw rd, imm(rs1)
I-Type
31:20
imm11:0
12 bits
19:15
14:12
rs1 funct3
5 bits
3 bits
Chapter 7 <13>
11:7
6:0
rd
op
5 bits
7 bits
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: lw fetch
STEP 1: Fetch instruction
CLK
CLK
PCNext
PC
A
RD
Instruction
Memory
Instr
A1
CLK
WE3
WE
RD1
A
A2
A3
WD3
RD2
Register
File
Chapter 7 <14>
RD
Data
Memory
WD
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: lw Reg Read
STEP 2: Read source operand (rs1) from RF
CLK
CLK
PCNext
PC
A
RD
Instr
19:15
A1
CLK
WE3
WE
RD1
A
Instruction
Memory
A2
A3
WD3
RD
Data
Memory
WD
RD2
Register
File
I-Type
19:15
31:20
imm11:0
12 bits
14:12
rs1 funct3
5 bits
3 bits
11:7
6:0
rd
op
5 bits
7 bits
lw rd, imm(rs1)
Chapter 7 <15>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: lw Immediate
STEP 3: Extend the immediate
CLK
CLK
PCNext
PC
A
RD
Instr
19:15
A1
CLK
WE3
WE
RD1
A
Instruction
Memory
A2
A3
WD3
31:20
RD
Data
Memory
WD
RD2
Register
File
ImmExt
Extend
Chapter 7 <16>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: lw Address
STEP 4: Compute the memory address
ALUControl2:0
CLK
PC
A
RD
Instr
19:15
Instruction
Memory
A1
WE3
A2
A3
WD3
31:20
MemWrite
0
CLK
WE
SrcA
RD1
RD2
SrcB
Register
File
ALU
CLK
PCNext
010
ALUResult
A
RD
Data
Memory
WD
ImmExt
Extend
Chapter 7 <17>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: LDR Mem Read
STEP 5: Read data from memory and write it
back to register file
RegWrite
1
CLK
PCNext
PC
A
RD
Instruction
Memory
Instr
19:15
WE3
A1
A2
11:7
SrcA
RD1
RD2
A3
WD3
31:20
010
SrcB
ALUResult
WriteData
Register
File
MemWrite
0
CLK
WE
Zero
ALU
CLK
ALUControl2:0
A
RD
Data
Memory
WD
ReadData
ImmExt
Extend
Chapter 7 <18>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: PC Increment
STEP 6: Determine address of next instruction
RegWrite
1
CLK
PC
A
RD
Instr
Instruction
Memory
19:15
A1
31:20
PCPlus4
WE3
A2
11:7
A3
WD3
+
PCNext
010
SrcA
RD1
RD2
SrcB
ALUResult
WriteData
Register
File
MemWrite
0
CLK
WE
Zero
ALU
CLK
ALUControl2:0
A
RD
Data
Memory
WD
ReadData
ImmExt
Extend
4
Chapter 7 <19>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: sw
Expand datapath to handle sw:
• Write data in rs2 to memory
• Example: sw t2, 0xc(s3)
sw rs2, imm(rs1)
S-Type
31:25
24:20
19:15
imm11:5
rs2
rs1 funct3
7 bits
5 bits
5 bits
Chapter 7 <20>
14:12
3 bits
11:7
6:0
imm4:0
op
5 bits
7 bits
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: Data-processing
• Immediate: now in {instr[31:25], instr[11:7]}
• Add control signals: ImmSrc, MemWrite
CLK
PC
A
RD
Instr
Instruction
Memory
19:15
WE3
A1
24:20
A2
11:7
A3
31:7
PCPlus4
ALUControl2:0
MemWrite
1
CLK
010
SrcA
RD1
RD2
WD3
+
PCNext
ImmSrc
1
SrcB
WE
Zero
ALU
RegWrite
0
CLK
ALUResult
WriteData
Register
File
A
RD
Data
Memory
WD
ReadData
ImmExt
Extend
4
S-Type
31:25
24:20
19:15
14:12
imm11:5
rs2
rs1 funct3
7 bits
5 bits
5 bits
3 bits
11:7
6:0
imm4:0
op
5 bits
7 bits
sw rs2, imm(rs1)
Chapter 7 <21>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: Immediate
ImmSrc ImmExt
{{20{instr[31]}}, instr[31:20]}
0
{{20{instr[31]}}, instr[31:25], instr[11:7]}
1
Instruction Type
I-Type
S-Type
I-Type
19:15
31:20
imm11:0
14:12
rs1 funct3
5 bits
12 bits
3 bits
11:7
6:0
rd
op
5 bits
7 bits
11:7
6:0
imm4:0
op
5 bits
7 bits
S-Type
31:25
24:20
19:15
imm11:5
rs2
rs1 funct3
7 bits
5 bits
5 bits
Chapter 7 <22>
14:12
3 bits
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: R-Type
• Instructions: add, sub, and, or, slt,
• Example:
add s1, s2, s3
op
rd, rs1, rs2
R-Type
31:25
24:20
funct7
rs2
7 bits
5 bits
19:15
14:12
rs1 funct3
5 bits
Chapter 7 <23>
3 bits
11:7
6:0
rd
op
5 bits
7 bits
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: R-Type
Read from rs1 and rs2 (instead of imm)
Write ALUResult to rd
RegWrite
ImmSrc
ALUSrc
PC
A
RD
19:15
Instr
Instruction
Memory
A1
24:20
A2
11:7
A3
WD3
31:7
PCPlus4
X
WE3
ALUControl2:0
0
SrcA
RD1
RD2
ResultSrc
0
WE
Zero
0 SrcB
1
Register
File
MemWrite
0
CLK
varies
ALU
PCNext
1
CLK
CLK
+
•
•
ALUResult
WriteData
A
RD
Data
Memory
WD
ReadData
1
0
ImmExt
Extend
Result
4
R-Type
31:25
24:20
funct7
rs2
7 bits
5 bits
19:15
14:12
rs1 funct3
5 bits
3 bits
11:7
6:0
rd
op
5 bits
7 bits
add rd, rs1, rs2
Chapter 7 <24>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: beq
Calculate branch target address: PCTarget = PC + imm
RegWrite
0
CLK
CLK
0 PCNext
PC
1
A
RD
Instr
Instruction
Memory
19:15
A1
24:20
A2
11:7
A3
SrcA
RD1
RD2
0 SrcB
1
Register
File
+
31:7
PCPlus4
MemWrite
0
CLK
ALUResult
WriteData
ResultSrc
X
WE
Zero
+
WD3
WE3
ImmSrc1:0 ALUSrc ALUControl2:0
10
0
110
ALU
PCSrc
1
A
RD
Data
Memory
WD
ReadData
1
0
PCTarget
ImmExt
Extend
Result
4
B-Type
31:25
24:20
imm12,10:5 rs2
7 bits
5 bits
19:15
14:12
11:7
rs1 funct3 imm4:1,11
5 bits
3 bits
5 bits
6:0
op
7 bits
beq rs1, rs2, Label
Chapter 7 <25>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: ImmExt
ImmSrc1:0 ImmExt
Instruction Type
00
01
10
I-Type
S-Type
B-Type
{{20{instr[31]}}, instr[31:20]}
{{20{instr[31]}}, instr[31:25], instr[11:7]}
{{19{instr[31]}}, instr[31], instr[7],
instr[30:25], instr[11:8], 1’b0}
I-Type
19:15
31:20
imm11:0
rs1 funct3
5 bits
12 bits
14:12
3 bits
11:7
6:0
rd
op
5 bits
7 bits
11:7
6:0
imm4:0
op
5 bits
7 bits
11:7
6:0
S-Type
31:25
24:20
19:15
14:12
imm11:5
rs2
rs1 funct3
7 bits
5 bits
5 bits
31:25
24:20
19:15
3 bits
B-Type
imm12,10:5 rs2
7 bits
5 bits
14:12
rs1 funct3 imm4:1,11
5 bits
3 bits
Chapter 7 <26>
5 bits
op
7 bits
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle RISC-V Processor
30
14:12
6:0
PCSrc
Control
ResultSrc
Unit
MemWrite
funct75 ALUControl2:0
funct3 ALUSrc
op
ImmSrc1:0
RegWrite
CLK
0 PCNext
PC
1
A
RD
Instr
Instruction
Memory
19:15
A1
24:20
A2
11:7
A3
WE3
SrcA
RD1
RD2
0 SrcB
1
Register
File
+
31:7
PCPlus4
WE
Zero
ALUResult
WriteData
+
WD3
CLK
ALU
CLK
A
RD
Data
Memory
WD
ReadData
1
0
PCTarget
ImmExt
Extend
Result
4
Chapter 7 <27>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Control
Zero
PCSrc
Branch
ResultSrc1:0
Op6:0
5
MemWrite
Main
Decoder
ALUSrc
ImmSrc1:0
RegWrite
ALUOp1:0
funct32:0
funct75
ALU
Decoder
Chapter 7 <28>
ALUControl2:0
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Control Unit: Main Decoder
op
Instruct RegWrite
ImmSrc
ALUSrc
MemWrite ResultSrc
Branch
ALUOp
3
lw
1
00
1
0
1
0
00
35
sw
0
01
1
1
X
0
00
51
R-type
1
XX
0
0
0
0
10
99
beq
0
10
0
0
X
1
01
Zero
PCSrc
Branch
ResultSrc1:0
Op6:0
5
Main
Decoder
MemWrite
ALUSrc
ImmSrc1:0
RegWrite
ALUOp1:0
funct32:0
funct75
ALU
Decoder
Chapter 7 <29>
ALUControl2:0
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Review: ALU
A
B
N
N
ALU
3 ALUControl
N
Y
Chapter 7 <30>
ALUControl2:0
Function
000
A&B
001
A|B
010
A+B
110
A-B
111
SLT
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Review: ALU
A
B
N
N
N
0
1
ALUControl2
N
Cout
+
[N-1] S
Zero
Extend
N
N
N
ALUControl2:0
Function
000
A&B
001
A|B
010
A+B
110
A-B
111
SLT
N
0
1
2
3
2
ALUControl1:0
N
Y
Chapter 7 <31>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Control: ALU Decoder
Zero
PCSrc
Branch
ResultSrc1:0
Op6:0
5
MemWrite
Main
Decoder
ALUSrc
ImmSrc1:0
RegWrite
ALUOp1:0
funct32:0
funct75
ALU
Decoder
Chapter 7 <32>
ALUControl2:0
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Control Unit: ALU Decoder
ALUOp
op5
funct3
funct75
Instruction
ALUControl2:0
00
X
X
X
lw, sw
01
X
X
X
beq
110 (subtract)
10
X
000
0
add
010 (add)
1
000
1
sub
110 (subtract)
X
010
0
slt
111 (set less than)
X
110
0
or
001 (or)
X
111
0
Slt
000 (and)
010 (add)
ALUOp1:0
op5
funct32:0
funct75
ALU
Decoder
Chapter 7 <33>
ALUControl2:0
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Example: or
op
Instruct RegWrite
51
R-type
ImmSrc
ALUSrc
XX
0
1
30
14:12
6:0
MemWrite ResultSrc
0
Branch
ALUOp
0
10
0
PCSrc
Control
ResultSrc
Unit
MemWrite
funct75 ALUControl2:0
funct3 ALUSrc
op
ImmSrc1:0
RegWrite
0 PCNext
CLK
CLK
PC
1
A
RD
Instr
Instruction
Memory
19:15
A1
24:20
A2
11:7
A3
WE3
XX
0
SrcA
RD1
RD2
0 SrcB
1
Register
File
+
31:7
PCPlus4
CLK
001
ALUResult
WriteData
0
0
WE
Zero
+
WD3
1
ALU
0
A
RD
Data
Memory
WD
ReadData
1
0
PCTarget
ImmExt
Extend
Result
4
Chapter 7 <34>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Example: or
30
14:12
6:0
PCSrc
Control
ResultSrc
Unit
MemWrite
funct75 ALUControl2:0
funct3 ALUSrc
op
ImmSrc1:0
RegWrite
0 PCNext
PC
1
A
RD
Instr
Instruction
Memory
19:15
A1
24:20
A2
11:7
A3
WE3
XX
0
SrcA
RD1
RD2
0 SrcB
1
Register
File
+
31:7
PCPlus4
CLK
001
ALUResult
WriteData
0
0
WE
Zero
+
WD3
1
ALU
0
CLK
CLK
A
RD
Data
Memory
WD
ReadData
1
0
PCTarget
ImmExt
Extend
Result
4
Chapter 7 <35>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Extended Functionality: addi
op
Instruct RegWrite
ImmSrc
ALUSrc
MemWrite ResultSrc
Branch
ALUOp
3
lw
1
00
1
0
1
0
00
35
sw
0
01
1
1
X
0
00
51
R-type
1
XX
0
0
0
0
10
99
beq
0
10
0
0
X
1
01
19
addi
1
00
1
0
0
0
10
Chapter 7 <36>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Extended Functionality: addi
ImmSrc
ALUSrc
00
1
1
addi
30
14:12
6:0
MemWrite ResultSrc
0
Branch
ALUOp
0
10
0
PCSrc
Control
ResultSrc
Unit
MemWrite
funct75 ALUControl2:0
funct3 ALUSrc
op
ImmSrc1:0
RegWrite
CLK
0 PCNext
PC
1
A
RD
Instr
Instruction
Memory
19:15
A1
24:20
A2
11:7
A3
WD3
CLK
WE3
SrcA
RD1
RD2
0 SrcB
1
Register
File
31:7
PCPlus4
WE
Zero
ALU
CLK
ALUResult
WriteData
+
19
Instruct RegWrite
+
op
A
RD
Data
Memory
WD
ReadData
1
0
PCTarget
ImmExt
Extend
Result
4
Chapter 7 <37>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Extended Functionality: jal
PCUpdate
Zero
PCSrc
Branch
PCUpdate
ResultSrc1:0
Op6:0
Main
Decoder
MemWrite
ALUSrc
5
ImmSrc1:0
RegWrite
ALUOp1:0
funct32:0
funct75
ALU
Decoder
Chapter 7 <38>
ALUControl2:0
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Datapath: ImmExt
ImmSrc1:0
ImmExt
Instruction Type
00
{{20{instr[31]}}, instr[31:20]}
I-Type
01
{{20{instr[31]}}, instr[31:25], instr[11:7]}
S-Type
10
{{19{instr[31]}}, instr[31], instr[7], instr[30:25],
instr[11:8], 1’b0}
B-Type
11
{{12{instr[31]}}, instr[19:12], instr[20],
instr[30:21], 1’b0}
J-Type
B-Type
I-Type
19:15
31:20
imm11:0
rs1 funct3
5 bits
12 bits
14:12
3 bits
11:7
6:0
rd
op
5 bits
7 bits
11:7
6:0
imm4:0
5 bits
31:25
24:20
19:15
imm12,10:5 rs2
7 bits
5 bits
24:20
19:15
14:12
imm11:5
rs2
rs1 funct3
7 bits
5 bits
5 bits
3 bits
11:7
rs1 funct3 imm4:1,11
5 bits
3 bits
6:0
op
5 bits
7 bits
31:12
11:7
6:0
op
imm20,10:1,11,19:12
rd
op
7 bits
20 bits
5 bits
S-Type
31:25
14:12
J-Type
Chapter 7 <39>
7 bits
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Extended Functionality: jal
op
Instruct
RegWrite
ImmSrc
ALUSrc
MemWrite
ResultSrc
Branch
ALUOp
PCUpdate
3
lw
1
00
1
0
10
0
00
0
35
sw
0
01
1
1
XX
0
00
0
51
R-type
1
XX
0
0
01
0
10
0
99
beq
0
10
0
0
XX
1
01
0
19
addi
1
00
1
0
01
0
10
0
111
jal
0
11
X
0
00
0
XX
1
Chapter 7 <40>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Extended Functionality: jal
RegWrite
ImmSrc
ALUSrc
MemWrite
0
11
X
0
jal
30
14:12
6:0
ResultSrc
Branch
ALUOp
PCUpdate
0
XX
1
00
PCSrc
Control
ResultSrc1:0
Unit
MemWrite
funct75 ALUControl2:0
funct3 ALUSrc
op
ImmSrc1:0
RegWrite
CLK
0 PCNext
PC
1
A
RD
Instr
Instruction
Memory
19:15
A1
24:20
A2
11:7
A3
WD3
CLK
WE3
SrcA
RD1
RD2
0 SrcB
1
Register
File
31:7
PCPlus4
WE
Zero
ALU
CLK
ALUResult
WriteData
+
111
Instruct
+
op
A
RD
Data
Memory
WD
ReadData
10
01
00
PCTarget
ImmExt
Extend
Result
4
Chapter 7 <41>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Processor Performance
Program Execution Time
= (#instructions)(cycles/instruction)(seconds/cycle)
= # instructions x CPI x TC
Chapter 7 <42>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Performance
30
14:12
6:0
PCSrc
Control
ResultSrc1:0
Unit
MemWrite
funct75 ALUControl2:0
funct3 ALUSrc
op
ImmSrc1:0
RegWrite
CLK
0 PCNext
PC
1
A
RD
Instr
Instruction
Memory
19:15
A1
24:20
A2
11:7
A3
WE3
SrcA
RD1
RD2
0 SrcB
1
Register
File
+
31:7
PCPlus4
WE
Zero
ALUResult
WriteData
+
WD3
CLK
ALU
CLK
A
RD
Data
Memory
WD
ReadData
10
01
00
PCTarget
ImmExt
Extend
Result
4
TC limited by critical path (lw)
Chapter 7 <43>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Performance
• Single-cycle critical path:
Tc1 = tpcq_PC + tmem + max[tmux + tRFread, text + tmux] + tALU + tmem + tmux + tRFsetup
• Typically, limiting paths are:
– memory, ALU, register file
– Tc1 = tpcq_PC + 2tmem + tRFread + tALU + 2tmux + tRFsetup
Chapter 7 <44>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Performance Example
Element
Parameter
Delay (ps)
Register clock-to-Q
tpcq_PC
40
Register setup
tsetup
50
Multiplexer
tmux
25
ALU
tALU
120
Decoder (Control Unit)
tdec
70
Memory read
tmem
200
Register file read
tRFread
100
Register file setup
tRFsetup
60
Tc1 = ?
Chapter 7 <45>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Performance Example
Element
Parameter
Delay (ps)
Register clock-to-Q
tpcq_PC
40
Register setup
tsetup
50
Multiplexer
tmux
25
ALU
tALU
120
Decoder (Control Unit)
tdec
70
Memory read
tmem
200
Register file read
tRFread
100
Register file setup
tRFsetup
60
Tc1 = tpcq_PC + 2tmem + tdec + tRFread + tALU + 2tmux + tRFsetup
= [50 + 2(200) + 70 + 100 + 120 + 2(25) + 60] ps
= 840 ps
Chapter 7 <46>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Single-Cycle Performance Example
Program with 100 billion instructions:
Execution Time = # instructions x CPI x TC
= (100 × 109)(1)(840 × 10-12 s)
= 84 seconds
Chapter 7 <47>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle RISC-V Processor
• Single-cycle:
+ simple
- cycle time limited by longest instruction (lw)
- separate memories for instruction and data
- 3 adders/ALUs
• Multicycle processor addresses these issues by
breaking instruction into shorter steps
o shorter instructions take fewer steps
o can re-use hardware
o cycle time is faster
Chapter 7 <48>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle RISC-V Processor
• Single-cycle:
+ simple
- cycle time limited by longest instruction (LDR)
- separate memories for instruction and data
- 3 adders/ALUs
• Multicycle:
+ higher clock speed
+ simpler instructions run faster
+ reuse expensive hardware on multiple cycles
- sequencing overhead paid many times
Chapter 7 <49>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle RISC-V Processor
• Single-cycle:
+ simple
- cycle time limited by longest instruction (LDR)
- separate memories for instruction and data
- 3 adders/ALUs
Same design steps
as single-cycle:
• first datapath
• then control
• Multicycle:
+ higher clock speed
+ simpler instructions run faster
+ reuse expensive hardware on multiple cycles
- sequencing overhead paid many times
Chapter 7 <50>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle State Elements
Replace Instruction and Data memories with a
single unified memory – more realistic
CLK
CLK
PCNext
WE
PC
EN
CLK
A
RD
Instr / Data
Memory
WD
Chapter 7 <51>
A1
A2
WE3
RD1
RD2
A3
Register
File
WD3
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: Instruction Fetch
STEP 1: Fetch instruction
IRWrite
CLK
CLK
CLK
PCNext
WE
PC
EN
A
RD
CLK
Instr
A1
WE3
RD1
EN
A2
Instr / Data
Memory
RD2
A3
Register
File
WD3
WD
Chapter 7 <52>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: lw get sources
STEP 2: Read source operand from RF and
extend immediate
IRWrite
CLK
CLK
PCNext
CLK
WE
PC
A
Instr
RD
Rs1
19:15
A3
WD3
I-Type
12 bits
14:12
rs1 funct3
5 bits
RD1
A
3 bits
RD2
Register
File
Extend
31:20
19:15
WE3
A2
WD
imm11:0
A1
EN
Instr / Data
Memory
31:20
CLK
CLK
11:7
6:0
rd
op
5 bits
7 bits
Chapter 7 <53>
ImmExt
lw rd, imm(rs1)
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: lw Address
STEP 3: Compute the memory address
IRWrite
CLK
PCNext
CLK
WE
PC
A
RD
CLK
CLK
Instr
Rs1
19:15
A1
WE3
RD1
A
EN
A2
Instr / Data
Memory
A3
WD
WD3
RD2
SrcB
ALUResult
ALUOut
Register
File
Extend
31:20
CLK
SrcA
ALU
CLK
ALUControl2:0
ImmExt
I-Type
31:20
imm11:0
12 bits
19:15
14:12
rs1 funct3
5 bits
3 bits
11:7
6:0
rd
op
5 bits
7 bits
Chapter 7 <54>
lw rd, imm(rs1)
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: lw Memory Read
STEP 4: Read data from memory
CLK
CLK
PCNext
PC
EN
IRWrite
CLK
WE
0
1
Adr
A
ALUControl2:0
Instr
RD
WD
Rs1
19:15
A1
WE3
RD1
A
A2
A3
WD3
CLK
RD2
SrcB
ALUResult
ALUOut
Register
File
Extend
31:20
Data
CLK
SrcA
EN
ReadData
Instr / Data
Memory
CLK
CLK
ALU
AdrSrc
ImmExt
I-Type
31:20
imm11:0
12 bits
19:15
14:12
rs1 funct3
5 bits
3 bits
11:7
6:0
rd
op
5 bits
7 bits
Chapter 7 <55>
lw rd, imm(rs1)
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: lw Write Register
STEP 5: Write data back to register file
CLK
CLK
PCNext
PC
EN
IRWrite
CLK
WE
0
1
Adr
A
RegWrite
WD
A1
WE3
RD1
A
A2
Rd
11:7
CLK
RD2
CLK
SrcA
EN
ReadData
Instr / Data
Memory
Rs1
19:15
ResultSrc1:0
CLK
CLK
Instr
RD
ALUControl2:0
SrcB
ALU
AdrSrc
ALUResult
Register
File
WD3
Extend
31:20
10
01
00
A3
Data
ALUOut
ImmExt
I-Type
31:20
imm11:0
12 bits
19:15
14:12
rs1 funct3
5 bits
3 bits
11:7
6:0
rd
op
5 bits
7 bits
Chapter 7 <56>
lw rd, imm(rs1)
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: Increment PC
STEP 6: Increment PC: PC = PC+4
PCWrite
AdrSrc
IRWrite
RegWrite
ALUSrcA1:0
ALUControl2:0
ResultSrc1:0
ALUSrcB1:0
PCNext
PC
EN
CLK
WE
0
1
Adr
A
Rs1
A1
WE3
RD1
01
A
A2
Rd
11:7
CLK
31:20
Data
00
RD2
01
A3
Register
File
WD3
Extend
4
CLK
SrcA
10
EN
ReadData
Instr / Data
Memory
WD
Instr
RD
19:15
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <57>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: sw
Write data in rs2 to memory
PCWrite
AdrSrc
MemWrite IRWrite
RegWrite ImmSrc1:0
ALUSrcA1:0
ALUControl2:0
ALUSrcB1:0
CLK
ResultSrc1:0
Zero
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
EN
CLK
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
A1
WE3
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
RD
19:15
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
00
01
10
10
ImmExt
Result
Chapter 7 <58>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: sw
Write data in rs2 to memory
PCWrite
AdrSrc
MemWrite IRWrite
RegWrite ImmSrc1:0
ALUSrcA1:0
ALU
CLK
OldPC
CLK
CLK
PCNext
PC
EN
WE
0
1
Adr
A
EN
CLK
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
Chapter 7 <59>
A1
WE3
A2
RD1
01
A
10
00
RD2
A3
Register
File
WD3
Extend
WriteData
ReadData
Instr / Data
Memory
WD
Instr
RD
19:15
00
CLK
CLK
01
4
10
ImmExt
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Datapath: beq
Calculate branch target address:
BTA = PC + imm
PCWrite
AdrSrc
MemWrite IRWrite
RegWrite ImmSrc1:0
ALUSrcA1:0
ALUControl2:0
ALUSrcB1:0
CLK
ResultSrc1:0
Zero
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
19:15
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
A1
WE3
A2
RD1
01
A
A3
Register
File
WD3
Extend
CLK
SrcA
10
00
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
01
4
00
01
10
10
ImmExt
Result
PC was already updated in Fetch stage, so need to save old PC
Chapter 7 <60>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle RISC-V Processor
CLK
PCWrite
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
MemWrite
ALUControl2:0
30
14:12
6:0
funct75
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
19:15
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
A1
WE3
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <61>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Control
PCUpdate
Zero
PCWrite
Branch
PCUpdate
RegWrite
MemWrite
Main
FSM
Op6:0
IRWrite
ResultSrc1:0
ALUSrcB1:0
ALUSrcA1:0
5
ImmSrc1:0
AdrSrc
ALUOp1:0
funct32:0
funct75
Op6:0
ALU
Decoder
ALUControl2:0
Instr
Decoder
ImmSrc1:0
Chapter 7 <62>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Control
PCUpdate
Zero
PCWrite
Branch
PCUpdate
RegWrite
MemWrite
Main
FSM
op6:0
IRWrite
ResultSrc1:0
ALUSrcB1:0
ALUSrcA1:0
ImmSrc1:0
5
AdrSrc
ALUOp1:0
funct32:0
funct75
op6:0
ALU
Decoder
ALUControl2:0
Instr
Decoder
ImmSrc1:0
Chapter 7 <63>
ALU Decoder
same as
single-cycle
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Control: Instr Decoder
op6:0
op
3
35
51
99
Instr
Decoder
ImmSrc1:0
Instruction
lw
sw
R-type
beq
Chapter 7 <64>
ImmSrc
00
01
XX
10
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle RISC-V Processor
CLK
PCWrite
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
MemWrite
ALUControl2:0
30
14:12
6:0
funct75
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
19:15
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
A1
WE3
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <65>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle Control: Main FSM
PCUpdate
Zero
PCWrite
Branch
PCUpdate
RegWrite
MemWrite
Main
FSM
op6:0
IRWrite
ResultSrc1:0
ALUSrcB1:0
ALUSrcA1:0
ImmSrc1:0
AdrSrc
ALUOp1:0
Chapter 7 <66>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Fetch
Reset
S0: Fetch
AdrSrc = 0
IRWrite
CLK
PCWrite
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
MemWrite
ALUControl2:0
30
14:12
6:0
0
0
0
funct75
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
1
0
XX
XX
XX
XXX
XX
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
19:15
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
A1
WE3
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <67>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Decode
Reset
CLK
PCWrite
S1: Decode
S0: Fetch
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
AdrSrc = 0
IRWrite
MemWrite
ALUControl2:0
30
14:12
6:0
0
X
0
funct75
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
0
00
0
XX
XX
XXX
XX
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
19:15
Rs1
24:20
Rs2
11:7
Rd
A1
WE3
A2
RD1
Register
File
WD3
31:7
00
Extend
01
4
CLK
SrcA
10
RD2
A3
Data
01
A
WriteData
ReadData
Instr / Data
Memory
WD
Instr
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <68>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Address
Reset
CLK
S1: Decode
S0: Fetch
AdrSrc = 0
IRWrite
PCWrite
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
MemWrite
op = lw
OR
op = sw
ALUControl2:0
30
S2: MemAdr
funct75
14:12
ALUSrcA = 10
ALUSrcB = 01
ALUOp = 00
6:0
0
X
0
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
0
0
XX
10
01
010
XX
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
19:15
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
A1
WE3
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <69>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Read Memory
Reset
S0: Fetch
S1: Decode
AdrSrc = 0
IRWrite
op = lw
OR
op = sw
S2: MemAdr
ALUSrcA = 10
ALUSrcB = 01
ALUOp = 00
op = lw
S3: MemRead
ResultSrc = 10
AdrSrc = 1
Chapter 7 <70>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Multicycle RISC-V Processor
CLK
S3: MemRead
ResultSrc = 10
AdrSrc = 1
PCWrite
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
MemWrite
ALUControl2:0
30
14:12
6:0
0
1
0
funct75
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
0
0
XX
XX
XX
XXX
10
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
WE3
A1
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
19:15
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <71>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Write RF
Reset
S0: Fetch
S1: Decode
AdrSrc = 0
IRWrite
op = lw
OR
op = sw
S2: MemAdr
ALUSrcA = 10
ALUSrcB = 01
ALUOp = 00
op = lw
S3: MemRead
ResultSrc = 10
AdrSrc = 1
S4: MemWB
ResultSrc = 01
RegWrite
Chapter 7 <72>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Write RF
CLK
S4: MemWB
ResultSrc = 01
RegWrite
PCWrite
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
MemWrite
ALUControl2:0
30
14:12
6:0
0
X
0
funct75
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
0
1
XX
XX
XX
XXX
01
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
WE3
A1
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
19:15
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <73>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Fetch Revisited
Reset
S0: Fetch
AdrSrc = 0
IRWrite
ALUSrcA = 00
ALUSrcB =10
ALUOp = 00
ResultSrc = 00
PCUpdate
• ALU isn’t being used
• Use ALU to calculate PC+4
Chapter 7 <74>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Fetch Revisited
Reset
S0: Fetch
AdrSrc = 0
IRWrite
ALUSrcA = 00
ALUSrcB =10
ALUOp = 00
ResultSrc = 00
PCUpdate
S1: Decode
op = lw
OR
op = sw
S2: MemAdr
ALUSrcA = 10
ALUSrcB = 01
ALUOp = 00
op = lw
S3: MemRead
ResultSrc = 10
AdrSrc = 1
S4: MemWB
ResultSrc = 01
RegWrite
Chapter 7 <75>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier
Main Controller FSM: Fetch Revisited
• PC+4: shown in blue
• Instr fetch: shown in gray
CLK
Reset
PCWrite
S0: Fetch
AdrSrc Control
Unit
IRWrite
ResultSrc1:0
AdrSrc = 0
IRWrite
ALUSrcA = 00
ALUSrcB =10
ALUOp = 00
ResultSrc = 00
PCUpdate
1
MemWrite
ALUControl2:0
30
funct75
14:12
6:0
0
0
ALUSrcB1:0
ALUSrcA1:0
funct3
ImmSrc1:0
op
RegWrite
Zero
1
0
XX
00
10
010
00
Zero
CLK
OldPC
PCNext
PC
EN
WE
0
1
Adr
A
RD
EN
CLK
Rs1
24:20
Rs2
11:7
Rd
31:7
Data
A1
WE3
A2
RD1
01
A
A3
Register
File
WD3
00
Extend
01
4
CLK
SrcA
10
RD2
WriteData
ReadData
Instr / Data
Memory
WD
Instr
19:15
00
CLK
CLK
SrcB
ALU
CLK
CLK
ALUResult
ALUOut
10
01
00
10
ImmExt
Result
Chapter 7 <76>
Digital Design and Computer Architecture: RISC-V Edition
Harris & Harris © 2020 Elsevier