Voltus-Fi EMIR Analysis Workshop
- The DSPF flow
Product versions: Voltus-Fi XL IC6.1.7 ISR22, SPECTRE171 ISR5
September 2018
Copyright Statement
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 2
Contents
Introduction to Voltus-Fi EMIR Analysis Workshop ...................................................................................... 4
The EMIR Solver Methods in MMSIM/SPECTRE ....................................................................................... 4
Direct Mode .......................................................................................................................................... 4
Iterated Mode ....................................................................................................................................... 5
Enabling EMIR Analysis in Analog Design Environment................................................................................ 8
Analyzing the EMIR Analysis Outputs ......................................................................................................... 21
IR Drop Analysis Results .......................................................................................................................... 24
Performing Structural Analysis ............................................................................................................... 28
Performing EM Analysis .......................................................................................................................... 31
Displaying and Querying EMIR Results ................................................................................................... 32
Additional Query Features .................................................................................................................. 33
Debugging Capabilities in Voltus-Fi............................................................................................................. 35
Performing the LRP Analysis ................................................................................................................... 35
Calculating Effective Resistance Between any Two Nodes on a Net ...................................................... 37
Performing What-if Analysis ................................................................................................................... 38
Static EMIR Analysis .................................................................................................................................... 41
References .................................................................................................................................................. 45
Videos.......................................................................................................................................................... 45
Support ....................................................................................................................................................... 45
Feedback ..................................................................................................................................................... 45
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Introduction to Voltus-Fi EMIR Analysis Workshop
Welcome to Voltus-Fi EMIR Analysis Workshop. This workshop will take you through IRdrop and Electromigration analysis flow utilizing our patent-pending technology in MMSIM
(APS/XPS) followed by visualization of results in Virtuoso Layout Editor.
This workshop is designed to work with IC617 the ISR20 and SPECTRE171 ISR5
releases or later. If you are interested in running LVS and extraction, then PVS161 and
EXT171 (or EXT181) are also required. There are no prerequisites for this workshop,
although the ADE XL or Explorer/Assembler workshop is highly recommended. Some
familiarity with physical design and the concepts of IR-drop and electromigration will be
helpful.
The EMIR Solver Methods in MMSIM/SPECTRE
Voltus-Fi is a new EMIR solution that comes integrated with the Spectre APS/XPS
simulators for high capacity and accuracy, supporting electromigration for both power and
signal nets along with IR drop. This new dynamic power EMIR and signal EM capability
uses a new patent-pending technology and is designed to provide very high capacity and
performance. Within this flow, Spectre® APS can be used for high accuracy EMIR
analyses; while Spectre® XPS can be deployed for high performance and high capacity
EMIR simulation of memories. Voltus-Fi can provide a very well-integrated visualization
experience inside the Virtuoso environment. Voltus-Fi EM engine is N7/N16/N20/N28
certified and supports all length and width-based rules.
In an EMIR flow, a circuit is evaluated together with the parasitic resistor and capacitor
network which models the IR drop and EM effect. The parasitic information comes from
a transistor-level and unreduced DSPF or SPEF, which contains additional information
about the width, length, and XY coordinates of the parasitic resistors. There are two
general approaches in APS/XPS EMIR solution – Direct and Iterated.
Direct Mode
When high accuracy is required, flat simulation of the entire system - circuit
and parasitic R’s and C’s – can be performed to accurately calculate EM/IR of any nets.
This approach is often referred to as “one-step” or “direct” method, where the EMIR
simulation performance and capacity is subject to the limitation of the circuit simulator
being used. For high accuracy EMIR analysis of small design blocks, or designs with
smaller numbers of RC nets, the direct EMIR analysis method is recommended.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 4
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Iterated Mode
To conduct EMIR simulation on circuits with much larger power and signal nets
in reasonable time, an alternative is to decouple the nonlinear circuit simulation from the
linear RC net analysis. You can iterate over only the linear RC net analysis by modifying
the layout. However, the nonlinear circuit simulation may be done only once (the
assumption is that the circuit does not change over iterations). This approach is often
referenced as the “two-step” or “iterated” method. The decoupling of the linear RC nets
from the non-linear circuit is not mathematically equivalent to the original design and
certain inaccuracy is introduced; however, it provides significant benefit in terms of
simulation performance and capacity.
To gain higher performance and higher capacity on medium to large designs, the iterated
EMIR analysis method is recommended. Both Spectre® APS and Spectre® XPS support
the iterated EMIR analysis.
The snapshot below compares Direct and Iterated solving methods.
Figure1: Direct and Iterated EMIR Analysis Methods
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 5
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
The Voltus-Fi EMIR flow diagram is shown below.
Figure2: Voltus-Fi EMIR Flow – Direct Method
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 6
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
The Voltus-Fi EMIR flow diagram for Iterated method is shown below.
Figure3: Voltus-Fi EMIR Flow - Iterated Method
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 7
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Enabling EMIR Analysis in Analog Design Environment
In this section…
You will learn how to setup the EMIR flow in ADE-L, ADE-XL, and Explorer (maestro
view). You will start with looking at the testbench schematic and the nets to analyze.
Action 1: tar xvzf VoltusFi_workshop.tar.gz
Action 2: cd VoltusFi_workshop
Action 3: Open file ‘sourceme’ for editing. If your environment sets up all tool installations
and licenses correctly, first comment out the lines 5 to 14 and then:
source sourceme
Alternatively, update the paths for software installations in the same section, and then
source the file.
Action 4: virtuoso &
The CIW along with the Library Manager will appear.
Action 5: In the Library Manager, select and open:
•
•
•
Library: Two_Stage_Opamp
Cell: DiffOpAmp_TRAN_top
View: schematic
The testbench schematic can be seen below.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 8
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure4: Opening the Testbench Schematic
In this workshop, we will simulate and analyze for EMIR a differential op amp (instance
name: I0). Descend into I0 schematic or layout to look at the DUT implementation.
We will analyze supply nets AVDD and AVSS for IR-drop, and all nets for EM.
Action 6 (optional): Let us look at the Quantus QRC setup for running extraction. You can
choose to skip this step and directly use DSPF “DiffOpAmp.dspf” in the next step.
Open DUT layout and bring up Quantus QRC form through QRC -> Run PVS-Quantus
QRC menu. LVS has already been run using PVS and the results are stored in directory
‘PVS_lvs_qrc’.
•
•
•
Library: Two_Stage_Opamp
Cell: DiffOpAmp
View: layout
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 9
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure5: Opening the Quantus QRC Form
Once the Quantus QRC form comes up, load the state, “EMIR”. This should set the
required options for running the EMIR flow.
Note: Pay close attention to the ‘Netlisting’ tab. Ensure that your setup matches the
snapshot below to generate a good DSPF required for EMIR analysis. In particular, XYcoordinates need to be written out in DSPF.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 10
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure6: Running Quantus QRC Parasitic Extraction – Netlisting Tab
When you hit the ‘OK’ button on the Quantus QRC form, it should generate a DSPF for
the DUT. You can use your new DSPF, or the original one included in the workshop in
subsequent steps (as mentioned earlier).
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 11
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Note: A DSPF file ‘DiffOpAmp.dspf.golden’ has been provided as a back-up in case
you overwrite DiffOpAmp.dspf and want to retrieve it.
At advanced nodes, some extra settings may be required for xDSPF generation.
Action 7a (for ADE-L users): Open the testbench schematic.
•
•
•
Library: Two_Stage_Opamp
Cell: DiffOpAmp_TRAN_top
View: schematic
Launch ADE L from schematic and load state ‘spectre_state1_emir’ from cellview. There
is another state ‘spectre_state1_emir_direct’ provided for reference EMIR setup using the
Direct solver method.
Figure7: Opening the ADE L Window
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 12
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Action 7b (for maestro or ADE-XL users): Open ‘maestro’ (or ‘adexl’) view for DUT
•
•
•
Library: Two_Stage_Opamp
Cell: DiffOpAmp
View: maestro (or adexl)
Double-click on the test ‘TRAN_EMIR_Iter’ to open Assembler as shown below. Test
‘TRAN_EMIR_Direct’ (disabled) has been created for reference EMIR setup.
Figure8: Opening Assembler view
Action 8: Enable the EMIR related options mentioned below (For maestro/ADEXL users,
these menus are also available through <testname> -> RMB).
•
•
Setup -> High-Performance Simulation
o Enable APS
Setup -> Simulation Files
o This option has fields to include the DUT DSPF or the SPEF (snapshot
below). Point to your parasitic file here.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 13
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure9: Opening the Simulation Files Setup Form
•
Setup -> EM/IR Analysis
o A form will pop-up allowing you to specify the EMIR options
The EM/IR Analysis Setup form will open as shown below for a new state/test. You will
notice that the path to the EM Tech File is already populated. This is controlled by the
following .cdsinit variable:
Example:
envSetVal("spectre.envOpts" "emTechFile" 'string
"$WORKDIR/pvs_qrc_decks/qrc/typical/ictfile")
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 14
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure10: Opening the EMIR Analysis Setup Form
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 15
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
The form is divided into four tabs: Analysis, Solver, Options, and Macro Model
Generation. We will now briefly go over the contents of each tab.
The Analysis Tab
•
Type -> Dynamic or Static. Dynamic EMIR analysis requires a DC or transient
simulation, while Static analysis can estimate IR-drop and EM current density
without performing a circuit simulation but based on current estimates provided by
the user. In this RAK, we will cover both dynamic and static analysis.
•
Net Selection –> Specify the nets to be analyzed in the schematic, choose one
or more analysis, and then click ‘Add’. You will find the Summary Information
section at the bottom gets populated with net+analysis combination. A pink infoballoon is displayed when you hover over the Net Name field to help you select
nets for analysis.
The Solver Tab
•
Solver Method -> The most commonly used methods are ‘direct’ and ‘iterated’.
‘profonly’ runs the first stage of the iterated flow while ‘iteronly’ is relevant if the
first EMIR simulation was run using iterated (or profonly), and then the layout
was modified to address any violations. The next simulation will benefit from
using ‘iteronly’ because it will solve only the R/RC parasitics again, but not the
circuit, thereby saving significant time.
•
Time Window Setup -> By default, for a transient analysis, EMIR analysis is run
over the entire simulation period. You can choose to provide different time
windows by enabling the “Time window” and adding the new start/stop times.
The Options Tab
•
Options -> Details about allowed emirutil options can be found in the “Postlayout
Simulation” chapter of the Spectre Circuit Simulator and Accelerated Parallel
Simulator User Guide.
You can choose from a list of advanced options pulldown menu or provide the
required option in ‘Additional Option’.
•
DSPF File Checking -> The DSPF file included through Simulation files is
automatically populated in this field. Clicking ‘Run’ will invoke the spfchecker
which checks the syntax of the DSPF/SPEF followed by opening spfchecker
output log. Spfchecker also compares the terminal names in DSPF and device
models and populates the Summary Section with spf aliasterm statements.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 16
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
The Summary Information section at the bottom of the form is updated as you make
changes in the form or click Add where applicable. This section contains the final set of
commands that will be used by APS/XPS for performing EMIR analysis.
The Macro Model Generation Tab
This tab does not need to be setup for block-level EMIR analysis.
Action 9: Now, let’s see how you enter the required options in the form.
The Analysis Tab
Net Selection
Press ‘Select’, this should bring up the testbench schematic prompting you to select the
nets for analysis.
•
To analyze all nets in the block for EM, select the instance, choose the analysis
and click Add.
•
•
Click Clear to remove the net names.
To analyze a particular supply/ground net for IR-drop and/or EM, select the
instance port(s) in the testbench schematic
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 17
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Emirutil Setup
•
The path to EM rule will be automatically populated through the .cdsinit setting.
You can point to a different EM rule file if required. When you do this, the Summary
Information is updated automatically.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 18
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
The Solver Tab
Solver Method
• Select the iterated method. The ADE L or XL reference setups included in the
workshop use the direct method’.
The Options Tab
DSPF File Checking
• When you click ‘Run’, a utility called Standard Parasitic Format (SPF) Checker or
‘spfchecker’ is invoked in the batch-mode to parse the DSPF. A log file will come
up after the spfchecker run has completed.
Summary Information
•
The summary section should look as below. The options visible here will be
translated into a file called emir.conf and passed on to APS during simulation.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 19
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Ensure that the Enable EMIR Analysis in Transient or DC Simulation option at the bottom
of the form is enabled.
Press OK on the form and EMIR setup is ready.
Action 10: Run the simulation. The simulation output should look as shown below.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 20
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Analyzing the EMIR Analysis Outputs
In this section…
We analyze the different kinds of outputs of EMIR analysis i.e. the text and HTML reports,
followed by the visualization of results overlaid on the DUT layout.
Action 1: Explore the new submenu called EM/IR Data added to view the EMIR results.
For ADE-L users, this can be accessed as shown below.
Figure11: Accessing the EM/IR Data Submenu in ADE L
For ADE-XL/maestro users, the option is available through the Results tab. RMB-click
on any output and navigate to the EM/IR Data.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 21
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure12: Accessing the EM/IR Data Submenu in ADE XL/Maestro
Action 2: Investigate the EM/IR reports by selecting EM/IR Data -> Report. From the popup that opens, you can choose to view the IR-drop reports (input.*.rpt_ir) and EM
reports (input.*.rpt_em) in either text or HTML formats. The ‘Mozilla’ browser will be
invoked automatically (if found in the user’s setup) to display the HTML reports.
Action 3: Prepare for visualizing the results in the Layout Editor by selecting EM/IR Data
-> Layout Analysis.
A pop-up window opens prompting you to choose the DUT Layout view being analyzed.
This should be the same view for which you ran LVS and extraction to generate a DSPF.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 22
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure13: Selecting the Layout View
Click OK to open the layout along with a form titled “IR/EM Results”. Choose between IR
and EM tabs depending on what you want to analyze first.
A few fields are automatically populated in the IR and EM tabs.
•
•
•
State Directory/Results File: Points to the simulation results generated by APS.
DFII Layermap: Points to a text file called “dfiilayermap” included in workshop.
This file maps the extraction layer names in DSPF to the DFII layer names.
Tech File (EM tab only): Points to the EM rule file specified in the ADE setup.
A snapshot of the form is shown below.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 23
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure14: Opening the IR/EM Results Form
IR Drop Analysis Results
Action 4: View the IR-drop results by clicking “Load Results” in IR tab. This will populate
the form with nets analyzed for IR-drop.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 24
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure15: Loading the IR-Drop Results in the IR/EM Results Form
Select IR -IR drop plot in the Rail Analysis dropdown menu and power net, AVDD from
the net selection browser. Click Show Plot.
This will overlay the plot on the layout as shown below.
Note: You can enable dimming in the Layout by selecting the Options main menu and
Display submenu to view a better violation display.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 25
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure16: Viewing the IR-Drop Plot on the Virtuoso Layout
You can customize the display options for the plots by using the options available in the
Display form appended to the right of the IR/EM Results form. This is shown in the
snapshot below.
The worst drop on supply net AVDD is around 6.5mV – there will be a slight difference
in results based on the solver method you chose while running APS (direct or iterated).
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 26
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure17: Customizing the Display Options for the IR-Drop Results Plot
Display
Filter
Custom
Range
The important fields/features of the IR/EM Results form are:
•
•
•
•
•
You can select to show plot of one net/all power nets/all signal nets or selected
nets.
The display filters are continuous filters; you can move the Min and Max sliders up
or down to change the range of IR-drop being shown in the layout. You might want
to Re-distribute Range to use all colors in the palette.
You can also write the custom range in Filter Range field.
You can toggle displaying voltage sources, color plot and Sync violation display
with DFII layers under ‘Display’ settings.
You can customize the results layers to view in Layout Editor from ‘Layers’
section.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 27
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Try to display results with drop > 0.005V showing only the violations within range. Layout
Editor display will look as below (The plot below corresponds to Iterated method).
Figure18: Displaying the IR-Drop Analysis Results for the Specified Range
Note: For details of all the features of the Display form, see the “IR Drop Analysis”
chapter in the Voltus-Fi Custom Power Integrity Solution XL User Guide.
Performing Structural Analysis
Structural analysis is a shape-based geometrical analysis that is used to quickly identify
power-grid weaknesses in designs and mark them on the Virtuoso layout for you to view
and debug. Structural analysis cuts down on the sign-off analysis time. This analysis is
available in the GUI mode.
You can perform structural analysis using the results of the IR drop analysis.
Action 5: Before running structural analysis, ensure that results have been loaded in the
IR tab and you have plotted them for net AVDD (Action 4). Now, switch to the Structural
Analysis tab. The Layer Map File field should be populated already.
Click Run.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 28
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
When you click Run, the options for performing the structural checks get enabled.
Figure19: Displaying the Structural Analysis Results
For more details, see the “Structural Analysis” chapter in the Voltus-Fi Custom Power
Integrity Solution XL User Guide. You can also click the Help button in the form.
Let us experiment with a couple of analysis options here.
1. Show Unconnected from Top Check
Select Show Unconnected from Top. You will notice that the section at the bottom of the
form gets populated with information about segments that do not get overlapped by the
next metal layer above.
You can enable Auto Zoom at the bottom of the form, and investigate the regions shown
as violations by selecting a row in the table.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 29
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure20: Structural Analysis Results – Show Unconnected from Top
2. Via Coverage Ratio check
This check is used to highlight the overlapping area of segments that have via(s), but the
via coverage is less as compared to size of overlapping metals. Via coverage ratio needs
to be specified by the user.
Scroll down in the form to find field Via Coverage Ratio check. Enter 0.2 in the field. You
will notice that via regions with coverage ratio less than 0.2 are highlighted in the layout.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 30
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure21: Structural Analysis Results – Via Coverage Ratio
Performing EM Analysis
VFI-XL uses the simulation database generated by Spectre APS/XPS simulators and
displays the results of the electromigration (EM) analysis on the Virtuoso layout. It also
generates text and HTML reports of the analyses and lets you query the analyses
results to view specific violations in the layout. This is used to debug the high EM violation
regions in the design.
Action 6: We will now perform EM analysis. Click the ‘IR’ tab and click Clear Results.
Then, switch to the EM tab and click Load Results.
The list box in the form is populated with all the nets analyzed for EM. This can be seen
in the snapshot below.
Under Plot Results, you will see different types of plots to choose from. Select ‘JAVG –
Current density/Limit – avg’, and net ‘outp’, and click on Show Plot.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 31
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure22: Viewing the EM Analysis Results
The EM plot shows a ratio of (actual current density) to (allowed density limit) as defined
in EM rule file. Therefore, a ratio >= 1 implies an EM failure. Select Show Only Failed and
click on Show Plot again (see encircled in green above)
Displaying and Querying EMIR Results
We will now explore another feature of the GUI by enabling “Violation Browser” in the
Display form (see it circled in blue in the snapshot above).
This brings up a docked Annotation Browser assistant in Layout Editor with the top 100
EM violation results. This feature also works in IR analysis. Switch to EM/IR tab in the
Annotation Browser to find the worst EM violations listed.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 32
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
When you select a violation in Annotation Browser, the Description section below
provides details about the violation e.g. layer, needed width to fix the violation.
Figure23: Viewing the EM violations in the Annotation Browser
In the Annotation Browser, you can customize the violation display by RMB -> View By,
and then choose from the drop-down menu options.
Additional Query Features
It is also possible to query the layout and back-annotate the corresponding violation(s) in
the Annotation Browser. There are two buttons in the form to help you achieve the same:
•
•
Zoom Select Max Violation
Get Value on Layout
Now, if you click Get Value on Layout, you will be prompted to draw a selection box in
the layout. Once you draw the box, the violations enclosed in your box will be highlighted
in the Annotation Browser (AB). You will also find that arrows are added in the Display
Filter range to indicate the values of the violations highlighted in AB.
The figure below shows the selection box created in the layout and the corresponding
violations in AB.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 33
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure24: Retrieving Violation Values from the Layout
Arrows
in display
filter
The Zoom Select Max Violation option works in the same way, where once you create
the selection box, Layout editor will zoom into the maximum violation found in the
selected region. The same violation will be selected in AB.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 34
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Debugging Capabilities in Voltus-Fi
Voltus-Fi has advanced capabilities to help you debug the root cause of violations or
behavior seen in EMIR analysis. There features are:
1. Plotting the Least-Resistive Path
2. Calculating Effective Resistance between any two nodes on a net
3. What-If(ECO) Analysis
The above features are available in the GUI from the IR/EM Results form. This is shown
below.
Figure25: Debugging Capabilities of VFI-XL
Performing the LRP Analysis
The least-resistive path (LRP) plot lets you identify weakly connected instances in the
design during early stages of power planning. The resistance for an instance pin is
calculated as the total resistance along the least resistance path. If an instance has
multiple power pins connected to the power grid, the LRP plot uses the pin with the worst
(highest) resistance value to plot the instance-based data. This plot highlights the current
path for the selected instance to the voltage source.
Action1: By default, this tab is disabled. To enable this tab, perform the following steps:
•
•
•
Select the IR tab.
Load the IR drop analysis results.
Select a net and click Show Plot.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 35
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure26: LRP Browser Tab of the IR/EM Results Form
LRP feature in Voltus-Fi-XL lets you plot LRP on demand for any node. You can view the
LRP for any high IR drop node by selecting it in the layout. There are two options provided
in the GUI:
• Get Layout Node lets you select a node on the layout and view its LRP.
• Get Marker Node lets select an object in the Annotation Browser and view the
LRP for the node on the selected marker.
For details of the LRP Analysis, see the “Plotting the Least-Resistive Path” section in the
“IR Drop Analysis” chapter of the Voltus-Fi Custom Power Integrity Solution XL User
Guide.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 36
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Video Demonstration for LRP Analysis
To view the demonstration on performing the LRP analysis in Voltus-Fi, see
Performing Least Resistive Path (LRP) Analysis using Voltus-Fi video.
Note: Access to this video will depend on the availability of a web browser and a
Cadence Online Support account.
Calculating Effective Resistance Between any Two Nodes on a Net
In VFI-XL, you can calculate the effective resistance between any two nodes (pins, tap
nodes, or subnodes) of the same net. This feature uses the DSPF file, used for Spectre
simulation, and the SPGS feature of Spectre. It works only for IR drop analysis.
Action1: By default, this tab is disabled. To enable this tab, perform the following steps:
• Select the IR tab.
• Load the IR drop analysis results.
• Select a net and click Show Plot.
• The Pin2PinR tab on the IR/EM Results form is enabled.
For details of the effective resistance analysis, see the “Calculating Effective Resistance
between any Two Nodes on a Net” section in the “IR Drop Analysis” chapter of the VoltusFi Custom Power Integrity Solution XL User Guide.
Video Demonstration for Performing Pin-to-Pin Resistance Check
To view the demonstration on performing pin-to-pin resistance check in Voltus-Fi, see
Performing Pin-to-Pin Resistance Check (Pin2PinR) Using Voltus-Fi video.
Note: Access to this video will depend on the availability of a web browser and a
Cadence Online Support account.
The figure below shows Pin2PinR calculation.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 37
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure27: Viewing the Pin2PinR Calculation
Performing What-if Analysis
The What-If analysis feature lets you analyze the impact of potential layout changes,
without implementing these changes in the layout, and re-extracting the xDSPF file.
These changes are also called the Engineering Change Order (ECO) changes.
The What-If (ECO) flow in Voltus-Fi-XL GUI is as follows:
• ECO commands are specified in the Voltus-Fi-XL GUI and the ECO file is
generated.
• Voltus-Fi-XL calls Spectre to perform the EMIR analysis. Fully accurate EMIR
simulation is performed.
• Only nets that are changed in the ECO statement are changed.
Action1: By default, this tab is disabled. To perform What-If (ECO) analysis:
• Load the IR drop analysis results
• Select a net and click Show Plot.
• The What-If (ECO) Analysis tab gets enabled.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 38
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure28: What-If (ECO) Tab of the IR/EM Results Form
In the example above, we are deleting a via in layer ‘via2’. This will change the IR-drop
results on AVDD as below.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 39
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure29: Results from What-If analysis
Worst
IR-drop
now
~15mV
Via2
deleted
from
here
For more details of the What-if ECO analysis, see the “What-If EMIR Analysis” chapter
of the Voltus-Fi Custom Power Integrity Solution XL User Guide.
Video Demonstration for What-If Analysis
To view the demonstration on performing what-if analysis in Voltus-Fi, see
Performing What-If Analysis Using Voltus-Fi video. The video provides a demonstration
of adding pins to the AVDD net running the add_pin ECO command.
Note: Access to this video will depend on the availability of a web browser and a
Cadence Online Support account.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 40
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Static EMIR Analysis
In this section…
We are going to run static EMIR analysis on the same DUT ‘DiffOpAmp’. Static EMIR
analysis is performed using a current consumption file provided by you without running a
transient or DC simulation. The currents specified at sub-circuit ports get applied to the
tap devices based on the width/length ratios of the devices in the design. Optionally, the
user can also provide currents per device or block to be used in the calculation.
The setup for running static analysis has already been created for the users.
Action 1a (for ADE-L users): Open the testbench schematic:
•
•
•
Library: Two_Stage_Opamp
Cell: DiffOpAmp_TRAN_top
View: schematic
Launch ADE L from schematic and load state ‘spectre_state1_emir_static’ from
cellview.
Action 1b: (for maestro or ADE-XL users): Open ‘maestro’ (or ‘adexl’) view for DUT
•
•
•
Library: Two_Stage_Opamp
Cell: DiffOpAmp
View: maestro (or adexl)
Ensure that test ‘Static_EMIR’ is enabled.
Action 2: Launch EMIR analysis form and explore how the options for static EMIR analysis
have been setup.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 41
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure30: Spectre EMIR Analysis Settings
Action 3: Explore the contents of the Static Current File. This file contains top-level and
instance-based port current. The overall accuracy of EMIR analysis will depend on how
much information you provide in this current file.
I0 AVDD 0.003
I0 AVSS -0.003
I0.MM0@37 AVDD 600e-6
I0.MM5@33 AVDD 600e-6
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 42
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Action 4: Run a simulation and go to EM/IR Data -> Layout Analysis to visualize the results
on the Layout Editor.
Note: Simulation in maestro (ADEXL) view appears to finish with an error, although the
EMIR run completes without issues. This happens because Spectre run did not perform
any analysis (DC/tran) during the static EMIR run. This will be fixed in an upcoming
release.
Plot IR-drop results for net ‘AVDD’ and enable the Violation Browser to view the worst 10
IR-drop points.
Figure31: Plotting the IR Drop Analysis Results for Net AVDD
You will find that the regions highlighted in Red, in the figure below, correspond to the
transistors that were specified in file ‘static_ifile.txt’ above with a current of
600uA each.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 43
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
Figure32: Viewing the Worst Violations on the Layout
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 44
Voltus-Fi EMIR Analysis Workshop -The DSPF flow (RAK)
References
The following related documents are available for reference:
▪
▪
▪
▪
▪
Voltus-Fi Custom Power Integrity Solution XL User Guide
Virtuoso Design Environment User Guide
Virtuoso Analog Design Environment L User Guide
Spectre Circuit Simulator and Accelerated Parallel Simulator User Guide
Virtuoso Layout Suite XL User Guide
Videos
The following Training courses are available on COS:
Transistor Level Power Signoff with Voltus-Fi
Support
Cadence Online Support provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 45