BIT INSTITUTE OF TECHNOLOGY ,
HINDUPUR
(APPROVED BY AICTE,AFFILATED TO JNTUA)
AN ISO 9001:2016 CERTIFIED INSTITUTE HINDUPUR-515201
DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING
BATCH NO: 3
Title: Design and Simulation of self repairable multiplexer
for fault tolerant systems using CMOS 45nm technology
Presented By:
K. Chetan Kumar (17F31A0407)
B. Nikhil Vashista (17F31A0428)
K. Rajababu (17F31A0431)
V. Sirisha (18F35A0404)
Guide:
Dr. SivaKumar.M, M.tech, phD
Associate Professor
Dept. of ECE
ABSTRACT
 Using VLSI more number of transistors can be
embedded on a single chip. As the space between
transistors or circuits decreasing the system or chip is
more susceptible to faults.
 Fault tolerant systems required to avoid inaccurate
results. Multiplexer is a device which selects input
signals based on select signal. The existing papers deal
with only self-checking multiplexer. In this paper a selfrepairing 2:1 multiplexer which can repair permanent
and transient faults is proposed.
 Two different architectures are proposed for selfrepairing multiplexer. First architecture is having
additional circuitry to repair the fault in
multiplexer.
 In second architecture the building blocks of
multiplexer like OR and AND gates itself are selfrepairable. These self-repairing multiplexer
architectures can detect and repair the single
and multiple faults. The proposed architectures
give 100% error recovery.
 The circuits are simulated using Mentor graphics
45nm tool and verified the functionality.
INTRODUCTION
 The simulation of the system may be inaccurate due to the
faulty occurrence. This may lead to improper results. So the
fault free architectures are very useful to suspect the faults.
 So for the exact operation of system the self repairing and
checking are needed. The circuit which detect the fault by
itself is known as self checking system.
 The circuit which produces correct output by repairing itself
is known as self repairing system. The performance of the
system depends upon the gates used in the design of circuit.
 The performance of proposed design can increase in terms of
power , PDP and delay by using limited gates.
EXISTING SYSTEM
In existing model, the full adder which consists of
AND, OR gates and 2X1 MUX are designed with
the 65nm technology.
In existing method the factors in terms of power,
delay, power delay product (PDP) are optimized
in high speed and average power consumed is
very high and power delay product is more, the
noise margin is high and other factors like drive
capability are more.
PROPOSED SYSTEM
 In order to resolve the issues which we are facing in
the existing methodology, we are proposing a model
using 45nm technology.
 It's mean that the minimum length of the transistor is
45nm.
 During the fabrication all second order effect are
considered regarding the particular fabricated
technology.
 It is used for reducing the current leakage within
transistors. Another prominent change in the design of
45 nm technology was the introduction of metal gates
Designing of AND gate
 When there is fault in the AND gate
which output is ‘y’, then f will
become logic 1 and circuit gives
output Op as inverted value of y.
 Similarly when there is no fault, then
f will give logic 0 and the circuit
output Op as the value of y.
A
0
0
1
1
Fig 1 : Faulty AND Gate
B
0
1
0
1
Y
1
1
1
1
F
1
1
1
0
O/P
0
0
0
1
Table 1 : Fault rectified AND Gate Truth Table
Fig 2 : Schematic Of Faulty AND Gate
The above figure shows the schematic of faulty AND gate which is combinations of
number of PMOS and NMOS logic is designed in 45nm technology .It is designed
with tanner S-EDIT Tool.
Fig 3 :Simulation Of Faulty And Gate
The above figure shows the simulation results of fault AND gate .It is simulated using
CMOS Tanner-SPICE (Simulation Program with Integrated Circuit Emphasis) Tool. Wave
forms are analyzed using W-EDIT(wave form editor).
FIG 4: Power Analysis Of AND GATE
FIG 5 : Delay Analysis Of AND GATE
FIG 6: PDP Analysis Of AND GATE
Designing of OR gate
 When there is fault in the OR
gate which output is ‘y’, then f
will become logic 1 and circuit
gives output Op as inverted
value of y.
 Similarly when there is no fault,
then f will give logic 0 and circuit
output Op as the value of y.
A
0
0
1
1
Fig 7 : Faulty OR Gate
B
0
1
0
1
Y
1
1
1
1
F
1
0
0
0
O/P
0
1
1
1
Table 2 : Fault rectified OR Gate Truth Table
Fig 8 : Schematic Of Faulty Or Gate
The above figure shows the schematic of faulty OR gate which is combinations of
number of PMOS and NMOS logic is designed in 45nm technology .It is designed with
tanner S-EDIT Tool.
Fig 9 : Simulation Of Faulty OR Gate
The above figure shows the simulation results of fault OR gate .It is simulated using CMOS
Tanner-SPICE (Simulation Program with Integrated Circuit Emphasis) Tool.Wave forms are
analyzed using W-EDIT(wave form editor).
FIG 10 : Power Analysis Of OR GATE
FIG 11 : Delay Analysis Of OR GATE
FIG 11 : PDP Analysis Of OR GATE
Designing of 2X1 Multiplexer
the circuit enclosed in square box shows
the basic structure of 2:1 multiplexer.
Remaining structure which is not
included in the square box is used for
repairing the above 2:1 multiplexer. The
circuit is able to detect all possible single
and multiple faults present in the 2:1
multiplexer and repairs the circuit. The
circuit gives 100% error recovery.
Fig 12 : Faulty 2x1 Multiplexer
 Assume there is a stuck at ‘1’ fault at y. Since y was stuck at ‘1’, it
will give always ‘1’ as the output. However when this value is
passed to repairing circuit, it detects the fault and produces
correct output.
 So when there is fault in multiplexer block, then output Op gives
the inverted value of y. If there is no fault, then y value is passed
to the output Op.
A
B
S
S
bar
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
Y O/P
A
B
S
S
bar
Y
O/P
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
Table 3.1 : 2X1 MUX Truth Table for
selection line ‘0’
0
0
1
1
Table 3.2 : 2X1 MUX Truth Table for
selection line ‘1’
Fig 13 : Schematic Of Faulty 2X1 MUX
Fig 14 : Simulation Of Faulty 2X1 Mux
FIG 15 : Power Analysis Of 2X1 MUX
FIG 16 : Delay Analysis Of 2X1 MUX
FIG 17 : PDP Analysis Of 2X1 MUX
Designing of Full Adder
 At the output of sum, the
VDD is connected so the
result is fault but the final
output of full adder is fault
free.
 The fault circuit is designed
to work under the fault
condition. The concept of
stuck at 1 is applied to
output sum and the output
obtained is a fault output.
 Even though fault occur it
rectifies the fault and sample
output is obtained.
Fig 18 : Faulty Sum Full Adder
 At the output of sum, the VDD is connected so the result is fault
but the final output of full adder is fault free.
 The fault circuit is designed to work under the fault condition.
The concept of stuck at 1 is applied to output sum and the
output obtained is a fault output.
 Even though fault occur it rectifies the fault and sample output
is obtained.
A
B
C
Sum
Fs
Cout
Fc
0
0
0
0
1
0
1
0
0
1
1
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
Table 4 : Full Adder Truth Table
Fig 19 : Schematic Of Faulty Sum Full Adder
Fig 20 : Simulation Of Faulty Sum Full Adder
FIG 21 : Power Analysis Of Sum Full Adder
FIG 22 : Delay Analysis Of Sum Full Adder
FIG 23 : PDP Analysis Of Sum Full Adder
Resultant Graphs
VOLTAGE(V) VS POWER(W)
8
POWER(W)
7
Rani
6
AND
5
4
FS
3
FC
2
OR
1
MUX
0
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
VOLTAGE(V)
Fig 24 : Simulation Results Of Full Adder ,Power Vs Vdd
VOLTAGE(V) VS DELAY(NS)
DELAY(NS)
250
200
Rani
150
AND
FS
100
FC
50
OR
MUX
0
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
VOLTAGE(V)
Fig 25 : Simulation Results Of Full Adder ,Delay Vs Vdd
1,8
2
VOLTAGE(V) VS PDP
1600
Rani
1400
AND
PDP
1200
FS
1000
FC
800
OR
600
MUX
400
200
0
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
VOLTAGE(V)
Fig 26 : Simulation Results Of Full Adder ,PDP Vs Vdd
Existing technology with 65nm
Power
(W)
AND
FC
FS
OR
MUX
4.57
5.58
5.58
9.85
90.92
Delay
(ns)
150.65
120.8
120.8
250.13
70.87
Proposed technology with 45nm
PDP
688.47
674.06
674.06
2463.78
6443.50
Power
(W)
1.33
1.59
1.59
7.22
1.36
Delay
(ns)
100.17
100.73
100.73
200.17
50.53
PDP
133.22
160.16
160.16
1445.22
68.72
Table 5 : Comparison Of Power, Delay, PDP With Existing And Proposed Technology.
CONCLUSION
In many systems ,the full adder is the building block ,so the faults in full adder may
lead to inappropriate simulation results. The faults occurred may be stuck at
‘1’,stuck at ‘0’, or may be bridge faults. In order to identify the fault or error in
circuit we need to verify each and every block to identify whether error or fault
occurred. So to decrease the complexity of circuit and to identify error once after
the design of circuit is completed .Fault free system of full adder is needed in
order to provide valid results. The proposed full adders are mainly used in
arithmetic operations ,microprocessors and digital signal processors etc...To get
100% error recovery the proposed full adder with self repairing fault free should be
used. The proposed full adder with no external inputs ,itself repair the fault. The
systems are evaluated and examined and the outputs .The proposed fault free full
adder circuit is verified.
FUTURE SCOPE
The need for low power design is also becoming a major issue in highperformance digital systems, such as microprocessors, digital signal processors
(DSPs) and other applications. Increasing chip density and higher operating
speed lead to the design of very complex chips with high clock frequencies.
Low power design is also required to reduce the power in high-end systems
with huge integration density and thus improve the speed of operation.
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