ELE 5209
COMPUTER ENGINEERING 3
Prof N. Magaji
SYLLABUS
Arithmetic Logic Unit: Construction and design. Binary adders and
design. Carry look -ahead and booth algorithm. Error detection and
correction codes. Parity checks. Minimum distance. Code distance.
Hamming code. Introduction to microprocessors.
Memories: memory hierarchy and access. ROMS, PROMS and
EPROMS. RAMS. Memory expansion and organization. Magnetic bubble
memories (MBMs). Magnetic surface storage devices. Special memories
and applications.
Interfacing and Data Transmission: interfacing logic families.
Interfacing with Buses. Interfacing digital and analog systems. Modems
and interfaces. The Schmitt trigger as an interface circuit.
Prof. Nuraddeen Magaji
Bayero University ,Kano
2019
ADDER CIRCUIT
Prof. N. Magaji ELE5209
The half adder adds two binary digits called as
augend and addend and produces two outputs
A
asHalf
sumAdder
and carry;A B
A
S  A B
B
Cout
Cout  A.B
B
S
B
S
C
A
0
0
1
1
B
0
1
0
1
C
0
0
0
1
S
A
0
1
1
0
2
ADDER CIRCUIT
Prof. N. Magaji ELE5209
The full-adder circuit adds three one-bit binary numbers (C A
B) and outputs two one-bit binary numbers, a sum (S) and a
A
B C
Cout S
carry (C1).
A
B
Full Adder
S  A B C
Cout  MAJ ( A, B, C )
Cout
C
S
Describing binary
summation of three onebit inputs Three inputs
and two outputs
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
X=A , Y=B C=Cn and
Cn+1=Cn
3
Prof. N. Magaji ELE5209
n-bit Adder
n
Problem with Half adder circuit
is that there is no way to
combine a sequence of adders
together
 the carry of one addition must
be passed to the next.
 Need a structure as:
carryin
a
b
r
carryout
Link 1-bit adders for n-bit
carryin
CarryIn0
A0
Prof. N. Magaji ELE5209
a
r0
b
A1
carryout/carry in
B1
A2
B2
r1
1-bit
Result1
ALU
CarryIn2 CarryOut1
1-bit
Result2
ALU
CarryIn3 CarryOut2
A3
1-bit
ALU
B3
a
b
B0
1-bit
Result0
ALU
CarryIn1 CarryOut0
CarryOut3
carryout
2 bit adder
A chain of 1-bit adders is formed
where the carryout of each becomes the carryin of the next.
The result is the sequence of results from LSB to MSB.
Note: we'll just build a 1 bit ALUand use 32
of them and 2 bit
Result3
Prof. N. Magaji ELE5209
An ALU (arithmetic logic unit)
ALU should be able to perform the following
operation
functions:
– logical and function
a
32
– logical or function
ALU
result
–arithmetic add function
32
b
–arithmetic subtract function
32
–arithmetic slt(set-less-then ) function
ALU Symbol
– logical nor function
• ALU control lines define a function to be performed on A and B.
1-bit ALU: ANDs, ORs, ADDs, and Compares a
or ~a, b or ~b
6
Prof. N. Magaji ELE5209
1-bit ALU for
the Most Significant Bit
The four operations—add,
subtract, AND, OR—are
found in the ALU of almost
every computer, and the
operations of most instructions
can be performed by this ALU.
But the design of the ALU is
incomplete.
One instruction that still needs
support is the a comparison
function:
set on less than (slt).
Prof. N. Magaji ELE5209
A 32-bit ALU
Constructed from
31 copies of the
4-function
1-bit ALU
and one special
4-function
1-bit ALU
for the MSB
Prof. N. Magaji ELE5209
The values of the three ALU
control lines Bnegate and Operation
and the
corresponding ALU operations
9
Problem: ripple carry adder is
slow
Prof. N. Magaji ELE5209
n
n
Is a 32-bit ALU as fast as a 1-bit ALU?
Is there more than one way to do addition?
u two extremes: ripple carry and sum-of-products
Can you see the ripple? How could you get rid of it?
c1
c2
c3
c4
=
=
=
=
b0c0
b1c1
b2c2
b3c3
+
+
+
+
a0c0
a1c1
a2c2
a3c3
+
+
+
+
a0b0
a1b1
a2b2
a3b3
c2 =
c3 =
c4 =
Not feasible! Why?
10
Carry-lookahead adder
Prof. N. Magaji ELE5209
n
n
n
c1
c2
c3
c4
An approach in-between our two extremes
Motivation:
u If we didn't know the value of carry-in, what could we do?
u When would we always generate a carry?
gi = ai bi
u When would we propagate the carry?
pi = ai + bi
Did we get rid of the ripple?
=
=
=
=
g0
g1
g2
g3
+
+
+
+
p0c0
p1c1
p2c2
p3c3
c2 =
c3 =
c4 =
Feasible! Why?
11
Multiplication
n
Prof. N. Magaji ELE5209
n
n
n
More complicated than addition
u accomplished via shifting and addition
More time and more area
Let's look at 3 versions based on grade school algorithm
0010
x_1011
(multiplicand)
(multiplier)
Negative numbers: convert and multiply
u there are better techniques, we won’t look at them
12
Prof. N. Magaji ELE5209
Multiplication: Implementation:
1st Version
13
Multiplication: Implementation:
Version
nd
2
Start
Prof. N. Magaji ELE5209
n
n
Multiplier = 32 bits, Multiplicand = 32 bits
Multiplier0 = 1
Product = 64 bits.
Product is 64 bit Zero
1. Test
Multiplier0
Multiplier0 = 0
1a. Add multiplicand to the left half of
the product and place the result in
the left half of the Product register
Multiplicand
2. Shift the Product register right 1 bit
32 bits
3. Shift the Multiplier register right 1 bit
Multiplier
Shift right
32-bit ALU
32 bits
Product
64 bits
Shift right
Write
32nd repetition?
No: < 32 repetitions
Control test
Yes: 32 repetitions
Done
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Multiplication: Implementation:
2nd Version(Add & Shift)
Prof. N. Magaji ELE5209
Multiplicand x Multiplier: 2ten x 3ten = 0010two x 0011two = 0110two
Iteration
Step
Multiplier Multiplicand Product
0
Initial values
0011
0010
0000 0000
1
1a: 1 => Prod = Prod + Mcand
0011
0010
0010 0000
2: Shift right Product
0011
0010
0001 0000
3: Shift right Multiplier
0001
0010
0001 0000
2
1a: 1 => Prod = Prod + Mcand
0001
0010
0011 0000
2: Shift right Product
0001
0010
0001 1000
3: Shift right Multiplier
0000
0010
0001 1000
3
1: 0 => no operation
0000
0010
0001 1000
2: Shift right Product
0000
0010
0000 1100
3: Shift right Multiplier
0000
0010
0000 1100
4
1: 0 => no operation
0000
0010
0000 1100
2: Shift right Product
0000
0010
0000 0110
3: Shift right Multiplier
0000
0010
0000 0110
Problem with 2nd Version: Half of product is always = 0!
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Multiplication: Implementation:
Booth’s Algorithm Final Version
n
Prof. N. Magaji ELE5209
n
Multiplier = 32 bits, Multiplicand = 32 bits
Product = 64 bits.
Initially add Multiplier to Right half of Product
i.e LeftProduct = 0, rightProduct = Multiplier
Multiplicand
32 bits
32-bit ALU
Product
Shift right
Write
Control
test
64 bits
16
Example of Booth’s Algorithm
n
3*7
First setup the columns and initial values.
n
This case 3 is in Q and M is 7.
Prof. N. Magaji ELE5209
n
u
But could put 7 in Q and M as 3
Example of Booth’s Algorithm
Prof. N. Magaji ELE5209
First cycle: Now look at Q0 and Q-1
With a 10, we Sub (A=A-M), then shift (always to the right)
Second cycle: looking at Q0 and Q-1
With a 11, we only shift.
Example of Booth’s Algorithm
Prof. N. Magaji ELE5209
2nd cycle Result
Third cycle, Q0 and Q-1 have 01
So we will Add (A=A+M), then shift
Example of Booth’s Algorithm
Prof. N. Magaji ELE5209
3nd cycle Result
4th cycle, Q0 and Q-1 have 00
So we only shift
Example of Booth’s Algorithm
Prof. N. Magaji ELE5209
4nd cycle Result
5th cycle, Q0 and Q-1 have 00
So we only shift
Example of Booth’s Algorithm
Prof. N. Magaji ELE5209
5th cycle Result
Since we are working in 5 bits, we only repeat 5 times
Prof. N. Magaji ELE5209
Example of Booth’s Algorithm
Result is A and Q so 0000010101 which is 21.
Note: The sign bit is the last bit in A.
Prof. N. Magaji ELE5209
Multiplication:
Shift of 7*3=21)
nd
2
Version(Add &
Multiplicand x Multiplier:7 x 3 = 00011x 00111 = 10101
Iteration
0
1
2
3
4
5
Step
Initial values
1a: 1 => Prod = Prod + Mcand
2: Shift left Multiplicand
3: Shift right Multiplier
1a: 1 => Prod = Prod + Mcand
2: Shift left Multiplicand
3: Shift right Multiplier
1: 0 => no operation
2: Shift left Multiplicand
3: Shift right Multiplier
1: 0 => no operation
2: Shift left Multiplicand
3: Shift right Multiplier
1: 0 => no operation
2: Shift left Multiplicand
3: Shift right Multiplier
Multiplier Multiplicand
Product
00011 00000 00111 0000 000000
00011 00000 00111 00000 00111
00011
0000 01110 00000 00111
00010
0000 01110 00000 00111
00010
0000 01110 0000010101
00010
0000 11100 0000010101
00000
0000 11100 0000010101
00000
0000 11100 0000010101
00000
000111000 0000010101
00000
000111000 0000010101
00000
000111000 0000010101
00000
001110000 0000010101
00000
001110000 0000010101
00000
000111000 0000010101
00000
011100000 0000010101
00000
011100000 0000010101
Chapter 1
Lecture 2
Prof. N. Magaji ELE5209
Arithmetic Logic Unit , takes the data from Memory registers.
Errors arise from overflow ,overflowing the signfic and and
overflowing the exponent
What causes an overflow error?
overflow error. An error that occurs when the computer attempts to
handle a number that is too large for it. Every computer has a welldefined range of values that it can represent. If during execution of a
program it arrives at a number outside this range, it will experience
an overflow error.
What is data overflow error ?
An overflow error that is created by storage assignment is referenced as
a data type overflow. ... If a data type is a single byte, and the data to be
stored is greater than 256 then there is an overflow error generated and
the program crashes because it has corrupted data
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15-Jul-19
Data Representation
What are three popular coding systems to represent
data?
Prof. N. Magaji ELE5209
ASCII—American
Standard Code for Information Interchange
used in just about every other computer

EBCDIC—Extended Binary Coded Decimal Interchange Code
– developed for the IBM 360 and used in all IBM mainframes since then
An 8-bit representation for 256 characters

Unicode—coding scheme capable of representing all world’s languages
ASCII
Symbol
00110000
00110001
00110010
00110011
0
1
2
3
EBCDIC
11110000
11110001
11110010
11110011
Prof. N. Magaji ELE5209
Types of errors
If a signal is carrying binary encoded data, such changes can alter the
meaning of the data. These errors can be divided into two types: Singlebit error and Burst error.
Single-bit Error
The term single-bit error means that only one bit of given data unit (such
as a byte, character, or data unit) is changed from 1 to 0 or from 0 to 1
as shown in Fig. 1.2.
Figure 1.2 Single bit error
Burst Error
The term burst error means that two or more bits in the data unit have
changed from 0 to 1 or vice-versa
Typical Example.
Example: Transmit: Come to my house at 17:25 …
Receive: Come tc my houzx at 14:25
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Types of errors
Prof. N. Magaji ELE5209
Burst Error
The term burst error means that two or more bits in the data unit have
changed from 0 to 1 or vice-versa
Figure 1.2 Burst Error
Burst errors are mostly likely to happen in serial transmission.
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Prof. N. Magaji ELE5209
Error Detection and Correction
Detection
Basic approach used for error detection is the use of
redundancy, where additional bits are added to facilitate
detection and correction of errors. Popular techniques are:
 Checksum
 Cyclic redundancy check
 Simple Parity check
 Two-dimensional Parity check
Error detection and correction is critical to accurate data
transmission, storage and retrieval.

Checksum: Bits are appended to every block that somehow encode


the information
Cyclic redundancy(CRC): CRC check Blocks of data entering the system,
based on the remainder of a polynomial division of their contents
A parity bit, or check bit, is a bit added to a string of binary code to ensure that
the total number of 1-bits in the string is even or odd.
Prof. N. Magaji ELE5209
Error Detection
A parity bit(cont,)
Add up the number of 1 bits in the byte, add a bit so that the number of
total 1s is even
00101011 has a parity bit of 0, 11100011 has a parity bit of 1
With more parity bits, we can not only detect an error, but correct it, or
detect 2 errors
Hamming Codes are a common way to provide high redundancy on
error checking
Checksums and CRCs are examples of systematic error detection.
In systematic error detection a group of error control bits is appended to
the end of the block of transmitted data.
This group of bits is called a syndrome.
Data transmission errors are easy to fix once an error is detected.
Just ask the sender to transmit the data again.
In computer memory and data storage, however, this cannot be done.
Too often the only copy of something important is in memory or on disk.
Thus, to provide data integrity over the long term, error correcting
codes are required
Prof. N. Magaji ELE5209
Error Correction
BINARY ERROR CORRECTING CODES: (ECC)
• 2k equally likely messages can be represented by k binary digits.
• If these k digits are not coded, an error in one or more of the k binary
digits will result in the wrong message being received.
• Error correcting codes is a technique whereby more than the minimum
number of binary digits are used to represent the messages.
• The aim of the extra digits, called redundant or parity digits, is to detect
and hopefully correct any errors that occurred in transmission
Types of Correction
Binary Codes :
Encoder and decoder works on a bit basis.
• Nonbinary Codes , Encoder and decoder works on a byte or symbol
basis.; Bytes usually are 8 bits but can be any number of bits.
– Galois field arithmetic is used.
– Example is a Reed Solomon Code
Prof. N. Magaji ELE5209
Error Correction(Hamming codes )
Block code example:
Information
Codeword
00
000101
01
010010
10
101101
11
111010
HAMMING BINARY BLOCK CODE WITH k=4 AND n=7
In general, a block code with k information digits and block length n is
called an (n,k) code.
Thus, this example is called an (7,4) code.
What is Hamming distance give an example?
Thus the Hamming distance between two vectors is the number of bits we
must change to change one into the other.
Example 1 Find the distance between the vectors [01101010] and
[11011011]. They differ in four places, so the Hamming
distance d(01101010,11011011) = 4.
All that we need to know is modulo 2 addition, ⊕:
0 ⊕ 0 = 0, 1 ⊕ 0 = 1, 0 ⊕ 1 = 1, 1 ⊕ 1 = 0.
Prof. N. Magaji ELE5209
Error Correction(Hamming codes )
Prof. N. Magaji ELE5209
Error Correction(Hamming codes )
Prof. N. Magaji ELE5209
Error Correction(Hamming codes )
Prof. N. Magaji ELE5209
Prof. N. Magaji ELE5209
Questions
Q1 (a)Why do you need error detection?
Ans: As the signal is transmitted through a media, the signal gets
corrupted because of noise and distortion. In other words, the
media is not reliable. To achieve a reliable communication through
this unreliable media, there is need for detecting the error in the
signal so that suitable mechanism can be devised to take
corrective actions.
Q1(b) Explain different types of Errors?
Ans: The errors can be divided into two types: Single-bit error and
Burst error.
Single-bit Error
The term single-bit error means that only one bit of given data unit (such
as a byte, character, or data unit) is changed from 1 to 0 or from 0 to 1.
Burst Error
The term burst error means that two or more bits in the data unit have
changed from 0 to 1 or vice-versa. Note that burst error doesn’t
necessary means that error occurs in consecutive bits
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Prof. N. Magaji ELE5209
Definations
Block length: 2ʳ − 1 where r ≥ 2
The codeword length is n. n has the form 2m – 1
The message length of the code is n – m.
H=m-by-n parity-check matrix
G=Generation matrix is m by n also
For linear block code(n,k,d)
m=n-k; k= 2m – m-1 and n= 2m – 1; d= minimum hamming
distance
Hamming(7,4) is a linear error-correcting code that encodes
four bits of data into seven bits by adding three parity bits.
Condition for hamming
m=n-k; k= 2m – m-1 and n= 2m – 1;
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Prof. N. Magaji ELE5209
Questions
Q2 (a) Explain the use of parity check for error detection?
Ans: In the Parity Check error detection scheme, a parity bit is
added to the end of a block of data. The value of the bit is selected
so that the character has an even number of 1s (even parity) or an
odd number of 1s (odd parity). For odd parity check, the receiver
examines the received character and if the total number of 1s is
odd, then it assumes that no error has occurred. If any one bit (or
any odd number of bits) is erroneously inverted during
transmission, then the receiver will detect an error.
(b) What are the different types of errors detected by parity check?
Ans: If one bit (or odd number of bits) gets inverted during
transmission, then parity check will detect an error. In other words,
only odd numbers of errors are detected by parity check. But, if
two (or even number) of bits get inverted, and then the error
remains undetected.
39
Prof. N. Magaji ELE5209
Questions
Q3 Suppose that C is a linear (7, 2, 5) code over Z13. Answer the following
questions about C. (Recall that a linear code is (n, k, d) if n is the word
length, k is the dimension, and d is the minimum distance.)
(a) What is |C|? (That is, how many code words are there?)
(b) What is the size of a generator matrix for C?
(c) What is the size of a parity check matrix for C?
(d) How many error’s can C detect?
(e) How many error’s can C correct?
Solution. (a) |C|= 132 = 169.
(b) A generator matrix G has size 2 by 7.(k by n)
(c) A parity check matrix H has size 5 by 7.(d by k)
(d) Since d = 5, C can detect d -1 = 4 errors.
(e) Since d = 5, C can correct (d -1)/2 = 2 errors.
40
Questions(cont.)
Prof. N. Magaji ELE5209
Q4
Consider a (6,3) linear block code defined by the generator matrix
(a) Determine if the code is a Hamming code. Find the parity check matrix
H of the code in systematic form.
(b) Find the encoding table for the linear block code.
(c) What is the minimum distance dmin of the code. How many errors can the code
detect. How many errors can the code correct.
(d) Draw the hardware encoder diagram.
(e) Find the decoding table for the linear block code.
(f) Draw the hardware syndrome generator diagram.
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Prof. N. Magaji ELE5209
Questions(cont.)
Q5
Complete Solution
(a) Testing for hamming code, we have
m = n−k = 6−3 = 3
k = 2m−m−1 = 23−3−1 = 4 not= 3
n = 2m−1 = 23−1 = 7 6= 6
Hence (6,3) is not a Hamming code.
42
Questions(cont.)
Prof. N. Magaji ELE5209
Q5(b) cont.
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Prof. N. Magaji ELE5209
Questions(cont.)
44
Prof. N. Magaji ELE5209
Questions(cont.)
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Prof. N. Magaji ELE5209
Questions(cont.)
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Prof. N. Magaji ELE5209
Questions(cont.)
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