BLESSINGBENZE B.S
3122224004002
ExNo:1(a)
Date:
SINGLE STAGE AMPLIFIERS - COMMON SOURCE
AIM:
To design Common Source circuit using 90nm technology and to perform its
pre-layout simulation.
SOFTWARE REQUIRED:
Cadence
virtuoso
THEORY:
The common-source (CS) amplifier may be viewed as a transconductanceamplifier or
as a voltage amplifier. As a transconductance amplifier, the input voltage is seen as
modulating the current going to the load. As a voltage amplifier,input voltage modulates
the amount of current flowing through the FET, changing the voltage across the output
resistance according to ohm’s law. However, the FET device's output resistance
typically is not high enough for a reasonable transconductance amplifier (ideally
infinite), nor low enough for a decent voltageamplifier (ideally zero).
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BLESSINGBENZE B.S
3122224004002
SCHEMATIC:
PRE-LAYOUT SIMULATION:
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BLESSINGBENZE B.S
3122224004002
RESULT:
Thus, the common source using 90nm technology was designed and its prelayout simulation was performed.
3
BLESSINGBENZE B.S
3122224004002
ExNo:1(b)
Date:
SINGLE STAGE AMPLIFIER - COMMON GATE
AIM:
To design Common Gate circuit using 90nm technology and to perform
SOFTWARE REQUIRED:
Cadence virtuoso
THEORY:
COMMON GATE:
The common-gate amplifier is one of three basic single-stage field-effect
transistor (FET) amplifier topologies, typically used as a current buffer or voltage
amplifier. In this circuit the source terminal of the transistor serves as the input, the drain
is the output and the gate is connected to ground, or "common," hence its name. The
analogous bipolar junction transistor circuit is the common-base amplifier.
SCHEMATIC:
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BLESSINGBENZE B.S
3122224004002
PRE LAYOUT SIMULATION:
RESULT:
Thus, the common gate using 90nm technology was designed and its prelayout simulation was performed.
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BLESSINGBENZE B.S
3122224004002
Ex No:1(c)
Date:
SINGLE STAGE AMPLIFIER -SOURCE FOLLOWER
AIM:
To design Source Follower circuit using 90nm technology and to perform
its pre-layout simulation. SOFTWARE
REQUIRED:
Cadence virtuoso
THEORY:
SOURCE FOLLOWER:
The common source follower circuit is used to drive a low-impedance load. A buffer
must be placed after the amplifier so as to drive the load with negligibleloss of the signal
level. The source follower (common drain) can operate as a voltage follower. The source
follower senses the signal at the gate and drives theload at the source, allowing the
source potential to “follow” the gate voltage.
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BLESSINGBENZE B.S
3122224004002
SCHEMATIC:
PRE-LAYOUT SIMULATION:
RESULT:
Thus, the source follower using 90nm technology was designed and its prelayout simulation was performed.
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BLESSINGBENZE B.S
3122224004002
Ex No: 2
Date:
CASCODE AMPLIFIER
AIM:
To design Cascode Amplifier and to perform Transient Analysis.
SOFTWARE REQUIRED:
Cadence virtuoso
THEORY:
The cascode amplifier consists of common source (CS) and common gate (CG)
configuration to achieve higher gain. The analysis and design of cascode amplifier hence
will start with the MOS device physics, analysis and design CS stage.
SCHEMATIC:
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BLESSINGBENZE B.S
3122224004002
PRE-LAYOUT SIMULATION:
RESULT:
Thus, the cascode amplifier was designed and transient analysis was performed.
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BLESSINGBENZE B.S
3122224004002
Ex No: 3
Date:
CURRENT MIRROR
AIM:
To design a current mirror circuit and to perform its pre-layout simulations using 90nm
technology.
SOFTWARE REQUIRED:
Cadence virtuoso.
THEORY:
CURRENT MIRROR:
A current mirror is a circuit designed to copy a current through one active device by
controlling the current in another active device of a circuit, keeping the output current
constant regardless of loading. The current being "copied" can be, and sometimes is, a
varying signal current.
SCHEMATIC:
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BLESSINGBENZE B.S
3122224004002
PRE-LAYOUT SIMULATION:
RESULT:
Thus, the current mirror circuit is designed and its pre-layout simulations are performed
using 90nm technology.
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BLESSINGBENZE B.S
3122224004002
Ex No: 4
Date:
DIFFERENTIAL AMPLIFIER WITH MOS LOADS
AIM:
To draw the Schematic of Differential Amplifiers and to perform Pre-Layout
simulation for 90nm technology.
SOFTWARE REQUIRED:
Cadence virtuoso.
THEORY:
A differential amplifier is a circuit whose output voltage is directly proportional to the
difference between voltages applied at it’s to inputs. Ideally, this amplification of voltage
difference is useful in eliminating noise signal which is common to both the inputs i.e., a
Common Mode Rejection Ratio of infinity. A typical CMOS differential amplifier circuit is
shown below in the Circuit Diagram. All MOSFETs are in saturation. Also, we can see
from the circuit that MOSFETs 3 and 4 act as a current mirror, hence are of the equal
dimensions. That’s the case with MOSFETs 5 and 6. For simplicity, let’s assume that
MOSFETs 1 and 2 are of equal dimensions too. The output Vout is taken across the load
capacitor C and is proportional to (Vin1 — Vin2).
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BLESSINGBENZE B.S
3122224004002
SCHEMATIC:
PRE-LAYOUT SIMULATION:
RESULT:
The schematic of the differential amplifier was drawn, the widths of the
MOSFETs were calculated and Pre-Layout simulation was done for 90nm process
technology.
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BLESSINGBENZE B.S
3122224004002
Ex No:5
Date:
VOLTAGE REFERENCE
AIM:
To design voltage reference circuits using 90nm CMOS technology and perform its
pre-layout simulation.
SOFTWARE REQUIRED:
Cadence virtuoso.
VOLTAGE REFERENCE:
THEORY:
A voltage reference is an electronic component or circuit that produces a constant DC
(direct-current) output voltage regardless of variations in external conditions such as
temperature, barometric pressure, humidity, current demand, or the passage of time.
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BLESSINGBENZE B.S
3122224004002
SCHEMATIC:
REFERENCE VOLTAGE:
RESULT:
Thus, the voltage reference using 90nm technology was designed and its prelayout simulation was performed.
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BLESSINGBENZE B.S
3122224004002
Ex No:6
Date:
GILBERT CELL
AIM:
To draw the Schematic of Gilbert Cell and to perform Pre-Layout simulation for 90nm
process technology.
SOFTWARE REQUIRED:
Cadence virtuoso.
THEORY:
The mixer is an essential block in any telecommunication system which has a critical
impact on the performances of all system functions. It is an analog multiplier, as shown in
Block Diagram, which allows a time multiplication of two signals, the first one (RF signal)
comes from the receiver antenna after it has been filtered and amplified, and the other
signal (LO signal) comes from a local oscillator.
Gilbert cell circuit diagram:
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BLESSINGBENZE B.S
3122224004002
The Gilbert Cell is composed of three differential pairs (M2, M3), (M4, M5) and (M6, M7)
each is composed of two identical transistors, all connected to a current source based on tail
transistor M1 The RF pair (M2, M3) provides the gain. It consists of two common-source
transistors, M2 and M3 that convert the differential input voltage in differential current.
The range of differential voltage Vid, for which the two transistors (M2, M3) are active at
the same time, depends on both the geometrical dimensions (W, L) and the generated
current IG through transistor M1. The currents I2, and I3 are then routed to two differential
pairs (M4, M5) and (M6, M7) controlled by a strong LO signal so that they operate in
switching mode [6]. Such a commutation block is the core of the circuit where RF and LO
signals are mixed. Finally, the total current I0 is converted into a voltage output IF (Vo1 Vo2) by a load (Rload). The width of input RF transistors block is determined, using a
technique based on the minimum noise to obtain optimal size of the width that is expressed
by
which for a 30GHz frequency comes out to be around 90nm. Owing to limitations in width,
assuming W = 30nm, generally for optimized performance the widths of the local oscillator
differential pairs and RF transistor block are kept the same. The width of the tail transistor
is calculated in such a way that Vds,sat is accommodated and it is calculated to be 3um.
SCHEMATIC
:
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BLESSINGBENZE B.S
3122224004002
PRE- LAYOUT SIMULATION:
RESULT:
The schematic of the Gilbert Cell was drawn, MOSFET widths were calculated
and Pre-Layout simulation was done for 90nm technology.
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