Name:Abhishek Shrivastav
Id:2022H1230192H
VLSI ASSIGNMENT
Objective:
To calculate the average of 7 numbers and 8 numbers and to compare the hardware
utilization and complexity for calculating the average of even numbers and odd
numbers
Computing average for 7 numbers:
Code:
`timescale 1ns / 1ps
module avg(a,b,c,d,e,f,g,z);
input [3:0]a,b,c,d,e,f,g;
parameter
N=7;
reg [N-1:0]sum;
output reg [N-1:0]z=7'b0000000;
reg [N-1:0]acc=7'b0000000;
reg [N-1:0]sum1;
reg [2:0]i;
always@(*)
begin
sum=a+b+c+d+e+f+g;
z=4'b0000;
acc=7'b0000000;
for(i=0;i<N;i=i+1)
begin
{acc,sum}={acc,sum}<<1;
z=z<<1;
if(acc>=N)
Name:Abhishek Shrivastav
Id:2022H1230192H
begin
acc=acc-N;
z=z+1;
end
end
end
endmodule
TESTBENCH:
//`timescale 1ns / 1ps
module tb_average();
reg [3:0]a,b,c,d,e,f,g;
wire [6:0]z;
avg a1(a,b,c,d,e,f,g,z);
initial
begin
a=4'b1010;b=4'b1010;c=4'b1100;d=4'b1010;e=4'b1010;f=4'b1100;g=4'b0101;
#10 a=4'b1110;b=4'b1110;c=4'b1100;d=4'b1010;e=4'b1110;f=4'b1100;g=4'b0101;
#10 a=4'b1111;b=4'b1111;c=4'b1101;d=4'b1110;e=4'b1111;f=4'b1101;g=4'b1111;
#10 a=4'b1111;b=4'b1111;c=4'b1111;d=4'b1111;e=4'b1111;f=4'b1111;g=4'b1111;
#50 $finish;
end
endmodule
Name:Abhishek Shrivastav
SIMULATION WAVEFORM:
RTL DESIGN:
Id:2022H1230192H
Name:Abhishek Shrivastav
Computing average for 8 numbers:
`timescale 1ns / 1ps
module average(a,b,c,d,e,f,g,h,z);
input [3:0]a,b,c,d,e,f,g,h;
output reg [7:0]z;
parameter
N=8;
reg [6:0]sum;
reg [6:0]sum1;
reg [6:0]sum2;
reg [6:0]sum3;
reg i;
always@(*)
begin
sum=a+b+c+d+e+f+g+h;
if(sum<8)
z=sum;
else if(sum>8)
begin
sum1=sum>>1;
sum2=sum1>>1;
sum3=sum2>>1;
z=sum3;
end
end
endmodule
Id:2022H1230192H
Name:Abhishek Shrivastav
Id:2022H1230192H
TESTBENCH:
//`timescale 1ns / 1ps
module tb_n_8();
reg [3:0]a,b,c,d,e,f,g,h;
wire [6:0]z;
adder a1(a,b,c,d,e,f,g,h,z);
initial
begin
a=4'b1010;b=4'b1010;c=4'b1100;d=4'b1010;e=4'b1010;f=4'b1100;g=4'b0101;h=4'b1111;
#10 a=4'b1110;b=4'b1110;c=4'b1100;d=4'b1010;e=4'b1110;f=4'b1100;g=4'b0101;h=4'b1111;
#10 a=4'b1111;b=4'b1111;c=4'b1101;d=4'b1110;e=4'b1111;f=4'b1101;g=4'b1111;h=4'b1111;
#10 a=4'b1111;b=4'b1111;c=4'b1111;d=4'b1111;e=4'b1111;f=4'b1111;g=4'b1111;h=4'b1111;
#50 $finish;
end
endmodule
SIMULATION WAVEFORM:
Name:Abhishek Shrivastav
Id:2022H1230192H
RTL DESIGN:
COMPARING THE HARDWARE AND COMPLEXITY WHILE
CALCULATING THE AVERAGE WHEN N IS EVEN OR ODD:
Hardware utilization when N is 7
Detailed RTL Component Info:
Adders
2 Input
7 Bit
Adders:= 7
7 Input
7 Bit
Adders:= 1
2 Input
4 Bit
Adders:= 7
2 Input
7 Bit
Muxes := 14
2 Input
4 Bit
Muxes := 12
2 Input
1 Bit
Muxes := 6
Muxes
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
Name:Abhishek Shrivastav
Id:2022H1230192H
Report Cell Usage:
Cell Count
CARRY4 2
LUT2
15
LUT3
33
LUT4
19
LUT5
61
LUT6
94
MUXF7 1
LD
4
IBUF
28
OBUF
4
Hardware Utilization when N=8:
Detailed RTL Component Info :
Adders :
8 Input
7 Bit
Adders := 1
2 Input
7 Bit
Muxes := 1
2 Input
1 Bit
Muxes := 1
Muxes :
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
Report Cell Usage:
Cell Count
CARRY4 2
Name:Abhishek Shrivastav
LUT3
13
LUT4
5
LUT5
13
LUT6
9
LD
4
IBUF
32
OBUF
8
Id:2022H1230192H
CONCLUSION:
Component
Adders
Muxes
LUTS
IBUF
OBUF
For N=7
15
32
222
28
4
For N=8
1(8 input)
2
40
32
8
When we write the code for N=7 we cannot do the right shift and we need to use division
algorithms as simple divide operator is not synthesizable in Verilog.The number of Luts used are
222 which is more as compared to the number of LUTS used when N=8.Same is the case with
adders and muxes.
When we write the code for N=8 we can simply right shift it three times to divide it by 8. Hence
the complexity will reduce largely.