VLSI MENTORS
SPURTHI B A
INPUTS TO PHYSICAL DESIGN
1. GATE LEVEL NETLIST(.v)
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The Synthesized and optimized Netlist is provided as input and it contains
cell information, net information and pin or port information.
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It mainly contains the list of nets and their logical connections to standard
cells and Macros.
2. PHYSICAL LIBRARY [LEF]
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Liberty Exchange Format [LEF] file contains physical information such as
shape, size, direction, and symmetry, input and output pins direction for each cell
in the design.
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Library exchange format (LEF) is an ASCII representation of the abstract of
the standard cells.
3. LOGICAL LIBRARY [ .lib or .db]
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It contains timing, power and area related information of all the cells in the
design.
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Timing information such as cell delay, setup and hold time, PVT parameters,
maximum transition, capacitance and fan out are defined.
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Power information such as Leakage power, internal power etc.
4. TECHNOLOGY FILE
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It contains technology-specific information such as physical and
electrical characteristics for each metal layer, and design rules i.e. shapes,
color, and stipple, area, and DRC rules between the metal layers.
5. TLU+ FILE
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It contains R, C parasitic information per unit length for each metal.
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These R, C parasitics are used for calculation of net delay.
6. SDC FILE
VLSI MENTORS
SPURTHI B A
-> Synopsys Design Constraints [SDC] contains all the timing constraints such
as Clock definitions, input and output delay, clock latency, clock uncertainty,
timing exceptions etc. are defined
OTHER INPUT FILES ARE:
-> MMMC [Multi – Mode Multi – Corner file] =It is used to generate
different analysis views based on different delay corners and constraints
mode.
-> UPF [Unified Power Format] = is an industry-wide power format
specification to implement low power techniques in a power-aware design
flow.
SANITY CHECKS
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Sanity checks are an important step for physical design engineers to
make sure that the inputs received for physical design are correct and
consistent. Checks such as library checks, netlist checks and SDC checks are
performed.
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Any issues in the input files may cause problems in the later stages.
Hence, the Import stage in design involves loading all the above inputs and
performing Sanity checks.