Digital Integrated Circuits A Design Perspective Adapted from Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories © Digital Integrated Circuits2nd Memories Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability © Digital Integrated Circuits2nd Memories Semiconductor Memory Classification Read-Write Memory Random Access Non-Random Access SRAM FIFO DRAM LIFO Non-Volatile Read-Write Memory Read-Only Memory EPROM Mask-Programmed E2PROM Programmable (PROM) FLASH Shift Register CAM © Digital Integrated Circuits2nd Memories Memory Timing: Definitions © Digital Integrated Circuits2nd Memories Memory Architecture: Decoders M bits Decoder S0 Word 0 S1 Word 1 S2 N M bits Word 2 SN 2 2 SN 2 1 words Storage cell S0 Word 0 A0 Word 1 A1 Word 2 A K2 1 Word N 2 2 Word N 2 2 Word N 2 1 Word N 2 1 K Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Storage cell = log2N Input-Output (M bits) Decoder reduces the number of select signals K = log2N Problem: ASPECT RATIO or HEIGHT >> WIDTH!? © Digital Integrated Circuits2nd Memories Array-Structured Memory Architecture L-K K+1 L-1 Amplify swing to rail-to-rail amplitude K-1 © Digital Integrated Circuits2nd Selects appropriate word Memories Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings © Digital Integrated Circuits2nd Memories Block Diagram of 4 Mbit SRAM Clock generator Z-address buffer X-address buffer Predecoder and block selector Bit line load Transfer gate Column decoder Sense amplifier and write driver CS, WE buffer © Digital Integrated Circuits2nd I/O buffer x1/x4 controller Y-address buffer [Hirose90] X-address buffer Memories Memory Timing: Approaches DRAM Timing Multiplexed Adressing © Digital Integrated Circuits2nd SRAM Timing Self-timed Memories Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended © Digital Integrated Circuits2nd Memories SRAM - Introduction Line – Horizontal select line that enables a single row of cells Bit Line – wire that connects the cells in a single column to the input/output circuitry Register cell / semiconductor memory Block Address – Wire length, power saving mode Word © Digital Integrated Circuits2nd Memories © Digital Integrated Circuits2nd Memories 6-transistor CMOS SRAM Cell WL V DD M2 M5 Q M1 BL © Digital Integrated Circuits2nd M4 Q M6 M3 BL Memories CMOS SRAM Analysis (Read) WL V DD M4 BL Q= 0 M5 V DD Cbit © Digital Integrated Circuits2nd M1 Q= 1 V DD BL M6 V DD Cbit Memories CMOS SRAM Analysis (Read) 1.2 Voltage Rise (V) 1 0.8 0.6 0.4 0.2 Voltage rise [V] 0 0 © Digital Integrated Circuits2nd 0.5 1 1.2 1.5 2 Cell Ratio (CR) 2.5 3 Memories CMOS SRAM Analysis (Write) WL V DD M4 M5 Q= 1 M1 BL = 1 © Digital Integrated Circuits2nd M6 Q= 0 V DD BL = 0 Memories CMOS SRAM Analysis (Write) © Digital Integrated Circuits2nd Memories 6T-SRAM — Layout VDD M2 M4 Q Q M1 M3 GND M5 BL © Digital Integrated Circuits2nd M6 WL BL Memories Resistance-load SRAM Cell WL V DD RL M3 BL RL Q Q M1 M2 M4 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem © Digital Integrated Circuits2nd Memories SRAM Characteristics © Digital Integrated Circuits2nd Memories 3-Transistor DRAM Cell BL 1 BL 2 WWL WWL RWL M3 X M1 CS M2 RWL V DD 2 V T X BL 1 BL 2 V DD DV V DD 2 V T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL-VTn © Digital Integrated Circuits2nd Memories 3T-DRAM — Layout BL2 BL1 GND RWL M3 M2 WWL M1 © Digital Integrated Circuits2nd Memories 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance CS D V = VBL – V PRE = V BIT – V PRE -----------C S + CBL Voltage swing is small; typically around 250 mV. © Digital Integrated Circuits2nd Memories DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD © Digital Integrated Circuits2nd Memories Sense Amp Operation V BL V(1) V PRE D V(1) V(0) Sense amp activated Word line activated © Digital Integrated Circuits2nd t Memories 1-T DRAM Cell Capacitor M 1 word line Metal word line SiO2 Poly n+ Field Oxide n+ Poly Inversion layer induced by plate bias Cross-section Diffused bit line Polysilicon gate Polysilicon plate Layout Uses Polysilicon-Diffusion Capacitance Expensive in Area © Digital Integrated Circuits2nd Memories SEM of poly-diffusion capacitor 1T-DRAM © Digital Integrated Circuits2nd Memories Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Trench Cell © Digital Integrated Circuits2nd Stacked-capacitor Cell Memories Periphery Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry © Digital Integrated Circuits2nd Memories Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder © Digital Integrated Circuits2nd Memories Hierarchical Decoders Multi-stage implementation improves performance ••• WL 1 WL 0 A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3 ••• NAND decoder using 2-input pre-decoders A1 A0 A0 A1 © Digital Integrated Circuits2nd A3 A2 A2 A3 Memories Dynamic Decoders Precharge devices GND VDD GND WL 3 VDD WL3 WL2 WL 2 VDD WL1 WL 1 V DD WL0 WL 0 VDD f A0 A0 A1 A1 2-input NOR decoder © Digital Integrated Circuits2nd A0 A0 A1 A1 f 2-input NAND decoder Memories 4-input pass-transistor based column decoder BL BL BL BL 0 A0 1 2 3 S0 S1 S2 A1 S3 2-input NOR decoder D Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count © Digital Integrated Circuits2nd Memories 4-to-1 tree based column decoder BL 0 BL 1 BL 2 BL 3 A0 A0 A1 A1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches © Digital Integrated Circuits2nd Memories Decoder for circular shift-register V DD WL V DD V DD WL 0 R f f f f R V DD V DD WL 1 f f f f R V DD 2 f f f f • • • V DD © Digital Integrated Circuits2nd Memories Logical Effort in Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder © Digital Integrated Circuits2nd Memories Logical Effort in Decoders with Precoder © Digital Integrated Circuits2nd Memories Sense Amplifiers DV C tp = ---------------Iav large make D V as small as possible small Idea: Use Sense Amplifer small transition s.a. input © Digital Integrated Circuits2nd output Memories Differential Sense Amplifier V DD M3 M4 y M1 bit SE M2 Out bit M5 Directly applicable to SRAMs © Digital Integrated Circuits2nd Memories Differential Sensing ― SRAM V DD PC V DD BL BL EQ V DD y M3 WL i M1 x SE V DD M4 M2 2y 2x 2x x SE M5 SE SRAM cell i Diff. x Sense 2x Amp V DD Output y SE Output (a) SRAM sensing scheme © Digital Integrated Circuits2nd (b) two stage differential amplifier Memories Latch-Based Sense Amplifier (DRAM) EQ BL BL VDD SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. © Digital Integrated Circuits2nd Memories Charge-Redistribution Amplifier V ref VL M2 M3 M1 C large VS C small Transient Response Concept © Digital Integrated Circuits2nd Memories Charge-Redistribution Amplifier― V EPROM DD SE Load M4 Out V casc M3 Cascode device Cout Ccol WLC Column decoder M2 BL WL © Digital Integrated Circuits2nd M1 CBL EPROM array Memories Single-to-Differential Conversion WL BL x Cell Diff. S.A. 2x 1 2 V ref Output How to make a good Vref? © Digital Integrated Circuits2nd Memories Open bitline architecture with dummy cells EQ L L1 L0 V DD R0 R1 L SE BLL CS … CS BLR CS Dummy cell © Digital Integrated Circuits2nd … SE CS CS CS Dummy cell Memories Voltage Regulator?? © Digital Integrated Circuits2nd Memories Voltage Regulator VDD Mdrive VDL VREF Equivalent Model Vbias VREF + Mdrive VDL © Digital Integrated Circuits2nd Memories Charge Pump © Digital Integrated Circuits2nd Memories DRAM Timing © Digital Integrated Circuits2nd Memories RDRAM Architecture Bus Clocks Data bus k k3 l memory array network mux/demux Column Row © Digital Integrated Circuits2nd demux packet dec. demux packet dec. Memories Address Transition Detection V DD A0 DELAY td A1 DELAY td A N2 1 DELAY td © Digital Integrated Circuits2nd ATD ATD … Memories Reliability and Yield © Digital Integrated Circuits2nd Memories Sensing Parameters in DRAM 1000 C D(1F) V smax (mv) 100 smax V , DD V , S C , S Q , D C C S(1F) Q S(1C) 10 V DD (V) Q S 5 C S V DD / 2 V smax 5 Q S / (C S 1 C D ) 4K 64K 1M 16M 256M 4G Memory Capacity (bits © Digital Integrated Circuits2nd 64G / chip) From [Itoh01] Memories 1. Noise Sources in 1T DRam BL substrate Adjacent BL CWBL a -particles WL leakage CS electrode Ccross © Digital Integrated Circuits2nd Memories Open Bit-line Architecture —Cross Coupling EQ WL 1 WL 0 WL C WBL D C WBL WL D WL 1 WL 0 BL BL C BL C C © Digital Integrated Circuits2nd C Sense Amplifier C BL C C C Memories Folded-Bitline Architecture WL 1 WL 0 C WBL WL 0 WL D WL D CBL BL … BL WL 1 C y x C C C C C Sense EQ Amplifier x CBL y CWBL © Digital Integrated Circuits2nd Memories Transposed-Bitline Architecture Ccross BL 9 BL SA BL BL 99 (a) Straightforward bit-line routing Ccross BL 9 BL SA BL BL 99 (b) Transposed bit-line architecture © Digital Integrated Circuits2nd Memories 3.Leakage PN junction & Subthreshold leakage Minimum WL - Refresh time Changing doping profile Operating at reduced temperature © Digital Integrated Circuits2nd Memories 3. Charge Carriers -Alpha-particles (or Neutrons) a -particle WL V DD BL n1 SiO 2 2 1 2 1 1 2 2 1 2 1 1 2 1 Particle ~ 1 Million Carriers © Digital Integrated Circuits2nd Memories Yield Yield curves at different stages of process maturity (from [Veendrick92]) © Digital Integrated Circuits2nd Memories Redundancy Row Address Redundant rows : Fuse Bank Redundant columns Memory Array Row Decoder Column Decoder © Digital Integrated Circuits2nd Column Address Memories Error-Correcting Codes Example: Hamming Codes e.g. B3 Wrong with 1 1 =3 0 © Digital Integrated Circuits2nd Memories Redundancy and Error Correction © Digital Integrated Circuits2nd Memories Sources of Power Dissipation in Memories V DD I DD 5 S C iD V if1S I DCP CHIP nC DE V INT f m selected C PT V INT f mi act I DCP n ROW DEC PERIPHERY m(n 2 1)i hld non-selected ARRAY mC DE V INT f COLUMN DEC V SS © Digital Integrated Circuits2nd From [Itoh00] Memories Data Retention in SRAM 1.30u 1.10u 0.13 m m CMOS Ileakage 900n 700n 500n Factor 7 (A)300n 0.18 m m CMOS 100n 0.00 .600 1.20 1.80 VDD SRAM leakage increases with technology scaling © Digital Integrated Circuits2nd Memories Data Retention in DRAM © Digital Integrated Circuits2nd Memories Data Retention in SRAM © Digital Integrated Circuits2nd Memories Suppressing Leakage in SRAM V DD V DD low-threshold transistor V DDL sleep V DD,int sleep V DD,int SRAM cell SRAM cell sleep SRAM cell SRAM cell SRAM cell V SS,int Inserting Extra Resistance © Digital Integrated Circuits2nd SRAM cell Reducing the supply voltage Memories Data Retention in DRAM © Digital Integrated Circuits2nd From [Itoh00] Memories