DIGITAL LOGIC EXERCISES AND SOLUTIONS
1. Calculate
(10111)2 times (110)2
Solution
= 10001010
2. Find the dual of the following expression;
(a’b +1)(cd + e’) + f(g’ + 0) + h
Solution:
The dual is found by replacing AND by OR, OR by AND, 0 by 1 and 1 by 0
[(a’ + b)· 0 + (c + d)· e’]· [f + (g’· 1)]· h
3. Find the complement of the following expression
[a’b’(c + d’)(c’ + d) + ab(c’d + cd’)]’
Solution:
= [(a’b’)’ + (c + d’)’ + (c’ + d)’]· [(ab)’ + (c’d’)’(cd’)’]
= [a + b + (c’d) + cd’][a’ + b’ + (c + d’)(c’ + d)]
=[a + b + (c’d) + cd’][a’ + b’ + (c + d’)(c’ + d)]
4. Express the following function as minterm and maxterm expansions using algebraic
and m (or M) notation.
f (a,b,c) = (b + c)(a ’+ b + c’)(a + c)
Solution
5. A vuvuzela is a very a very disturbing annoying instrument used mostly by football
fans when supporting and cheering their teams. As a team, you seek to develop a
denoising system that can be represented by the block A below. The idea is to
develop a new vuvuzela that can respond to the force applied in blowing air into it
in 5 phases denoted as v, w ,x, y, and z. blowing the vuvuzela at different force
produces of corresponding tone which is instrumental and not noise. On blowing at
different forces in quick succession that looks like blowing at different forces
simultaneously, a chord will be produced then followed by a sound (a nice sound)
from combinations of keys, v, x, and z while other combinations should be quiet. The
sound should be produced only if;
 Exactly one level of force is applied when blowing it
 Any possible blown air combination of phases v, x, z is applied.
All other combinations produce no sound.
i. Develop a truth table of B = f (v, w, x, y, z)
ii. Draw a Karnaugh map for function B. (If you find a case where the value of B does
not matter, then you can use it as a don’t care)
iii. Minimize and express the function B in Sum of Products (SOP) form.
iv.
Applying de Morgan rules, find the complement of function B in question iii
above
v. Using only four-input NOR gates, draw a circuit of function B.
Solution
i.
0
1
2
3
4
5
6
Develop a truth table of B = f (v, w, x, y, z)
v
w x
y
z
B
v
16 1
0
0
0
0
0
0
17 1
0
0
0
0
1
1
18 1
0
0
0
1
0
1
19 1
0
0
0
1
1
0
20 1
0
0
1
0
0
1
21 1
0
0
1
0
1
1
22 1
0
0
1
1
0
0
w
0
0
0
0
0
0
0
x
0
0
0
0
1
1
1
y
0
0
1
1
0
0
1
z
0
1
0
1
0
1
0
B
1
1
0
0
1
1
0
7
8
9
10
11
12
13
14
15
ii.
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Draw a Karnaugh map for function B. (If you find a case where the value of B
does not matter, then you can use it as a don’t care)
B = 1 for v, w, x, y, z, vxz, vx, vz, xz = 9 tones.
If no key is pressed, then we don’t need to have B = 0, as no sound will be
generated, B can as well be B = 1, so we can use this case as don’t care, B =
X.
v= 0
yz
yz
wx
00
01
11
10
iii.
v =1
00 01 11 10
X 1 0 1
1 1 0 0
0 0 0 0
1 0 0 0
wx
00
01
11
10
00 01 11 10
1 1 0 0
1 1 0 0
0 0 0 0
0 0 0 0
Minimize and express the function y in Sum of Products (SOP) form.
B = f (v, w, x, y, z) = (0 + 1 + 4 + 5 + 16 + 17 + 20 + 21) + (0 + 8) + (0 + 2)
=(v’w’x’y’z’ + v’w’x’y’z + v’w’xy’z’+ v’w’xy’z + vw’x’y’z’ +vw’x’y’z +
vw’xy’z’ + vw’xy’z) + (v’w’x’y’z’ + v’w’x’yz’) + (v’w’x’y’z’ + v’wx’y’z’)
=w’y’ + v’w’x’z’ +v’x’y’z’
iv.
Applying de Morgan rules, find the complement of function B in iii.
Using de Morgan theorem 5 a & b;
(a + b)’ = a’.b’
(a.b)’ = a’ + b’
B = w’y’ + v’w’x’z’ +v’x’y’z’
B’ = (w’y’ + v’w’x’z’ +v’x’y’z’)’
B’ = (w’ + y’)’.(v’+w’+x’+z’)’.(v’+x’+y’+z’)’
or
B’ = (w + y).(v + w + x + z).(v + x + y + z)
v.
Using only four input NOR gates, draw a circuit of function y.
B’ = ((d’ + y’)’+(v’+d’+x’+z’)’+(v’+x’+y’+z’)’)’
B= (B’)’
6. Consider the circuit shown below. The propagation delay tpd of the inverters G1 to
G3, and the clock-to-Q delay tclk-Q of the flip-flops FF1 and FF2, are in the range of 0.5
ns to 1.0 ns. The setup and hold times of the flip-flops FF1 and FF2 are 1.3 ns and 1.1
ns respectively. The clock to FF2 is driven through a delay element DLY with a delay
of tdly.
i.
Assuming that tdly = 0 ns and using only the setup time constraint, calculate
the maximum operating frequency of the clock signal CLK.
ii.
Show whether hold time for FF1 is violated assuming that tdly = 0 ns.
iii.
If there is time violation, how can it be eliminated?
Solution
(i)
Ignoring any hold time violation, the path from Q1 (FF1 Q output) to D2
governs the worst-case timing. This gives:
tclk ≥ 2 * td(max) + tcq(max) + tsu
Therefore
tclk ≥ 2 * 1ns + 1ns + 1.3ns = 4.3ns
fclk(max) = 232.6MHz.
(ii)
The shortest delay from Q2 (FF2 Q output) to D1 (FF1 D input) is:
tcq(min) + td(min) = 1.0 ns
which is shorter than the hold time requirement of FF1, i.e. 1.1ns. Therefore
there is hold time violation at FF1 D input.
(iii)
To eliminate the hold time violation, we want to delay the arrival time at
D1 by at least 0.1ns. This can be achieved by delaying to clock to FF2 by the
same amount of 0.1ns. Therefore the minimum value required for tdly is
0.1ns.
7. Assume that the inverter in the figure below has a propagation delay of 5 ns and the
AND gate has a propagation delay of 10 ns. Assume that X is initially 0, Y is initially
1, X becomes 1 for 80 ns, and then X is 0 again.
i.
Write down the function of Z
in form of XY and XZ
ii.
Draw a timing diagram for the network comparing X, Y, and Z.
Solution
Function =
Z = XY = XZ'
8. Consider the circuit below and the table giving various maximum propagation delays
and other timing parameters for the circuit elements.
i.
Determine the minimum clock period for which this circuit is guaranteed to
operate correctly. Show how you arrived at your answer.
ii.
Assume that the minimum propagation delay for all gates and the clock-to-Q of the
flipflops is 0.5ns. Will the hold time for the Flip-Flops labeled FFD and FFE be
violated? Give an answer for both flip-flops and explain each answer.
Solution
i. Determine the minimum clock period for which this circuit is guaranteed to
operate correctly. Show how you arrived at your answer.
Period = TClock-to-Q + TAND + TNAND + TAND + TSet-up
= 3 + 5 + 4 + 5 + 2 = 19 ns
ii.
Assume that the minimum propagation delay for all gates and the clock-to-Q of
the flipflops is 0.5ns. Will the hold time for the Flip-Flops labeled FFD and FFE
be violated? Give an answer for both flip-flops and explain each answer.
FFD has a hold time violation because Th is 1.5ns, and the minimum time for a
transition on the D input to FFD is a min of Tclock-to-q (a->d) + min of Tand (d>g)
= 0.5 + 0.5 = 1ns < 1.5ns -> violation.
FFE does not have a hold time violation. The quickest change that could occur
would come through the path cfhj or cfij, both of which have a clock-to-q + min
gate + min gate
= 0.5 +0.5 +_0.5 = 1.5ns, just meeting the hold time, so no violation.
9. The Figure below shows a generic state machine. Assume that the state is encoded
using 5 bits.
i.
Differentiate between a Moore machine and a Mealy machine.
ii.
Does this circuit violate the hold time constraint? Explain
iii.
If so, how could you eliminate the violations? If not, what is the smallest
clock skew for which hold time violations are possible?
iv.
What is the smallest safe clock period for this circuit (without any
modifications to handle hold time violations)?
v. If the clock goes from low to high at time t0, during what time period must
the inputs be stable?
vi.
Suppose that two copies of this circuit are instantiated together, with the
output of one connected to the input of the other. For this combined circuit,
what is the minimum safe clock period?
Solution
i.
ii.
The outputs in a Moore machine depend only on the present state. The
outputs in a Mealy machine depend on both the present state and the
present input.
Does this circuit violate the hold time constraint?
hold time + clock skew = 1.5 ns > 1ns
= min ff delay + min combinational delay, so hold time violations
iii.
If so, how could you eliminate the violations? If not, what is the smallest
clock skew for which hold time violations are possible?
Add delay to the feedback path from the outputs of the flip flops.
iv.
What is the smallest safe clock period for this circuit (without any
modifications to handle hold time violations)?
max ff delay + max combinational delay + setup + skew
= 4 + 5 + 1 + 1 = 11 ns
v.
If the clock goes from low to high at time t0, during what time period
must the inputs be stable?
From t0 – 4 ns to t0 + .5 – 1
= t0 – 0.5 ns.
vi.
Suppose that two copies of this circuit are instantiated together, with the
output of one connected to the input of the other. For this combined circuit,
what is the minimum safe clock period?
max ff delay + max combinational delay + setup + skew
= 4 + (4 + 3) + 1 + 1 = 13 ns
10. A digital comparator is a logic circuit that takes two n-bit numbers A and B as input
and compares the magnitude of A and B. It has three outputs, G, E, and L, where
G=1 only if A>B, E=1 only if A=B, and L =1 only if A<B. A 4-bit magnitude
comparator (for unsigned numbers) is to be constructed from two 2-bit comparators
as shown in Figure 5. One of these will compare the high-order 2-bits (a3a2 and b3b2)
of each input and the other will compare the lower 2-bits (a1a0 and b1b0). The
outputs, greater (Gin), equal (Ein), and less (Lin) from the lower-bits comparator
become additional inputs to the higher-bits comparator. The inputs to the lower-bits
comparator are labeled G0, E0, and L0.
iii.
For what values of the inputs A and B will the result of the lower-bits
comparator (Gin, Ein, and Lin) influence the overall outputs G, E and L?
Explain.
iv.
If both 2-bit comparator units are to contain identical logic circuits, specify,
for the lower bits comparator, what values the inputs G0, E0, and L0 should
have in order for the complete 4-bit comparator to operate properly.
v.
Give a logic expression for G in terms of a3, a2, b3, b2 and Gin using either
AND, OR, NOT, or XOR logic operators where needed.
Solution
i.
For what values of the inputs A and B will the result of the lower-bits
comparator (Gin, Ein, and Lin) influence the overall outputs G, E and L?
Explain.
for E =1 to happen, Ein must be 1;
If a3 = b3 and a2 = b2, Gin or Lin will affect G or L.
ii.
If both 2-bit comparator units are to contain identical logic circuits, specify, for
the lower bits comparator, what values the inputs G0, E0, and L0 should have in
order for the complete 4-bit comparator to operate properly.
G0 = 0,
E0 = 1,
L0 = 0.
iii.
Give a logic expression for in terms of a3, a2, b3, b2 and Gin using either AND,
OR, NOT, or XOR logic operators where needed.
G = a3b3’ + (a3 ⊕b3)’ • a2b2’ + (a3 ⊕b3)’ • (a2 ⊕b2 ) •Gin
11. The hydraulic steering device of a dish antenna for satellite tracking works by
adjusting the elevation using a hydraulic ram. Oil can be pumped into the ram to
raise the elevation. The hydraulic seals leak pressure very slowly such that
additional oil has to be pumped periodically to maintain a constant elevation. Two
output signals are provided by the hydraulic system: ABOVE19 and ABOVE20
which equal 1 whenever the elevation of the disk is above 19 and 20 degrees
respectively from the horizontal.
a. Using either latches or flip-flops, design a circuit to keep the elevation of
the dish between these two limits. Your circuit should have an output signal
PUMP which equals 1 when you want the pump to increase the hydraulic
pressure and hence raise the elevation of the dish.
b. Show the truth table of your design
Solution
12. A four piston car engine must to go through four strokes namely; intake, compression,
power, and exhaust, all of equal duration resulting in a state sequence as shown in
Figure 6. On the first stroke the inlet valve is open and the outlet is closed; on the
second stroke the inlet is closed and compression occur; on the third stroke a spark is
delivered leading to rotation by the crankshaft; and at the forth stroke, the outlet is
open for the exhaust from the explosion to vent. Then the first stroke comes again and
the cycle repeats. Your work is to design a controller for the system, with a clock for
input and with three outputs: one to open the inlet, one to open the outlet, and one to
ignite the spark. Assume that if the control to open a valve isn’t asserted, the valve
closes (spring-loaded valve). The frequency of the clock will determine the speed of
engine. The design should be based on the following questions.
i.
Determine the number of flip-flops required and the type of coding scheme
to use.
ii.
Develop a state table for the system.
iii.
Form a present-state next-state table and determine input conditions for the
chosen flip-flops.
iv.
Using Karnaugh maps, determine the flip-flop inputs equations and the
output combinational logic.
v. Draw the resulting circuit diagram
State Sequence of Engine Cycle
Solution
i. Determine the number of flip-flops required and the type of coding scheme to
use.
Step 1. Each of the four strokes is a different state. Since two flip-flop outputs can
represent four states, two flip-flops are required to design a controller.
Step 2. Naturally, a positional binary code can be used to assign flip flop outputs (state
variables) to the states:
Such coding could work properly. However, we observe that the system has three
outputs, and the proper functioning of the engine requires that outputs be asserted
only during their intended states. We see that in the sequence 00 01 10 11, two flipflop
outputs try to change at once between second and third states and between last and
first states. Because of unequal propagation delays in flip-flops, it is possible that two
flip-flops will not change simultaneously and that a glitch will occur and will cause
the system to function unexpectedly before it gets to the expected next state. Instead
of positional binary code, two-bit Gray code can be used. In Gray code, numbers
change only one bit at a time.
ii. Develop a state table for the system.
Rearranged (according to the Gray code) state table for the system is:
iii. Form a present-state next-state table and determine input conditions for the
chosen flip-flops
Step 3:(we use J-K flip flop in this design).
iv. Using Karnaugh maps, determine the flip-flop inputs equations and the output
combinational logic.
Step 4.
JB = A , KB = A' ; JA = B' , KA = B
Step 5. The output combinational logic can be determined from the second table
(rearranged for Gray code) given in step 2.
INLET = B'A' ; OUTLET = BA' ; SPARK = BA
v. Draw the resulting circuit diagram
Step 6. Draw the circuit diagram
13. Design a serial 2’s complementer with shift register and a flip-flop. The binary number
is shifted out from one side and it’s 2’s complement shifted into the other side of the
shift register.
Solution
14. Design a counter with T flip-flops that goes through the following binary repeated
sequence: 0, 1, 3, 7, 6, 4.
i.
Develop the state table
ii.
Develop the simplified functions of the system using K-map
iii.
Show that when binary states 010 and 101 are considered as don’t care conditions,
the counter may not operate properly. Find a way to correct the design.
Solution
15. In a gym and fitness centre, there are some shower stalls like the one represented in
Fig. 50 that have to be automated to generate cycles of contrasting hot (48 °C), warm
(26 °C) and cold (4 °C) water sprays simply clicking a single start push button (SB).
After clicking the SB, initially warm water flows for 50 s (H = C = ‘1’), then hot water
(H = ‘1’, C = ‘0’) for 10 s, and thirdly cold water (H = ‘0’, C = ‘1’) for 20 s, and this
cycle is repeated another time; finally the system goes idle (H = C = ‘0’) to wait for
another user service. During the operation the R_LED turns on and the water
solenoid valve (SV) is on. Design the digital control system connected to the valves’
power driver for controlling this system.
16. A washing machine control circuit has 4 inputs: WASH, THERMOSTAT, FULL,
EMPTY and 4 outputs: HOT, COLD, MOTOR and PUMP. When they are high, the
outputs turn on the hot and cold taps, the main motor and the draining pump
respectively. THERMOSTAT goes high when the water in the machine is above the
required temperature; FULL and EMPTY indicate (when high) that the machine is
completely full or completely empty of water respectively; they are both low when it
is half full. Draw a Karnaugh map for each output and hence write down the Boolean
equations which describe the operation of the washing machine control circuit.