VLSI Design Automation of a
Montgomery Multiplier using
Astro by Synopsys
Steven Hubbard
Overview
Montgomery Multiplier for RSA Encryption
Physical Design – ASIC and SoCs
ASIC Advantages
Astro Place and Route by Synopsys
Montgomery Multiplier Circuit Synthesis
Results
RSA Public-Key Cryptosystem
Developed by Rivest, Shamir, and
Adleman in 1978
Private Key contains two large prime
numbers, p and q, as well as a secret
exponent d
Public Key consists of n = p * q, with
exponent e
Requires Modular Exponentiation
Decryption involves larger exponentiation
Montgomery Multiplication
Efficient technique for computing modular
exponentiations
Does not require division in taking
modulus
Replaces with bit shifting, which is fast and
easy in hardware
Simple conversion to Montgomery Domain
done before and after Multiplication
Very Large Scale Integration (VLSI)
Computer Aided Design of Complex
Circuits
„
Tools for VLSI Produced by Synopsys
Used for Application Specific Integrated
Circuits (ASIC) and Systems On Chips
(SoCs)
Application Specific Integrated
Circuits (ASIC)
Advantages
„
„
„
Speed
Area
Power Consumption
Disadvantages
„
„
Manufacturing Time (FPGA time about half)
Cost
Astro – Place and Route Tool
Creates Physical Design Layout
Uses 3 Primary Inputs
„
„
Gate Level Netlist from Verilog
Standard Cell Library of Target Technology
Also contains timing information for the cells
„
Design Constraints (SDC File)
Clock Speeds
Input / Output Delays
Astro Tutorial
Provided by Synopsys
Primary Resource for Project
„
„
„
Tutorial Version: 3.6
Designed for Astro Version: 2003.09-SP1
Astro Version in Lab: 2004.06-SP1
Used same steps for Montgomery
Multiplier Circuit Synthesis
Astro Tutorial
Consists of 12 section which step through
place-and-route and other tools.
Not all sections used, not needed for
circuit.
Will be a primary resource for ECE 681 –
VLSI Design Automation class.
Montgomery Multiplier Circuit
Synthesis
VHDL Code
„
„
Provided by Hoang Le
Montgomery Multiplier Used in Elliptic Curve
Method Circuit
Use Design Analyzer in on Unix Server to
convert to Verilog and create SDC Timing
File
Montgomery Multiplier Circuit Synthesis –
Library and Cell Creation
First steps in Astro
Create Library
„
Expand Netlist from Verilog Code
Link Technology files and Reference
Library
„
„
Technology File - designs.tlu.18.tf
Reference Library - tcbn90g
90 nm circuit
Load Timing Constraints from SDC File
Montgomery Multiplier Circuit Synthesis –
Library and Cell Creation
Create Cell
„
„
„
Power / Ground Ring
P/G Strap
Standard Cells
Montgomery Multiplier Circuit Synthesis –
Optimizations and Placement
Pre and Post Placement Optimization
„
Frequent Optimizations run throughout
process to lower delay and verify design
Place Blocks
„
Arrange Standard Cells
Create Clock Tree Synthesis
„
Drive all clocked components without
connecting them to a single port.
Multiplier Cell after Placement
Montgomery Multiplier Circuit Synthesis –
Routing
Routing the Design
„
Connect Cells with Metal
More Optimization
Design Checks
„
Cross Talk
Check that signals will not affect adjacent wires
Multiplier Cell after Routing
Additional Astro Tools
ECO
„
Update circuit without recreating entire layout
Netlist Verification using Formality
„
Verify that the input and output Netlist are the same
Astro Rail
„
Create Voltage Drop Map and Electromigration Map
Static Timing Analysis using Primetime
„
Signoff quality static timing analysis and delay
calculation
Multiplier Clock Tree
Multiplier Voltage Drop Map
Montgomery Multiplier Circuit Synthesis –
Timing Reports
Based on SDC file
Generated Throughout Process
„
Usually Changes with optimization and
analysis
Show delay, report in terms of “Slack”
„
Difference between required delay and actual
delay
Steps through Critical Path
Montgomery Multiplier Timing
Results
Three Synthesis Cases
„
„
„
10 ns delay
5 ns delay
2.5 ns delay
Same circuit run on FPGA at 200 MHz or
5ns delay
Montgomery Multiplier Timing
Results
Slack
Total Delay
10 ns Delay
3.7089
6.2911
5 ns Delay
0.1477
4.8523
-2.1415
4.6415
2.5 ns Delay
Conclusions
Powerful Tool to create Physical Layouts
Need to Analyze Critical Path to see if
speed can be increased
Does not look like good Circuit Structure
for ASIC
Questions ?