Cairo University
Faculty of Engineering
Department of Electronics and Electrical Communications
Third Year
Electronics 3 (ELC301)
Practice Sheet 3
(Dynamic CMOS)
1-Implement the function F’=ABC(D+EG) as a dynamic gate
a) Size the PDN for a worst case resistance equal to that of the unit inverter
b) Size the PUN so that the pre-charge resistance is one tenth of the worst case pull down
resistance
c) Find the total capacitance at the output node
d) Find the duty cycle of the clock
e) Find an expression for maximum frequency in terms of Ro and Co
f) If leakage current is 1nA and output capacitance is 100pF, acceptable logic ‘1’ must be above
0.9Vdd and Vdd=3V; what is the minimum operating frequency
2-For the logic function F’=A(BCD+EGHK)
a) write down the input pattern over two complete cycles which would lead to worst case output at
the end of the second evaluate due to charge sharing
b) If Internal nodes have a capacitance one tenth the output node, what is the worst case output
seen due to charge sharing
3-For logic function F’=ABCD+EGHK (internal nodes have 5% of the output node capacitance)
a) Write the input pattern in the second evaluate which will lead to no charge sharing regardless
of what happened in earlier phases
b) Find the worst possible output due to charge sharing
c) Write the input in the second pre-charge which will nullify all charge sharing regardless of input
in the second evaluate
d) Write the inputs for the first pre-charge and evaluate which will nullify all charge sharing
regardless of what happens in second cycle