DIGITAL ASIC IC DESIGN GP
ROADMAP
Required Knowledge
- Principles [Logic, MP, DSP, Digital Electronics, VLSI]
- HDL [Verilog]
- ASIC Design Flow
- RTL
- RTL Verification (Testbench, etc.)
- Synthesis [Goals, Constraints, Tools, Static Timing Analysis (STA)]
- Place and Route (PnR)
- Tools
- Scripting [TCL or Perl] (A Plus)
Schedule Overview
Approx. Time: 1.5 Months (6 Weeks) to finish two parallel sub tracks.
• Practical:
• Digital ASIC Design with Verilog- Dr. Paul Franzon
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
• Introduction to Digital ASIC Design - VLSI School [Quizzes&Assignments]
• Theoretical Basis:
•
•
•
•
•
FPGA Prototyping with Verilog Examples
Principles of VLSI RTL Design: A Practical Guide
The Art of Hardware Architecture
Constraining Designs for Synthesis and Timing Analysis
Digital IC Design Courses - Dr. Hesham Omran
Sources
• Important before Starting:
•
Digital Design Career Overview
https://gofile.io/d/OFFpE8
•
ASIC vs FPGA Comparison
http://www.signoffsemi.com/asic-vs-fpga//
•
Digital ASIC IC Design Flow
https://prezi.com/view/fjnKPHNDRw9jC5Bihzeh/
•
ModelSim Tutorials [ModelSim PE Student Edition]
https://www.mentor.com/company/higher_ed/modelsim-student-edition
https://www.youtube.com/watch?v=9mpRF6bAY1g
https://www.youtube.com/watch?v=t4LcbG5tnHY&t=307s
• Videos Playlists:
•
Digital ASIC Design with Verilog - Dr. Paul Franzon
https://www.youtube.com/playlist?list=PLfGJEQLQIDBN0VsXQ68_FEYyqcym8CTDN
•
Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
http://www.eng.biu.ac.il/temanad/digital-vlsi-design/
https://www.youtube.com/playlist?list=PLZU5hLL_713x0_AV_rVbay0pWmED7992G
•
Introduction to Digital ASIC Design - VLSI School
https://vlsi-school.thinkific.com/courses/101
•
Digital IC Design Courses - Dr. Hesham Omran
https://www.youtube.com/playlist?list=PLMSBalys69yzvAKErDt7tT7O-iIKPlOCP
https://www.youtube.com/playlist?list=PLMSBalys69yxoIjeZ2Q3fxs69cGCU14B1
https://www.youtube.com/playlist?list=PLMSBalys69yw1tSoF42QW9jbbC0-UeCAy
• Textbooks:
•
FPGA Prototyping by Verilog Examples
https://drive.google.com/file/d/1MplwouwD9kBATaWpdpEskm0p_bOR84PJ/view?usp=sharing
•
Principles of VLSI RTL Design: A Practical Guide
https://drive.google.com/file/d/1WZL6uToBzi5Fex-g_OQIMvkYHOxCyZxM/view?usp=sharing
•
The Art of Hardware
https://drive.google.com/file/d/16Y2_6JcJX_qwsHLnZz-p3Ut68k0PSU7k/view?usp=sharing
•
Constraining Designs for Synthesis and Timing Analysis
https://drive.google.com/file/d/1GcLNzbxiZwvyCZKdSJdeMwso8G8_p3Ia/view?usp=sharing
• Practicing on Projects:
•
FPGA 4 Students - Verilog Projects
https://www.fpga4student.com/p/verilog-project.html?m=1
•
ASIC World - Verilog Projects
http://www.asic-world.com/verilog/index.html
Schedule (Week by Week)
• Week 1
Day
Tasks
• Introduction to Digital ASIC Design - VLSI School
Weeks 1 & 2 - Course Introduction & Verilog Basics
1
• FPGA Prototyping with Verilog Examples
Chapter 1: Gate-level Combinational Circuit
• Introduction to Digital ASIC Design - VLSI School
Week 3 - Combinational Logic
2
• FPGA Prototyping with Verilog Examples
Chapter 3: RT-level Combinational Circuit - Sections 3.1:3.5
• Introduction to Digital ASIC Design - VLSI School
Week 4 - Sequential Logic
3
• FPGA Prototyping with Verilog Examples
Chapter 3: RT-level Combinational Circuit - Sections 3.6:3.8
• Introduction to Digital ASIC Design - VLSI School
Week 5 - Finite State Machines
4
• FPGA Prototyping with Verilog Examples
Chapter 3: RT-level Combinational Circuit - Sections 3.9.1:3.9.4
• Introduction to Digital ASIC Design - VLSI School
Week 6 - Testbenches
5
• FPGA Prototyping with Verilog Examples
Chapter 4: Regular Sequential Circuit - Sections 4.1:4.2
• Introduction to Digital ASIC Design - VLSI School
Week 7 - Digital VLSI Flow
6
• FPGA Prototyping with Verilog Examples
Chapter 4: Regular Sequential Circuit - Sections 4.3:4.4
• Week 2
Day
Tasks
• Introduction to Digital ASIC Design - VLSI School
Week 8 - Introduction to Synthesis
1
• FPGA Prototyping with Verilog Examples
Chapter 4: Regular Sequential Circuit - Section 4.5.1
• Introduction to Digital ASIC Design - VLSI School
Week 9 - Course Project
2
• FPGA Prototyping with Verilog Examples
Chapter 4: Regular Sequential Circuit - Sections 4.5.2: 4.5.3
• Introduction to Digital ASIC Design - VLSI School
Week 10 - Practice Test
3
• FPGA Prototyping with Verilog Examples
Chapter 5: FSM - Sections 5.1:5.2
4
• FPGA Prototyping with Verilog Examples
5
• FPGA Prototyping with Verilog Examples
6
Chapter 5: FSM - Sections 5.3.1:5.3.2
Chapter 7: Selected Topics of Verilog - Sections 7.1:7.5
• Week 3
Day
Tasks
1
• Principles of VLSI RTL Design: A Practical Guide
2
• Principles of VLSI RTL Design: A Practical Guide
3
• Principles of VLSI RTL Design: A Practical Guide
4
• Principles of VLSI RTL Design: A Practical Guide
5
• Principles of VLSI RTL Design: A Practical Guide
6
• The Art of Hardware Architecture
Chapter 1: Introduction to VLSI RTL Designs
Chapter 2: Ensuring RTL Intent - Sections 2.1:2.7
Chapter 3: Timing Analysis - Sections 3.1:3.3
Chapter 3: Timing Analysis - Sections 3.4:3.8
Chapter 3: Timing Analysis - Sections 3.9:3.13
Chapter 1: The World of Metastability
• Week 4
Day
Tasks
1
• Principles of VLSI RTL Design: A Practical Guide
2
• Principles of VLSI RTL Design: A Practical Guide
3
• Principles of VLSI RTL Design: A Practical Guide
4
• Principles of VLSI RTL Design: A Practical Guide
5
• Principles of VLSI RTL Design: A Practical Guide
6
• Principles of VLSI RTL Design: A Practical Guide
Chapter 4: Clock Domain Crossing (CDC) - Sections 4.1:4.9
Chapter 5: Power - Sections 5.1:5.7
Chapter 5: Power - Sections 5.8:5.13
Chapter 6: Design for Test (DFT)
Chapter 7: Timing Exceptions
Chapter 8: Congestion
• Week 5
Day
Tasks
1
• Digital ASIC Design with Verilog - Dr. Paul Franzon
2
• Digital ASIC Design with Verilog - Dr. Paul Franzon
3
• Digital ASIC Design with Verilog - Dr. Paul Franzon
4
• Digital ASIC Design with Verilog - Dr. Paul Franzon
5
• Digital ASIC Design with Verilog - Dr. Paul Franzon
6
• Digital ASIC Design with Verilog - Dr. Paul Franzon
Videos 1&2
Videos 3:6 (Introduction)
Videos 7:9 (Timing)
Videos 10:12 (Timing, Clock Domain Crossing)
Videos 13:14 (Verilog11)
Videos 15:17 (Verilog12)
• Week 6
Day
Tasks
1
• Digital ASIC Design with Verilog - Dr. Paul Franzon
2
• Digital ASIC Design with Verilog - Dr. Paul Franzon
3
• Digital ASIC Design with Verilog - Dr. Paul Franzon
4
• Digital ASIC Design with Verilog - Dr. Paul Franzon
5
• Digital ASIC Design with Verilog - Dr. Paul Franzon
6
• Digital ASIC Design with Verilog - Dr. Paul Franzon
Videos 18:21 (Verilog13 & Verilog14)
Videos 22:24 (Verilog21)
Videos 25:27 (Verilog22)
Videos 28:30 (Verilog23)
Videos 31 (Verilog Examples)
Videos 32:34 (Finite State Machine)
• Week 7
Day
Tasks
1
• Digital ASIC Design with Verilog - Dr. Paul Franzon
2
• Digital ASIC Design with Verilog - Dr. Paul Franzon
3
• Digital ASIC Design with Verilog - Dr. Paul Franzon
4
• Digital ASIC Design with Verilog - Dr. Paul Franzon
5
• Digital ASIC Design with Verilog - Dr. Paul Franzon
6
• Digital ASIC Design with Verilog - Dr. Paul Franzon
Videos 35:38 (Complexity)
Videos 39:40 (Partitioning & Techniques)
Videos 41:42 (CPU)
Videos 43:46 (Verify)
Videos 47:48 (Low Power)
Videos 49:50 (DFT)
• Week 8
Day
Tasks
1
• Digital ASIC Design with Verilog - Dr. Paul Franzon
2
• Digital ASIC Design with Verilog - Dr. Paul Franzon
3
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
4
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
5
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
6
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
Videos 51 (FPGA)
Video 52 (Memories)
Lecture 1: Introduction
Lecture 2: Verilog
Lecture 3: Logic Synthesis - Part 1
Lecture 4: Logic Synthesis - Part 2
• Week 9
Day
Tasks
1
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
2
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
3
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
4
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
5
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
6
• Digital VLSI Design (RTL to GDS) - Dr. Adam Teman
Lecture 5: Timing (STA) - 1
Lecture 5: Timing (STA) - 2
Lecture 6: Moving to the Physical Domain
Lecture 7: Standard Cell Placement
Lecture 8: Clock Tree Synthesis
Lectures 9 & 10: Routing & Packaging and I/O Circuits