Line and Code coverage of counter
Verilog Code
//code
module count(a,n,clk);
output [3:0]a;
input [3:0] n;
input clk;
reg [3:0]a;
initial a=4'b000;
always @(posedge clk)
a=(a==n) ?4'b000:a+1'b1;
endmodule
//test bench
// Code your testbench here
// or browse Examples
module counttb;
wire [3:0]a;
reg [3:0] n;
reg clk;
count g1(a,n,clk);
initial
begin
n=4'b1010;
clk=0;
end
always #2 clk=~clk;
initial #40 $stop;
endmodule