System service call SVC
NVIC
Embedded Systems
KRKSastry
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System Service Call
• SVC (System Service Call) and PendSV (Pended System Call) are two exceptions targeted at software and OS.
• SVC is for generating system function calls. Example: instead of allowing user programs to directly access
hardware, an OS may provide access to hardware via an SVC.
• When a user program wants to use certain hardware, it generates the SVC exception using SVC instructions,
and then the software exception handler in the OS is executed and provides the service the user application
requested.
• In this way, access to hardware is under the control of the OS, which can provide a more robust system by
preventing the user applications from directly accessing hardware.
• SVC can also make software more portable because the user application does not need to know the
programming details of the hardware.
• The user program will only need to know the Application Programming Interface (API) function ID and
parameters
• The actual hardware level programming is handled by device drivers
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SVC contd ..
• SVC is generated using the SVC instruction. An immediate value is required for this instruction, which works
as a parameter-passing method. The SVC exception handler can then extract the parameter and determine
what action it needs to perform.
Example: SVC 0x3 ; Call SVC function 3
• When the SVC handler is executed, you can determine the immediate data value in the SVC instruction by
reading the stacked Program Counter value, then reading the instruction from that address and masking out
the unneeded bits.
• If the system uses a PSP for user applications, you might need to determine which stack is used first. This can
be determined from the link register value when the handler is entered.
SVC and SWI (ARM7)
• Traditional ARM processors (such as the ARM7) have a software interrupt instruction (SWI). The SVC has a
similar function, and in fact the binary encoding of SVC instructions is the same as SWI in ARM7. However,
since the exception model has changed, this instruction is renamed to make sure that programmers will
properly port software code from ARM7 to the Cortex-M3.
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SVC as a Gateway for OS Functions
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PendSV
• Due to the interrupt priority model in the Cortex-M3
• you cannot use SVC inside an SVC handler (because the priority is the same as the current priority).
Doing so will result in a usage fault.
• For the same reason, you cannot use SVC in an NMI handler or a hard fault handler.
• PendSV (Pended System Call) works with SVC in the OS.
• Although SVC (by SVC instruction) cannot be pended (an application calling SVC will expect the required task
to be done immediately), PendSV can be pended and is useful for an OS to pend an exception so that an
action can be performed after other important tasks are completed.
• PendSV is generated by writing 1 to the NVIC PendSV pending register.
• A typical use of PendSV is context switching (switching between tasks). Example, a system might have two
active tasks, and context switching can be triggered by:
• Calling an SVC function
• The system timer (SYSTICK)
• Let’s look at a simple example of having only two tasks in a system, and a context switch is triggered by
SYSTICK exceptions
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A Simple Scenario Using SYSTICK to Switch Between Two Tasks
If an interrupt request takes place before the SYSTICK exception, the SYSTICK exception will preempt the
IRQ handler.
In this case, the OS should not carry out the context switching. Otherwise the IRQ handler process will be
delayed, and for the Cortex-M3, a usage fault is generated if OS tries to switch to Thread mode when an
interrupt is active.
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Problem with Context Switching at the IRQ
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• The PendSV exception solves the problem by delaying the context-switching request until all other IRQ handlers have
completed their processing. To do this, the PendSV is programmed as the lowest priority exception. If the OS detects
that an IRQ is currently active (IRQ handler running and preempted by SYSTICK), it defers the context switching by
pending the PendSV exception.
1. Task A calls SVC for task switching (for example, waiting for some work to complete).
2.
The OS receives the request, prepares for context switching, and pends the PendSV exception.
3.
When the CPU exits SVC, it enters PendSV immediately and does the context switch.
4.
When PendSV fi nishes and returns to Thread level, it executes Task B.
5.
An interrupt occurs and the interrupt handler is entered.
6.
While running the interrupt handler routine, a SYSTICK exception (for OS tick) takes place.
7.
The OS carries out the essential operation, then pends the PendSV exception and gets ready for the context switch.
8.
When the SYSTICK exception exits, it returns to the interrupt service routine.
9.
When the interrupt service routine completes, the PendSV starts and does the actual context switch operations.
10. When PendSV is complete, the program returns to Thread level; this time it returns to Task A and continues the
processing.
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NVIC
• The Nested Vectored Interrupt Controller, or NVIC, is an integrated part of the Cortex-M3 processor. It is
closely linked to the Cortex-M3 CPU core logic. Its control registers are accessible as memory-mapped
devices.
• Besides control registers and control logic for interrupt processing, the NVIC also contains control registers
for the MPU, the SYSTICK Timer, and debugging controls..
• The NVIC supports upto 240 external interrupt inputs (IRQs). The exact number of supported interrupts is
determined by the chip manufacturers when they develop their Cortex-M3 chips.
• In addition, the NVIC also has a Non-maskable Interrupt (NMI) input. The actual function of the NMI is also
decided by the chip manufacturer. In some cases this NMI cannot be controlled from an external source. The
NVIC can be accessed as memory location 0xE000E000.
• Most of the interrupt control status registers are accessible only in privileged mode, except the Software
Trigger Interrupt register, which can be set up to be accessible in user mode.
• The interrupt control/status register can be accessed in word, half word, or byte transfers.
• The “special registers” are accessed via MRS and MSR instructions.
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The Basic Interrupt Configuration
• Each external interrupt has several registers associated with it: Enable and clear enable registers, Setpending and clear-pending registers, Priority level, Active status
• In addition, a number of other registers can also affect the interrupt processing:
• Exception-masking registers (PRIMASK, FAULTMASK, and BASEPRI)
• Vector Table Offset register
• Software Trigger Interrupt register
• Priority Group
Interrupt Enable and Clear Enable
• The Interrupt Enable register is programmed via two addresses. To set the enable bit, you need to write to
the SETENA register address; to clear the enable bit, you need to write to the CLRENA register address.
• enabling or disabling an interrupt will not affect other interrupt enable states. The SETENA/CLRENA registers
are 32 bits wide; each bit represents one interrupt input.
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Interrupt Pending and Clear Pending
• If an interrupt takes place but cannot be executed immediately (for instance, if another higher-priority
interrupt handler is running), it will be pended.
• The interrupt pending status can be accessed through the Interrupt Set Pending (SETPEND) and Interrupt
Clear Pending (CLRPEND) registers. Similarly to the enable registers, the pending status controls might
contain more than one register if there are more than 32 external interrupt inputs.
• The pending status registers can be changed, so you can cancel a current pended exception or generate
software interrupts via the SETPEND register.
Priority Levels
• Each external interrupt has an associated priority-level register, which has a maximum width of 8 bits and a
minimum width of 3 bits. Each register is further divided into preempt priority level and sub-priority level
based on priority group settings. The priority-level registers can be accessed as byte, half word, or word.
• The number of priority-level registers depends on how many external interrupts the chip contains.
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Active Status
• Each external interrupt has an active status bit.
• When the processor starts the interrupt handler, the bit is set to 1 and cleared when the interrupt return is
executed.
• However, during an interrupt service routine execution, a higher-priority interrupt might occur and cause a
preemption. During this period, despite the fact that the processor is executing another interrupt handler, the
previous interrupt is still defined as active.
• The active registers are 32-bit but can also be accessed using half word or byte-size transfers. If there are more
than 32 external interrupts, there will be more than one active register. The active status registers for external
interrupts are read-only.
PRIMASK and FAULTMASK Special Registers
• The PRIMASK register is used to disable all exceptions except NMI and hard fault.
• It effectively changes the current priority level to 0 (highest programmable level). This register is programmable
using MRS and MSR instructions.
• MOV R0, #1
• MSR PRIMASK, R0 ; Write 1 to PRIMASK to disable all ; interrupts
• MOV R0, #0
• MSR PRIMASK, R0 ; Write 0 to PRIMASK to allow interrupts
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• PRIMASK is useful for temporarily disabling all interrupts for critical tasks. When PRIMASK is set, if a fault takes
place, the hard fault handler will be executed.
• FAULTMASK is just like PRIMASK except that it changes the effective current priority level to 1 so that even the hard
fault handler is blocked. Only the NMI can be executed when FAULTMASK is set.
• FAULTMASK is cleared automatically upon exiting the exception handler. Both FAULTMASK and PRIMASK registers
cannot be set in the user state.
• In some cases you might want to disable interrupts only with priority lower than a certain level. In this case, you
could use the BASEPRI register. To do this, simply write the required masking priority level to the BASEPRI register.
For example, if you want to block all exceptions with priority level equal to or lower than 0x60, you can write the
value to
BASEPRI:
• MOV R0, #0x60
• MSR BASEPRI, R0 ; Disable interrupts with priority ; 0x60-0xFF
• To cancel the masking, just write 0 to the BASEPRI register:
• MOV R0, #0x0
• MSR BASEPRI, R0 ; Turn off BASEPRI masking
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BASEPRI
• The BASEPRI register can also be accessed using the BASEPRI_MAX register name. It is actually the same register,
but when you use it with this name it will give you a conditional write operation. (As far as hardware is concerned,
BASEPRI and BASEPRI_MAX are the same register, but in the assembler code they use different register name
coding.)
• When you use BASEPRI_MAX as a register, it can only be changed to a higher priority level; it cannot be changed to
lower priority levels. Example , instruction sequence:
1. MOV R0, #0x60
2. MSR BASEPRI_MAX, R0 ; Disable interrupts with priority ; 0x60, 0x61,..., etc
3. MOV R0, #0xF0
4. MSR BASEPRI_MAX, R0 ; This write will be ignored because it is lower level than 0x60
5. MOV R0, #0x40
6. MSR BASEPRI_MAX, R0 ; This write is allowed and change the masking level to 0x40
• To change to a lower masking level or disable the masking, the BASEPRI register name should be used. The
BASEPRI/ BASEPRI_MAX register cannot be set in the user state.
• As with other priority-level registers, the formatting of the BASEPRI register is affected by the number of
implemented priority register widths. For example, if only 3 bits are implemented for priority-level registers,
BASEPRI can be programmed as 0x00, 0x20, 0x40 … 0xC0, 0xE0.
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SYSTICK Timer
• It is integrated with the NVIC and can be used to generate a SYSTICK exception (exception type #15).
• In many operating systems, a hardware timer is used to generate interrupts so that the OS can carry out task
management—for example, to allow multiple tasks to run at different time slots and to make sure that no
single task can lock up the whole system.
• To do that, the timer needs to be able to generate interrupts, and if possible, it should be protected from
user tasks so that user applications cannot change the timer behavior.
• The Cortex-M3 processor includes a simple timer. Since all Cortex-M3 chips have the same timer, porting
software between different Cortex-M3 products is simplified.
• The timer is a 24-bit down counter. It can use the internal clock (FCLK, the free running clock signal on the
Cortex-M3 processor) or external clock (the STCLK signal on the Cortex-M3 processor).
• However, the source of the STCLK will be decided by chip designers, so the clock frequency might vary
between products. You should check the chip’s datasheet carefully when selecting a clock source.
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SYSTICK Control and Status Register (0xE000E010)
• The SYSTICK Timer can be used to generated interrupts. It has a dedicated exception type and exception
vector. It makes porting operating systems and software easier because the process will be the same across
different Cortex-M3 products.
• The SYSTICK Timer is controlled by four registers.
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SYSTICK Timer contd ..
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SYSTICK Timer contd ..
• The Calibration Value register provides a solution for applications to generate the same SYSTICK interrupt
interval when running on various Cortex-M3 products.
• To use it, just write the value in TENMS to the reload value register. This will give an interrupt interval of
about 10 ms.
• For other interrupt timing intervals, the software code will need to calculate a new suitable value from the
calibration value.
• The TENMS field might not be available in all Cortex-M3 products (the calibration input signals to the CortexM3 might have been tied low), so check with your manufacturer’s datasheets before using this feature.
• Aside from being a system tick timer for operating systems, the SYSTICK Timer can be used in a number of
ways:
• as an alarm timer,
• for timing measurement, and more.
• The SYSTICK Timer stops counting when the processor is halted during debugging.
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