Uploaded by Mani Vannan

RTL

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DSP:1
STACK
OPCODE_id(40:0)
ADD_GEN
STACK_out(40:0)
OPCODE_id(40:0)
WRITE_CONTROL
ADD_out(48:0)
DATA_in(48:0)
CLK
CLK
CLK
DATA_WRITE_COMPLETE(4:0)
RST
RST
RST
CLK
DATA_out(40:0)
RAM_BLOCK
DATA_in(40:0)
PROGRAM_MEMORY1
DATA_out(40:0)
PROM_in(40:0)
rd_add(7:0)
CLK
wr_add(7:0)
wr_add(7:0)
ALU
CONTROL_UNIT
ALU_sel(2:0)
A(15:0)
DATA_out(31:0)
B(15:0)
B(15:0)
OP_id(4:0)
DATA_id(4:0)
DSP_sel(3:0)
INTERRUPT_COMPLETE(4:0)
A(15:0)
INTERRUPT_COUNTER(4:0)
INTERRUPT_COUNTER(4:0
OUTA(31:0)
OUTA(31:0)
OUT_MAC(31:0)
OUT_MAC(31:0)
OUT_SHIFT_ID(15:0)
OUT_SHIFT_ID(15:0)
INTERRUPT
RST
ST
wr_en
ADGN
CLK
OPCODE_id_out(4:0)
RST
CLK_2
CTRL
INTERRUPT_out
rd_en
SELECT(2:0)
OUT(31:0)
CLK
INTERRUPT_COMPLETE_ALU(4:0)
INTERRUPT_COMPLETE_DSP(4:0)
INTERRUPT
PM
RST
wr_en
OPCODE(3:0)
RST
PROCESS_COMPLETE(4:0)
OUT_a(31:0)
DATA_WRITE_COMPLETE(4:0)
PROCESS_COMPLETE(4:0)
OUT_mac(31:0)
A16
RB
PROCESS_COUNTER(4:0)
PROCESS_COUNTER(4:0)
REQUEST_COUNTER(4:0)
REQUEST_COUNTER(4:0)
OUT_sid(15:0)
PROCESS_COMPLETE_ALU(4:0)
PROCESS_COMPLETE_DSP(4:0)
STACK_in(40:0)
CLK
INTERRUPT
CLK_2
RST
CU
EXECUTE
A(15:0)
A(15:0)
B(15:0)
B(15:0)
OPCODE(3:0)
DATA_id(4:0)
OPCODE_id(4:0)
A(15:0)
INTERRUPT_COMPLETE(4:0)
B(15:0)
DATA_in(40:0)
OPCODE(3:0)
DSP_UNIT
ALU_in(2:0)
DATA_out(40:0)
OP_id(4:0)
OUT_M(31:0)
SELECT(3:0)
DSP_in(3:0)
PROCESS_COMPLETE(4:0)
CLK
OUT_S_ID(15:0)
INTERRUPT
SEL_in(2:0)
rd_add(7:0)
RST
PROCESS_COMPLETE(4:0)
SEQ_in(3:0)
CLK
INTERRUPT
INTERRUPT_out
INTERRUPT
RST
rd_en
EX
DSP
DSP
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