module EXECUTE(CLK, RST,
DATA_in_REQ, DATA_in_INT,DATA_in_PROM, PROCESS_COMPLETE, INTERRUPT_COMPLETE,
DATA_out,DATA_out_ALU_DSP, ALU_in, DSP_in, ALU_out,DSP_out, rd_en_REQ, rd_add_REQ, rd_en_INT, rd_add_INT);
input CLK,RST;
input [41:0]DATA_in_REQ,DATA_in_INT,DATA_in_PROM;
input [3:0]DSP_in;
input [2:0]ALU_in;
input [5:0]PROCESS_COMPLETE,INTERRUPT_COMPLETE;
output reg [41:0]DATA_out,DATA_out_ALU_DSP;
output reg [3:0]DSP_out;
output reg [2:0]ALU_out;
output reg rd_en_REQ,rd_en_INT;
output reg [7:0]rd_add_REQ,rd_add_INT;
reg [7:0]j,i; reg [1:0]STATE_I;
reg [2:0]STATE_REQ,STATE_INT;
reg [5:0]DATA_in_old_INT,DATA_in_old_REQ; always @ (posedge CLK)
begin
if (RST)
begin
{DATA_out,rd_en_REQ,rd_en_INT,rd_add_REQ,rd_add_INT,STATE_I,STATE_REQ,STATE_INT,
DATA_out_ALU_DSP,DSP_out,ALU_out,DATA_in_old_INT,DATA_in_old_REQ,i,j}=0;
end
else begin
{DATA_out_ALU_DSP,DSP_out,ALU_out}={DATA_in_PROM,DSP_in,ALU_in};
case(STATE_I)
2'b00:begin
rd_en_INT = 1'b1;
rd_add_REQ = i;
if (DATA_in_INT[1] == 0) STATE_I = 2'b01;
else STATE_I = 2'b10;
end
2'b01:begin
case (STATE_REQ)
3'b000 : begin
rd_en_REQ = 1'b1;
rd_add_REQ = j; if(DATA_in_old_REQ != DATA_in_REQ[5:0]) begin
DATA_in_old_REQ = DATA_in_REQ[5:0]; STATE_REQ = 3'b001;
STATE_I = 2'b0;
end
else begin STATE_REQ = 3'b000; STATE_I = 2'b0; end
end
3'b001 : begin
rd_en_REQ = 1'b0;
DATA_out = DATA_in_REQ;
if(PROCESS_COMPLETE == DATA_in_old_REQ) begin
j=j+8'b00000001;
STATE_REQ = 3'b010;
STATE_I = 2'b0;
end
else begin STATE_REQ = 3'b001; STATE_I = 2'b0; end
end
3'b010 : begin
rd_en_REQ = 1'b1;
rd_add_REQ=j;
if((DATA_in_REQ[5:0] != DATA_in_old_REQ)&&(DATA_in_REQ[5:0] != 5'b0))
begin DATA_in_old_REQ=DATA_in_REQ[5:0]; STATE_REQ = 3'b001; STATE_I = 2'b0;
end
else begin STATE_REQ = 3'b010; STATE_I = 2'b0; end
end endcase
end
2'b10:begin
case (STATE_INT)
3'b000 : begin
rd_en_INT = 1'b1;
rd_add_INT = i; if(DATA_in_old_INT != DATA_in_INT[5:0]) begin
DATA_in_old_INT = DATA_in_INT[5:0]; STATE_INT = 3'b001;
STATE_I = 2'b0;
end
else begin STATE_INT = 3'b000; STATE_I = 2'b0; end
end
3'b001 : begin
rd_en_INT = 1'b0;
DATA_out = DATA_in_INT;
if(INTERRUPT_COMPLETE == DATA_in_old_INT) begin
i=i+8'b00000001;
STATE_INT = 3'b010; STATE_I = 2'b0;
end
else begin STATE_INT = 3'b001; STATE_I = 2'b0; end
end
3'b010 : begin
rd_en_INT = 1'b1;
rd_add_INT=i;
if((DATA_in_INT[5:0] != DATA_in_old_INT)&&(DATA_in_INT[5:0] != 5'b0))
begin DATA_in_old_INT=DATA_in_INT[5:0]; STATE_INT = 3'b001;
STATE_I = 2'b0;
end
else begin STATE_INT = 3'b010; STATE_I = 2'b0; end
end endcase
end
endcase
end
end
endmodule