Introduction to Xilinx System Generator PRESENTED BY DR G GANESH KUMAR ASSISTANT PROFESSOR SNIST Contents Introduction to Xilinx System Generator Installation and Setup of Design Tools Introduction to Simulink and Xilinx Blockset Xilinx System Generator Design Flow Creating Simulink and System Generator Designs HDL Co-Simulation Hardware Verification Summary Xilinx System Generator System Generator is a DSP design tool from Xilinx® that enables the use of the MathWorks model-based Simulink® design environment for FPGA design. Previous experience with Xilinx FPGAs or RTL design methodologies are not required when using System Generator. Designs are captured in the DSP friendly Simulink modeling environment using a Xilinx specific blockset. System Generator provides a system integration platform for the design of DSP FPGAs that allows the RTL, Simulink®, MATLAB® and C/C++ components of a DSP system to come together in a single simulation and implementation environment. System Generator supports a black box block that allows RTL to be imported into Simulink and co-simulated with either ModelSim or Xilinx® Vivado® simulator, and provides a Vitis™ HLS block that allows integration and simulation of C/C++ sources Installation and Setup of Design Tools System Generator for DSP is a part of the Vivado Design Suite. You must use the Xilinx Design Tools installer to install System Generator. Before invoking the Xilinx Design Tools installer, it is a good idea to make sure that all instances of MATLAB® are closed. When all instances of MATLAB are closed, launch the installer Choosing MATLAB for System Generator Supported MATLAB for System Generator versions Introduction to Simulink and Xilinx Blockset Simulink, which runs in MATLAB, is an interactive tool for modeling, simulating, and analyzing dynamical systems. The Xilinx System Generator, a high-performance design tool, runs as part of Simulink. The System Generator elements bundled as the Xilinx Blockset, appear in the Simulink library browser MATLAB The MathWorks MATLAB provides a technical computing environment that facilitates rapid exploration of mathematical solutions to systems problems Extensive libraries for math functions, signal processing, DSP, communications, and much more Visualization: Large array of functions to plot and visualize your data and system and design Simulink Visual Data Tool The MathWorks Simulink provides a model-based design environment for the development of executable specs of dynamic systems Fully integrated with the MATLAB engine Graphical block editor Event-driven simulator Models parallelism Extensive library of parameterizable functions Simulink blockset: math, sinks, and sources DSP blockset: filters or transforms, for example Communications blockset: modulation or DPCM, for example Simulink Blockset Xilinx Blockset Overview of System Generator for DSP The industry’s system-level design environment (IDE) for FPGAs Integrated design flow from the Simulink software to the BIT file Leverages existing technologies MATLAB , Simulink HDL synthesis IP Core libraries FPGA implementation tools Simulink library of arithmetic, logic operators, and DSP functions (Xilinx blockset) BIT and cycle-true to FPGA implementation Arithmetic abstraction Arbitrary precision fixed-point, including quantization and overflow Simulation of double precision as well as fixed point Overview of System Generator for DSP VHDL and Verilog code generation for Zynq™, Virtex™- 7, Virtex-6, Virtex-5, Virtex-4, Spartan™6, Spartan-3E, and Spartan-3 family devices Hardware expansion and mapping Synthesizable VHDL and Verilog with model hierarchy preservation Mixed-language support for VHDL/Verilog Automatic invocation of the CORE Generator software to utilize IP cores ISE project generation to simplify the design flow HDL testbench and test vector generation Constraint file (XCF), simulation DO file generation HDL co-simulation via HDL C-simulation Verification acceleration by using hardware-in-the-loop through Parallel Cable IV, Platform Cable USB, and Network-based as well as Point-to-Point Ethernet connections System Generator Design Flow Simulink Software Verification HDL Co-simulation Verification Hardware Co-Simulation Verification Create Simulink Design Sine wave block wired to Scope output block Generating Sine Wave Double click on the sine wave block set and change the frequency to “2*pi/150”. Click on the run simulation Output Interacting with System Generator Design Gateway In Gateway Out System Generator Token Creating a System Generator Design
