Creating a MAC Using the Xilinx System Generator Lab
Introduction
In this lab, you will create a MAC (Multiplier Accumulator) with a multiplier and an accumulator using System
Generator for DSP, and estimate the resource utilization using the Resource Estimator block of the System
Generator. After simulating the design in Simulink, you will generate VHDL code and cores from this design,
and implement the MAC in the Xilinx Vivado Foundation development software.
Objectives
After completing this lab, you will be able to:
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Create and simulate a design in System Generator
Run the System Generator token to generate VHDL code
Run designs through the System Generator design flow
Implement the design in Xilinx Vivado software environment and generate a bit stream file
Software
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Vivado 2018.2
Matlab2017b
Design Description
Use System Generator under Simulink environment running under MATLAB to create a MAC:
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Multiplier input data widths of 12 bits and 8 bits of signed data
Multiplier output width of 20 bits
Accumulator output width of 27-bits
Procedure
This lab is separated into steps that consist of general overview statements that provide information on the
detailed instructions that follow. Follow these detailed instructions to progress through the lab.
This lab comprises 6 primary steps: You will introduce Xilinx Blocks, analyze precision and sample rate,
create a MAC using Xilinx blocks, configure and simulate the MAC, and, finally, generate the HDL code.
Note: If you are unable to complete the lab at this time, you can download the lab files for this module from
the Xilinx University Program site at http://www.xilinx.com/university
General Flow for this Lab
Step 1:
Introduce
the Xilinx
Blockset
Step 4:
Configure
the Design
Step 2:
Evaluate the
precision and
analyze the
effect on output
Step 5:
Estimate the
Resources
Step 3:
Designing a
12 x 8
MAC
Step 6:
Generate
the VHDL
Core
Introduce Xilinx Blockset
1-1.
Step 1
Start MATLAB and change working directory to lab2. Open a Simulink
Browser. Become familiar with the blocks in the Xilinx blockset by creating
a simple design that includes sine wave source, gateway in/out blocks, and
a scope sink.
1-1-1. Start MATLAB program by clicking: Start > All Programs > Xilinx Design Tools > Vivado
2014.4 > System Generator > System Generator.
1-1-2. Change to the lab2 directory: type cd c:/xup/dsp_flow/labs/lab2 in the command window.
1-1-3. Type simulink at the MATLAB command prompt or open the Simulink Library Browser by
clicking the corresponding button in the MATLAB toolbar.
1-1-4. Look at the blocks available in the Simulink Library Browser. The following blocksets, among
others, should appear:
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Simulink (sources and sinks)
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Signal Processing Blockset
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Xilinx Blockset
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Xilinx Reference Blockset
1-1-5. Create a “new model” blank sheet by clicking the Create a new model button of the Simulink
Library Browser.
Figure 1. Create New Model.
1-2.
Create a design using Xilinx Gateway I/O and System Generator blocks.
1-2-1. Add the Sine Wave (set frequency to 2*pi*1/150) source and Scope sink from the Simulink
library and connect them together.
1-2-2. From the Xilinx Blockset (in the Simulink Library Browser), open Basic Elements and drag
the Gateway In block onto the design sheet. Drop it on the connection between the Sine Wave
and the output Scope. It will automatically insert itself.
1-2-3. Double-click Gateway In to open the Block Parameters, and set the Number of bits to 8 and
Binary Point to 2.
1-2-4. Verify that Quantization is set to round, and overflow to saturate.
1-2-5. Similarly, drag a Gateway Out block onto the sheet, and drop it between the Gateway In block
and the output Scope block.
Figure 5. Drag Gateway In and Gateway Out Blocks.
1-2-6. Add a Simulink MUX between the Gateway Out and the Scope by using Simulink > Signal
Routing (see Figure 2).
1-2-7. Add an additional net between the Sine Wave and the MUX (see Figure 2).
Note: This will make the scope display both the double-precision sine wave and the user-defined
precision sine wave that has gone into and back out of the Xilinx gateways
1-2-8. Add a system generator token from the Xilinx Blockset > Basic Elements library to the design.
1-2-9. To view the number of signals going into the MUX, select Wide Nonscalar Lines, Signal
dimensions, and Port data types under the Other Displays >Signals & Ports menu.
1-2-10. Update the diagram: select Edit > Update Diagram.
Note: Now look at your port types. Notice that the gateway in block has changed the signals from
double-precision to fixed-point types. Fixed-point looks like Fix_8_2 in this case.
Figure 2. Gateway In and Out with MUX.
Analyze Precision and Sample Rate
2-1.
Step 2
Analyze the precision on a sine wave after modifying the gateway in
quantization/ overflow options and sampling period.
2-1-1. Using Simulation > Model Configuration Parameters dialog box, set the stop time to 500, and
click OK.
2-1-2. Run the simulation and observe a jagged sine wave adjacent to the smooth sine wave, indicating
quantization effects (the difference between the double precision floating point of MATLAB and
the fixed point FIX_8_2 of the block).
Figure 3. Quantization Effects
2-1-3. Double-click Gateway In, change the Output Data Type parameter to Unsigned from Signed,
and click Apply.
2-1-4. Run the simulation and observe the scope output.
Note: Because the value is unsigned, the negative portion of the sine wave is saturated to zero.
Figure 4. Unsigned Data, Wrap Overflow, Truncate Quantization Output
2-1-5. Change the Quantization to truncate, the output type to Signed, and simulate.
Figure 5. Signed data, Saturate Overflow, Truncate Quantization
2-1-6. Reduce some of the quantization error by changing the binary point from two to six, click apply,
and run the simulation.
Note: You will see a smoother sine wave because more of the quantization error has been
removed. The number of fractional bits was increased from two to six.
Figure 6. Reduced Quantization Error with Increased Number of Fractional Bits
2-1-7. Change the sample period from one to five, click Apply, and run the simulation.
Click close when a message appears indicating a more efficient sample rate setting for the
Simulink System Period of the System Generator token. The message indicates that the system
clock will run 5 times faster than the System Generator design.
Figure 7. Warning Message indicating to update Simulink System Period
Figure 8. Signed Data, Saturate Overflow, Truncate Quantization Output
Note: As the sample period is increased (that is, the sampling is fewer times), the quantization
error is increased.
2-2.
Analyze the precision of a ramp function after increasing the sample
period.
2-2-1. Replace the sine wave source with the ramp function from the Simulink Sources.
2-2-2. Open the Configuration Parameters dialog box.
2-2-3. Change the Stop Time to 100, and click OK.
2-2-4. Change the Binary Point to 0 and the Sample Period to 10 for the Gateway In block.
2-2-5. Click Apply, and run the simulation.
You will get the warning. Click Close. Observe the output - the ramp is coarse due to slow sampling
period.
Figure 9. Ramp Source, Sampling Period 10
2-2-6. Change the Gateway In Sample Period to 1 and run the simulation.
You will see the ramp is smoother as sampling period has improved.
Figure 10. Ramp Source, Sampling Period 1
2-2-7. Close the worksheet. You do not need to save the worksheet.
Create a MAC Using Xilinx Blocks
3-1.
Step 3
Create a MAC in Simulink using Xilinx blocks according to Figure 11.
Figure 11. The 12 x 8 MAC Using Xilinx Blockset
3-1-1. In the project sheet, select File > New > Model.
A new Simulink project opens.
3-1-2. Add two ramp inputs and a step function to the worksheet.
Figure 12. Input Sources for the MAC
3-1-3. Change step function input to have initial value to 1 and final value to 0.
This will drive the reset of the accumulator.
3-1-4. Add Xilinx Gateway In blocks to the three inputs and wire them up.
Figure 13. Gateway In blocks connected for the three Simulink sources
3-1-5. Add delay blocks (improve FPGA performance) from the Xilinx Basic Elements library and
connect them to the gateway in blocks.
Figure 14. Add Registers for Performance
3-1-6. Add the multiplier and the accumulator from the Xilinx Math library and wire them up.
Figure 15. Add the Multiplier and the Accumulator
3-1-7. Add the output delay block and connect it to the output of the accumulator.
Figure 16. Add Output Delay for Performance
3-1-8. Add a gateway out block and connect it to the delay block.
3-1-9. Add and connect Scopes to the gateway out and Mult inputs (Ramp inputs after delay) so you
can monitor both input and output
The final diagram should look like the figure below.
Figure 17. Add Gateway Out and Scopes
3-1-10. Add the System Generator block to the design.
Configure the inputs and simulation parameters as specified below. Next,
simulate the MAC in Simulink and verify the design functionality
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Configure the first gateway in1 as 12-bits, binary point 0, data type signed, and sampling
period 1.
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Configure the second gateway in2 as 8-bits, binary point 0, data type signed, and sampling
period 1.
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Set the third gateway in3 to Boolean data type.
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Configure the multiplier block with latency of 3 and Use embedded multipliers (in
Implementation tab) option box checked.
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Configure the accumulator Number of bits to 27, and set the Overflow method to Wrap.
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Open the Model Configuration Parameters dialog and set the Stop Time to 2500.
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Add a System Generator token to the design.
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Run the simulation and analyze the results.
Figure 18. Simulink Output with Multiplier Having Maximum Pipelining
Using Hardware Co-simulation
System Generator provides hardware co-simulation, making it possible to incorporate a design
running in an FPGA directly into a Simulink simulation. "Hardware Co-Simulation" compilation
targets automatically create a bitstream and associate it to a block. When the design is simulated
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Open a System Generator model, then open the System Generator token. This populates
the token with all the available compilation targets. You will now see the compilation
target Zedboard on the System Generator token as shown below.
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Select Zedboard. Under the Part menu, you will see the only valid available device is
selected by default.
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Click Generate. The compilation status shows as follows
After generation completed click OK
You will see that the Hardware co-Simulation block is generated.
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Copy the generated hwcosim_lib by right clicking on it and paste it on the main model
and do the connections as follows:
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Double-click on the JTAG Co-sim block, it shows as follows
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Click on advance and uncheck the Reset Zynq board before configuration
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Click on Cable and it should appears as follows
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Click Apply and OK
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Now the design is ready for Co-Simulation. Click the Start Simulation button in the model window
toolbar to start the Co-Simulation.
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The System Generator will first download the bitstream associated with the block "JTAG Co-sim".
When the download completes, System Generators reads the inputs from Simulink simulation
environment and send them to the design on the board using the JTAG connection. System
Generator then reads the output back from JTAG and sends it to Simulink for displayed.
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After the simulation is completed, we can verify the results by comparing the simulation output to
the hardware output on the scopes.