FinFET, Nano-Sheet cell design ,
Now & Road Ahead
An educational perspective
Etienne SICARD
Professor INSA University of
Toulouse, France
DAY 3
FUTURE TRENDS IN 3-NM NANOSHEET CELL DESIGN
Contents
Contents
 Context
 Nano-Sheet FET
 Microwind
 Designing with Nano-Sheet
 Ring Oscillator
 Examples
 Node 2nm/20Å
 Node 1.5nm/15Å
 Discussion & Conclusion
31/08/2023
INSA Toulouse
4
References
 Open archive on 3-nm Nano-Sheet implementation in
Microwind
 Based on 15 scientific references
 https://hal.science/hal-03377556
References
 Han, W., & Wang, Z. M. (Eds.).
(2013). Toward Quantum FinFET (pp.
54-67). Springer.
 Chauhan, Y. S., (2015). FinFET
modeling for IC simulation and
design. Elsevier Science.
 Saha, S. K. (2020). FinFET Devices for
VLSI Circuits and Systems. CRC Press.
 Nanowires, Recent Progress - Xihong
Peng IntechOpen - (2021)
https://www.intechopen.com/books/10071
Context
FUTURE TRENDS IN 3-NM NANOSHEET CELL DESIGN
Context
 Nano-Sheet (NS), Gate-All-Around (GAA), Muti-Bridge-Channel (MCB) ,
RibbonFET announced in all roadmaps
 Samsung first
 TSMC & Intel should follow
20-50 times smaller
This Talk
100
mm2
50
Logic
Memory
45 nm
IO
FET
mm2
Logic
Memory
32 nm
NanoSheet
FINFET
MOSFET
19 mm2
I
O
Logic
I
O
Memory
20 nm
10 mm2
Logic
Memo
ry
I
O
14 nm
5 mm2 3 mm2
2 mm2 1,5 mm2 1 mm2 0,5 mm2
Logic
Memor
y
I
O
Logic
Memory
I
O
Logic
I
O
Memory
10 nm 7 nm 5 nm
L
o
gi
M
c
e
m
or
y
I
O
L
o
g
M
i
e
c
m
o
r
y
I
O
L
o
g
M
ei
c
m
I
O
o
r
y
3 nm 2 nm 1 nm
Context
 “The technology
node represents
the minimum
feature size” is not
Minimum feature
valid anymore
 3nm node has
8nm minimum
feature size;
 Nearly impossible
to fabricate layers
below 5nm (50Å,
30 Si atoms)
This Talk
size
3NM : 8nm
100
Expected 3nm
10
1
130
nm
90
65
45
32
Node
20
14
10
7
5
3
2
1
Context
 Principles: gain space, improve speed and save power, without significant
shrinking of the technology
 Gain Space: 8T, 7T, 5T, 4T, 2T…
 Improve Speed: FinFET replaced by Nano-sheet FET
 Save power: reduce capacitance, reduce resistance
Context
 IMEC scaling roadmap showing the saturation of horizontal scaling “Contacted
Gate Pitch” (CGP), but reduction of cell height (CH)
This Talk
Weckx, P., (2019, December). Novel forksheet device
architecture as ultimate logic scaling device towards 2nm. In
2019 IEEE International Electron Devices Meeting (IEDM)
(pp. 36-5). IEEE.
Context
 Traditional 7 Tracks (old style design) vs. 5 tracks (3NM design)
 Less space for internal routing (Dlatch, Complex gates)
 Less space for large width (4-8 λ, not more)
Nanosheet FET
This Talk
 Going 3D
[Huang 2020] Huang, V., Shim, D., Simka, H., & Naeemi, A. (2020,
December). From Interconnect Materials and Processes to Chip Level
Performance. In 2020 IEEE International Electron Devices Meeting
(IEDM) (pp. 32-6). IEEE.
This
talk
Nanosheet FET
Gate
Gate
Gate
Source
Source
Drain
Drain
Source
Drain
W
Nanosheet
Fi
n
MOS FET
Fin FET
Nano-Sheet FET
T
H
W
Weq=W
H
T
Weq=2 H+T
Weq=6H+6T
Nanosheet FET
-30%
 The difficulty to scale down
furthermore obliges
semiconductor industry to gain
space through device innovation
-50%
1mA
 FinFET is better, smaller, faster,
more efficient that MOSFet
 NanoSheet FET is event better,
smaller, faster & more efficient
 3D-NanoSheet FET should be
even better (2025, 1.5nm/15Å)
-75%
1mA
1mA
MosFET
FinFET
NSFET
1mA
3D-NSFET
Nanosheet FET
Highest current is
the best
Current
(log)
 We want more current (ION),
with less leakage (IOFF),
within a reduced silicon area
0=no
channel
ION 1mA
1
0
1
FinFET
NSFET
IOFF
ION
NSFET
FinFET
MosFET
1=channel
MosFET
0
Voltage
(Lin)
IOFF 1nA
Lowest leakage is
the best
NanoSheet FET
MOS
Complementary
FET
High K Metal Gate to
increase field effect
Current drive
(mA/µm)
Nano-Sheet
FET
FinFET for increasing
drive current and
reducing leakage
Strain to increase
mobility
2.5
FINFET
2.0
MOSFET
1.5
1.0
Ioff:
100nA/µm
10nA
1 nA
0.5
0.0
130
Intrinsic perf.
90
65
Gate material
45
32
Strain
20
14
10
7
Technology node (nm)
5
3
20A
18A
NSFET
15A
10A
CFET
Nanosheet FET
3NM vs 5NM
 At the same frequency, consume less power per stage
 At the same power dissipation, go faster
Wang, M., et al. (2020, November). Design Technology CoOptimization for 3 nm Gate-All-Around Nanosheet FETs. In 2020
IEEE 15th ICSICT
Nanosheet FET
 Search for a successor to
MOSFet started in
1991
1990’s
Hisamoto, D., Kaga, T., & Takeda, E.
(1991). Impact of the vertical
SOI'DELTA'structure on planar device
technology. IEEE Transactions on
Electron Devices, 38(6), 1419-1424.
2004
Sung-Young Lee et al., "A novel sub-50 nm
multi-bridge-channel MOSFET (MBCFET) with
extremely high performance," Digest of
Technical Papers. 2004 Symposium on VLSI
Technology, 2004. (Samsung)
Nanosheet FET
 Search for a successor to FinFET
2011
Ernst, T., (2011). Ultra-dense silicon nanowires:
A technology, transport and interfaces
challenges insight. Microelectronic
Engineering, 88(7), 1198-1202.
2020
Huang, C. Y., (2020, December). 3-D Selfaligned stacked NMOS-on-PMOS nanoribbon
transistors for continued Moore’s law scaling.
In 2020 IEEE IEDM
Nanosheet FET
 https://www.anandtech.com/show/16815/samsung-deployment-of-3nm-gae-ontrack-for-2022
“We reached out to Samsung and a
representative confirmed that the
3GAE [Early] technology is still on
track for ramp in 2022. From the slide,
we can see that MBCFET-based
3GAP [Production] will enter its HVM
phase sometime in 2023.”.
Nanosheet FET
 https://www.anandtech.com/show/16639/tsmc-update-2nm-in-development-3nm-4nm-on-trackfor-2022
“In 2022, the world's largest contract
maker of chips will roll out its brandnew N3 manufacturing process, which
will keep using FinFET transistors”
“Gate-all-around FETs (GAAFETs)
are still a part of TSMC's development
roadmap. The company is expected to
use a new kind of transistors with its
'post-N3' technology (presumably N2)”.
Nanosheet FET
 https://www.intel.com/content/www/us/en/newsroom
• Intel 20A has initiated the angstrom
era with two breakthrough
technologies:
• RibbonFET ™ (NS-FET)
• PowerVia™ (Back-Side Power
delivery).
• Starting 2024
• Intel 18A delivers an additional 10%
improvement (End 2024). Shrink in
feature sizes (State of the art ASML
lithography Twinscan 0.55 NA, 8nm
resolution)
• Intel Next could introduce stacked
N & P (CFET)
Intel
Nanosheet FET
 The number of NS
seems confidential
but…
Intel shows a 3 NS
device
Samsung shows a 3
NS device
TSMC seems to go
for 3 NS…
 So we use 3 stacked
nano-sheets at start…
Samsung
TSMC ?
Nanosheet FET
 NS FET restores the fine tuning of Ion
NS FET
Ion (µA)
1000
750
slow
Yes we can
Very
fast
fast
FinFET
4 Fins
500
3 Fins
25
0
2 Fins
1 Fin
0
4
5
6
7
8
9
10
Width
(lambda)
11
12
13
14
15
Nanosheet FET
http://bsim.berkeley.edu/models/bsimcmg/
100..11
0
FinFET
111
Nanosheet
Microwind
Gate
pitch
 Microwind works in lambda units (λ)
 Not optimum layout but independent
of technology
 Design rules have remained nearly the
same for 20 years
 λ is 4nm in 3NM (NOT half of
technology)
 Minimum channel length is 2 λ
 Contacted gate pitch (CGP) is 10 λ
 Metal pitch (MP) is 6 λ (3+3)
Metal
pitch
Channel
length
Microwind
Design parameter
Unit
Device Height
Gate length
Nanosheet
thickness
Nanosheet spacing
Nanosheet width
Number of
nanosheets
VDD
Ieff nFET
Subthresold slope
[Weckx 2019]
[Das 2020]
nm
nm
nm
[Kim
2021]
55
11
5
[Yoon
2020]
50
12
5
Microwind
43
8, 10
5
[Jeong
2020]
60
12
5
60
15
5
nm
10
10
5
10
10
10
nm
24
13
20
42
26
16 (Slow)
45
8
5
3
4
4
3
3
32 (Fast)
3
V
µA
0.7
90 (LP)
0.7
70
0.6
20 (LP)
0.7
233 (HP)
0.7
30 (LP)
0.65
100 (LP-slow)
mV/Dec
180 (HP)
70
75
40 (Overdr)
60-70
100
60 (HP)
n.a
125 (HP-slow)
60
Microwind
Slow/Fast
nsFET
Parameter
Width (W)
Length (L)
Slow
Fast
4λ
2λ
8λ
2λ
Dummy gates at
right & left of the
active device
nsFET screen in
Microwind
Microwind
Cross-section A-A’
 nsFET.MSK
Channel
width 4 λ
A
(16 nm)
nsFET gate
Nanosheet
spacing
10 nm
A’
Contact gate pitch 10 λ (40 𝑛𝑚)
Low-power nsFET W= 4 λ (16 𝑛𝑚)
Nanosheet
thickness
5 nm
Microwind
Channel
width (W)
 nsFET.MSK
x6
nsFET gate
NS total width
eq. to “good old”
MOS width
Nano-sheet
thickness
(TNS)
MO
S
5 nm
Microwind
A
 Slow vs Fast
Slow:
Channel
width 4 λ
(16 nm)
A’
Fast nsFET W= 8 λ 𝑡𝑜𝑝
Slow nsFET W= 4 λ 𝑏𝑜𝑡𝑡𝑜𝑚
No restriction on intermediate values
Can be larger than 8 λ
Fast: Channel
width 8 λ
(32 nm)
Microwind
Fast device
S
D
Dummy
Gate
Active
Gate
Dummy
Gate
Slow device
Nano sheets
Microwind
 Device options Low Power (LP, default) or High Performance (HP)
 Through option layer
 W can be adjusted continuously starting 4 λ
Microwind
 N-Device: Low
Power – Slow :
Weq=144nm
Ion 250 µA,
Ieff=100µA,
Ioff = 0.25 nA
@0.65V
ION
IOFF
Microwind
 N-Channel
NanoSheet
device
Low Power –
Slow: Ion=250
µA
Ioff=0.25 nA
Low Power –
Fast: Ion=400
µA
Ioff=0.41 nA
High Performance
Fast
Ion=500 µA
Ioff=4.7 nA (x10 !)
Microwind
 P-Device: Low
Power – Slow :
Weq=144nm ,
Ion 214 µA,
Ieff=90 µA,
Ioff = 0.3 nA
@0.65V
ION
IOFF
Microwind
 Evaluation of the
NSFet
Capacitance
 Target: 100
aF/device
Wang, M., (2020, November).
Design Technology CoOptimization for 3 nm Gate-AllAround Nanosheet FETs. In
2020 IEEE 15th ICSICT
Designing with Nano-Sheet
 No Well, no polarization
No need for
VDD
polarization
contact of n-well
No need for
nwell below
pFET device
No need for
nwell layer
(disabled)
Designing with Nano-Sheet
CGP 40 nm
 Contacted Gate Pitch, Metal Tracks
5 metal tracks (5T)
Shared VDD
Track 1
Track 2
Track 3
Track 4
Shared VSS
80
nm
Metal pitch
24 nm
Cell
height
120 nm
120
nm
Designing with Nano-Sheet
Slow Inverter (Width 4 λ)
3-nm technology
A
Nano-sheet nFET
A’
Nano-sheet pFET
Designing with Nano-Sheet
 Metal stack
Main
target
Pitch

nm
Used for
M7, M8
4
24
192
Supply
M5, M6
3
18
144
Long routing
M3, M4
2
12
96
Medium
routing
M1, M2
1.4
8
64
Short routing
6
48
Intra-cell
routing
Gate, Local 1
interc.
Ring Oscillator
 RO3, FO3 (3 stages, Fan-out 3)
 Fast and furious mode: Large W, High Power option
Ring Oscillator
 Microwind vs
selected
publications
Active power
per stage (µW)
HP 3nm
120
0.75
0.8
100
HP 5nm
80
[Samavedam 2020] 5-nm
0.7
[Ahmed 2020] 2-nm @ 0.65V
0.8
Microwind, LP FinFET
5nm(0.65V)
LP 5nm
60
2nm
0.7
40
[Ryckaert 2019] 5-nm
VDD=0.65
Microwind, HP
NanoSheet 3nm(0.65V)
0.6
20
0.5
150
Microwind, HP FinFET
5nm(0.65V)
0.5
200
250
300
Ring-Oscillator Frequency per stages (GHz)
Examples
Demo
 Basic gates (basicgates-5T.MSK) : Nand2, Nor2, Nand3, Or3, And3
Examples
Demo
 RS NOR (RSNor.MSK)
 Active pulses : positive
31/08/2023
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Examples
 6-Transistor SRAM made by
(good) students
 Regular design
 Still, some silicon area is spared
 The topology enables to
duplicate the cell in X & Y
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Examples
Demo
 Expert SRAM design
 6 transistor
implementation
Data, nData,
BL, nBL,
Sel
 Takes advantage of
all possible shared
signals & contacts
 SRAM-6T3nm.MSK
Examples
Demo
 Shi, Fu, Mi: 2 players (ShiFuMi.MSK)
 Nice topological approach, but spared area
31/08/2023
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Examples
 Edge-sensitive register
 dreg-safe.MSK
 Based on transmission
gates
 Simpler designs
sometimes do not
work
 800 x 500 nm
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Examples
Demo
 Counter 0..15 (Count15.sch)
 Based on 3-stage D-REG
 Very compact design (320 x 270 nm per stage : 75% area reduction)
 Plenty of DRC errors, not manufacturable
 Counter4bits.MSK
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Examples
 ADC 2 bits
 Resistance scale
 3 open-loop amplifiers
 Coding logic
31/08/2023
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Examples
 Almost
working…
 C0 do not
switch properly
 The resistance
scale needs to
be adapted
 Vref0 should
be higher
31/08/2023
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Example
 From the educator’s viewpoint
Nano-Sheet is similar to MOSFet
design
Even simpler because n-well
constraints have disappeared
Continuous Ion instead of FinFET
discrete current (1,2..4 fins)
NS-FET easier to use than FinFET
NS-FET generation should cover 20252030 IC products, including 6G
NS-FET design introduced at INSA in
2021 smoothly
Students attracted by state-of-the-art
IC performances
Node 2nm/20A
 Road Ahead: Buried power layer introduced starting 2nm/20Å
MOS
options
Strain
High K
dielectrics
180
90
45
22
nm
nm
nm
nm
31/08/2023
FinFET
NanoSheet
FET
Buried
Power
Layer
Stacked
N&P
Stacked
tiers
14
3
20
15
10
nm
nm
A
A
Super
FinFET
INSA Toulouse
A
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Node 2nm/20A
 Open archive on 2-nm/20A NanoSheet implementation in
Microwind (2022)
 https://hal.science/hal-03902018
 Based on 40 scientific references
 Main novelty: Buried Power
Rail (BPR)
 First tests with INSA students
autumn 2023
 A lot of room for research &
publication
 First step to 3D ICs
https://hal.science/hal-03902018
Node 2nm/20A
Balls
 Buried Power Rail
(BPR)
VDD
 VDD and VSS
buried in the
substrate
VSS
 No more upper
metal tracks
needed for supply
 Increase cell
density
Balls
VSS
VDD
(Free for
routing)
Device
Device
BPV
BPR-VSS
Substrate
 Reduce supply
resistance
BPR-VDD
Micro-via
Balls
31/08/2023
INSA Toulouse
VSS
VDD
57
Node 2nm/20A
7nm-FINFET – 7 tracks (24nm)
 More compact
design for NS
FET as compared
to FinFET
 Horizontal power
rails routed
below the cell
 Reduced metal
pitch (20nm)
2nm-NSFET – 5 tracks (20nm)
192 nm
100 nm
 Cell height nearly
divided by 2
inv5Tracks vs inv7Tracks.MSK
Node 2nm/20A
A
B
B’
150 nm
A-A’
A’
B-B’
Node 2nm/20A
 Nano-Through Silicon
Vias connect Buried
Power layers to backside VDD/VSS
 n-TSV pitch aligned to
2 BPR pitch
 Ideally, the wafer
should be ultra thin
(0.5µm) for optimum
electrical/thermal
properties [Jourdain
2022]
 Total resistance 200
Ω/µm
BPR
pitch
180 nm
nTSV
diameter
90 nm
M1-M8
Layers
NS-FET layer
BPR
Tungsten
n-TSV
Supply
BPR
Ultra-thin
substrate
0.5µm
Tungsten
n-TSV
Back Side
Metal
Supply
Jourdain, A., (2022, May). Buried Power Rails and Nano-Scale TSV: Technology Boosters
for Backside Power Delivery Network and 3D Heterogeneous Integration. In 2022 IEEE
72nd Electronic Components and Technology Conference (ECTC) (pp. 1531-1538). IEEE.
Node 2nm/20A
Nano-sheet FET
Upper metal
Via to BPR
Inverter
Inverter
BPR
Via to BPR
BPR
n-TSV
n-TSV
inv-bpr-tsv.MSK
8/31/2023
INSA Toulouse
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Node 2nm/20A
 Available in industry 2025
31/08/2023
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Node 1.5nm/15A
 Road Ahead : Stacking N-FET & P-FET: the C-FET
MOS
options
Strain
High K
dielectrics
180
90
45
22
nm
nm
nm
nm
FinFET
NanoSheet
FET
Buried
Power
Layer
Stacked
N&P
Stacked
tiers
14
3
20
15
10
nm
nm
A
A
Super
FinFET
A
Node 1.5nm/15A
 Stacked pFET & nFET
(C-FET)
 Common gate for both
devices
 Simple connection from
nFet to VSS BPR by
short via (vBPR)
 Simple connection N to
P by via P/N
 Connection from pFet to
VDD BPR using stacked
VBPR and Via P/N
 Completely new design
approach
31/08/2023
Metal
Contact
Pfet with 3
stacked nano
sheets
Out
Common gate
for Nfet &
PFet
P to VDD :
vBPR+via
B/N
Via
P/N
Nfet with 3
stacked nano
sheets
Dummy gate
Short Via
BPR to Nfet
(vBPR)
Buried Power
Rail (BPR)
Channels with
gate all around
Node 1.5nm/15A
 NAND2 design
 Sub-ps unloaded
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Node 1.5nm/15A
Ring Oscillator
 3 stages, fan out 1
 Incredible 17µW per
stage, 535 GHz per
stage
 Not yet calibrated to
publications
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Node 1.5nm/15A
 Many publications related to C-FET
 Publication from Intel on C-FET
 Intel “Next” appearing on roadmaps
 Announcement of TSMC 1.4nm/14A (2027)
31/08/2023
Opportunities in 3-D stacked CMOS transistors,
Radosavljević, 2021, Fig. 7
INSA Toulouse
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Discussion
31/08/2023
Technology
node
Year of
Key Innovations
introduction
Application note Microwind
90nm
65nm
45nm
2003
2004
2008
hal-03324305
hal-03324309
hal-03324315
32nm
20nm
2010
2013
SOI substrate
Strain silicon
2nd generation strain, 10 metal
layers
High-K metal gate
Replacement metal gate, Double
patterning, 12 metal layers
14nm
7nm
5nm
3nm
2nm
1.5nm
1.0nm
2016
2017
2021
2021
2024
2027
2030
FinFET
FinFET Quadruple patterning
FinFET EUV
Nano-sheetFET
NSFet & Buried Power
Stacked NSFet, Buried Power
Stacked tiers
hal-01541171
hal-01558775
hal-03254444
hal-03377556
hal-03902018
To appear 2024
INSA Toulouse
hal-03324299
hal-03324322
68
Discussion
• Small reduction of metal pitch, gate pitch unchanged
• Very difficult to scale down further more
• However, cell height has been drastically reduced
Parameter
7nm
5nm
3nm
2nm/20A
1.5nm/15A
1.0nm/10A
0.7nm/7A
Device
FinFET
FinFET
Nano-Sheet
Nano-Sheet
Stacked NS
Stacked CFET
Stacked CFET
3
3
3+3
4+4
4+4
2
4
Nano-sheets
Tiers
λ (nm)
4
4
4
4
3.5
3.5
3.0
Metal 1 pitch (λ)
6
6
6
5
5
5
5
Metal 1 pitch (nm)
24
24
24
20
17
17
15
Gate pitch (CGP)
40
40
40
40
35
35
30
Routing tracks
7
7
5
5
3
3x2
3x2
Yes
Yes
Yes
Yes
Buried Power Rail
Cell heigth (nm)
192
192
160
100
50
50
50
VDD (V)
0.7
0.65
0.65
0.65
0.65
0.60
0.60
EDUC.
DEV.
RESEARCH
ADV. RES.
Education
Discussion
 We support research on
1.5nm/15A node
 50 PDF online at
https://filez.insatoulouse.fr/k24x
 Application note 1.5nm/15A
CFET to appear 2024
 We plan to adapt Microwind to
multi-tier (10A, 7A)
 Jugaad – Frugal innovation
Conclusion
 The Nano-Sheet FET device has
been implemented in Microwind
 This technology should be dominant
in 2025-2030 for high-end ICs
including 6G
 Three major companies to be
involved : Samsung, TSMC, Intel
 Buried power layer & back-side
power delivery in 2nm/20A
 Stacked P/N devices (CFET) in
1.5nm/15A
 Future: stacked tiers (10A, 7A)
 Opportunities for research in novel
cell design
 Application notes released to
support research in nano-CMOS
technology
31/08/2023
INSA Toulouse
71
Thank you for your
attention
Etienne.sicard@insa-toulouse.fr