Embedded Design
and Architecture
Tien Pham Van, Dr. rer. nat.
Hanoi University of Science and Technology
Compiled with reference to other presentations
Embedded Networking Research Group
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Tel: +84-243-8693596
Outlines
•
•
•
•
•
Specification
System architecture
Co-design
Hardware components
Modeling languages and tools
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
Parts of an Embedded System
EMBEDDED SYSTEM
USER
I/O
MEMORY
PROCESSOR
HARDWIRED UNIT
• Application-specific logic
• Timers
• A/D and D/A conversion
ENVIRONMENT
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
Embedded Networking Research Group
Email: tien.phamvan1@hust.edu.vn
School of Elec. and Telecom - Hanoi University of Science and Technology
C9-411, Dai Co Viet str. 1, HBT, Hanoi
Tel: +84-243-8693596
Design flow: inside a tool
Embedded Networking Research Group
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Co-design: Complex Systems
• Abstraction
– Reduce the number of objects managed by a
design task, e.g., by grouping objects using
hierarchy
– Computer-aided design (CAD) example
• Logic level: transistors grouped into gates
• Register transfer level (RTL): gates grouped into
registers, ALUs, and other RTL components
Embedded Networking Research Group
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Generic Co-Design Methodology
Synthesis
• Specification
• Allocation
• Partitioning
• Scheduling
• Communication
synthesis
model
task
Analysis
&
Validation
Note: design
models may
be captured
in the same
language
Implementation
• Software synthesis
• Hardware synthesis
• Interface synthesis
Embedded Networking Research Group
Email: tien.phamvan1@hust.edu.vn
School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
• Hardware and Software Co Design - System
Integration - Embedded System & RTOS YouTube
https://www.youtube.com/watch?v=w-KHW7ZxMW8
Embedded Networking Research Group
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System Specification
• Describes the functionality of the system
without specifying the implementation
• Describes non-functional properties such as
performance, power, cost, and other quality
metrics or design constraints
• May be executable to allow dynamic
verification
Embedded Networking Research Group
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System Specification Example
B0: top
behavior
• integer
variable
• boolean
variable
shared
write
sync
child
behavior
read
sync
Graphical
representation:
• Hierarchy
• Concurrency
• Transitions
between
behaviors
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Behaviors
• Sequential: B1, B2, B3
• Concurrent: B4, B5
• Atomic: B1
• Composite:
B2
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System Specification Example (cont.)
Producerconsumer
functionality
• B6 computes a
value
• B4 consumes the
value
• Synchronization
is needed: B4
waits until B6
produces the
value
Embedded Networking Research Group
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shared
write
sync
read
sync
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System Specification Example
• Atomic behaviors
B1( )
{
stmt;
...
}
B3( )
{
stmt;
...
}
B6( )
{
int local;
…
shared = local + 1;
signal(sync);
}
Embedded Networking Research Group
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B7( )
{
stmt;
...
}
B4( )
{
int local;
wait(sync);
local = shared - 1;
...
}
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Allocation
• Selects the type and number of components
from a library and determines their
interconnection
• Implements functionality so as to
– Satisfy constraints
– Minimize objective cost function
• Result may be customization of a generic
target architecture
Embedded Networking Research Group
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Tel: +84-243-8693596
Allocation Example
PE1
PE2
Proc1
LMem1
bus1
IF1
GMem1
ASIC1
LMem2
bus2
IF2
bus3
IF3
system bus
PE: Processing Element
LMem: Local Memory
GMem: Global Memory
IF: Interface
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Arbiter1
Target Architecture Model
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Partitioning
• Defines the mapping between the set of
behaviors in the specification and the set of
allocated components in the architecture
– Satisfy constraints
– Minimize costs
• Not yet near implementation
– Multiple behaviors in a single PE (scheduling)
– Interactions between PEs (communication)
• Design model
– Additional level of hierarchy
– Functional equivalence with specification
Embedded Networking Research Group
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Partitioning Example
synchronization variables
Top
shared
sync
B1_start
B1_done
B4_start
PE0
PE1
controlling
behavior B1_ctrl
B1_start
B1_done
B4_start
B4_done
Child (B1)
assigned to
different PE
than
parent (B0)
B4_ctrl
B4_done
System model after partitioning
Embedded Networking Research Group
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• Hardware/Software Partitioning - 1 - YouTube
https://www.youtube.com/watch?v=Gkp753foAgE
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Scheduling
• Given a set of behaviors and optionally a set
of performance constraints, determines a
total order in time for invoking behaviors
running on the same PE
• Maintains the partial order imposed by
dependencies in the functionality
• Minimizes synchronization overhead
between PEs and context-switching overhead
within each PE
Embedded Networking Research Group
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Scheduling
• Ordering information
– Known at compile time
• Static scheduling
• Higher inter-PE synchronization overhead if inaccurate
performance estimation, i.e., longer wait times and
lower CPU utilization
– Unknown until runtime (e.g., data-, eventdependent)
• Dynamic scheduling
• Higher context-switching overhead (running task
blocked, new task scheduled)
Embedded Networking Research Group
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Scheduling Example
shared
Scheduling
decision:
• Sequential
ordering of
behaviors
on PE0, PE1
• Synchronization
to maintain
partial order
across PEs
• Optimization - no
control behaviors
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sync
B6_start
B3_start
B6_start
sync
B3_start
System model after static scheduling
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Scheduling Example (cont.)
• Atomic behaviors
B1( )
{
…
signal(B6_start);
}
B6( )
{
int local;
wait(B6_start);
…
shared = local + 1;
signal(sync);
}
Embedded Networking Research Group
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B3( )
{
wait(B3_start);
...
}
B7( )
{
stmt;
...
}
B4( )
{
int local;
wait(sync);
local = shared - 1;
…
signal(B3_start);
}
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Communication Synthesis
• Implements the shared-variable accesses
between concurrent behaviors using an interPE communication scheme
– Shared memory: read or write to a sharedmemory address
– Local PE memory: send or receive messagepassing calls
• Inserts interfaces to communication channels
(local or system buses)
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Communication example
lbus0
IF0
lbus2
sbus
IF1
IF2
PE1
B6
B7
B3
Arbiter
B1
Shared_mem
Synthesis
decision:
PE0
• Put all
global
variables
into
Shared_mem
• New global
variables in Top
lbus1
B4
System model after communication synthesis
Embedded Networking Research Group
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Communication Example (cont.)
• Atomic behaviors
B1( )
{
…
signal
(*B6_start_addr);
}
B3( )
{
wait(*B3_start_addr);
...
}
B6( )
{
int local;
wait (*B6_start_addr);
…
*shared_addr = local + 1;
signal(*sync_addr);
}
Embedded Networking Research Group
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B7( )
{
stmt;
...
}
B4( )
{
int local;
wait (*sync_addr);
local = *shared_addr - 1;
…
signal (*B3_start_addr);
}
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Communication Example (cont.)
• Atomic behaviors
IF0( )
{
stmt;
...
}
IF1( )
{
stmt;
...
}
IF2( )
{
stmt;
...
}
Arbiter( )
{
stmt;
...
}
Shared_mem( )
{
int shared;
bool sync;
bool B3_start;
bool B6_start;
}
Embedded Networking Research Group
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Implementations
– Processor: compiler translates model into
machine code
– ASIC: high-level synthesis tool translates model
into netlist of RTL components
– Interface
• Special type of ASIC that links a PE with other
components
• Implements the behavior of a communication channel
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RTL
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High level synthesis
• https://youtu.be/gTuWkoOq1k0?t=481
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Case study – Xilinx HLS
• Introduction to Vitis High-Level Synthesis
(HLS) - YouTube
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Hardware Component Design
Reference to “Embedded System Design”, by
Peter Marwedel
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Overview
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Block diagram
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Inputs
• Acceleration sensors (inertial measurement
units): accelerometers, gyros
• Image sensors: CCCD, CMOS
• Biometric sensors
• Artificial eyes
• RFID
• Automotive sensors
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Processing unit – hardware tech
• ASIC: high energy-efficient, high cost of designing
and manufacturing, less flexible
– MPW (multi-project wafer) may decrease a bit, but hard
to correct errors
• Reconfigurable logic: FPGA, CLPD
• Processors and controllers
–
–
–
–
–
–
ARM, MIPS, x86/ATOM
Multi-core
DSP
VLIW
GPU
MPSoC
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Processors
Flexibly programmable
Less energy-efficiency than ASIC
Off-the-shelf (COTS)
Diverse (as presented earlier) to meet various
applications
• Well-know families: X86/ATOM, ARM, MIPS,
PowerPC, DSP
•
•
•
•
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• Types of Processor, Units of Processor,
Classifications of Processor, Embedded
System - YouTube
https://www.youtube.com/watch?v=obknO3gA92E
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ARM case study
• Comparison with CISC:
https://youtu.be/AADZo73yrq4?t=639
• Architecture details: ARM Processor
Fundamentals – YouTube
https://www.youtube.com/watch?v=8028NpYig8s
• Wiki: ARM architecture - Wikipedia
https://en.wikipedia.org/wiki/ARM_architecture_famil
y
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Energy efficiency
• CMOS circuits are preferred
• Dynamic power consumption (associated
with switching) + Static power consumption
• Measures to improve efficiency
– Parallel execution
– Dynamic power management (DPM)
– Dynamic voltage and frequency scaling (DVFS)
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Code size efficiency - compression
• ARM design:
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Execution time efficiency
• To reduce execution time without increasing clock speed.
Output element xs corresponds to a weighted average over the last n signal
elements of w and can be computed iteratively, adding one product at a time.
Processors for DSP are designed such that each iteration can be encoded as a
single instruction.
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Very long instruction word – VLIW processors
• Instructions explicitly identify operations to be performed in
parallel. This is possible with explicit parallelism instruction
set computers (EPICs)
• Detection of parallelism is moved from the processor to the
compiler, which saves energy at run-time
• Several operations or instructions (called fields) are encoded
in a long instruction word and are assumed to be executed in
parallel. Each field controls certain hardware units
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Multi-core
• Multiple cores are integrated into a single die
• Cache: L1 is private, L2 is shared
• Cores can be homo- or heterogeneous
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Graphics Processing Unit - GPU
•
•
•
To run a large number of computations concurrently in order to achieve
the desired performance.
GPU runs many fine-grained threads at the same time. If some thread
gets blocked, e.g., due to waiting for memory, the core will execute some
other thread.
The instructions contained in a thread can also be executed concurrently,
e.g., by using multiple pipelines.
SIMD: single instruction
multiple data
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MPSoC (multiprocessor SoC)
• Heterogeneous core systems also contain GPU, DSP
• Additional modules such as MMU, interfaces for peripherals,
etc may be integrated into a single die
• Mapping is critical for energy efficiency
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Microcontrollers
• Small computer that contains processors, memory, and I/O
peripherals
• Mixed signal microcontrollers are common, integrating
analog components needed to control non-digital electronic
systems
• They generally retain functionality while waiting for an event
such as a button press or other interrupts
• Power consumption may be very low thanks to flexible
control of component states
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Microcontrollers - components
•
•
•
•
•
•
•
•
•
•
central processing unit: 4-bit processors to complex 32-bit or 64-bit
volatile memory (RAM) for data storage
ROM, EPROM, EEPROM or Flash memory for program and operating
parameter storage
discrete input and output bits, allowing control or detection of the logic
state of an individual package pin
serial input/output such as serial ports (UARTs)
other serial communications interfaces like I²C, Serial Peripheral
Interface and Controller Area Network for system interconnect
peripherals such as timers, event counters, PWM generators, and
watchdog
clock generator – often an oscillator for a quartz timing crystal, resonator
or RC circuit
many include analog-to-digital converters, some include digital-to-analog
converters
in-circuit programming and in-circuit debugging support
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Reconfigurable logic
• Harmonized between slow software solutions and expensive
ASIC
• FPGA is the most popular, beside CPLD
• Be suitable for:
–
–
–
–
Fast prototyping
Low-volume apps
Real-time systems
Enhanced level of parallel processing
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A close-up view
CLB
Switchbox
Routing
Channel
Routing
Channel
IOB
Configuration
Bit
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Configurable logic
• Configurations (generated from VHDL, Verilog) define both
hardware and software operations, and can be stored
persistently in ROM, flash, or temporally in RAM
• Integrated processors:
– Hardcore: ZynQ ultrascale MPSoC, which contains ARM cortex cores
– Softcore: Microblaze
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Memory
• Working memory: DRAM
• Registers: very fast, but limited
– RISC processors: possibly hold both opcode and operands
• Persistent memory: flash, hard disk, cloud
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Memory - cache
• Cache, TLB (translation look-aside buffer), SPM (scratchpad
memory): to resolves speed difference between RAM and
registers
– Cache: use of tags (subset of address bits) to look for a valid copy;
parallelly reading multiple entries before selecting the right one; levels
L1, L2 and possibly L3 integrated into processor
– TLB: for virtual memory management; associated with MMU
– SPM: to access when simple address decoder signals an address to be in
the range of SPM; can be in the same die with processor (hence called
on-chip memory)
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Cache
Embedded Networking Research Group
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Communication
• Means/media: wireless (radio, infrared), optical (fibers), and
wires
• Requirements:
–
–
–
–
–
–
–
–
–
Real-time constraint: TDMA vs CSMA/CA
Efficiency: hardware utilization, wires, energy
Bandwidth
Latency
Event-driven
Security/privacy
Safety/robustness
Fault-tolerance
Maintainability/diagnosability
Embedded Networking Research Group
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Typical communication means
• Sensor/actuator bus
• Field bus:
– Controller Area Network (CAN): inexpensive connectivity between
controllers and peripherals; widely used in automotive industry and
later in smart home; based on differential signaling and arbitration
using CSMA/CA (hence starvation possibly occurs)
– Time-Triggered Protocol (TTP): This is a protocol for fault-tolerant
safety systems like airbags in cars
– FlexRay™: a TDMA protocol developed by the FlexRay consortium
(BMW, Daimler AG, GM, Ford, Bosch, Motorola, and Philips)
– LIN (Local Interconnect Network): This is a low-cost communication
standard for connecting sensors and actuators in the automotive
domain
– MAP: MAP is a bus designed for car factories
– EIB: The European Installation Bus (EIB) is a bus designed for smart
homes.
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Typical communication means
• The Inter-Integrated Circuit (I2C) Bus : This is a simple lowcost bus designed to communicate at short distances (meter
range) with relatively low data rates. The bus needs only four
wires: ground, SCL (clock), SDA (data), and a voltage supply
line
• Wired multimedia communication: For wired multimedia
communication, larger data rates are required. For example,
MOST (Media Oriented Systems Transport) is a
communication standard for multimedia and infotainment
equipment in the automotive domain. Standards like IEEE
1394 (FireWire) may be used for the same purpose
• Wireless communication: This kind of communication is
becoming more popular. Popular interfaces include cellular,
LoRA, Bluetooth, ZigBee, etc
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Outputs
• Display: Organic displays are emitting light
and can be fabricated with very high
densities. In contrast to LCDs, they do not
need backlight and polarizing filters. Major
changes are therefore expected in these
markets
• Electro-mechanical devices: These influence
the environment through motors and other
electro-mechanical equipment
– Actuators can be a huge motors to microsystems
• Key techniques:
– DAC: not easy to integrate into digital chips
– PWM: output voltage depends on values stored in
registers
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Energy matters
• Source: mainly battery powered; energy harvesting has
been emerging (photovoltaic, piezoelectric,
thermoelectric generators, kinetic energy, ambient
electromagnetic radiation )
• Storage: non-rechargeable/rechargeable battery,
capacitor
• Energy-efficiency:
– Appropriately controlling hardware operations
– Properly selecting hardware tech: FPGA, ASIC, DSP,
Processors…
– Programming differently (unlike many HUST students…)
Embedded Networking Research Group
Email: tien.phamvan1@hust.edu.vn
School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
Embedded Modeling: tools
and languages
Reference to “Embedded System Design”,
by Peter Marwedel
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
Model concept
• In embedded world, system under design (SUD) must
be modeled for researching specifications
• “A model is a simplification of another entity, which can
be a physical thing or another model. The model
contains exactly those characteristics and properties of
the modeled entity that are relevant for a given task. A
model is minimal with respect to a task if it does not
contain any other characteristics than those relevant
for the task”
• Models are described in modeling languages, which
describes system and component specifications
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Required capabilities of modeling languages
Behavioral and structural hierarchy
Component-based design
Concurrency
Synchronization and communication
Timing behaviors
State/exception-oriented behavior
von Neumann MoC is
composed of tasks,
Presence of programming elements
process and threads
with communications,
Executability
which has no timing
Portability and flexibility
description
Termination
Support for the design of dependable systems (e.g. formal
verification)
• Appropriate model of computation (MoC) – not von Neumann MoC
•
•
•
•
•
•
•
•
•
•
•
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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MoC
• MoC defines:
– components and their organization of computations, e.g. procedures,
processes, functions, and finite state machines
– communication protocols: describe methods for communication between
components, e.g. asynchronous message passing and rendezvous-based
communication
• Relations between components are represented in task graphs
and process networks
– Nodes represent computations
– Edges represent relations between components: causal dependence,
timing, information exchange, etc
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
MoC - what task graph includes
•
•
•
•
•
Timing information: arrival time, execution time, deadline…
Types of relations between computations: precedence, I/O, etc
Exclusive access to resources
Periodic schedules, e.g. DSP
Hierarchical graph nodes
Embedded Networking Research Group
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MoC – communication fashions
• Shared memory
– Fast but difficult in multiprocessor system without common physical
memory
– Critical sections must be identified
• Message passing
– Loosely coupled processors
– Three kinds: blocking, non-blocking, and extended rendezvous/remote
invocation
Embedded Networking Research Group
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MoCs and languages
Embedded Networking Research Group
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Early phase design – Use Case
Embedded Networking Research Group
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Early phase design – Sequence Charts and
Time/Distance Diagrams
Embedded Networking Research Group
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Early phase design – Differential Equation
• Modeling a bouncing ball
Embedded Networking Research Group
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Communicating Finite State Machines (CFSMs) StateCharts – for shared mem. comm.
Embedded Networking Research Group
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Communicating Finite State Machines (CFSMs) SDL for message-based com.
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Data Flow – Kahn Process Network
• A distributed model of computation in which a group
of sequential processes communicate through FIFO channels.
• Reading from a channel is blocking while writing is nonblocking
Embedded Networking Research Group
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Data Flow – SDF (static data flow)
• A directed graph that facilitates scheduling and buffer calculation
– Node: actor
– Edge: token
Embedded Networking Research Group
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Data Flow –Simulink
• Computational graph structures are also frequently used in
control engineering.
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–
–
An approach of model-based design
Analog blocks included
Ideal timing (fast) model is assumed
Code generation for various language implementation: C, VHDL...
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Control Flow – Petri Nets
• Very comprehensive descriptions of control flow. Conditions,
events, and a flow relation are the key elements. An event is
associated with pre- and post-condition
Embedded Networking Research Group
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Activity Diagram
• A UML diagram that
includes extended
Petri nets
Embedded Networking Research Group
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Discrete event-based languages - TLM
• Only care about events, not modeling continuous
[physical] time
• Separation between computation and
communication
• In TLM (transaction-level modeling), the emphasis
is more on the functionality of the data transfers
— what data are transferred to and from what
locations — and less on their actual
implementation, that is, on the actual protocol
used for data transfer
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
Discrete event-based languages - TLM
•
•
•
A: untimed model/specification model; B: component assembly model
C: bus arbitration model; D: bus functional model
E: cycle-accurate computation model; F: implementation model
Embedded Networking Research Group
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TLM – Spec C
• Spec C models systems as
hierarchical networks of
behaviors communicating
through channels.
• Spec C descriptions consist of
behaviors, channels, and
interfaces
Embedded Networking Research Group
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TLM – SystemC
• TLM modeling and the separation
between communication and
computation are also available in
SystemC™. Similar to SpecC, SystemC
provides channels, ports, and
interfaces as abstract components for
communication
• System C comprises a notion of
processes executed concurrently.
Their execution is controlled by calls to
wait primitives and sensitivity lists
(lists of signals for which value
changes start a re-execution of code)
• Hardware synthesis starting from
SystemC has become available
Embedded Networking Research Group
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P&R: Place & Route
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SystemC
Embedded Networking Research Group
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Discrete Event-Based Languages – VHDL
•
VHDL is another HDL which is based on the discrete event paradigm.
Unfortunately, it does not support a clear distinction between
communication and computation, and reusing components is more
difficult
Embedded Networking Research Group
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Discrete Event-Based Languages – [System]Verilog
•
Much like VHDL. Verilog versions 3.0 and 3.1 are also known as
SystemVerilog. They include numerous extensions to Verilog 2.0:
– additional language elements for modeling behavior,
– C data types such as int and type definition facilities such as typedef and
struct,
– definition of interfaces of hardware components as separate entities,
– standardized mechanism for calling C/C++ functions and, to some extent, to
call built-in Verilog functions from C,
– significantly enhanced features for describing an environment (called test
bench) for the hardware circuit under design (called CUD), and for using the
test bench to validate the CUD by simulation,
– classes known from object-oriented programming for use within test
benches,
– dynamic process creation, standardized interprocess communication and
synchronization, including semaphores,
– automatic memory allocation and deallocation,
– language features that provide a standardized interface to formal
verification
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
von Neumann languages
•
•
•
CSP (communicating sequential processes) is one of the first languages
comprising mechanisms for interprocess communication
ADA is the language to address dependability and maintainability, with
all software written in the same real-time programming
Communication libraries:
– MPI (message passing interface)
– OpenMP
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Levels of Hardware Modeling
•
•
•
•
•
•
•
•
System-level models: represents both embedded system and the
environment. Examples are VHDL-AMS, Verilog-AMS SystemC-AMS, etc
Algorithmic level: simulates algorithms run on the system, e.g. H26x
Instruction set level: works on compiled algorithm, counts instructions
execution time
RTL level: models all the RTL components, including arithmetic/logic units
(ALUs), registers, memories, multiplexers, and decoders
Gate level: provides more accurate information about signal transition
probabilities, power estimations and delay
Circuit model: works on circuit theory and its components e.g. current and
voltage sources, resistors, capacitances, inductances, etc. Simulations
involve partial differential equations
Layout models: reflects the actual circuit layout. Such models include
geometric information
Process and device models: represents model fabrication process
Embedded Networking Research Group
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Comparison of languages and tools
Embedded Networking Research Group
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Combination of multiple languages and tools
Embedded Networking Research Group
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Unified Modeling Language - UML
• A language includes diagrams representing many models of
computations
• Various diagrams of deployment, package, class,
communication, component, object, interaction overview, and
composite structure are provided
• Combination of UML and others such as SDL, C++ is possible
Embedded Networking Research Group
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Review
• Workflows of specification, co-design and
synthesis
• Detailed implementation of partitioning,
allocation, scheduling, and communication
• Systematically understanding hardware
architecture
• How to work on modeling languages and
tools
Able to take over assignment projects!
Embedded Networking Research Group
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School of Elec. and Telecom - Hanoi University of Science and Technology
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Tel: +84-243-8693596
