IEEE JOURN.4L OF SOLID-ST.iTE CIRCUITS, VOL.
2456
[5’1
[61
[71
switching delays using CMOS/
in 1971 Int. Solid-State
Circuit Conj., Dig. Tech. Papers, p. 225,
E. J. Boleliy and J. E. Meyer, “High-performance
low-power
CMOS
memories
using
silicon-on-sapphire
technology,”
IEEE
J. Solid-State
Circuits
(Special
Issue on Micropower
Electronics),
vol. SC-7, pp. 135-145, Apr. 1972.
R. W. Bower, H. G. Dill, K. G. Aubuchon, and S. A. Thompson, ‘[MOS field effect transistors by gate masked ion implantation,”
IEEE
!t’’rams. Electron
Devices,
vol. ED-15, pp.
757-761, Oct. 1968.
J. Tihanyi,
“Complementary
ESFI MOS devices with gate
self adjustment
by ion implantation,”
in Proc. 5,th Iwt. Conj.
Microelectronics
in Munich,
Nov.
27–29, 1972. MunchenWien, Germany:
R. Oldenbourg
Verlag, pp. 437447.
E. J. Boleky,
“The performance
of complementary
MOS
transistors on insulating
substrates,” RCA Rev., vol. 80, pp.
372-395,
5>
OCTOBER 1974
1970.
formation
in an insulated
gate field
[81 K. Goser, ‘[Channel
effect transistor ( IGFET)
and its emrivalent circuit .“ Sienzen.s
Forschungsund Entwiclclungsbekhte,
no. 1, pp.’ 3-9, 1971.
“Accurate
metallization
[91 A. E. Ruehli and P, A. Brennan,
capacitances for integrated
circuits and packages,” IEEE
J.
Solid-State
Circwits
(Corresp.), vol. SC-8, pp. 289-290, Aug.
1973.
(Siemens
Netzwerk
Analyse
Programm
Paket),
[101 SINAP
Siemens AG, Munich, Germany.
‘[Aufteilung
der Gate-Kanal[111 K, Goser and K. Steinhubl,
Design
H.
DENNARD,
RIDEOUT,
Michael Pomper,
238 of this issue.
Jeno Tlhanyi,
for
238 of this issue.
of Ion-Implanted
Very
ROBERT
NO.
Kapazitat
auf Source und Drain im Ersatzschaltbild
eines
und Ent wicldwrgsMOS-Transistors,”
Siemenx Forxchungsberichte
1, no. 3$ pp. X4-286, 1972.
[121 J. R. Burns, “Switching
response of complementary+symmetry MOS transistors logic circuits,”
RCA
Rev.,
vol. 25,
pp. 627481, 1964.
[131 R. w. Ahrons and P. D. Gardner, ‘[Introduction
of technology and performance
in complementary
symmetry
circuits,” IEEE
J. Solid-State
Circuits
(Special Issue on Technology
jor Integrated-Circuit
Design),
vol. SC-5, pp. 24–29,
Feb. 1970.
[141 F. F. Fang and H. Rupprecht,
“High performance
MOS integrated
circuits
using ion implantation
technique,”
presented at the 1973 ESSDERC,
Munich,
Germany,
[31 E. J. Boleky, ‘%ubnanosecond
SOS silicon-gate
technology,”
[41
SC-9,
Small
H.
Absfracf—This
paper considers
the design, fabrication,
and
characterization
of very small MOSI?ET switching devices suitable
for digital integrated
circuits using dimensions
of the order of 1 p.
Scaling relationships
are presented which show how a conventional
MOSFET
can be reduced in size. An improved small device structure is presented
that uses ion implantation
to provide shallow
source and drain regions and a nonuniform
substrate doping profile. One-dimensional
models are used to predict the substrate
doping profile
and the corresponding
threshold
voltage versus
source voltage characteristic.
A two-dimensional
current transport
model is used to predict the relative degree of short-channel
effects
for different
device parameter
combinations.
Polysilicon-gate
MOSFET’S
with channel lengths as short as 0.5 ~ were fabricated,
and the device characteristics
measured and compared with predicted values. The performance
improvement
expected from using
these very small devices in highly miniaturized
integrated
circuits
is projected.
Manuscript
received May 20, 1974; revised July 3, 1974.
The aubhors are with the IBM T. J. Watson Research Center,
Yorktown
Heights, N.Y. 10598.
and
please see p.
biogra~hy,
please
see p.
with
Dimensions
GAENSSLEN,
BASSOUS,
a photograph
and biography,
MOSFET’S
Physical
LIEMBER, IEEE, FRITZ
MEMBER) IEEE, ERNEST
for a photograph
AND ANDRE
HWA-NIEN
YU,
R. LEBLANC,
LIST
MEMBER, IEEE, V. LEO
MEMBER, IEEE
OF SYMBOLS
a
Inverse
D
threshold characteristic.
Width of idealized step function
semilogarithmic
slope of subpro-
fde for chaDnel implant.
AW,
Work
function
difference
and substrate.
Dielectric
constants
for
between
gate
silicon
and
silicon dioxide.
Drain current.
Boltzmann’s
Unitless
constant.
scaling
constant.
MOSFET
Effective
channel length.
surface mobility.
Intrinsic
carrier
concentration.
Substrate acceptor concentration.
Band bending in silicon at the onset of
strong
inversion
for zero substrate
voltage.
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et al. : ION-IMPLANTED
DENN.4m
MOSFET’S
257
*,
Built-in
(1
Charge
Q.,,
Effective
t ox
Gate oxide thickness.
T
Vd, v,, v.,
junction
potential.
oxide charge.
Absolute
VaubDrain,
Vd.
V,-.”b
v,
w.,Wd
Source
w
MOSFET
Source
temperature.
relative
voltage
depletion
layer
Fig. 1. Illustration
of device scaling principles
with K = 5. (a)
Conventional
commercially
available
device
structure.
(b)
Scaled-down device structure.
relatively
forming
over
the
monly
a decrease
optical
used
new
contact
in
the
techniques,
widely
used
while
ing
for
X-ray
[6]
Full
realization
of
tion
lithographic
new
device
be
the
of
order
leads
These
undesirable
large
the
portion
gate
is
the
For
these
short-channel
down
the
source
ess,
junction
dimensions,
in
device
drain
can
(e.g.,
etc. )
also
an
characteristics.
depletion
along
over
the
most
a reduction
in
turns
a
under
on,
the
which
has
been
shown
be avoided
by
scaling
gate
with
insulator
the
thicknhorizontal
decreasing
the substrate
the
doping
con-
paper
small
device
for very small
all-implanted
a simple
centration
MOSFET’S.
of doping
profile in the channel
creased in a controlled
atoms
allows
First,
introduce
strate
structure
sensitivity
the substrate
con-
doping
region under the gate to be inmanner. When combined with a
reduced
or drain-
the scaling
principles
MOSFET
to obtain
capable
of improved
of the
per-
scaling
are based on two analytical
model
that
predicts
for long channel-length
two-dimensional
current-transport
the device turn-on
ap-
The predicted
compared
;vith
mensional
simulation,
experimental
the
that
from
both
data.
of chan-
analyses
Using
sensitivity
the
of
and a
predicts
as a function
results
tools:
the sub-
devices,
model
characteristics
nel length,
the
are
two-di-
design
to
Yarious parameters
is shown. Then, detailed attention
is
design,intendedfor zero substrate
givcll to all alternate
which
offers
of the
some
advantages
The
concise
circuits
in
principles
dccreming
lIOSFET
the-art
of
manner
the
the
switching
n-channel
with
the paper
that
device
general
size
respect
concludes
improvements
DEVICE
the ability
a low
thresh-
has significantly
(e.g., drain-to-gate
one-dimensional
from integrated
to accurately
a
proach is then presented. Next, the fabrication
process
for an improved
scaled-down
device structure
using ion
implantation
is described. Design considerations
for this
of this paper is to show how
leads to an improved
design
scaled-down
gives
verification
performance
of ion implantation
main-
combination
a thicker
Experimental
sion
A major consideration
the use of ion implantation
The
with
structure
a 200-A
is to be reduced to 1 ~.
favor-
while
design
to a conventional
Finally,
length
of very
are more
effects,
begins by describing
are applied
old control.
if the channel
formation
which
all-implanted
capacitances
bins,
is required
which
and reliably.
can be fabricated
and which
[7],
[8].
Applying
this scaling approach to a
centration
properly designed conventional-size
MOSFET
shows that
gate insulator
bias.
be traded
capacitances).
formance.
FET
substrate
It
proportionately
and increasing
a very
the
is
This
the
regions
an
voltage
thickness
sheet resistance.
in
channel
if desired, which has well-controlled
to-substrate
source-
of
of 350-A
reproducibly
allows
device which
old characteristics,
char-
can then
to short-channel
features
gate insulator
the
extend
device
these
which
drain
voltages.
effects
of
devices
applications,
the
respect
an acceptable
dimensions
when
silicon
effect
depth,
voltages
the
the
dimensions
while
length)
and
at which
high
vertical
reducing
switching
voltage
by
applied
in
“short-channel”
threshold
aggravated
that
that
channel
region
electrode.
using
significant
the
of
undesirable
the
become
surrounding
gate
is known
with
implantation
interelectrode
switching
circuits
ion
switching
which
and
gate insulator
source and drain
this
(“backdate”)
sensitivity”
shallow
of
high-resolu-
development
“substrate
Second,
taining
print-
fabrication,
MOSFET
changes
changes
regions
[1] – [4]
structures
reduced
able
dimensions.
integrated
(i.e.,
new
the
design,
small
the
capability.
these
substrate,
of the threshold
tends to be easier to fabricate
been
projection
and
small
the
1 p. It
has
starting
the sensitivity
off for a thicker
times
Of
writing
requires
very
very
spacing
to
of
This
is com-
fabrication
technologies,
digital
of
today.
optical
benefits
concerns
for
to-drain
the
for
paper
which
high-resolution
techniques
acterization
of
and
for
ten
doped
reduces
to changes in the source-to-substrate
patterns
to
industry
pattern
exhibited
designs,
optimized
suitable
[5]
five
approach
device
lithography
also
This
beam
circuit
of
masking
experimental
have
can
linewidth
semiconductor
electron
techniques
integrated
in
lightly
implant
lithographic
semiconductor
offer
(b)
width.
INTRODUCTION
N
N~=25x10’6/cm
a
(a)
widths.
resolution
_-
-
NA=5 x 10’5/cm3
to substrate.
voltage.
drain
channel
=.
~N+o
.___,
to source.
relative
and
&*200A
-OILhp
‘+
5P
L’l
volt-
a
Gate threshold
HIGH
GATE
:N+
___,
1,
/l
/L\
‘+
--0
source, gate and substrate
ages.
Drain voltage
EW
tox=loooh
GATE ~
on the electron.
and
devices.
lllOSFET
to thresh-
with
to
use these very
a discus-
be expected
small
FET’s.
SCALING
scaling
design
increasing
Fig.
[9]
[7],
[8]
trends
to
the
in
a
a
followed
performance
1 compares
with
show
be
a state-ofscaled-down
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of
258
IEEE
clevice
be
clesignecl
described
1 (a)
following
later.
is reasonably
vices
It
by
uses
substrate
voltage
sensitivity.
tant
criterion
source
thethreshold
digital
because
voltage
the
rameters
mum
give
bias. It would
a
and (2) prevent
mately
of 5 X 10’5
increased
value
of sub-
is an imporemploying
difficult
if
a factor
of
increases
by more than
illustrated
in Fig.
the channel
length
arises primarily
plied
the penetration
of approximately
modify
of the
12-15 V this pene-
the surface potential
lower the threshold
In
order
values
the potential
three
all
variables:
linear
faCtOr
dimension,
clirnensions
K, e.g.,
refer
to
new
il~cludes vertical
ness, junction
scaled-down
dimensions
(i.e., Na’
a
device,
length
=
~Na).
The
obtained
using
reduction
in channel
The scaling
parameters
example,
thickdi-
Second, the voltdoping
concen-
the same scaling
in Fig.
corresponds
factor
1 (b’) was
to the desired
length to 1 p,.
were developed
by observing
that the depletion layer widths in the scaled-down
device
arc reducecl in proportion
to the device climensions due to
the reducecl potentials
ancl the increased doping. For example,
w,’
The
{[2cs,(V~’
threshold
voltage
in clirect pro~ortion
that the clcvicc will
reducecl
voltage
voltage
equation
V,’
=
V,-,,,JK)l/CIKN.
+
at turn-on
(1)
}”2 m w,/Ic.
[9]
is also decreased
to the reduced device voltages
so
function
properly
in a circuit with
levels.
This
is shown
for the scaled-down
(tO=/KCOf) { –Q,.,,
+
across the source
by the threshold
device.
[~~,,~K~a(+s’
+
region
that
the MOSFET
due to the
h] (.V.’/n,
or drain
under
).
tOx/K-
w/K
V,
L/ii
—
–
equation
~7t –
K
—
)
by a, factor
of
assuming
no
is reduced
slightly
applied
voltages,
Actually,
the mobility
impurity
scattering
electric
field
of
field
given
(Vet/K)
by
=
(3)
Id/K
for any given
K,
in
set
mobility.
clue to increased
doped substrate.
the scaling
patterns
distribution
[9]
change
in the heavier
to generalize
clevice
above. For
vd/~
is seen to be reduced
electric
junctions,
the gate, can be re-
clescribe the MOSFET
current
(–)(
P,,,e..
and
approach
current
is maintained
to in-
clensity.
in the
The
scaled-
clown device except for a change in scale for the spatial
coordinates.
Furthermore,
the electric field strength
at
any
corresponding
V’/x’.
Thus,
changed
locity
is un?hanged
velocity
due to scaling
effects
will
From
hence,
any
in both
fixed
current
by scaling,
saturation
per unit
ve-
neglecting
crystal
lattice
is reduced
of channel
This is consistent
=
is also un-
devices,
due to the
V/c
because
at any point
(3), since the clevice current
channel
K, the
is unchanged
and,
be similar
cliff erences
dimensions,
by
point
the carrier
microscopic
width
with
IV
the same
sheet density of carriers (i.e., electrons per unit gate area)
moving at the same velocity.
In the vicinity
of the clrain,
the carriers
extent
=
slightly
(2kT/q)
may be scaled as demonstrated
~,_
clude
reduction
increasing
in (1)
approxi-
K.
It is possible
by the same factor
clesign shown
relationships
drop
characteristics
scaling
as the horizontal
the substrate
using
5 which
K =
First,
unitless
This
and width.
Third,
agnin
in
such as gate insulator
to the device are reduced
(e.g., V~S’ = Vd,,/K).
tration
is increased,
smaller
doping.
the primed
etc., as well
of channel
ages applied
by
where
for
a transformation
and
reduced
&’K,
depth,
by
voltage,
are
t,ox’ =
the
mensions
scaled
suitable
appearing
since they rcxnain
=
poten-
V,,,,,) /K. Thus,
by scaling clown the apbias more than the other applied voltages,
All of the equations
and significantly
voltage.
to clesigl~ a new device
L, the device is
of
(~,, +
substrate
d
will
actually
CIUCeC{
by
pa-
1974
for zero substrate
the *’ terms
eloping since ~0’ @ *,’
1 (a),
region surrounding
the clrain into the area
controlled
by the gate electrode. For a maxi-
ch-ain voltage
tration
that
or across the depletion
design
OCTOBER
(i.e., the surface
inversion
exact scaling
of the source voltage.
the
CIRCUITS,
However,
the fixed substrate bias supply normally
used
with n-channel
devices can be adjusted
so that (~,,’ +
L to about, 5 p. This
from
appear
constant,
V,,,,; ) =
circuits
becomes
in the silicon
at the onset of strong
a
switching
limit
depletion
normally
to
is the band bencling
tial)
the design
clevice
restriction
with
OF SOLIC)-STATE
p-type
substrates)
the work function
difference
A~Vf is
of opposite sign, ancl approximately
cancels out *,J. ~.’
2 V relative
doping
sensitivity
two o~er the full range of variation
For
chosen
to give an acceptable
in
followers
detech-
thickness
bias
The substrate
Fig.
diffusion
insulator
A substrate
to
in
a~ailable
conventional
I:r of approximately
to the source potential.
cm-3 is low enough
principles
shown
of commercially
using
ancl substrate
doping
scaling
structure
a 1OOO-A gate
gate threshold
strate
device
larger
typical
fahricatecl
niques.
the
The
JOURFJ.iL
Thus,
will
move away
in the new device,
the clensity
bc higher
from
the surface
to a lesser
due to the shallower
of mobile
carriers
in the space-charge
per unit
region
complementing
the higher density
clue to the heavier doped substrate,
cliffusions.
volume
around
the
will
drain,
of immobile
charge
Other scaling rela-
tionships
in Table
for power density, delay time, etc., are given
I ancl will be discussed in a subsequent section
on circuit
performance.
In order to verify
Vs-s,,,/K)]’”}
the scaling
relationships,
two sets of
experimental
+
In
(2)
creased
the reduction
insulator
the voltage
cases of interest
opposite
to that
+
~.’)
in Tt is primarily
thickness,
and doping
(AJVf
tOx/K,
while
due to the de-
devices
were fabricated
with gate insulators
o
of 1000 ancl 200 A (i. e., K = 5). The measured drain voltage
characteristics
of these devices, normalized
to W/L = 1,
the
are
=
V,/K.
(~)
changes
in
terms tend to cancel out, In most
(i.e., polysilicon
of the substrate
gates of doping
or aluminum
type
gates on
shown
quite
of
the
confirms
in
similar
smaller
the
Fig.
when
~
9.
clevice
scaling
The
plotted
tin-o
sets
with
voltage
reduced
predictions.
by
of
characteristics
and
a factor
In
Fig.
current
of
2,
five,
the
Authorized licensed use limited to: Universidad de Sevilla. Downloaded on November 01,2023 at 18:40:47 UTC from IEEE Xplore. Restrictions apply.
are
scales
which
exact
DENNARD et at. : ION-IMPbiNTED
MOSFET’S
259
1,5~
GATEVOLTAGE [V]
20
tox=100ox
10-
L
*w=5p
v~ub=-?v
+= sO.65V
0.5-
5
Q
0
5
15
10
20
DRAINVOLTAGE[V]
(a)
GATE VOLTAGE[v]
0.3
0.2
3
.
0 IF
+ ~
o
0
I
2
3
4
DRAIN VOLTAGE[v]
(b)
Expcrimentzd
drain voltage characteristics
ventional,
and (b) scaled-down structures shown
malized to W/L = 1.
Fig.
for (a) conin Fig. 1 nor-
2.
drain
3.5
voltage
is large
charact cristics
=10001!
=5V
tox
3.0
‘ds
When
linear
VSu~=-7V
2.5
the
to cause pinchoff
expected
linear
and the
relationship,
proj ccted to intcrccpt
the gate voltage axis this
relationship
defines a threshold
voltage useful for
most logic circuit
1#, =0,65V
fid
enough
exhibit
design purposes.
Onc area in which the dcvicc characteristics
fail to scale
is in the subthrcshold
pr weak inversion
region of the
2,o
[#A] ’’2,,5
turn-on
characteristic.
dependent
1.0
B@ow threshold,
on V, with
a, [10], [11] which
an inverse
1,, is exponentially
scmilogarithrnic
for the scaled-down
slopc,
device is given
by
0.5
,
(
4
.8
1,2
flv,’
volts
a ()dccadc
1.6
= d log,, 1,,’
GATE VOLTAGE[V]
Fig. 3. Experimental
turn-on
characteristics
for conventional
and scaled-down devices shown in Fig. 1 normalized
to W/L
= 1.
match
on
the
current
since
there
is some
tude
of the
channel
istics
(see
with
width
an
approximate
shows
for
dcviccs
with
threshold
five
~~
and
voltage
is
verified
versus
the
length
Appendix).
larger
scale
L1orc
and
Icngth
the
heavier
in
scaled-down
Fig.
accurate
which
of ten
doped
from
the
SIIOJVS
tllc
for
the
cases
‘(on”
a
the
factor
of
cxpcrirncntal
the
larger
clcvice.
[ 12]
and
shi~)
of
room
the
This
istic
thereby
In
The
to
and
particular
the
above,
concern
of
to
cause
mobility
current
scaling
rclation-
devices
for
does
the
lT70uld
surface
one
behavior
property
but this
effective
design
the linear
reduce the operating
~/K),
the
invalidate
subthreshold
nonscaling
is of
in
order
temperature
the
(i.e., T’ =
increase
(3).
to also extend
to ~ one could
in (4)
<% significant,
that
original
Shon-nj
( 11]. In an attempt
relationships
temperature
chip
in mobility
That
state
scaling
dcviccs
same
pcrccnt
by
magni-
character-
substrate.
correctly
For
the
is the same as for the original
lJaramctcr
~ is important
to dynamic
memory
circuits
because it determines the gate voltage excursion rcq~lired
to go froln tile low Current “off” state to the high current
fortuitous
in the
on
characteristics
devices.
be
data
dimensions
scales
3,
to
to normalize
reduction
turn-on
thought
uncertainty
used
also
~T.
is
experimental
which
must
not
accept
scale’
subthreshold
Ininiaturc
operation
the,
at
fact
as desired.
character-
dynamic
menl-
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IEEE
260
t~*
JOURNAL
OF SOLID-STATE
under
the gate electrode
drain
are then
and
drain
extend
(a)
With
would
tend
would
cause
to
by the
merge
punchthrough
lower
\
I
1
V,,,=
at
junctions
tern
which
in
high
avoids
1974
further
the
into
these
lighter
doped
doped
chosen
which
in the
extreme,
However,
the
electric
field
favorable
when
regions
material
or,
voltages.
effects
is properly
the
control
drain
and
surface
these depletion
lighter
a more
doped
4(b),
for the case of a
regions under the source
of threshold
give
concentration
-Iv
much
heavier
deeper junctions
a loss
OCTOBER
at the edges of the source
inhibited
layer, roughly
pictured
in Fig.
turned-off
device. The depletion
substrate.
CIRCUITS,
the
shal-
substrate
patdoping
when it is not too
(i.e.,
light),
The
device
planted
width
[cf.
)
gives
-..
“.-.
circuits
which
require
low
source-to-drain
Fig.
scaling
In’
with
contrast,
just
presented
a l-,P channel
the
the
capability
shown
in Fig.
4 (b).
initial
substrate
corresponding
afforded
The
doping
length
shown in Fig.
improved
is lower
process
study
mask
process
n-channel
when the device
the
is turned
surface
on with
on the device.
sensitivity
With
this
doped
region
depletion
layer
the source grounded.
the gate insulator
to as much ‘as 350A
improvement
thickness
and still
maintain
low
implanted
implanted
n+ regions
p-type
surface
of depth
layer.
The
in substrate
gate
Though
the eventual
depletion
drain
design
in
device
channel
MOS~ET’s
for the
ion-implanted
MOS-
now be described.
to
fabricate
on
a test
lengths
A four-
polysilicon-gate,
chip
ranging
which
from
contains
0.5 to 10 p.
aim is to use electron-beam
For
this
to
the
regions
purpose
for the gate pattern
which
are
7.5 x 1015cm-’).
isolation
in
ing
dry
pattern
silicon
After
x
FET’s
growth
of the
about
for the thick
here, and be-
are available.
gate
The
(i.e.,
is not described
presented
techniques
only
as 1.5 p
processing.
2 CI. cm
of fabrication
to the work
surface.
All
oxide,
the channel
implantations
in order
Follow-
low
Next,
energy
oxide
n“ source
layer.
performed
diffusion
a 3500-A
thick
of
poly -
doped n’, and the gate regions
and
drain
by a high energy
10’5 atoms/cm’)
same 350-A
were
to restrict
implantation,
layer was deposited,
deep were formed
(4
was
adj scent
after gate oxide growth
the implanted
regions.
silicon
subsequent
The method
suitable
is required
as small
B“ ions were
low dose (6.7 x 101’ atoms/cmz)
into the wafers, raising the boron doping near
(40 keV),
implanted
the
the
between
thermal
resolution
uses lines
resistivity
as it is not essential
cause several
high
which
reduced
substrate
delineated.
is to use shal-
comparable
for maximum
will
used
with
can be increased
a reasonable
threshold
voltage as will be shown later.
Another aspect of the design philosophy
gate field,
ment.
Thus, when the source is biased above ground potential,
the depletion’ layer will extend deeper into the lighter
doped substrate,
and the additional
exposed “bulk”
charge will be reasonably
small and will cause only a
modest increase in the gate-to-source
voltage required to
turn
was
MOSFET’s
devices
oxide
within
performance
gate oxide and the expected
ION-IMPLANTED
fabrication
face layer
be completely
OF
used in this
starting
heavier
the
to 3 V for the sc-sled-down
FET’s
used throughout
the unimplanted
structure
of Fig. 4(a).
The concentration
and the depth of the implanted
surthis
but
a design objective
compared
the
also
uses an
is
of four, and an implanted
boron surface layer having a
con’eentration
somewhat
greater than the concentration
are chosen so that
over
a factor
device
by about
gate
gate insulator
exposure, it was more convenient
to use contact masking with high quality
master masks for process develop-
by ion implantation
ion-implanted
that
design
capacitance,
for the thicker
FABRICATION
lead to the
polysilicon
The thicker
of Fig. 4(a).
leakage
DEVICE DESIGN
considerations
device structure
utilizing
gate
increase,
4(b),
The
ION-IMPLANTED
the
was set at 4 V for the ion-implanted
voltage
cross sections for (a) scaled-down device struccorresponding
ion-implanted
device structure.
of
regions.
self-
process which
in this respect is offset by the decreased
threshold
,y~~=-lv
currents.
4 (a).
reduced
benefit
. . . . . . . . . . . . . . .1(
.. . . . . . .
layer
from the substrate
by the ion implantation
overlap
To compensate
4. Detailed
ture, and (b)
The
the
the ion-im-
depletion
and 4(b) ], and due to the natural
source and drain
-...
7.5x lo15cnl-3
Fig.
will
4(a)
with
increased
the source and drain
afforded
reduces
.
p-Si
1
ory
Figs.
are reduced
due to the
separating
alignment
(b)
capacitances
structure
As”
implantation
During
regions
(100 keV),
this
2000-A
high dose
through
step, however,
Authorized licensed use limited to: Universidad de Sevilla. Downloaded on November 01,2023 at 18:40:47 UTC from IEEE Xplore. Restrictions apply.
the
the
DENNARD
ei!
al.:
ION-IMPLANTED
MOSS13T’s
261
V,(fo, vw~=-l) [v]
z:~
,,-.,
_
:\
6-
t5
m‘E ~ ~
l!i
!
ORIGINAL
IMPLANT
\, i
Ns
;
~
e
-i
~
X3 -/
Z*
+IOEALIZED
STEP
FUNCTION
;
\\
:
‘1
;,
;
/
2+
#
4
I-
0
AFTER
ANNEALING
~ \l‘.,
_
‘...
tdb
Fig. 5. Predicted substrate doping profile for basic ion-implanted
device design for 40 keV BI1 ions implanted
through the 350-A
gate insulator.
Fig. 6. Calculated
and experimental
substrate sensitivity
characteristics for non-implanted
devices with 200- and 350-A gate
insulators,
and for corresponding
ion-implanted
device with
350-A gate insulator.
polysilicon
ing, the boron
plant,
gate masks
absorbing
the channel
all of the As”
etching
process
used to delineate
sloping
sidewall
which
ions underneath
(or source)
allows
overlap
implantations
sulating
contact
layer
greatly
regions,
and
2000-A
contact
source and drain
regions
during
the final
an annealing
annealing
modeling
substrate
atoms/cm~
oxide,
doping
channel
is shown
cent
of
the
in Fig.
incident
were 50 O/D
for the
a final
in-
using
Then,
regions
the
were de-
and delineated.
shallow
implanted
by a suitably
penetration
is 6.5
x
of the
implantation
CHANNEL)
profile
for
5. Since
dose,
10~1 atoms/cm2.
sian
function
For
40 keV
deviation
were
[ 131. After
The
is given
added
B“
the
due to
metaliza-
in forming
to the
ions,
taken
the heat
the
by
the
background
projected
as 1300
treatments
ANALYSIS
on
A and
6.7
the
oxide
dose
representation
in
lightly
3 per-
the
doping
500
silicon
at the
dashed
range
gate
and
time
Gaus-
level,
iV~.
standard
i%, respectively
of the subsequent
process-
the
final
offers
the advantage
parameters.
inter-
concentration.
For
to use a simple,
ideal-
of the doping
profile,
predicted
that
The
profile
rather
well
it can be described
three
profiles
by a few
shown
in Fig.
5
all have the same active dose.
Using the step profile,
old voltage
tions
a model
has been developed
of Poisson’s
equation
[11 ], The
the vertical
with
dimension
effects. Results
plots
condi-
considers
account
voltage
only
for horizontal
of the model
the threshold
solutions
boundary
model
and cannot
thresh-
piecewise
appropriate
Fig.
6 which
for determining
from
one-dimensional
short-channel
are shown
versus
in
source-
to-substrate
bias for the ion-implanted
step profile shown
in Fig. 5. For comparison,
Fig. 6 also shows the substrate
characteristics
a 200-A
doping,
X 10’1
350-A
absorbs
concentration
the
it is convenient
simple
sensitivity
density.
the 40 keV,
active
surface
ap-
step. After
incident
the
and
(LONG
implant
purposes
ized, step-function
with
The
reflect from the silicon-oxide
raise
proximates
to decrease the fast-state
ONE-DIMENSIONAL
thereby
out the
step of 400 “C for 20 min
gas was performed
in the silicon
and
spreading
was accomplished
junction
at
face
using
as shown by the solid line in Fig. 5. ‘The step profile
was deposited
the
the
11 min
deposition.
to
to avoid
diffusing
were obtained
out the
was applied
directly
chosen metallurgy
alloying
a computer
program
developed
by F. F. Morehead
of
our laboratories.
The program assumes that boron atoms
profiles
to anneal
holes to the n+ and polysilicon
Electrical
by the heavier
in a
of ASP5
and 40 fI/D
thick
chemical-vapor
as shown
dashed line. These predicted
follow
the AS’5 implant,
and the metalization
tion
at 900°C,
sheet resistances
areas. Following
oxide
steps that
adequate
without
and drain
low-temperature
fined,
20 min
doses. Typical
the source
polysilicon
penetration
is redistributed
The
to be of the order of 0.2
processing
is more than
damage
implanted
for
the im-
there.
the gates results
a slight
is estimated
include
which
implantation
from
the edges of the gates, The gate-to-drain
p, The high temperature
1000°C,
region
dose incident
and
for
gate insulator
for
gate insulator
a hypothetical
like
stant background
the
the implanted
doping
nonimplanted
and a constant
device
device
background
having
structure
a 350-A
and
like the nonimplanted
a con-
structure.
The nonirnplanted
200-A case exhibits
a low substrate
sensitivity,
but the magnitude
of the threshold
voltage
is also low. On the other
hand,
the nonimplanted
350-A
case shows a higher threshold,
but with an undesirably
high substrate sensitivity.
The ion-implanted
case offers
both
a sufficiently
high
threshold
voltage
and a reason-
ably low substrate sensitivity,
particularly
for V~.S,,I~>
1 V. For Vs..,,,,, < 1 V, a steep slope occurs because the
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262
IEEE
surface
inversion
the depletion
not
exceed
planted
tion
layer
region
~,
the
step
V..,,,,,
V,.,u,b
reasonably
200-A
allows
higher
adequate
conditions
relatively
the
implanted
design margin
level
bias
so that,
which
the threshold
will
for
//
//
+//
//
+//
+/’
‘T-
10-s
+1
4’
I
g
a
K
n
i
/
;1
~ ,8(3 ~vfie~Qd~
y{~,~l’
10-9
is
/-EXPERIMENTAL,
L=9,75p
h86p J.17Y I
,~-lo If
0.0
0,2
0.4
0.6
1.2
I ,0
0.8
.1.4
GATE VOLTAGE, Vg (V)
which
worst
case.
reduce
the
still
,+f
,+
/’r’f’
voltage
design
under
effects
as required
of
to 4 V)
10-7
U
K
K
~
range
the threshold
enough so that the device can be turned
conduction
H“
~-
slowly
substrate
1974
OCTOBER
lop
1,2+
,+/
Vd ❑4V
v,u~=-IV
-m
substrate
potential
However,
considerably),
im-
10-6
to the slope of the non-
(e.g., short-channel
threshold
~
the deple-
doped
CIRCUITS,
CALCULATED,——
L= 0,8/L
gate does
doped
OF SOLID-STATE
,~-5
while
over the operating
similar
for
the
heavier
a fixed
(e.g., ground
design.
is significantly
the
then increases
with
low and very
implanted
under
the lighter
sensitivity
of the source voltage
is obtained
1 V, at inversion
>
Thus,
– 1 V, the substrate
of
into
voltage
[11],
silicon
width
now extends
and thethreshold
with
in the
For
region.
region
in the channel
JOURNAL
Fig. 7. Calucu!at.ed
acteristic
for basic
lengths with V,u, z
be high
and experimental
subthreshold
turn-on charion-implanted
design for various channel
– 1 V, V. z 4 V.
off to a negligible
dynamic
memory
given
Fig.
ap-
r
1
i
i
,
1
I
1
1
plications.
Experimental
results
measurements
10 ,p) which
agree
this
have
result,
well
with
10’1 atoms/cm2
x
of 40 kel’
rather
than
and 6,7
drain
by
the
into
gate.
which
uniform
data
curve.
design
CHANNEL)
A
value
due
channel
this
which
been
[14],
the
leads to
developed
problem
is
an electric
field
the ioncurrent
transport
[16]
utilized.
The
Chang
strate
of Kennedy
computer
program
and P. IIwang
doping
The
profiles
numerical
calculate
and Mock
was
current
the turn-on
the
was
by
abrupt
W.
sub-
for these devices.
transport.
behavior
vice by a point-by-point
[15],
modified
[171 to handle
considered
model
was used to
de-
of the device
cur-
rent I“or increasing
values of gate voltage.
Calculated
results are shown in Fig. 7 for two values of channel
longlength in the range of 1 p., as well as for a relatively
channel
device
with
L
to a width-to-length
=
ratio
of 4 V was used in all
rcdllccd
shifts
to the
order
to a lower
threshold
and a drain
cases. As the
voltage
characteristics
behavior.
This
current
level
identified
at
from
jected
is
acteristics
substrate
threshold,
in
all
cases
with
MOSFET’S
can
also
be
the
manner
device
current
the
the
computed
of
Fig.
prochar-
3 they
gave
a resultant
The technique
pendix.
small
various
and
show
Another
short
devices
tially
constant
amount
L
>
were meas-
the
different
data
from
7
curves,
values of L.
is shown
is plotted
threshold
further
in Fig.
calculated
2 p, and falls
with
model.
in the Ap-
of this
as L is decreased
dccrca.ses more rapidly
Vt,
lengths
are plotted
voltage
The
at
used
is described
the somewhat
the threshold
for
in
A was
the chan-
with
of presentation
length.
10-7
determining
results
agreement
considering
form
small
error
with
current
of the two-dimensional
experimental
good
of
channel
for experimentally
for very
‘Ike
designs considered
gave a higher
the value
lu-ed to test the predictions
of channel
Vqz
actual
When
concentrations
with
tion
m
in
the
V*.
so, for simplicity,
make
(a linear
plotted
0.75 V. Some of the other
occurs at about
Id
as
4 X 10-8 A at threshold
for all device lengths. The band
bending, +,, at this threshold
condition
is approximately
8 where
a transi-
3
voltage,
were
especially
of the
Fig.
threshold
Fig.
tion from the exponential
subthreshold
behavior
response on this semilogarithmic
plot) to the
square-law
length
characteristic
due to a lowering
The threshold
the turn-on
voltage
channel
of 1 p, the turn-on
of threshold
design with
nel length
cases were normalized
of unity,
gate voltage
voltage.
10-7 A where
10 ,fl. All
Fig. 8. Experimental
and calculated
dependence
voltage on channel length for basic ion-implanted
V,.b = –1 v, v. = 4 v.
heavier
of the ion-implanted
computation
910
by the non-
pattern
that is difficult
to approximate.
For
implanted
case, the two-dimensional
numerical
model
12345678
SOURCE-DRAIN SPACING, L (MICRONS)
of the
controlled
have
structure
the
for the
penetration
normally
behavior
profile
lengths,
to account
to
region
I_J???5
ANALYSIS
short-channel
for the ion-implanted
doping
higher
some models
for
These
was used to achieve
is inadequate
lowering
the
account
implant
sufficiently
While
complicated
6 from
(i.e., L =
calculated
the slightly
model
voltage
field
effects.
the
(SHORT
For devices with
one-dimensional
in
long devices
1011 atoms/cm2.
x
TWO-DIMENSIONAL
threshold
also
no short-channel
reasonably
35 keV, 6
are
made on relatively
voltage
in
as a funcis essen-
by a reasonably
2 to 1 p, and then
reductions
in L, For
Authorized licensed use limited to: Universidad de Sevilla. Downloaded on November 01,2023 at 18:40:47 UTC from IEEE Xplore. Restrictions apply.
DENNARDet
ION-IMPLANTEDMoSF@i3
al.:
263
CALCULATED THRESHOLD VOLTAGE
vd=+4v
“9
[ VOLTS ) FOR Ids = 10-7 AMPERES
y_?-.~
L=o.8p
BASIC
laop
N+
lo2p
10p
DESIGN
(a)
]
7.5E15
J v,”~‘ ~ Vm
?
DEEPER
~+
m
N+
SOURCE/ORAIN
----
JUNCTIONS
Fig.
9.
Experimental
implanted
Curve
tracer
V, gate
circuit
drain
design
with
parameters;
voltage
(U
than
give V~ = l. O&
alone.
applications
This
on a given
chip,if
istics
nel length
are shown
condition.
The general
tochipdue
effects
short-channel
taken
from
energy
atoms/cm2,
respectively.
degree of control
drain
larger
observed
results
threshold
voltage
indicated
voltages.
simulations
in Fig.
as a function
The first perturbation
of channel
Viewed
device
length
would
(from
1.0 to 1.2 p) to obtain
design.
junctions
in perspective.
This
voltage
another
of
for the
representa-
to give an apfor the shorter
way, the minimum
puts
a threshold
the value
Another
was considered
lighter
by
concentration
The results
values
length
have to be increased
the basic
same threshold
The
has been discussed thus far.
in threshold
devices in Fig. 10(b).
higher
Su
im-
parameters.
tabulates
for
a factor
in the
comparable
to
shallower
perturbation
from
Fig. 10. Threshold
voltage
calculated
using two-dimensional
rent transport
model
for various
parameter
conditions.
band voltage
of –1.1
V is assumed,
considering
is about
more
that. the boron
20 percent
short-channel
calculated
pared
effects
values
to the basic design.
good substrate
is completely
depleted
[Fig.
the
1O(C) ].
to be similar
to the
show
concentration
[Fig.
appreciably
for this
tions.
This
with
Also,
with
region,
threshold
concentration
[Fig.
to
give
10(d) ]. With
case for
with
a device
the
same
the shallower
a
long-channel
profile,
and
onlY
less
depth
lines
turn-on
from
layer
In
L
may
the drain
into
this
due
the source
drop across those j unc-
silicon
conditions,
under
near
+$, appears
help prevent
the
0.8 p. is
of the basic
around
and doping
in the
fact,
=
is apparently
widths
particularly
the band bending,
which
improvement
these bias
tion
heavier
effect.
important
at threshold,
as deep, wiih
for this case
less short-channel
the same as for an L = 1.0 ,p. device
about
much
half
source.
such a cascj again
10 (e) 1. The calculations
case of deeper j unc~ions. The next possible departure from
the basic design is the use of a shallower boron implantaonly
a grounded
to give the same long-chan-
a heavier
the lower voltage
give
with
have
doped region
with
nel threshold
and drain
device
to
implanta-
bias and still
considers
depletion
layer
com-
The last design perturbation
to the reduced
surface
the
thresholds
since the heavier
at turn-on
that
However,
the shallower
of 2, with
devices proved
region,
With
sensitivity
layer
channel
identical
design.
a slightly
in the silicon
occur.
to use zero substrate
depletion
in the
would
show almost
tion it is possible
threshold
the
dose implanted
curA flat-
less in this case, it was expected
was the use of a sub-
a long-channel
for smaller
by 20 percent
of the
:TRATE
@vm
in Figs.
and 6.0 X 10’1
depth to 0.4 ,P. This was found
doping
drain
to the basic design was an increase
reduction
basic design which
for
channel
10(a) is an idealized
Fig.
is the
No ex-
were also used to test
10 which
tion for the basic design that
in junction
chansource
data
a B“
of the design to various
are given
preciable
using
.
character-
a I.I-,P
devices.
and dose of 35 keV
The two-dimensional
the sensitivity
for many
of different
with
were
devices
plantation
strate
to this short-
as large as 4 V. The experimental
were
is reason-
9 for the grounded
traneous
6-9
be set
shape of the characteristics
for much
voltages
this
MOSFET
same as those observed
P
0.3 pwould
be tolerable
indeed
in Fig.
xj=o.4p
4
an expected
voltage
The experimental
for an ion-implanted
voltage
of L could
over
because of the tracking
can be achieved.
(b)
“
L = 1.3 *
would
ion12.2 ~,
0.5 V apart.
value
Forexample,
basic
W =
.30 Q, drain
1 ,P so that,
O.l Vfromchip
effect
devices
ofL
resistance
each
for
1.1 p, and
of L, the threshold
ably well controlled.
circuit
load
the nominal
greater
range of deviation
channel
characteristics
—1 V, L =
V in 8 steps
applications
somewhat
voltage
Vs.~ =
the
the
source
across this
where
is
where
depletion
the penetration
region
the
gate
of field
the
device
is controlled.
Authorized licensed use limited to: Universidad de Sevilla. Downloaded on November 01,2023 at 18:40:47 UTC from IEEE Xplore. Restrictions apply.
IEEEJouRNALoF soLm-STATECIRCUITS,
264
1.2
1
[
i
I
I
i
,<p:*--————
—*—
~ Lo -1
0
~ 0.8
I
1
I
OCTOBER 1974
*—*
k—
2
~
%’
a
i
~ 0,6.+
f
o
1
>
20 KeV,6Ellcm”2
2 0.4 g
Fig.
VOLTS (EXI?)
+ Vd = 0,05
g 0,2 I
11
0.0
01234
● Vd =4 VOLTS (EXH
A Vd =4 VOLTS (THEORY)
I
I
I
I
I
678910
L?(p)
1
t
11.
Experimental
voltage
on channel
and
calculated
length
for
dependence
ion-implanted
of
zero
I
threshold
substrate
bias
design.
CHARACTERISTICS OF THE ZERO SUBSTRATE
‘“’r————————————l
BIAS DESIGN
Since the last
be better
worthwhile
mental
and tested
obtain
10”
atoms/cm2
implanted
[11].
11 and corresponds
for a small
length,
channel
Data
4 V applied
much
on source-to-substrate
Bll
well
voltage
fully.
of
to the
to
it is
Experi-
were
In this
implant
layer
on threshold
less variation
as expected.
appears
effects,
design
lengths.
to the drain
very
drain
10(e)
more
to this
a shallower
1OOO-A depth
showing
its properties
various
6.0 x
in Fig.
of short-channel
corresponding
with
devices with
Data
shown
in terms
to review
devices
20 keV,
design
behaved
built
case a
was used to
voltage
in Fig.
calculated
values.
of threshold
The dependence
with
channel
of threshold
voltage
bias is shown in Fig. 12 for differ-
a constant
show that
low value for this measurement.
The results
the substrate
sensitivity
is indeed about the
voltage
was held at
same for this design with zero substrate bias as for the
original
design with V.u~ = —1 V. Note that the smaller
characteristic
values
with
of source
The turn-on
design,
a somewhat
both
I?ig. 13 for
flatter
relatively
(and drain)
experimental
different
lower
substrate
sensitivity
thresholds
for the zero substrate
and calculated,
values
of L. The
design
offers
version,
old
improved
turn-on
with
suitable
gate to ground.
gravates
design
For
the turn-on
if the device
for
[18].
with
V@
such
strong
is turned
elevated
Thus,
=
in-
subthresh-
applications
characteristic
Furthermore,
the situation
the basic
preferred,
control
is offset by the flatter
characteristic.
noise margin
barely
threshold
this advantage
the
of Fig.
13 is
off by bringing
its
temperature
ag-
for dynamic
memo~,
– 1 V presented
earlier
bias
are shown
relatively
in
small
shift in threshold for the short-channel
devices is evident;
however, the turn-on rate is considerably
slower for this
case than for the V,ub = – 1 V case shown in Fig. 7. This
is due to the fact that the depletion
region in the silicon
under the gate is very shallow for this zero substrate bias
case so that a large portion of a given gate voltage change
CIRCUIT PERFORMANCE WITH SCALED-DOWN DEVICES
The
very
performance
small
improvement
MOSFET’S
in
expected
integrated
from
circuits
of
using
com-
parably
small dimensions
is discussed in this section.
First, the performance
changes due to size reduction alone
are obtained
from the scaling
considerations
given earlier.
The influence
on the circuit
performance
due to the
structural
changes of the ion-implanted
design is then
discussed.
is dropped across the gate insulator
capacitance
rather
than across the silicon depletion
layer capacitance.
This
Table I lists the changes in integrated
circuit performance which follow from scaling the circuit
dimensions,
is discussed
voltages,
in some detail
for these devices
is
at high
voltage.
characteristics
Fig.
12. Substrate
sensitivity
characteristics
for ion-implanted
zero substrate
bias design with
channel
length
as parameter.
is also given in this figure,
of L, The drain-to-source
show
Vsource
-substrate
(VOLTS)
for these
is presented
ent values
devices
~,o,
o
approximately
in another
paper [11 ]. The consequence for dynamic
memory
plications
is that, even though the zero substrate
apbias
and substrate
doping
in the same manner
as the
device changes described with respect to Fig. 1. These
changes are indicated
in terms of the dimensionless
scal-
Authorized licensed use limited to: Universidad de Sevilla. Downloaded on November 01,2023 at 18:40:47 UTC from IEEE Xplore. Restrictions apply.
DENNASDet at.: 10N-1MH,.4NTED
iWOSFET’S
,.-5
,
265
,
20 KeV,6EII
TABLE
cm-z
SCALING
]o-6 . V,=4V
v$,~=o
Parameter
.
/.
W%~~ENTAL
Line
+
resistance,
Normalized
,0-8
L=l.lp .
10-9
~.li)o(
*)
Line
Line
L=lOp
A
;
CTvj
,[
o
R~
=
pL/Wt
drop
0.2
0.4
1.0
0.6 .0.8
vg [v]
1.4
1.2
pacitances
are driven
ances V/I
giving
1
TABLE
SCALING RESULTS
or Circuit
device
density
circuits
from
or circuit
Power
Power
L, W’
Na
K2
II,
are necessarily
of the more
1/.
1/.
VC/Z
dissipation/circnit
density
VI/A
VI
etching,
l/K
constant
very small
which
1
comparable
volubility
would
It
K. Justifying
be tedious,
is argued
so
that
miniaturized
these results
only
circuits
This follows
in digital
MC)SFET
ance
circuits
V/I
of each device
lower
given
voltage
the supply
by
a voltage
is unchanged
is made that parasitic
negligible
examined
to the reduced
are either
level
is given.
are reduced
because the quiescent
detail
in the
supply
or unchanged
subsequently.
voltages
by scaling,
The circuits
because
by
resistance
the device
of a given
K.
factor
constant
ages. The response time
scaling.
An
are
will
line
ages are reduced
Noise
margins
generated
at
density
voltage
Vt
which
by the lower
signal
to the same
but
voltage
at
volt-
because of the reduction
which
the electrode
by K’ in the area of these com-
is partially
spacing
by
cancelled
K
by the decrease
due to thinner
insulating
directly
with
the
current
levels) ~ but
to the lower
operating
limited
by
its
is K
volt-
transmission
time
constant
in a scaled-down
causes
a
circuits,
latively
minor,
of
is increased
concern,
these conductivity
but
micron
circumvented
the power
conductor
reliability
they
in high
buses and
significant
The
by
K,
conventional
problems
become
dimensions.
In
are refor
problems
may
linebe
performance
circuits
by
the use of n+ doped
avoiding
by widening
lines for signal propagation.
swings,
Due to the reduction in dimensions, all circuit elements
(i.e., interconnection
lines as well as devices) will have
their capacitances
reduced by a factor of K. This occurs
ponents,
limit
assumptions
speeds inherent
in the scaled-down
devices when signaI
propagation
over long lines is involved, Also, the current
properly
are reduced,
these
be
operate
noise coupling
solid
R~C, which is unchanged by scaling; however, this makes
it difficult
to take advantage
of the higher switching
as well if each parameter
internally
for
where
of an unterminated
is characteristically
to
becomes
in such a line is therefore
decreased
levels
divider
widths
accuracy.
the
down
considerations
Under
drop
in comparison
on
to remain
films
lines
line increases
The IR
(with
greater
metal
scattering
scaling
MOSFET
the same time
impurity
because
and is also reasonable
in conductivity.
K.
(e.g.j
is considered
semiconducting
the resistance
scales as shown in (2), and furthermore
because the
reduced
tolerance spreads on Vt should be proportionately
percentage
and
increase
threshold
in (2) is controlled
doped
widths
the mean free path
to the thickness),
arise
of the conductors
the
for
(until
times
elements
which
any
of problems
requirements
conductivity
levels
of two or more devices, and because the resist-
assumption
either
treatment
voltages
in proportion
or some intermediate
consisting
a. simplified
all nodal
voltages.
here in great
with
is reasonable
circuit
is decreased only by
resolution
dimensions
degenerately
ing factor
along
by K2,
even if many
area of conductors
the thicknesses
reduced
levels,
Since the
K8.
unchanged.
a number
while the length
etc. ). The
1/.
1 /K2
a re-
integrated
the cross-sectional
stringent
by
Thus,
is essentially
in Table
by
1/.
ca-
resist-
with
is also reduced
on a given
problem
the fact that
K
device
and current
constant,
are placed
is decreased
Factor
reduced
times
is improved
remains
It is assumed here that
dlmensiontO.,
concentration
V
1
unchanged
transition
product
area of a given
the power
As indicated
PERFORMANCE
Scaling
by the
These
duced by K’ due to the reduced voltage
I
Parameter
widths.
in the delay time of each circuit by a
power dissipation
of each circuit is re-
so the power-delay
FOR CIRCUIT
layer
decreased
sultant reduction
factor of K. The
and experimental
subthreshold
turn-on
charion-implanted
zero substrate
bias design.
Capacitance
EA It
Delay time/circuit
K
K
depletion
chip, the cooling
Device
Doping
Voltage
Current
Factor
K
IR~/V
response time R~C
current
density
I/A
more
Device
Scaling
voltage
and reduced
.
“
13. Calculated
acteristics
for
LINES
.
,0-10
Fig.
II
FOR INTERCONNECTION
/
,0-7
~
&
RESULTS
in
films
Use of the
paper
will
give
ion-implanted
similar
devices
performance
considered
improvement
in this
to that
of the scaled-down
device with K = 5 given in Table I.
For the implanted
dcviccs with the higher operating voltages (4 V instead
(0.9 V instead
of 3 V)
and higher
of 0.4 V), the current
threshold
level will
voltages
be reduced
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IEEEJOURNALOFSOLID-STATE
CIRCUrrS,OCTOBER
1974
266
to (Vg — T’t) ‘/tox
to about
in proportion
current
in the scaled-down
per circuit
ate about
devices,
a factor
ing ancl dec~:ased
such
essentially
junction
depth.
so that
in a typical
12
I
I
1
J
II -
im-
will
show
substrate
dop-
Some capacitance
the
circuit
lines
overall
would
847
capacitance
and for the directly
+/
~
be
be somewhat
20 KeV,6EII Cniz
Vg=Vt+ 0.5 VOLTS
V,j =0.05 VOLTS
v~ub=f)
9–
ele-
would
+/:
10-
–
z
x6 z
z
& 5-
less
of two. The delay time per circuit which
to VC/I
thus appears to be about the
same for the implanted
micron
lines
interconnection
unchanged
improvement
less in the
due to the lighter
as metal
than a factor
is proportional
of two
and n+ interconnection
the same improvement
ments
of the
is thus about the same in both cases. All device
capacitances
planted
80 percent
device. The power dissipation
scaled-down
/!
+
+/
4-
devices shown in Fig. 4,
L= Lma~k-AL
/
1
3/
NJMMARY
This
paper
has considered
characterization
vices.
of very
These
solution
integrated
lithographic
pattern
writing.
leads
some
an all ion-implanted
formance.
A
with
a l-P
lower
circuits
ion-implanted
an n-channel
control,
4 x
350-A
10’5 atoms/cm’
~gate insulator,
– 1 V. Also
tended
from
from
the
for
presented
an increased
sizable
using
of view
MOSFET
source-folmemories.
bias
that
subthreshold
implant,
substrate
small
MOSFET)S
comparably
small
dimensions
in
of
in-
suffers
range.
Finally
A
technique
channel.
perimental
length
for
determining
L for very
data is described
small
the
used
to determine
L.
that
pendent
intercept
the device
channel
=
(Al)
LP.m
turned
sheet
on in the below-pinchoff
resistance
is relatively
inde-
versus L~,,k will
of L. Then, a plot of w&han
t,he Lm.,ll axis at AL because AL = L~.~~ — L,
where AL is the processing
reduction
sion
etching.
due to exposure
and
is illustrated
The experimental
14 were obtained
in the mask dimenAn
example
of this
in Fig. 14.
of W and l?,,,.
values
as follows.
First,
used in Fig.
the sheet resistance
of the icm-implanted
n+ region was determined
using a
relatively
large four-point
probe structure.
Knowing
the
n+ sheet resistance
drain
resistance
allows
us to compute
the source and
R. and R., and to deduce W from
of a long, slender,
ance can be calculated
R,,hnn= VC,,J1,
circuits
n+ line. The channel
the
resist-
from
= (V, – I,(R,
+ R. + 2Rc + R1omi))/Id,
(A2)
of
was projected.
DETERMINATION
technique
length,
from
where Rc is the contact
resistance
of the source or drain,
and Rla,,l is the load resistance of the measurement
circuit. Id was determined
at VO = Vt + 0.5 V with a small
APPENDIX
EXPERIMENTAL
0, and with
region,
resistance
attractive
but
expected
integrated
a
bias
design
is more
turn-on
was
that used a 35
implant,
a 100
control
improvement
very
of experimental
on the observation
technique
turn-
sensitivity
source/drain
an applied
4
where li,(.~~~ 1s the channel resistance, and pCl,~~the sheet
resistance of the channel. For a fixed value of V~ — Vt >
proved
of subthreshold
of threshold
performance
Illustration
WR.w
degree of
was an ion-implanted
zero substrate
the point
14.
channel
device paof the study
high-density
lMOSFET
B“ channel
As”
and
Fig.
model
structures
and substrate
achieved by an experimental
keV, 6,0 x 10” atoms/cm’
keV,
transport
the relative
combination
on range, threshold
3
area. or per-
polysilicon-gate
for
2
approach
such as those used in dynamic
The most satisfactory
/1
,f/,!,!I
Lmosk (})
requirements
device
current
length
00
AL=0.86P
device can
scaling
arising
from different
The general objective
channel
/
can bc used to overcome
in predicting
short-channel
effects
rameter combinations.
I-
high-re-
It was then shown how
sacrificing
use with
highly
relationships
technological
structure
without
valuable
was to design
by
/
de-
as electron-beam
this direct
two-dimensional
for
particularly
fabricated
gate insulators.
these difficulties
to
show how a conventional
challenging
such as very thin
applicable
such
and
switching
set of scaling
in size; however,
to
modified
circuits
techniques
that
fabrication,
MOSFET
are
A consistent
were presented
be reduced
the design,
small
considerations
miniaturized
2-
OF GHANNEL
LENGTH
the
electrical
applied drain voltage of 50 or 100 mV. The procedure is
more simple and accurate if one uses a set of MOSFET’S
having different
values of L~.,~ but all with the same
from
value
effective
MOSFET’S
here. The technique
ex-
is based
L.,..],
of W,nnsl,.Then
one needs only to
in cwder to determine
plot
Rchan
AL.
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versus
DENNARDet U1.: ION-IMPL.4NTEDMOSFET’S
267
ACKNOWLEDGMENT
We wish to acknowledge
Robert
Terrell,
contributions
of
B. L. Crowder
and F. F. ?vIorehead who provided
ion implantations
and related design information.
the
Also
important
Chang
Walker
the valuable
were the contributions
to
two-dimensional
and V. DiLonardo
paration
and testing
of l?. Hwang
device
assisted
activities.
with
The
cated by the staff of the silicon
pre.
at the
[11
F. Fung, M. Hatzakis,
and C, H. Tingj “Electron-beam
cation
of ion implanted
high-performance
FET
J. Vat. Sci. Technol.,
vol. 10, p. 1082, 1973.
fabricircuits, ”
[2]
J. M. Pankrantz,
gain,
low-noise
lithography,
“ in
Research
center.
RE~EREN-CES
Tech.
1973, pp. 44-46.
Dec.
[31
[41
H. T. Yuan,
and L. T. Creagh,
“A
transistor
fabricated
with
electron
Dig.
Int.
Electron
Devices
H, N. Yu, R. H. Dennard,
T. H. P. Chang,
“.kn
experimental
high-density
memory
with electron
beam,”
in IAWCC Dig.
inn
. . !w–wl
‘R. C. Henderson,
R. F. W. Pease,
~:~
[91
[111
Tech.
[131
[141
[151
[161
[171
[181
masking,
IBM
Electron
thin
memory
communication
1973,
Voshchenkow,
P.
p-channel
electron
Meeting,
photoresist
Fritz
L. Kuhn,
devices,”
H.
and
and H.
presented
Washington,
D. C.,
of electron
beam
Semicond,
Silicon
R. Huff
and
R. R. Bur-
S. E. Schuster,
Solid-State
Circuits,
V. L. Rideout,
F,
1972.
‘{Device
F. F. Fang and
trons in inverted
1968,
for ion
Develop.,
implanted
n-channel
to be published.
A. B. Fowler, “Transport
Si surfaces,
” Ph~s.
Rev.
elec169, p. 619,
W. S. Johnson,
IBM
System
Products
Division,
E. Fishkill,
N. Y., private
communication.
H, S. Lee, “An
analysis
of the threshold
voltage
for short
channel
IGFET’s,”
Soiid-State
Electron.,
1973.
D. P. Kennedy
and P. C. Murley,
“Steady
cal theory
for the insulated
gate
field
IBi14 J. Res. Develop,,
vol. 17, p. 1, 1973.
vol.
state
effect
16, p.
1407,
mathematitransistor,
”
M. S. Mock,
“A two-dimensional
mathematical
model
of
the insulated-gate
field-effect
transistor,”
Solid-State
Electron., vol. 16, p, 601, 1973.
Division,
W. Chang and P. Hwang, IBM System Products
Essex Junction,
Vt,, private
communication.
R. R. Troutman,
“Subthreshold
design
considerations
for
insulated
gate field-effect
transistors,
” IEEE
J. Solid-State
Circuits,
vol.
SC-9, p. 55, April
1974.
gineering,
Munich,
Technical
Germany.
Germany,
as Assistant
of Electrical
in
Pro.
En-
University
of Munich,
During
this period
he
was working
on the synthesis
of linear
and
the IB”M
T. J. Watson
Re.
~i~ital
networks.
In 1966 he joined
search Center,
Yorktown
Heights,
N,Y.,
where he is currently
a
member
of a semiconductor
device
and process
design
group.
His current
technical
interests
involve
various
aspects of advanced
integrated
circuits
like
miniaturization,
device
simulation,
and
u.~
ion implantation,
assignment
at the
From
IBM
Scptcmbcr
Laboratory,
is a member
of the
1973 he was on a. one
Boeblingen,
Germany,
Nachrichtentechnische
year
Gesell-
MOS-
properties of
vol.
in Tuebingen,
tran.
compleIEEE
J.
vol. SC-7, pp. 146-153,
April
Gaensslen,
and A. LeBlanc,
was born
Prior
to 1966 he served
fessor in the Department
Dr. Gaensslcn
Sclmft.
“Design
Gaensslen
versity
of Munich,
Munich,
1959 and 1966, respectively.
14, p.
N. Yu,
at the
H,
Germany,
on October
4, 1931, He received
the Dipl.
Ing and Dr. Ing. degrees in electrical
engineering
from
the Technical
Uni-
layers
vol.
R. M. Swanson
and J. D. Meindl,
“Ion-implanted
mentary
MOS transistors
in low-voltage
circuits,”
considerations
IBM
J. Res.
and devclo~ment
of
Since 1963 he has been
at the IBM
T. J. Watson
Research
Center,
Yorktown
Heights,
N. Y., where he worked
with a group exploring
large-scale
integration (LSI),
while making
contributions
in cost and yield models,
MOSFET
device and integrated
circuit
design, and FET
memory
cells and organizations.
Since
1971 he has been manager
of a
group
which
is exploring
high density
digital
integrated
circuits
using advanced
technology
concepts
such as electron
beam ~attcrn exposure.
ranlithoDec.
of n-channel
insulated-gate
field-effect
J. Res. Develop.,
vol. 17, p. 430, 1973.
H.
applications,
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gess, eds., pp. 830-841,
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R. H, Dennard,
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resolution
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vol.
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dom
access
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memory
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with
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[51
Pittsburgh,
In 1958 he joined
the IBM
Research
Division
where his experience
included
study
of new devices
and circuits
for logic
and
were fabri-
facility
T. J. Watson
technology
Technology,
J. J.
the mask
devices
born
in
the B.S.
and M .S. degrees
in electrical
engineering
from ,Southern
Methodist
University,
Dallas, Tex., in 1954 and 1956, respectively,
and
the Ph.D. degree from Carnegie
Institute
of
and W.
computations.
H. Dennard
(M’65)
was
Tex., in 1932. He received
Hwa-Nien
Yu
(M’6,5)
was born
in Shanghai,
China, on January
17, 1929. He received
the
B. S., M.S,, and Ph,D,
degrees in electrical
engineering
from
the University
of Illinois,
Urbana,
in 1953, 1954, and 1958, respectively.
While
at the University,
he was a Research
Assistant
in the Digital
Computer
Laboratory
and worked
on the design of the
Illiac-11
computer,
Since joining
the IBM
Research
Laboratory
in 1957, he has been
engaged
in various
exploratory
solid-state
device research
activities.
After
working
with the Advanced
Systems Development
Division
from
1959 to 1962, he rejoined
the
Research
Division
in 1962 to work
on the ultra-high
speed germenium
dcvicc
technology.
Since 1967, he has been engaged
in
advanced
silicon
LSI device technology
research.
He is currently
the Manager
of Semiconductor
Technology
at the IBM
T. J.
Watson
Research
Center,
Yorktown
Heights,
N.Y.
Dr. Yu is a member
of Sigma Xi.
Authorized licensed use limited to: Universidad de Sevilla. Downloaded on November 01,2023 at 18:40:47 UTC from IEEE Xplore. Restrictions apply.
IEEE
268
V.
Leo
N.J.
gree
Rideout
in 1941. He
with honors
(S’61–M’65)
was
received
the
in 1963 from
B.S.E.E.
dethe Univer-
born
JOURNALOF SOLID-STATE
CIRCUITS,OCTOBER
1974
1959 where
in
sity
of Wisconsin,
Madison,
the M.S.E.E.
degree
in 1964 from
Stanford
University,
assisted
Schottky
current
transport
in
platinum
on semiconductors.
From
1963 to 1965 he was a member
of the technical
staff
Bell Telephone
Laboratories
where he worked
on high-frequency
germanium
transistors
on potassium
tantalate.
of
ently
the
and metal-semiconductor
Schottky
barriers
In 1966 he spent
a year as a Research
engaged
Mr.
the
in
fabrication
of
Bassous
American
density
of 20 technical
Dr. Rideout
Beta Pi, Eta
silicon
FET
papers
technology.
He is the author
versity
of London,
degree
in physical
Brooklyn,
Brooklyn,
From
British
1954
Boys’
to
1959
School,
he
England
from
the
1965.
taught
Alexandria,
on
in 1953,
Polytechnic
Chemistry
Egypt.
of
for
and
He
went
to
MS.
of
at
the
France
in
on
infra
A. Edison
Research
Orange,
N.J.,
where
the
the
and
processes
used
in
circuits.
Electrochemical
Advancement
R. LeBlanc
Society
of
(M’74)
and
Science.
received
the
Mexico,
Prior
to
the D. SC. degree in
from
the University
Albuquerque,
joining
in
IBM,
Vt., in 1957, he was
an electrical
engineer
and
the
Institute
Physics
materials
respectively,
and
trical
engineering
Tau
September
1,
from
the Uni-
1 year
B.S.
degree
in electrical
engineering,
and
the
M.S. degree in physics
from the University
of Vermont,
Burlington,
in 1956 and 1959,
New
Egypt,
chemistry
of
integrated
Andre
and 3 U.S. Patents.
Londonj
chemistry
N.Y. in
study
silicon
is a member
or co-author
is a member
of the Electrochemical
Society,
Kappa
Nu, Phi Kappa
Phi, and Sigma Xi.
Ernest
Bassous was born in Alexandria,
1931. He received
the B. SC. degree in
the
Association
Assistant
in the department
of Materials
Science
at the Technological
University
of Eindhoven,
Eindhoven,
The Netherlands,
studying
acoustoelectric
effects in cadmium
sulphide.
In 1970 he
joined
IBM
Research
in the device research group of Dr. L. Esaki
where he worked
on fabrication
and contact
technology
for multiheterojunction
“superlattice”
structures
using
gallium-arsenidephosphide
and gallium-aluminum-arsenide.
Since 1972 he has been
a member
of the semiconductor
device
and circuit
design group
of Dr. R. Dennard
at the IBM
T. J. Watson
Research
Center,
Yorktown
Heights,
N.Y,
His present
research
interests
concern
high
for
his activities
included
studies
in arc discharge
phenomena,
ultra
violet
absorption
spectroscopy,
and
organic
semiconductors,
In 1964 he joined
the IBM
Research
Laboratory,
Yorktown
Heights,
N.Y.,
to work
As a member
of the Research
staff he is pres-
sili-
barriers,
worked
worked
at the Thomas
Laboratory
in West
Stanford,
Calif.,
and the Ph.D.
degree
in
materials
science in 1970 from
the University
of Southern
California
(U.S.C.),
Los
Angeles.
His thesis
work
at U.S.C.
under
Prof.
C. R. Crowell
concerned
thermally
cide
he
red
detectors
at
the
Centre
National
d’Etudes
des Telecommunications,
Issy-lesMoulineaux,
Seine.
From
1960 to 1964 he
elecof
1962.
Essex
Junction,
affiliated
with
G.E. as
and also with Sandia
Cor~oration
in conjunction
with
the University
of New Mexico.
in 1959 he took an educational
leave of
absence to complete
his doctorate.
He is presently
a member
of
the Exploratory
Memory
Group
at the IBM
Laborato~,
Essex
Junction,
where his current
technical
interest
includes
a study
of
short-channel
MOSFET
devices.
He has authored
five publics.
tions
ports.
Dr.
and
twelve
LeBlanc
papers,
is a member
as well
as several
of Sigma
Xi
and
IBM
Tau
Technical
Beta
Authorized licensed use limited to: Universidad de Sevilla. Downloaded on November 01,2023 at 18:40:47 UTC from IEEE Xplore. Restrictions apply.
Pi.
Re-