2:1 multiplexer (for selecting between A and NOT A)
4:1 multiplexer (for selecting between the two inputs and the output of the adder)
4-bit adder (for addition and subtraction)
Here's the truth table for the ALU:
Mode Select Operation
Y
0
00
A AND B
AND
0
01
A OR B
OR
0
10
A XOR B
XOR
0
11
NOT A
NOT A
1
00
A+B
ADD
1
01
A-B
SUB
Here's how you can implement the ALU using the components mentioned above: Implement the
NOT A operation using a 2:1 multiplexer. The select input of the multiplexer should be
connected to the Select input of the ALU. Connect A to one input of the multiplexer and NOT A
to the other. The output of the multiplexer should be connected to the input of the 4:1
multiplexer. Implement the addition and subtraction operations using a 4-bit adder. Connect A
and B to the inputs of the adder. Connect the carry-out output of the adder to an LED for
overflow detection. Connect the sum output of the adder to one input of the 4:1 multiplexer.
Implement the selection between the NOT A and A inputs and the output of the adder using a
4:1 multiplexer. Connect the output of the multiplexer to the output of the ALU. Implement the
AND, OR, and XOR operations using logic gates. Connect inputs A and B to the appropriate
inputs of the logic gates. Connect the outputs of the logic gates to the remaining inputs of the
4:1 multiplexer. Convert the output Y to a 7-segment display using a decoder.
In this lab, we designed a fully functional 4-bit ALU with logic and arithmetic operations
based on the specifications provided in Table 1. The ALU had two inputs, A and B, each 4-bit,
and two 2-bit select inputs for selecting operations, along with a 1-bit select Mode for selecting
the unit, either arithmetic or logic. The ALU output Y, which is 4-bit, was converted to a
7-segment display. For the results from arithmetic operations, an additional 7-segment display
was used to show the tens digit if the value was over 10, or to indicate the negative sign if the
value was less than 0. An LED light was assigned to reflect the situation when overflow
occurred.
To implement the ALU, we used a 2:1 multiplexer and a 4:1 multiplexer, along with a
4-bit adder for addition and subtraction operations. We also used logic gates to implement the
AND, OR, and XOR operations. The NOT A operation was implemented using the 2:1
multiplexer, and the selection between the NOT A and A inputs and the output of the adder was
done using the 4:1 multiplexer. The output Y was then converted to a 7-segment display using a
decoder.
In conclusion, the designed ALU met the specifications provided in Table 1 and could
perform various arithmetic and logic operations with 4-bit inputs, providing an output that could
be easily displayed using a 7-segment display.