IMX250 / IMX252 / IMX264 / IMX265
Support Package
Preliminary
The data except this specification conform to those of IMX250, IMX252, IMX264,
IMX265.
1. Description
This support package is intended to support product development.
2. Description Items
◆ Guideline for designing the printed circuit board
◆ Low voltage serial LVDS output interface
c.
◆ Communication port (4-wire serial)
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◆ Communication port (I C)
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◆ Pattern Generator (PG) function
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◆ How to get sensor information
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◆ Lens design guideline
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◆ FD white spots
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◆ FAQ
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits.
Rev. 2.0
1
IMX250 / IMX252 / IMX264 / IMX265 Support Package
Contents
1.
Description ---------------------------------------------------------------------------------------------------------------------------------- 1
2.
Description Items -------------------------------------------------------------------------------------------------------------------------- 1
3.
Guideline for designing the printed circuit board ------------------------------------------------------------------------------------ 4
3.1.
Application circuit.---------------------------------------------------------------------------------------------------------------------- 4
3.1.1.
Power supply pins ------------------------------------------------------------------------------------------------------------------ 4
3.1.2.
Other Pins ---------------------------------------------------------------------------------------------------------------------------- 6
3.2.
(Reference) Component -------------------------------------------------------------------------------------------------------------- 7
3.2.1.
Power supply IC -------------------------------------------------------------------------------------------------------------------- 7
3.2.2.
Decoupling capacitors ------------------------------------------------------------------------------------------------------------- 8
3.3.
Notes for designing patterns of printed circuit board. --------------------------------------------------------------------------- 9
Power supply pins ------------------------------------------------------------------------------------------------------------------ 9
3.3.2.
Wiring patterns for image output signals ( Low-voltage LVDS serial output ) -----------------------------------------12
c.
3.3.1.
In
4-wire Serial Communication Port ----------------------------------------------------------------------------------------------------13
4.1.
Overview --------------------------------------------------------------------------------------------------------------------------------13
4.2.
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4.
Register write/read operation -------------------------------------------------------------------------------------------------------14
I C interface communication port -----------------------------------------------------------------------------------------------------16
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5.
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Overview --------------------------------------------------------------------------------------------------------------------------------16
5.2.
Overview of the communication protocol-----------------------------------------------------------------------------------------18
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5.1.
State control (start, restart, stop of the communication) -------------------------------------------------------------------18
5.2.2.
Acknowledge bit -------------------------------------------------------------------------------------------------------------------18
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5.2.1.
Write/read operation of the registers ----------------------------------------------------------------------------------------------19
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5.3.
Note for access to register--------------------------------------------------------------------------------------------------------------20
7.
Pattern Generator ------------------------------------------------------------------------------------------------------------------------21
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6.
7.1.
Feature ----------------------------------------------------------------------------------------------------------------------------------21
7.2.
Register map for pattern generator function -------------------------------------------------------------------------------------22
7.3.
Common setting item for the PG ---------------------------------------------------------------------------------------------------26
7.4.
8.
List of Pattern --------------------------------------------------------------------------------------------------------------------------27
How to get sensor information ---------------------------------------------------------------------------------------------------------30
8.1.
Register map for sensor information ----------------------------------------------------------------------------------------------30
8.2.
The description of reading data ----------------------------------------------------------------------------------------------------30
8.2.1.
Type name Information -----------------------------------------------------------------------------------------------------------30
8.2.2.
Monochrome / Color Information -----------------------------------------------------------------------------------------------30
9.
Lens design guideline -------------------------------------------------------------------------------------------------------------------31
9.1.
10.
Optical system -------------------------------------------------------------------------------------------------------------------------31
9.1.1.
IMX250 / IMX264 Optical dimension ------------------------------------------------------------------------------------------31
9.1.2.
IMX252 / IMX265 Optical dimension ------------------------------------------------------------------------------------------32
9.1.3.
CRA characteristics of recommended lens -----------------------------------------------------------------------------------33
FD white spots ----------------------------------------------------------------------------------------------------------------------------35
Rev. 2.0
2
IMX250 / IMX252 / IMX264 / IMX265 Support Package
11.
FAQ -----------------------------------------------------------------------------------------------------------------------------------------37
11.1.
In case the image cannot be displayed with the finished sensor board ---------------------------------------------------37
11.2.
In case there is noise observed in the output image---------------------------------------------------------------------------37
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Revision History ------------------------------------------------------------------------------------------------------------------------------------38
Rev. 2.0
3
IMX250 / IMX252 / IMX264 / IMX265 Support Package
3. Guideline for designing the printed circuit board
In this section we explain the design guideline of the printed circuit board layout and mount.
3.1.
Application circuit.
3.1.1.
Power supply pins
(1). Please design the suitable filter in power supply line to reduce influence of a power supply noise and to
prevent an unnecessary radiation. Especially, the parts to analog power supply pin need to choose the one
that is small direct current resistance because that pin is sensitive to the voltage change. The voltage change
becomes the factor of horizontal line noise.
(2). We suggest that the use of reasonable noise filters on the power-line for suppressing the radiation noise from
the lines.
(3). B5, F11, H5, K12, L5, B9.Pin (Analog 3.3V) is sensitive signals for noise. So these pins and other power
supply should not have the common impedance.
c.
(4). Please mount peripheral parts (capacitor) near the element as much as possible.
In
(5). Please make patterns of Power supply (3.3V, 1.8V, 1.2V) as wide as possible.
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(6). Please put capacitors at each power pin. And avoid putting a capacitor of total capacity value at multiple pins
in order to reduce parts.
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As short as possible
As short as possible
VDDHOFG(3.3V)
B5
VDDHPX
A9
VSSHPX
0.1uF
VDDHOFG
F8
F11
VDDHPX
C4
VSSHPX
H5
0.1uF
C5
VDDHTRX
D8
VDDHAN(3.3V)
VDDHCM
VDDHAN
B9
C3
VSSHCM
VSSHAN
C9
C15
VDDHCM
VSSHAN
D10
C14
VSSHCM
VSSHAN
E10
0.1uF
0.1uF
10uF
4.7uF
VDDHRST(3.3V)
0.1uF
VSSHPX
VSSHPX
E5
VSSHPX
VSSHPX
VSSHPX
VDDHCM
VSSHCM
H13
VSSHCM
J4
VSSHCM
J13
VSSHCM
K4
VSSHCM
G5
VDDHCP
D7
VSSHCP
G4
VDDHTRG
VSSHCP
B12
VDDHTM
C12
VSSHTM
10uF
H4
VSSHPX
K13
VSSHPX
L4
VSSHPX
B4
1.0uF
VDDHCP(3.3V)
0.1uF
VSSHPX
VSSHPX
VDDSUB
F6
1.0uF
E11
VDDSUB(3.3V)
0.1uF
VSSHPX
E8
J12
D14
VDDHTRG(3.3V)
0.1uF
E7
VSSHCM
0.1uF
0.1uF
E4
VDDHCM
10uF
VSSHPX
D11
J5
D3
0.1uF
F7
VDDHPX
VDDHPX
E9
C2
0.1uF
VDDHTRX(3.3V)
VSSHPX
L5
E6
As short as possible
VDDHPX
VDDHRST
K12
0.1uF
0.1uF
As short as possible
22uF
F5
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0.1uF
VDDHCM(3.3V)
10uF
S
0.1uF
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22uF
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VDDHPX1(3.3V)
22uF
The inserted components are preferred to have small
DC resistance. Because analog power lines is sensitive
to the voltage change. If it is possible, should not put
the parts. However, for noise removal, please consider
placing it near the filter circuit of power source.
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The inserted components are preferred to have small
DC resistance. Because analog power lines is sensitive
to the voltage change. If it is possible, should not put
the parts. However, for noise removal, please consider
placing it near the filter circuit of power source.
VDDHTM(3.3V)
VDDHSEL(3.3V)
F9
4.7uF
VDDHSEL
0.1uF
1.0uF
0.1uF
As short as possible
Reference design for analog power supply pins.
Rev. 2.0
4
IMX250 / IMX252 / IMX264 / IMX265 Support Package
As short as possible
Ferrite beads or Filter circuit
As short as possible
As short as possible
VDDMIF(1.8V)
VDDLSC(1.2V)
4.7uF
4.7uF
N8
VDDMIF
N5
VSSMIF
N9
VDDMIF
N6
VSSMIF
VDDLCN(1.2V)
10uF
F16
VDDLSC
VDDLCN
H16
F15
VSSLSC
VSSLCN
H15
G1
VDDLSC
VDDLCN
J1
G2
VSSLSC
VSSLCN
J2
M1
VDDLSC
VDDLCN
K16
M2
VSSLSC
VSSLCN
K15
M9
VDDLSC
M6
VSSLSC
M16
VDDLSC
M8
VSSLSC
M15
VSSLSC
U8
VSSLSC
0.1uF
0.1uF
0.1uF
0.1uF
N7
VSSMIF
N10
VSSMIF
N11
VSSMIF
N12
VSSMIF
P8
VSSMIF
P9
VSSMIF
R8
VSSMIF
R9
VSSMIF
0.1uF
0.1uF
4.7uF
0.1uF
4.7uF
0.1uF
4.7uF
0.1uF
VDDLCB(1.2V)
VDDLCB
D2
VDDMIO(1.8V)
1uF
0.1uF
0.1uF
VDDLCB
D15
0.1uF
PVLM(1.2V)
VDDLCB
H12
0.1uF
M7
F10
0.1uF
4.7uF
PVLM
0.1uF
VDDLCB
K5
VDDLPA(1.2V)
VDDLPA
M10
VSSLPA
M11
0.1uF
4.7uF
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0.1uF
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Reference design for digital power supply pins.
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1.0uF
VDDMIO
Rev. 2.0
5
IMX250 / IMX252 / IMX264 / IMX265 Support Package
(7). We recommend to implement the power supply IC as close to the sensor as possible. If cannot, use wider
power supply pattern of lower DC resistance, implement the large (10uF or more) decoupling capacitor close
to the sensor. With regard to pattern, please refer to “3.3. Notes for designing pattern of printed circuit board”.
GND
GND
Sensor
10~22μF
Analog power IC
for sensor
1μF or
4.7μF
Power supply board
0.1μF
Wireing length 10cm (If it is possible)
Bypass capacitor : 10 -22 uF (If necessary)
It is preferable to put capacitor separately in each power pin
If you bring power line together, please bring it together near the IC,
and make pattern wide to reduce common impedance
As short as possible
GND
In
c.
Please keep the route of the return current by making GND path fat as well as
power supply line.
The pattern between power IC and image
sensor should be close as much as possible
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Other Pins
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VCP1, VCP2, VBGR pin is sensitive to noise. Please place the capacitors near the pins. As for the capacity of a
capacitor, it is desirable to insert the value according to the example of an application circuit.
As short as possible
Te
As short as possible
S
C7
VCP2
VCP1
D6
4.7uF
4.7uF
4.7uF
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4.7uF
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3.1.2.
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Layout of power supply IC and decoupling capacitors of large capacity
B8
VRLOFG
B7
VRLTRX
VRLTRG
C6
VRLWSS
A7
A8
VRLSEL
VRLRST
C11
C10
VBGR
VRLGND
C8
0.22uF
As short as possible
Reference design for other pins.
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
3.2.
(Reference) Component
The following describes the components used reference information. When in actual use, please contact the
manufacture for each component.
Power supply IC
Please select the power supply IC of better PSRR characteristics. Fluctuation of the power supply voltage will cause
the horizontal line noise. In that case, we recommend that you use a series regulator.
Please note that when using switching power regulator of the following points.
(1). When using switching power regulator, magnetic field inducted by inductor might cause the noise
of the image.
(2). Encapsulated (shield) type inductor is recommended.
In
c.
(3). Mounting direction of the inductor also affects (increase or decrease) the noise level.
Good
Wire-wound drum type
(non-encapsulated)
Wire-wound drum type
(encapsulated)
Good
Lamination layer type
(similar to encapsulated)
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Bad
Encapsulated/non-encapsulated type inductor
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3.2.1.
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
Decoupling capacitors
Please use non-polar capacitors. It is possible to operate the sensor by using typical ceramic capacitors.
(1). All the power supply voltage are smaller than 3.3 V so you can use any 1608M size capacitors of any
characteristics in the graph. When you use 1005M size capacitors, you should select
characteristics-B device. Characteristics-F device should not be chosen.
(2). Decoupling capacitors for each pin are sensitive to image quality. Please implement sufficient
capacity of the decoupling capacitors according to the power supply condition. If you use capacity
that is small one and large one, please put the small one near the sensor. Please refer to Application
circuit for details.
(3). The capacity of the laminated layer ceramic capacitors will decrease in regard to the impressed DC
bias voltage by piezo-electric effect. It will be more obvious when using smaller size and larger
capacity, please check the specification sheet of each devices. (Graph below shows the
characteristics.)
Capacitance: 0.1μF
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110%
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100%
90%
1005_X5R_16V
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80%
1005_B_16V
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70%
60%
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0603_X5R_6.3V
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50%
40%
0603_B_6.3V
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30%
1005_X5R_25V
1005_F_16V
20%
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Capacitor Charge [%]
0%
1
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0
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10%
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3.2.2.
2
3
4
5
6
7
8
9
10
DC Bias Voltage [V]
DC bias vs. capacity
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
3.3.
Notes for designing patterns of printed circuit board.
3.3.1.
Power supply pins
(1). The peripheral devices (capacitors) of the sensor should be mounted as close to the power supply
pins as possible. Longer wire length might cause the degradation of the image quality.
(2). Surface power/ground plane and inner layer power/ground plane should be connected with enough
number of the vias ( Vertical Interconnect Access ) . Please make each pattern the same electric
potential.
Stacked ceramic capacitor
Staked ceramic capacitor
Please connect ground plane and
internal layer by a lot of via.
(Please make each pattern the same
electric potential.)
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Sensor
PWB
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PWB
PAD pattern
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PAD pattern
Please connect ground plane and
internal layer by a lot of via.
(Please make each pattern the same
electric potential.)
As close as possible.
Sensor
Mount the capacitors as close
to the pin as possible with using
“pad on hole” technology.
Mount the sensor and
capacitors on the same side
of print circuit board surface.
Sensor and capacitors are
mounted on the different sides of
print circuit board surface.
Example of capacitor mounting
Rev. 2.0
9
IMX250 / IMX252 / IMX264 / IMX265 Support Package
(3). The noise on the B5 / F11 / H5 / K12 / L5.pin (VDDHPX), and B9.pin (VDDHAN) degrades the image quality. So
VDDHPX and VDDHAN should not have the common impedance. Following drawing is the example of the
layout of the power supply patterns.
Analog Power Supply (3.3 V)
Analog GND
Interface Power Supply (1.8 V)
Interface GND
Digital Power Supply (1.2 V)
Digital GND
Clock
Data output
In
GND
A1
Out
U1
Other VDDH pin
Signal I/O
VDDHPX
(B5, H5, L5.pin)
Via to Analog Power plane
Other VDDH pin
Top View
Analog Power plane
VDDHPX (F11, K12)
VDDHAN (B9.pin)
A16
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Other VDDH pin
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An example of B5 / F11 / H5 / K12 / L5, and B9.pin wiring patterns. (With 3-terminal regulator)
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(4). Loop of the ground pattern might propagate the noise to the other patterns (ex. Power supply
pattern) so the ground pattern recommends Land pattern. Its recommended to use the common
single GND plane for Analog GND and Digital GND.
A1
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U1
Analog Power Supply (3.3 V)
Analog GND
Interface Power Supply (1.8 V)
Interface GND
Digital Power Supply (1.2 V)
Digital GND
Clock
Data output
Signal I/O
Via to GND plane
Top View
Don’t make the ground loop.
It’s recommended to use the common single GND plane for
Analog GND and Digital GND.
GND plane
U16
A16
GND pattern
Rev. 2.0
10
IMX250 / IMX252 / IMX264 / IMX265 Support Package
Other notes
Digital signal pattern on the other layer should not be in parallel with the power supply patterns, terminals of VCP1,
VCP2, VRLSEL, VRLTRX, VRLOFG, VRLTRG, VRLGND, VRLRST, VBGR and these lines.
U1
A1
Analog Power Supply (3.3 V)
Analog GND
Interface Power Supply (1.8 V)
Interface GND
Digital Power Supply (1.2 V)
Digital GND
Clock
Data output
Signal I/O
Good
c.
Top View
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Bad
A16
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U16
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Signal Wire Routing
Rev. 2.0
11
IMX250 / IMX252 / IMX264 / IMX265 Support Package
Wiring patterns for image output signals ( Low-voltage LVDS serial output )
(1). When choosing low-voltage LVDS output mode, signal wires ( DLOPxy and DLOMxy, DLCKPy and
DLCKMy ) must be paired.
(2). Meander pattern should make pattern as close to the output pins ( near the sensor ) as possible.
U1
Meander pattern
>90°
Terminal
resistance
：100Ω
To Receiver
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Delay tune routing
Top View
ch
U16
S
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Example of wiring patterns for LVDS serial output signal
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(3). We recommend delay tune wiring for image signals, especially delay of each differential pair signal
and Data and its Strobe signal should be controlled by using meander wiring. Turning point angle of
the wire should be greater or equal to 90 degree. ( obtuse angle )
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3.3.2.
(4). Decoupling capacitors for power supply for image signal output ( VDDM ) should be mounted close
to the power supply pins of the package of the sensor with using small size ( 1005M or 0603M )
laminated layer ceramic capacitor.
<For your reference>
Validity of the image signal can be checked by “eye pattern” of the signals. With the adequate loading and delay
tuned condition, you can see clear “eye pattern” with sufficient margin of the threshold and the noise level for the
receiver.
This is an example of eye pattern.
Typical
Amplitude
Eye Pattern
1 bit
Eye pattern of the image signal
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
4. 4-wire Serial Communication Port
This section describes the operation of 4-wire serial interface.
Overview
Characteristics of 4-wire serial interface.
(1). 3-wire serial interface consists of serial data input ( SDI ), serial clock ( SCK ), and chip enable
( XCE ). SDO is the data output port for read out the value in the registers.
(2). Data transfer is done in unit of 8bit ( 1byte ). In case of continuous communication, no limitation for
the numbers of byte for the communications. ( However, limited by communication period. )
(3). LSB first protocol.
Ex.) When sending 8’h28 LSB first transfer is 0001 0100.
Serial data input
SDO
Serial data output
Maximum frequency is 13.5 MHz
Change the value at falling edge of SCK,
latch the value by rising edge
Output the value synchronous to the falling
edge of SCK
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SDI
Communication is active for XCE is low.
c.
SCK
description
Initialize the register value.
In
XCE
function
Initialize the system
Enable the
communication
Serial clock for
communication
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Terminal name
XCLR
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CMOS Sensor
XCLR when low, all the registor values are initialized.
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[K3.pin] XCLR
Input
[L2.pin] XCE
Input
[L3.pin] SCK
Input
O
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XCE While XCE is low, communication is activated. After XCE is low, 1st byte is the ChipID[7:0], 2nd byte
Is the address[7:0] of the register, and followings are the data from/to registers.
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4.1.
SCK Write/Read operation is synchronized to SCK
SDI input the ChipID, address, and the register value
[M3.pin] SDI
Input
SDO output the register value when ChipID is declared 82h to 92h.
[L1.pin] SDO
Output
4-wire Communication Function
Rev. 2.0
13
IMX250 / IMX252 / IMX264 / IMX265 Support Package
Register write/read operation
Both of register write and read operation, ChipID, address and register value are declared to SDI. When ChipID is
02h to 12h, value is written to the register designated by the address. When ChipID is 82h to 92h, the value is read
out from the register designated by the address. Write and read operation can be done continuously while XCE is
low.
XCE
SCK
SDI
Chip.ID
02h to 12h
Address
xxh
DATA
xxh
SDO
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Write Operation
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DATA
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When write operation, the order of the commands to SDI is as follows. 1st byte: ChipID is selected among from 02h
to 12h, 2nd byte: address to write, 3rd byte and after: register value. SDO output the current value ( Before write ) of
the register designated by the address.
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XCE
SDI
SDO
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SCK
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4.2.
Chip.ID
82h to 92h
Address
xxh
DATA
xxh
DATA
xxh
Read Operation
When read operation, the order of the commands to SDI is as follow. 1st byte: ChipID is selected among from 82h to
92h, 2nd byte: address to read, 3rd byte and after : invalid data SDO output the value of the register designated by
the address.
Rev. 2.0
14
IMX250 / IMX252 / IMX264 / IMX265 Support Package
The example of communication timing to writing to continuous address as shown table 1 is shown below.
Table1. The example of writing registers
XCE
bit
Default
value
20h
[7:0]
00h
00h
E8h
21h
[7:0]
00h
00h
10h
22h
[7:0]
00h
00h
01h
SCK
SDI
02h
20h
SDO
E8h
10h
01h
00h
00h
00h
Setting value
before
After
Address
Write operation to continuous address
es
In
c.
Write E8h to address 20h first. And with keeping XCE low, by writing 10h, 01h in succession, these values are set to
consecutive addresses (21h and 22h). The example of reading communication timing to writing to continuous
address as shown table 1 as shown table 2 is shown below.
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Table2. The example of reading registers
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XCE
82h
20h
00h
00h
00h
bit
Default
value
20h
[7:0]
00h
E8h
E8h
21h
[7:0]
00h
10h
10h
22h
[7:0]
00h
01h
01h
E8h
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SDO
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SDI
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SCK
Setting value
before
After
Address
10h
01h
Read operation to continuous address
In case of reading out the value from the registers, write 82h to 92h as the ChipID then designate the address to read.
After that input the dummy data to SDI. In read mode, input data are discarded and no register is updated, current
register values are output from SDO continuously.
Rev. 2.0
15
IMX250 / IMX252 / IMX264 / IMX265 Support Package
5. I2C interface communication port
2
This section describes the operation of I C interface.
5.1.
Overview
2
I C Communication mode.
Mode
Data rate
Correspondant
Standard mode
100 kbps
○
Fast mode
400 kbps
○
High speed mode
3.4 Mbps
×
Slave address
MSB
SLAMODE = 0
Slave
Address
[7:1]
10h
SLAMODE = 1
1Ah
LSB
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
1
0
0
0
0
R/W
0
0
1
1
0
1
0
R/W
In
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[7]
es
Slave address
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Characteristics of I2C communication
no
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- I2C consists of 2 wires of serial data and serial clock.
- Unit of the communication is 8 bit ( 1 byte ), bi-directional communication.
ch
And in case of continuous communication, no limitation for the numbers of byte for the communications.(However, limited by
Te
communication period. )
S
- Acknowledge bit ( ACK/NACK ) is required at the end of communication.
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- MSB first protocol
Ex.) When sending 28h MSB first : 0010 1000.
2
- I C is the bi-directional communication and the “master” side controls the communication, the “slave” side is controlled by
master.
- IC is the bi-directional communication and the “master” side controls the communication, the “slave” side is controlled by
master. The “master” always provides the for the data.
-While communication, the device transferring the data is the transmitter, and the device receiving the data is the receiver.
The “slave” provides acknowledge bit.
- The sensor will be the slave.
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
Master
Slave(CMOS Sensor)
Slave address
・Start condition
・Repeated-start condition
・Stop condition
Transmitter
Receiver
Data（SDA)
Clock(SCL)
ACK/NACK
Receiver
Transmitter
Clock(SCL)
Data（SDA)
In
c.
ACK/NACK
gi
es
Relation between the sensor and the ISP when I2C communication.
no
lo
Master execute the following communication.
- Generate slave address ( declare the device to be slave. Sensor is the slave here. )
Te
ch
- Generate “start condition”, “repeated start condition”, and “stop condition”.
While communication, the device transforming the data is the transmitter, and the device receiving the data is the receiver.
S
Master can work as both transmitter and receiver, slave also work as both. Transmitter generates the data ( SDA ) and the
acknowledge bit.
FR
AM
O
clock ( SCL ), receiver generates the acknowledge Bit ( ACK/NACK ) and master always generates the clock ( SCL ) for
Reference design for I2C serial communication is shown below. Please connect XCE and OVDD when I2C communication.
In addition, SCL, SDA, please pull up to 1 kΩ OVDD.
I2C communication
1.8V
10kΩ
L2
XCE
SDO
L1
SLAMODE
K1
OPEN
1.8V
1kΩ
1kΩ
10Ω
L3
SCL
M3
SDA
Reference design for I2C serial communication
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
5.2.
Overview of the communication protocol
Data is transferred by SDA port. The transition timing of the SDA follows the rule below.
- State control ( start, restart, stop of the communication ) is done while SCL is “high”.
- When data transfer, SDA toggles while SCL is “low”
5.2.1.
State control (start, restart, stop of the communication)
The conditions of start ( start condition ), restart ( repeated start condition ), and stop ( stop condition ) of the communication
is shown below. State control is done by master device.
State condition
condition
SDA toggles from High to Low while SCL is high
Repeated start condition
start condition while stop condition is of the previous data transfer is
In
c.
Start condition
es
not Declared
SDA toggles from Low to High while SCL is High.
no
Acknowledge bit
ch
5.2.2.
lo
gi
Stop condition
Te
Data transfer is done in unit of 8 bit ( 1 byte ). The acknowledge bit is generated for every 8 bit data transfer and added after
S
the last ( 8th ) bit to indicate that receiver normally received the data. When receiver wants to stop the communication by the
FR
AM
O
internal interrupt or etc. receiver generates the negative acknowledge bit ( NACK ).
- Master must send the slave address after declaration of the “Start condition” and “Repeated start condition”.
- When slave generators the negative acknowledge bit, master declares the stop condition and stops the communication
immediately.
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
5.3.
Write/read operation of the registers
Write/read operation of the registers are executed as shown below.
Master：Transmission Slave：Reception
Master：Reception Slave：Transmission
Internal processing of the sensor
Start
Condition
Sensor
is Slave device and slave address is fixed
Sensor is Slave device and slave address
value
(0010000
at SLAMODE=0)
or (0011010 at
is fixed value （0011010）
b
SLAMODE=1).
Slave Address[7:1]
Optional
Designate the address of the register Select whether designate
the register address or not designate the register address.
In case of “not designate”, data cannot be written into the
register.
Held
(Read Only)
0
ACK: acknowledge
NACK: negative acknowledge
*when sensor generates the NACK, master must stop the
communication immediately by generating “stop condition”.
c.
ACK
In
Address[15:8]
ACK
es
Designate the address of register to access.
16 bit address, send in MSB first protocol. Receiver will generate
the ACK/NACK for every 8 bit communications.
lo
gi
Address[7:0]
Write
Te
Operation
DATA[7:0]
ACK/NACK
O
S
Read
Repeated
Start
Conditon
no
ACK
FR
AM
1
ch
Register
Address
Slave Address[7:1]
1
Continuance
Write
End
Stop
Condition
When write the data to the registers of continuous
address, address will be automatically incremented
so write data can be sent right after the ACK without
designating the address.
When terminate the communication, declare “stop
condition”. When sensor(slave) generates the NACK,
master must declare “stop condition” and terminate
the communication.
ACK
DATA
Readout
End
NACK
Address increment
Continuance
ACK
Address increment
Stop
Condition
I2C Register setting flow chart
Rev. 2.0
19
IMX250 / IMX252 / IMX264 / IMX265 Support Package
6. Note for access to register
When writing the value to registers, we recommend “Read-modify-write” to avoid the trouble caused by inadequate
over write of the register. For example “VREVERSE” value is assigned to address of 0Eh [0] , “HREVERSE” value is
assigned to address of 0Eh [1]. When update HREVERSE value after writing VREVERSE, VREVERSE value in
address of 0Eh [0] should be kept. “Read-modify-write” can prevent the wrong overwrite of the value
Ex.) In case of writhing the value 1d to VREVERSE and HREVERSE
In case of “no Read-modify-write”
1) HREVERSE = 1d … set value 02h to address: 0Eh
Address: 0Eh
0
0
0
0
0
0
1
0
2) VREVERSE = 1d … set value 01h to address: 0Eh
c.
01h
0
0
0
0
0 0
VREVERSE=1d
lo
gi
HREVERSE=0d
1
es
0
In
Address: 16h
Te
ch
no
Writing the VREVERSE value 01h to address 0Eh without considering
HREVERSE bit in 0Eh [1], HREVERSE will be changed.
S
In case of “Read-modify-write”
FR
AM
Address: 0Eh
0 0 0 0 0
O
1) VREVERSE = 1d … set value 02h to address: 0Eh
0
1
0
0
1
0
2) Read register value
0
0
0
0
0
Read out the current value and store the value in the memory area of MCU
3) HREVERSE = 1d … set value 01h to address: 0Eh
01h
Address: 0Eh
0 0 0 0 0
0
1
1
Bit operation “add” with the value stored in step 2)
03h
Address: 0Eh
0 0 0 0 0
0
1
HREVERSE=1d
1
VREVERSE=1d
Write value after bit operation (No overwrite of VREVERSE value)
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
7. Pattern Generator
This chapter explains the pattern generator function.
Feature
The pattern generator provides the following patterns.
◆ Multiple Pixels Pattern
◆ Sequence Pattern 1
◆ Sequence Pattern 2
◆ Gradation Pattern
◆ Horizontal 1 Row Pattern
◆ Vertical 1 Column Pattern
◆ Horizontal 1 Row and Vertical 1 Column Pattern
◆ Stripe Pattern of the Arbitrary Value
◆ Checks Pattern of the Arbitrary Value
c.
◆ Color Bar which Changes Horizontally
O
S
Te
ch
no
lo
gi
es
In
◆ Color Bar which Changes Vertically
FR
AM
7.1.
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
Register map for pattern generator function
The Register map for Pattern Generator is shown below.
Please set via sensor standby.
Please refer to the datasheet for registers setup other than those lists.
Chip ID = 04 (Write: Chip ID = 02h, Read: Chip ID = 82h, I2C: 30**h)
Address
bit
22h
[7:0]
Register Name
Default value
after reset
By
By
register
address
01h
01h
Description
Fixed to F0h
Reflection
timing
S
Chip ID = 04 (Write: Chip ID = 04h, Read: Chip ID = 84h, I2C: 32**h)
Register Name
PGREGEN [0]
1
PGTHRU [0]
2
PGCLKEN [0]
PG operation enabled
0h : PG OFF
1h : PG ON
Back Ground Transient
0h : Invalid
PGMODE=00h / 06h;
The background is fixed to "0h".
PGMODE=04h / 05h;
The background is set to PGDATA2.
1h : Valid
Clock control for PG
0h : Clock stop
1h : Clock operation
Set to “1h” when using Pattern Generator
PG mode setting
00h: Multiple pixels Pattern
01h: Sequence Pattern 1
02h: Sequence Pattern 2
03h: Gradation Pattern
04h: Horizontal 1 Row Pattern
05h: Vertical 1 Column Pattern
06h: Horizontal 1 Row and Vertical
1 Column Pattern
07h: Stripe Pattern of the arbitrary value
08h: Checks pattern of the arbitrary value
0Ah: Color bar which changes horizontally
0Bh: Color bar which changes vertically
Others: Setting prohibited
c.
0
Description
In
bit
Default value
after reset
By
By
register
address
Reflection
timing
0
S
1
S
1
S
S
3
4
5
6
O
38h
Te
ch
no
lo
gi
es
Address
FR
AM
7.2.
PGMODE [4:0]
7
06h
00h
S
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
3Dh
3Eh
3Fh
Reflection
timing
LSB
00h
Horizontal Start Address
0 or more is valid.
PGHPOS [12:0]
0000h
S
00h
MSB
Fixed to 0
Fixed to 0
Fixed to 0
LSB
-
Vertical Start Address
0 or more is valid.
00h
000h
S
ch
no
lo
gi
PGVPOS [11:0]
es
In
c.
0
0
0
MSB
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Te
3Ch
Description
0
0
0
0
S
3Ah
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Register Name
O
39h
bit
FR
AM
Address
Default value
after reset
By
By
register
address
00h
-
PGHSTEP [7:0]
Interval of horizontal pixels
00h is prohibited
00h
00h
S
PGVSTEP [7:0]
Interval of vertical pixels
00h is prohibited
00h
00h
S
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
45h
46h
47h
Reflection
timing
PGHPNUM [7:0]
Number of horizontal pixels
00h is prohibited
01h
01h
S
PGVPNUM [7:0]
Number of vertical pixels
00h is prohibited
01h
01h
S
In
c.
LSB
Set PGDATA1
gi
es
00h
0000h
S
ch
no
lo
PGDATA1 [12:0]
Te
44h
Description
00h
MSB
Fixed to 0
Fixed to 0
Fixed to 0
LSB
0
0
0
S
41h
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Register Name
O
40h
bit
FR
AM
Address
Default value
after reset
By
By
register
address
PGDATA2 [12:0]
-
00h
Set PGDATA2
0000h
S
00h
MSB
Fixed to 0
Fixed to 0
Fixed to 0
0
0
0
-
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
55h
0Ah
0
1
0
1
0
0
0Ah
0Ah
0h
-
Reflection
timing
S
S
-
-
3Ch
03Ch
S
gi
es
BLKLEVEL [11:0]
In
Black level offset value setting
Set to “000h” when using
Pattern Generator
c.
LSB
lo
54h
Do not rewrite
MSB
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
no
4Ah
to
53h
PGHGSTEP [1:0]
ch
49h
0
1
2
3
4
5
6
7
[7:0]
to
[7:0]
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Color bar width setting
16 pixels unit
00h and 01h are prohibited
Fixed to 0
Fixed to 1
Fixed to 0
Fixed to 1
Fixed to 0
Fixed to 0
The increment of gradation pattern
00b; +1 / 01b: +2 / 10b: +4 / 11b: prohibited
COLORWIDTH [7:0]
Te
[7:0]
Description
0
0
0
0
00h
-
S
48h
Register Name
O
bit
FR
AM
Address
Default value
after reset
By
By
register
address
Rev. 2.0
25
IMX250 / IMX252 / IMX264 / IMX265 Support Package
Common setting item for the PG
The output area of the PG pattern is the effective area of each mode. ( The area shown in the blue of the following
figure is output area. ) In a pattern ( 0, 4, 5, 6 ) that specifies the location, the origin of horizontal is the next pixel of
SAV4th and the origin of vertical is the next line of frame information line. By the register PGTHRU, the background
can be selected to "Fixed 0h ( Pattern 0, 6 )" and "Setting PGADATA2 ( pattern 4, 5 )" and "Through" (imaging data).
The figure below shows the details.
SAV
Invalid line
EAV
Invalid line
Frame Information Line
( PGHPOS, PGVPOS ) = ( 0, 0 )
EAV
Valid line
es
In
c.
SAV
Valid line
gi
SAV
Invalid line
EAV
Invalid line
no
lo
Output Area of Pattern Generator
Te
ch
PG settings
O
The range of the signal output
S
The output range for each output resolution is limited with the value of the following table.
FR
AM
7.3.
Output value
Resolution
Min.
Max.
01h
FEh
10bit
001h
3FEh
12bit
001h
FFEh
8bit
* IMX264 / IMX265 support only 12bit .
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
List of Pattern
The pattern which it outputs by this function is shown below.
* IMX264 / IMX265 support only 12bit.
0. Multiple pixels Pattern
Register
PGMODE = 00h
PGDATA1
PGDATA2
PGHPOS
PGVPOS
PGHPSTEP
PGVPSTEP
PGHPNUM
PGVPNUM
Pattern
Notes
Generate multiple pixels pattern.
PGDATA1: Data pattern at the location specified
by PGVPOS and PGHPOS
The output level of the next point to the right is
PGDATA1 + PGDATA2. Since (every each
vertical line)
The output level is increasing at PGDATA1 +
PGDATA2 × n (n=2, 3, 4…).
It clips with the MAX value and returns to the
startup level.
In
c.
PGVPOS: Specify the vertical start address
PGHPOS: Specify the horizontal start address
PGHPSTEP: Interval of horizontal pixels
( 0h is prohibited )
PGVPSTEP: Interval of vertical pixels
( 0h is prohibited )
PGHPNUM: Number of horizontal pixels
( 0h is prohibited )
PGVPNUM: Number of vertical pixels
( 0h is prohibited )
es
gi
lo
no
ch
Te
1. Sequence Pattern 1
Register
PGMODE = 01h
Notes
Outputs the sequential pattern of 1 pixel width
O
S
Pattern
12bit: FFEh/555h/AAAh/001h
10bit: 3FEh/155h/2AAh/001h
8bit: FEh/55h/AAh/01h
FR
AM
7.4.
2. Sequence Pattern 2
Register
PGMODE = 02h
Pattern
Notes
Outputs the following sequential pattern
12bit:
FFEh/FFEh/FC0h/FC0h/C3Ch /C3Ch/
333h/333h/AAAh/AAAh/001h/FFEh
10bit:
3FEh/3FEh/3F0h/3F0h/30Fh/30Fh/
0CCh/0CCh/2AAh/2AAh/001h/3Feh
8bit:
FEh/FEh/FCh/FCh/C3h/C3h/
33h/33h/AAh/AAh/01h/FEh
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
3. Gradation Pattern
Register
PGMODE = 03h
PGHGSTEP
Pattern
Notes
Outputs the following gradation pattern
Minimun* to Maximun
It reaches the max and increases from 000h*
again.
* : Output value is set to 001 h.
PGHGSTEP : increment
00b; +1 / 01b: +2 / 10b: +4 / 11b: prohibited
4. Horizontal 1 Row Pattern
Register
PGMODE = 04h
PGDATA1
PGVPOS
Pattern
Notes
Outputs 1 row pattern with 1 pixel width at
registered address.
( Valid in the effective pixel region )
5. Vertical 1 Column Pattern
Register
PGMODE = 05h
PGDATA1
PGHPOS
lo
gi
es
In
c.
PGDATA1: Specify the output value
PGVPOS: Specify the vertical address
Te
ch
no
Pattern
Notes
Outputs 1 column pattern with 1 pixel width at
registered address.
( Valid in the effective pixel region )
FR
AM
O
S
PGDATA1: Specify the output value
PGHPOS: Specify the horizontal address
6. Horizontal 1 Row and Vertical 1 Column Pattern
Register
Pattern
PGMODE = 06h
PGDATA1
PGDATA2
PGHPOS
PGVPOS
Notes
Outputs 1column/row pattern with 1 pixel width at
registered address.
( Valid in the effective pixel region )
PGDATA1: Specify the output value of the column.
PGDATA2: Specify the output value of the row.
PGHPOS: Specify the horizontal address
for column.
PGVPOS: Specify the vertical address for row.
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
7. Stripe Pattern of the arbitrary value
Register
PGMODE = 07h
PGDATA1
PGDATA2
Notes
Outputs the vertical stripe pattern of the arbitrary
value by 1-pixel width.
PGDATA1: Specify the output value
PGDATA2: Specify the output value
Pattern
Notes
Outputs the checkered pattern of the one pixel
spacing with the arbitrary value.
PGDATA1: Specify the output value
PGDATA2: Specify the output value
10. Color bar which changes horizontally
Register
PGMODE = 0Ah
COLORWIDTH
lo
gi
es
In
c.
8. Checks pattern of the arbitrary value
Register
PGMODE = 08h
PGDATA1
PGDATA2
Pattern
Te
ch
no
Pattern
Notes
Outputs the color bar which changes horizontally.
COLORWIDTH: Color bar width setting
* 00h and 01h are prohibited
FR
AM
O
S
COLORWIDTH ×16 pixel unit
COLORWIDTH
11. Color bar which changes vertically
Register
Pattern
PGMODE = 0Bh
COLORWIDTH
COLORWIDTH
Notes
Outputs the color bar which changes vertically.
COLORWIDTH: Color bar width setting
* 00h and 01h are prohibited
COLORWIDTH ×16 pixel unit
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
8. How to get sensor information
Following sensors can be confirmed the sensor information of Type name and monochrome (LL) / color (LQ) by
reading the values of the register as shown below.
8.1.
Register map for sensor information
The Register map for sensor information is shown below.
Please refer to the datasheet for registers setup other than those lists.
Chip ID = 03 (Write: Chip ID = 03h, Read: Chip ID = 83h, I2C: 31**h)
Address
bit
Register Name
Description
6
7
[6:0]
7
49h
Type name Information
Monochrome / Color Information
Type name
011111010
IMX250
011111100
IMX252
100001000
IMX264
100001001
IMX265
Te
ch
no
lo
gi
Data
es
In
8.2. The description of reading data
8.2.1. Type name Information
0
1
Monochrome / Color
O
Data
S
Monochrome / Color Information
Color (LQ)
FR
AM
8.2.2.
Read only
c.
48h
Reflection timing
Monochrome (LL)
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
9. Lens design guideline
This section describes the information to select the lens.
IMX250 / IMX264 Optical dimension
◆ Image size
Diagonal 11.1 mm (type 2/3)
◆ Number of recommended recording pixels
All pixel scan
: 2448 (H) × 2048 (V)
1080p-Full HD
: 1920 (H) × 1080 (V)
approx. 5.01 M pixels
approx. 2.07 M pixels
◆ Unit cell size
3.45 µm (H) × 3.45 µm (V)
In
c.
◆ Recommended lens F number
2.8 and larger ( close side )
gi
es
◆ Recommended Exit Pupil Distance
- 100mm to -∞ (for B/W)
ch
no
lo
Image formation on IMX250 / IMX264 with the lens for type 1/1(16 mm) and 2/3 (11 mm) is shown below. Note to be
caused the mechanical vignetting in using type 2/3 at the corner, a little.
16 mm
16 mm
11 mm
S
Te
11 mm
O
9.1.1.
Optical system
FR
AM
9.1.
7.093 mm
3.781 mm
11.07 mm
7.67 mm
6.679 mm
8.501 mm
All-pixel
1080p-Full HD
Relation between Image Circle and the Pixel Area
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
IMX252 / IMX265 Optical dimension
◆ Image size
Diagonal 8.9 mm (type 1/1.8)
◆ Number of recommended recording pixels
All pixel scan
: 2048 (H) × 1536 (V)
1080p-Full HD
: 1920 (H) × 1080 (V)
approx. 3.15 M pixels
approx. 2.07 M pixels
◆ Unit cell size
3.45 µm (H) × 3.45 µm (V)
◆ Recommended lens F number
2.8 and larger ( close side )
◆ Recommended Exit Pupil Distance
- 100mm to -∞ (for B/W)
11 mm
es
11 mm
In
c.
Image formation on IMX252 / IMX265 with the lens for type 2/3(11 mm) and 1/2 (8 mm) is shown below. Note to be
caused the mechanical vignetting in using type 1/2 at the corner, a little.
8 mm
no
lo
gi
8 mm
8.89 mm
3.781 mm
7.67 mm
6.679 mm
O
S
Te
7.121 mm
ch
5.327 mm
FR
AM
9.1.2.
All-pixel
1080p-Full HD
Relation between Image Circle and the Pixel Area
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
9.1.3.
CRA characteristics of recommended lens
The recommended CRA characteristics is 0.0 degrees all over the image height (0 – 100 %), because the target
E.P.D. is infinite.
*We assume that the worst case of E.P.D. is -100mm. The CRA characteristics of -100mm E.P.D. is described below.
The real CRA should be smaller than the table below.
CRA characteristics of IMX250 / IMX264
3.00
2.00
1.50
1.00
0.50
50
60
70
80
90
100
es
40
gi
Image height [%]
ch
no
lo
100%
0%
2056pixels
30
Te
20
S
10
CRA
(deg)
0.00
0.16
0.32
0.48
0.63
0.79
0.95
1.11
1.27
1.43
1.59
1.74
1.90
2.06
2.22
2.38
2.54
2.69
2.85
3.01
3.17
O
0
In
0.00
Image height
(mm)
0.00
0.28
0.55
0.83
1.11
1.38
1.66
1.94
2.21
2.49
2.77
3.04
3.32
3.60
3.87
4.15
4.43
4.70
4.98
5.26
5.54
Optical center
FR
AM
CRA [deg]
2.50
(%)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
c.
3.50
2464 pixels
Rev. 2.0
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
CRA characteristics of IMX252 / IMX265
3.00
2.50
1.50
1.00
0.50
0.00
0
10
20
30
40
50
60
70
80
90
100
Image height [%]
CRA
(deg)
0.00
0.13
0.25
0.38
0.51
0.64
0.76
0.89
1.02
1.15
1.27
1.40
1.53
1.65
1.78
1.91
2.04
2.16
2.29
2.42
2.55
no
lo
gi
1544pixels
0%
es
In
c.
100%
Image height
(mm)
0.00
0.22
0.44
0.67
0.89
1.11
1.33
1.56
1.78
2.00
2.22
2.44
2.67
2.89
3.11
3.33
3.56
3.78
4.00
4.22
4.45
S
O
2064 pixels
Te
ch
Optical center
FR
AM
CRA [deg]
2.00
(%)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
CRA characteristics
CRA ( Chief Ray Angle ) indicates the optimum angle of the chief ray for the image height, independent from the
aperture size of the lens. This sensor assumes the recommended EPD ( Recommended exit pupil distance ) is
farther than -100mm and the angle of chief ray is theoretically directional light ( perpendicular for the imaging plane ).
CRA characteristics table shown above is calculated with assuming short exit pupil distance case, precisely -100mm.
CRA
EPD
Image height
Sensor
CRA characteristics
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
10. FD white spots
This sensor takes the common floating diffusion transistor (FD) architecture to widen the aperture ratio of the pixel.
When FD has the leak current or other defect, white spot consist of 2 pixels (vertical 2 pixels) will appear.
Gb
TRG1
R
or
Output
TRG0
B
FD
Gr
In
Overview of FD white spot
c.
FD White spot
Single-pixel white spot
O
S
Te
ch
Level(mV)
no
lo
gi
es
The signal level of single-pixel white spots (due to the defect of single pixel) increases according to the accumulation
time. On the other hand, FD white spot is constant to the accumulation time. There exist the dependency to the
temperature, but characteristics are various according to the cause of the spots.
FR
AM
FD white spot
1/120
[sec]
1/60
[sec]
1/30
[sec]
Feature of FD white spot
(Both single-pixel white spots and FD white spots are same level at 60 frame/s)
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
FD white spot is different from single white pixel, cluster spots, then usual dynamic compensation might not be able
to conceal it. Static compensation will be necessary. Please consider to use the static compensation of the ISP.
Image data
ISP
(static compensation circuit)
Sensor output
with FD white spots
Image data
After compensation
Read out the address
information of FD white spots
from the memory
Store the address
information of FD white
spots previously
Memory
(internal / external of the ISP)
FR
AM
O
S
Te
ch
no
lo
gi
es
In
c.
Address information of FD
white spots of the sensor
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
11. FAQ
11.1. In case the image cannot be displayed with the finished sensor board
Description
Remark
Please confirm that
the power supply
design is according to
the specification
- Please confirm that the applied power supply voltage level is within
the recommended range (Analog Power 3.3 ±0.15V Interface Power:
1.8 ±0.1V , Digital power: 1.2 ±0.1V.)
- Please confirm that the power supply capacity is enough for the total
current consumption requirement of the board including the sensor
- Please confirm that the direction of the sensor (the foot print of the
board and the chip) is correct
Refer to the DC
characteristics section
of the specification
Please confirm that
the register
communication is
done correctly
- Please confirm that the sensor has come out of the standby mode.
Read register of address 00h and confirm that 00h has been written in
the register. (See the specification or the register communication
description of this document for the register read sequence )
- Please double check the communication protocol if the register
cannot be written correctly.
- In case of 4-wire serial communication, the LSB first protocol should
be followed for both register read and write.
- In case of 4-wire serial communication, it is necessary to assign the
ChipID and Address again after the XCE has been set high.
- Please reset the sensor through the XCLR pin right after power-on
- After power-on and exit of the standby mode, the default setting is
16ch output in All-pixel 12bit mode. Please make the register settings
according to the desired operation mode.
Refer to
P.13 of this document
no
lo
gi
es
In
c.
Check Item
Te
ch
11.2. In case there is noise observed in the output image
Noise Condition
Check Item
Remark
- Please confirm that the decoupling capacitor of the power supply has
sufficient capacitance and is put close to the sensor pin.
- Please also confirm that the decoupling capacitor of VCP1, VCP2,
VBGR pin has sufficient capacitance as well.
Refer to
P. 4 of this document
Horizontal stripes
with random timing,
not always present
- Please confirm that the register communication timing and the sensor
data output timing are not overlapped. Conduct the register
communication during the assigned period of the operation mode.
Posterization, bit loss
- Please confirm that the bit depth of the captured image data and that
of the output image data are matched
- It is possible that the data capture timing is critical. Please compare
the output waveform of the DO pin against that of the DCK pin to
confirm that there is no problem with the data capture timing.
Regarding the
communication timing,
refer to the Operation
mode section of the
specification.
Regarding the timing,
refer to the AC
characteristics section
of the specification.
FR
AM
O
S
Vertical or horizontal
stripes, always
present
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IMX250 / IMX252 / IMX264 / IMX265 Support Package
Revision History
Version
Date
Page
Rev.1.0
30-Jan-15
---
Rev.1.1
10-Feb-15
P6
Remarks
First edition
Correction :
Figure of Reference design for digital power supply pins
Add :
Section of IMX252 Optical dimension
Rev.1.2
06-Mar-15
P38
Section of IMX252 CRA characteristics
Correction :
c.
Recording pixels of All Pixel scan
Add :
In
All page
es
IMX264, IMX265
P14 to 16
Chapter of Package center, optical center, Package Outline and
lo
18-Sept-15
no
Rev.1.3
gi
Delete : The sections written on Datasheet
ch
Reflow Profile
Add :
Te
P33
Rev.1.5
25-Sept-15
FR
AM
Rev.1.4
O
S
Section of How to get sensor information
13-Nov-15
Correction :
P33 - 34
CRA characteristics
Correction :
P17
Figure of Reference design for I2C serial communication
Rev. 2.0
38
IMX250 / IMX252 / IMX264 / IMX265 Support Package
Version
Date
Page
Remarks
Correction :
P22
Chip ID = 02, Address = 22h.Setting value
Correction :
P22 - 25
Chapter of “Register map for pattern generator function”
Add :
P25, P29
Constrained condition of COLORWIDTH register
15-Apr-16
Correction :
P30
Type name Information
Correction :
P31
Correction :
In
P32
c.
Figure of 1080p Pixel Area for IMX250 / IMX264
O
S
Te
ch
no
lo
gi
es
Figure of 1080p Pixel Area for IMX252 / IMX265
FR
AM
Rev.2.0
Rev. 2.0
39