COMMUNICATION
Nonvolatile Memory
www.advelectronicmat.de
New Floating Gate Memory with Excellent Retention
Characteristics
Shuopei Wang, Congli He, Jian Tang, Xiaobo Lu, Cheng Shen, Hua Yu, Luojun Du,
Jiafang Li, Rong Yang, Dongxia Shi, and Guangyu Zhang*
voltage shift. Obviously, both the nonvolatility and program/erase voltages are
dependent on the quality and thickness of
the tunnel oxide layer. Reducing the thickness of the tunneling oxide layer has been
tried to reduce the program/erase voltage
and enhance the level of integration.[3–6]
However, as the thickness of the tunneling
oxide layer decreases, the leakage current
from the floating gate becomes larger,
resulting in storage information loss.
Conventional silicon-based flash memory
are approaching their physical limits.
Consequently, a potential solution is to
explore novel materials and new memory
structures.
Atomically thin 2D materials have
emerged during the last decade as one
of the most active research subjects due
to their unique properties. van der Waals
heterostructure prepared by stacking different 2D materials together can combine
excellent properties of each layered component and offer a
unique approach to many challenges.[7–10] For instance, mono­
layer transition metal dichalcogenides (TMDs) such as moly­
bdenum disulfide (MoS2), has been extensively studied as field
effect transistor (FET) channel material for high on/off ratio
and immunity to short channel effects.[11–17] Furthermore, the
lack of dangling bonds at the interface between the 2D materials would suppress the appearance of interface states and
charge traps which are common in silicon-based devices.[2,18,19]
Based on these 2D materials, flash memory with floating-gate
or charge-trap structures, has been reported recently.[20–26] In
such devices, one or more components are replaced by 2D
materials, while the tradeoff between operation voltage and
In current flash memory, there is an inevitable tradeoff between the operation
voltage and the retention time due to the incorporation of very thin tunneling
layer in the device structure. In this work, a new type of robust floating gate
nonvolatile memory based on 2D materials is introduced to reduce the operation voltage and promote the data retention time. By taking the advantage of
a dual-gate structure, as-fabricated devices exhibit excellent performance with
low operation voltage (as low as 5 V even the tunneling layer tBN ≥ 10 nm),
long retention time (on/off ratio with negligible degeneration over 105 s), and
ultralow off-leakage current (10−13 A, which is very attractive for ultralowpower applications). Charges trapped in the top gate originated from the
capacitive coupling between the back and top gates are found to be responsible for the nonvolatile behavior. The new charge trapping mechanism,
which is distinguished from that in the conventional single-gate memory
devices, enables charge tunneling through a thicker tunneling layer at a low
operation voltage. The achieved MoS2 nonvolatile memory with outstanding
performances has great potentials for future information storage.
Flash memory is the most widely used nonvolatile memory
device currently.[1,2] In order to comply with the rapidly
increasing demand of storage capacity and performance, new
strategies are needed. Currently, standard flash cell is basically
a floating-gate structure, which is comprised of a channel layer,
a tunnel oxide, and a data floating gate (FG) layer completely
surrounded by dielectrics, a control oxide, and a gate electrode.
Being electrically isolated, the FG acts as the storing layer in
the device. When applying a voltage on the gate electrode, electrons (holes) were allowed to tunnel from the channel layer to
the FG layer through the thin tunnel oxide, causing shifting in
the threshold voltage (Vth). The logic states are defined by the
current upon a read voltage within the window of the threshold
S. P. Wang, Dr. C. L. He, J. Tang, Dr. X. B. Lu, C. Shen, Dr. H. Yu,
Dr. L. J. Du, Prof. J. F. Li, Prof. R. Yang, Prof. D. X. Shi, Prof. G. Y. Zhang
Beijing National Laboratory for Condensed Matter Physics
and Institute of Physics
Chinese Academy of Sciences
Beijing 100190, China
E-mail: gyzhang@iphy.ac.cn
S. P. Wang, J. Tang, Dr. X. B. Lu, C. Shen, Dr. H. Yu,
Dr. L. J. Du, Prof. R. Yang, Prof. D. X. Shi, Prof. G. Y. Zhang
School of Physical Science
University of Chinese Academy of Sciences
Beijing 100190, China
DOI: 10.1002/aelm.201800726
Adv. Electron. Mater. 2019, 1800726
S. P. Wang, Prof. R. Yang, Prof. G. Y. Zhang
Songshan-Lake Materials Laboratory
Dongguan 523808, Guangdong Province, China
Dr. C. L. He
Institute of Advanced Materials
Beijing Normal University
Beijing 100875, China
Prof. R. Yang, Prof. D. X. Shi, Prof. G. Y. Zhang
Beijing Key Laboratory for Nanomaterials and Nanodevices
Beijing 100190, China
Prof. G. Y. Zhang
Collaborative Innovation Center of Quantum Matter
Beijing 100190, China
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Figure 1. Structure of the memory device. a) Schematic structure of the memory device. b) Optical microscopy image of an individual memory device.
The dash lines outline the MoS2 flake. c) Raman and PL spectra for encapsulated MoS2 (h-BN/MoS2/h-BN) (red line) at 2.33 eV excitation. d) AFM
image of MoS2 transferred on h-BN. A height profile was extracted.
retention time seems still to be inevitable, due to sharing the
same structure with conventional silicon-based device.
To reduce the operation voltage and promote the data retention time of a floating gate memory device, we here propose
a new type of robust nonvolatile memory devices with a dualgate structure based on a heterostructure of MoS2 and hexagonal boron nitride (h-BN). The stacking order of floating gate
is different from conventional floating-gate memory. Instead of
at the same side of the channel layer, the control gate and the
floating gate with an extra pad in our device are designed at
the both sides of the channel layer, between which the capacitive coupling will play a significant role for the nonvolatile
memory behavior (seen in Figure S1, Supporting Information).
The charge trapping mechanism in this new type of memory
devices is distinguished from the traditional flash memory
device, enabling charge tunneling through a thicker tunneling
layer, i.e., h-BN layer, at low operation voltages. For a tunneling
layer thickness tBN ≥ 10 nm, devices show operation voltage less
than 5 V, while having excellent retention characteristics (negligible degeneration over 105 s). The new type of memory devices
also shows an excellent memory performance with endurance
up to 105 cycles, suggesting a great stability and reliability. The
charge trapped in the top gate originated from the capacitive
coupling between the back and top gates through the large extra
bonding pad was found to be responsible for the nonvolatile
behavior. The achieved MoS2 nonvolatile memory with excellent performances has great potential for information storage.
Figure 1a illustrates the structure of the dual-gate memory
device. The device was fabricated on a Si wafer covered with
300 nm thick SiO2 layer. The monolayer MoS2 channel was first
encapsulated with h-BN layer by using dry transfer technique
Adv. Electron. Mater. 2019, 1800726
(Figure S2, Supporting Information).[27] The Ti/Au was then
deposited to serve as top gate and contact. Figure 1b displays
an optical microscopy (OM) image of a typical memory device.
Figure 1c shows the photoluminescence (PL) spectra of the
encapsulated MoS2, exhibiting a single exciton peak at 1.86 eV
that originated from the direct interband recombination of
the photogenerated excitons.[28,29] The Raman spectrum of the
heterostructure, shown in the inset of Figure 1c, shows two
characteristic peaks of MoS2 at 385.4 and 405.9 cm−1, which
are attributed to the in-plane vibration of Mo and S atoms
(mode), and the out-of-plane vibration of S atoms (mode),
respectively.[30,31] The difference in frequencies between the
two peaks, i.e., 20.5 cm−1, is indicative of a monolayer MoS2
flake.[32] The atomic force microscopy (AFM) image of MoS2/hBN heterostructure is displayed in Figure 1d, showing a clean
interface. The thickness of the MoS2 flake was measured to be
0.7 nm, corresponding to monolayer MoS2,[33] consisting with
the Raman and PL results.
Figure 2a shows the I–V curves of a typical device under
the different back gate voltages Vbg. The source–drain current
(Id) varies linearly with the source–drain voltage (Vd), indicating good ohmic contacts. To verify the data storage capability of the memory device, the transfer characteristic was further investigated, as shown in Figure 2b. Vbg was swept from
+5 to −5 V (red curve) and back to +5 V (cyan curve) with fixed
Vd = 100 mV, while the top gate electrode was disconnected
(floated). A noticeable hysteresis can be observed for two different sweep directions of Vbg, which is crucial for a memory.
The large hysteresis is characterized by a maximum voltage
shift ∆V of ≈3.3 V. It should be mentioned that the floated top
gate plays an important role for the hysteresis. When sweeping
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Figure 2. Electrical characteristics of a memory device. a) Output characteristics curve of the memory device at different Vbg. b) Transfer characteristic
with Vbg sweeping from −5 to +5 V and reverse, at a fixed Vd = 100 mV. c) Transfer characteristic under different Vbg sweeping from ± 10 to ± 60 V, at
a fixed Vd = 100 mV. d) Memory window extracted from (c). The top gate size is 100 µm × 100 µm.
the back gate with top gate grounded, the curve shows negligible hysteresis (Figure S3b, Supporting Information). The state
of the device will also change when the top gate is grounded
after programming process (Figure S4, Supporting Information). Besides, devices without top gates also show negligible
hysteresis (Figure S5, Supporting Information). Thus, we infer
that the charge trapped in the top gate should be responsible
for the hysteresis behavior.
The hysteresis window of such devices can be modulated by
gradually changing the maximum of back gate voltage (Vbg max).
As shown in Figure 2c, the hysteresis window can be enlarged
when Vbg max becomes larger. The shift of the voltage toward
negative and positive direction corresponds to the hole and
the electron trapping, respectively. The larger shift of the
voltage toward positive direction indicates that electrons are the
majority carriers for charging and discharging in the floating
gate. This behavior can be attributed to different tunnel barrier
heights for electrons and holes.[23,34] Memory window, described
by the maximum voltage shift ∆V during the log dual sweep of
Vbg, was extracted and displayed in Figure 2d. It can be seen
that ∆V shows a linear relationship with Vbg max. The ratio of
the memory window and the sweeping range can reach more
than 60%. Note that ∆V = 60 V under Vbg max = 60 V, which is
very large compared to previous memory device.[20–23,25]
The dynamic behavior of these devices was also investigated to verify their high performances. Switching between
different resistance states is achieved by applying voltage
pulses to the back gate, while the source was grounded and the
drain was biased at 100 mV. Figure 3a shows the result from
Adv. Electron. Mater. 2019, 1800726
a typical device. The device is initially in a high current level,
corresponding to the ON state. Then a positive voltage pulse
(+5 V, 100 ms) was applied on the back gate of the device,
leading to a 140 nA current spike. When the back gate voltage
was reset to 0 V, the device was set to the OFF state, holding a
stable low current of ≈10−12 A. The device was restored to the
initial ON state (40 nA) when applying a symmetric negative
pulse (−5 V, 100 ms). The MoS2 based memory device could be
switched between ON and OFF states stably and reliably.
The reliability of the memory device is crucial for nonvolatile data storage. Both retention time and cyclic endurance were
investigated. As shown in Figure 3b, highly reliable retention
characteristics can be achieved. The device was programmed
to the ON (OFF) state through one −5 V (+5 V) voltage pulse
with pulse width of 100 ms. Data retention in each state was
acquired independently for the ON state (≈10−6 A) and OFF
state (10−14 to 10−12 A). Negligible degradation was observed
over 105 s. The dashed lines in Figure 3b indicate the extrapolated retention time beyond 10 years, which demonstrates
that the memory device has a long retention time. It is estimate that, after 10 years (108 s), the on and off currents show
no appreciable change, while maintaining an on/off ratio of
106. The endurance test was performed in sequential voltage
pulses (±5 V, 100 ms), which were applied to the back gate of
the device. As shown in Figure 3c, the memory devices remain
high on/off ratio of 106 within 105 cycles. It is important to
compare the key parameters between our device and previous
state-of-the-art MoS2 based memory devices. As shown in
Table S1 (Supporting Information), our memory device shows
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Figure 3. a) The dynamic switching behavior between ON and OFF states induced by applying alternating Vbg pulses (±5 V, 100 ms) with a time interval
of 2.3 s. b) Retention time characteristic of Id in the ON and OFF states. Each state was read at Vbg = 0 V, Vd = 100 mV after programmed (erased)
by one pulse voltage of + 5 V (−5 V) and width of 100 ms on the gate. The dashed lines indicate the extrapolated tendency. c) Endurance test of the
memory device. The applied pulse voltages (±5 V, 100 ms) are shown in the inset. The current reads at Vbg = 0 V, Vd = 100 mV.
an outstanding performance in low operation voltage, long
retention time, and good endurance characteristic. Due to the
thicker tunneling layer in our devices compared to other MoS2
based memory devices, our device shows much better reliability
and stability.
We infer that charges trapped in the top gate of our devices
originate from the capacitive coupling between the back and the
top gates. A schematic of dual-gate memory device with capacitances was shown in Figure 4a. In this device geometry, there
are three capacitances, including the top gate capacitance Ctg, the
back-gate capacitance Cbg, and the coupling capacitance between
the back and the extra pad Cbt. The capacitive coupling between
the back and the top gates through large extra pad area cannot be
negligible.[35,36] In this case, with the top-gate electrode disconnected, if the device is measured by sweeping the back gate then
the effective total back-gate capacitance is C = C bg + (C tg−1 + C bt−1 )−1
. The coupling capacitance can cause the transfer curve deviate
from the nominal nonhysteresis behavior (Figures S3 and S5,
Supporting Information). From this point of view, it can also
explain some strange behaviors of dual gate structure devices,
such as mobility overestimation, in early reports.[13,37]
To further investigate the origin of the nonvolatile effect,
we designed the dual-gate devices with different sizes of top
gates (here including the connection extra pad) and different
thicknesses of the tunneling layer. As shown in Figure S6a
(Supporting Information), we fabricated a few of dual-gate
devices made of one single MoS2 flake with the same channel
lengths but with different connection extra pad sizes of 8, 20,
Adv. Electron. Mater. 2019, 1800726
20, 2545, 10 280 µm2, respectively. Transfer characteristics of
devices with different sizes of top gates (Vbg max = 50 V) were
shown in Figure S6b (Supporting Information). Figure 4b
shows the correlation between the memory windows and the
extra pad sizes. It can be clearly seen that the memory window
increases with the extra pad sizes. Based on these results, we
infer that the hysterics behavior results from the capacitive
coupling between the back and the top gates. Figure 4c shows
the I–V curves of the memory device under different thicknesses of top dielectric h-BN layers. The relationship between
the memory window and the h-BN thickness is summarized in
Figure 4d, exhibiting a linear correlation. Being different from
the conventional floating-gate memory devices, in which the
memory’s stability depend on the charge tunneling through
thin dielectric layer, our dual-gate memory devices work at
thick h-BN layers, e.g., 45 nm, still exhibit very stable retention
and endurance behavior via charge tunneling.[21–23]
In order to further understand the charge transfer process in our devices, the electric field distribution within the
device was analyzed by finite element simulations, displayed
in Figure S7 (Supporting Information). The electric field was
more enhanced nearby the source/drain areas, which enables
charges tunneling from source (drain) to top gate. Simulation results for devices with different top gate lengths of
10, 5, and 3 µm (corresponding to different extra pad sizes),
are shown in Figure S7b (Supporting Information), electric
field between source/drain and top gate increase with the
increasing of the top gate length which enables more charges
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Figure 4. Effect of the size of top gate and the thickness of h-BN on the memory window. a) Device structure, showing the capacitances discussed in
the text. b) The relationship between ΔV and top gate size. c) Transfer characteristic of device with different top h-BN thickness (8, 18, 30, and 45 nm,
respectively). d) The relationship between ΔV and h-BN thickness, which is extracted from (b).
tunneling from source (drain) to top gate. In case of top gate
length of 10 µm, the electric field is largely enhanced. These
results suggest that the memory window increases with the
top gate size.
Figure 5a–d shows the schematics of memory operation at
states of programming, reading after programming, erasing,
and reading after erasing. For programming, when a positive
voltage was applied at the back gate, negative charges appeared
in the large top-gate bonding pad near the interface of Au/hBN originated from the capacitive coupling. Simultaneously,
due to the law of charge conservation, equal numbers positive
charges will be repelled away from this area, distributing on
Figure 5. Schematic illustration of memory operation at the states of a) programing, b) reading after programing, c) erasing, d) reading after erasing.
The dashed arrows indicate the tunneling direction of electrons and holes from the source (drain) electrodes/channel into floating gate.
Adv. Electron. Mater. 2019, 1800726
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the other side of surface of the Au top gate nonuniformly, as
shown in Figure 5a. On the other hand, most positive charges
would move to the region near the drain/source and the region
above the channel because of the shield effect of drain/source
and 2d channel, resulting in a large electrical field between
the top gate and the source (drain), as the simulation results
shown in Figure S7 (Supporting Information), which enables
electrons tunneling from the source (drain) to the top gate,
marked by the dashed arrows in Figure 5a. After removing
the Vbg, there would be some residual net charges (electrons)
trapped in the top gate, which would redistribute through the
entire top gate. Then the device was read in the OFF state,
as shown in Figure 5b. Analogously, the erasing and reading
after erasing process were illustrated in Figure 5c,d, and some
holes would be trapped in the top gate. The charge trapping
mechanism due to the capacitive coupling, distinguished from
the conventional floating-gate memory devices, enables charge
tunneling through thicker tunneling layer at low operation
voltages.
In conclusion, we fabricated robust nonvolatile memory
devices based on h-BN/MoS2/h-BN dual-gate structure with
excellent performances in terms of low operation voltages,
endurance up to 105 and long retention time over 105 s.
Furthermore, using MoS2 as the channel layer, our memory
devices exhibit ultimately low leakages and off-state current of ≈10−13 A. The capacitive coupling between the back
and the top gates was found to be responsible for the nonvolatile behavior. The charge trapping mechanism, distinguished from the conventional floating-gate memory devices,
enables charge tunneling through thicker tunneling layer at
low operation voltages. Our realization of robust nonvolatile
memory based on dual-gate structure provides an avenue
for future electronics engineering by using van der Waals
heterostructure.
Experimental Section
Heterostructure Fabrications and Characterizations: Monolayer
MoS2 flakes were mechanically exfoliated from the bulk MoS2 onto
polydimethyl siloxane (PDMS) substrates. To identify the layer
number of MoS2, optical imaging thus confirmed by AFM, Raman, and
PL was used. Heterostructure were prepared by sequent transferring
mechanically exfoliated MoS2 and h-BN flakes through a homemade transfer tool. The transferred heterostructure samples were
annealed in gas mixture of H2/Ar (10 sccm/150 sccm) for 120 min
at 300 °C to remove residuals. As-fabricated MoS2 on h-BN were
characterized by AFM (MultiMode IIId, Veeco Instruments) using
tapping mode under ambient conditions. The Raman and PL spectra
were carried out on a Horiba Jobin Yvon LabRAM HR-Evolution
Raman microscope with an excitation laser wavelength of 532 nm,
laser power of 10 mW, and laser spot size of ≈1 µm at room
temperature.
Device Fabrications and Characterizations: As transferred device
were spin coated with a polymethylmethacrylate (PMMA) photoresist
followed by electron beam lithography (EBL, Raith-eline). Then, the Ti
(2 nm)/Au (20 nm) metal electrode leads were deposited in electron
beam evaporation followed by a standard metal lift-off process. The
electronic characterizations were measured by an Agilent B1500A
parameter analyzer at room temperature.
Electrostatic Simulation: Device simulations were carried out with the
Comsol Multiphysics package.
Adv. Electron. Mater. 2019, 1800726
Supporting Information
Supporting Information is available from the Wiley Online Library or
from the author.
Acknowledgements
This work was supported by the National Science Foundation of China
(NSFC) under Grant No. 11834017, 61734001, 51572289, and 11574361,
the Strategic Priority Research Program of Chinese Academy of Sciences
(CAS) under Grant No. XDB30000000, the Key Research Program of
Frontier Sciences of the CAS under Grant No. QYZDB-SSW-SLH004, and
the National Key R&D program under Grant No. 2016YFA0300904 and
Youth Innovation Promotion Association CAS under Grant No. 2018013.
Conflict of Interest
The authors declare no conflict of interest.
Keywords
floating gate, MoS2, nonvolatile memory, van der Waals heterostructure
Received: October 16, 2018
Revised: December 10, 2018
Published online:
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