LABORATORY MANUAL
Digital Electronics and Integrated Circuits
Complied and Tested By:
Engr. Syed Sajjad Hussain Rizvi
Engr. Muhammad Khalid
Engr. Syed Safdar Hussain
STUDENT INFORMATION
Name: ____________________________________________
Registration No: ___________________________________
Semester: _________________________________________
Program: _________________________________________
Email Address: ____________________________________
INDEX
S No.
List Of Experiment
1.
To study and prepare the NOT, OR, AND gate using BJT transistor.
2.
To design transistorized NOR and NAND gate circuit using BJT.
3.
To Determine the Fan-out of digital IC.
4.
To determine I and V parameter of Digital IC.
5.
To design NOT OR and AND gate using N-Channel MOSFET
6.
To design NAND and NOR gate using N-Channel MOSFET
7.
To design and implement tri-state logic device
8.
To implement digital to analog conversion using DAC 0808.
9.
To implement analog to digital conversion using ADC 0804
10.
Introduction to Wincupl
11.
Programming Logical NOT, OR, AND, XOR, NOR, NAND, XNOR
for GAL16v8 using Wincupl
12.
Programming Logical expression on GAL16v8 using Wincupl
13.
Programming Logical expression on GAL16v8 using Wincupl
14.
Programming Binary Full Adder on GAL16v8 using Wincupl
Date
Remarks
SAFETY RULES AND OPERATING PROCEDURES
1. Note the location of the Emergency Disconnect to shut off power in an
emergency. Note the location of the nearest telephone.
2. Students are allowed in the laboratory only when the instructor is present.
3. Drinks and food are not allowed near the lab benches.
4. Report any broken equipment or defective parts to the lab instructor. Don’t open,
remove the cover, or attempt to repair any equipment.
5. When the lab exercise is over, all instruments, except computers, must be turned
off. Return components to Lab Administrator. Your lab grade will be affected if
your laboratory station is not tidy when you leave.
6. University property must not be taken from the laboratory.
7. Do not move instruments from one lab station to another lab station.
8. Do not tamper with or remove security straps, locks, or other security devices.
9. Do not disable or attempt to defeat the security camera.
ANYONE VIOLATING ANY RULES OR REGULATIONS MAY BE DENIED
ACCESS TO THESE FACILITIES.
I have read and understand these rules and procedures. I agree to abide by these rules and
procedures at all times while using these facilities. I understand that failure to follow
these rules and procedures will result in my immediate dismissal from the laboratory and
additional disciplinary action may be taken.
________________________
Student Signature
___________
Date
_______________
Lab Name
LABORATORY SAFETY INFORMATION
Introduction
The danger of injury or death from electrical shock, fire, or explosion is present while
conducting experiments in this laboratory. To work safely, it is important that you
understand the prudent practices necessary to minimize the risks and what to do if there is
an accident.
Electrical Shock
Avoid contact with conductors in energized electrical circuits. Do not touches someone
who is being shocked while still in contact with the electrical conductor or you may also
be electrocuted Instead, press the Emergency Disconnect. This shuts off all power.
Make sure your hands are dry. The resistance of dry, unbroken skin is relatively high and
thus reduces the risk of shock. Skin that is broken, wet or damp with sweat has a low
resistance.
When working with an energized circuit, work with only your right hand, keeping your
left hand away from all conductive material. This reduces the likelihood of an accident
that results in current passing through your heart.
Be cautious of rings, watches, and necklaces. Skin beneath a ring or watch is damp,
lowering the skin resistance. Shoes covering the feet are much safer than sandals.
If the victim isn't breathing, find someone responsible from Iqra University Programs. If
the victim is unconscious or needs an ambulance, contact the Program Office for help or
call 115 ( EDHI ).
Fire
Transistors and other components can become extremely hot and cause severe burns if
touched. If resistors or other components on your breadboard catch fire, turn off the
power supply and notify the lab instructor. If electronic instruments catch fire, press the
Emergency Disconnect Button. These small electrical fires extinguish quickly after the
power is shut off. Avoid using fire extinguishers on electronic instruments.
Explosion
When using electrolytic capacitors, be careful to observe proper polarity and do not
exceed the voltage rating. Electrolytic capacitors can explode and cause injury. A first aid
kit is located on the soft board near the door.
GUIDELINES FOR LABORATORY NOTEBOOK
The laboratory notebook is a record of all work pertaining to the experiment. This record
should be sufficiently complete so that you or anyone else of similar technical
background can duplicate the experiment and data by simply following your laboratory
notebook. Record everything directly into the notebook during the experiment. Do not
use scratch paper for recording data. Do not trust your memory to fill in the details at a
later time.
Organization in your notebook is important. Descriptive headings should be used to
separate and identify the various parts of the experiment. Record data in sequential order.
A neat, organized and complete record of an experiment is just as important as the
experimental work.
Object A brief but complete statement of what you intend to find out or verify in the
experiment should be at the beginning of each experiment.
Diagram: A circuit diagram is drawn and labeled so that the actual experiment circuitry
could be easily duplicated at any time in the future. Be especially careful to record all
circuit changes made during the experiment.
Equipment List: List of items which have a direct effect on the accuracy of the data. It
may be necessary later to locate specific items of equipment for rechecks if discrepancies
develop in the results.
Procedure: In general, lengthy explanations of procedures are unnecessary. A brief.
Short commentaries along side the corresponding data is being provided.
Data: Think carefully about what data is required and prepare suitable data tables.
Record instrument readings directly. Do not use calculated results in place of direct data;
however, calculated results may be recorded in the same table with the direct data. Data
tables should be clearly identified and each data column labeled and headed by the proper
units of measure.
Results: The results should be presented in a form which makes the interpretation easy.
Large amounts of numerical results are generally presented in graphical form. Tables are
generally used for small amounts of results. Theoretical and experimental results should
be on the same graph or arrange in the same table in a way for easy correlation of these
results.
Conclusion: This is your interpretation of the results of the experiment as an engineer.
Be brief and specific. Give reasons for important discrepancies.
TROUBLESHOOTING HINTS
1. Be sure that the power is turned on.
2. Be sure the ground connections are common.
3. Be sure the circuit you built is identical to that in the diagram. (Do a node by node
check.)
4. Be sure that the supply voltages are correct.
5. Be sure that the equipment is set up correctly and you are measuring the correct
parameter.
6. If steps 1 through 5 are correct, then you probably have used a component with
the wrong value or one that doesn't work. It is also possible that the equipment
does not work (although this is not probable) or the breadboard you are using may
have some unwanted paths between nodes. To find your problem you must trace
through the voltages in your circuit node by node and compare the signal you
have to the signal you expect to have. Then if they are different use your
engineering judgment to decide what is causing the different or ask your lab
assistant or course instructor.
EXPERIMENT # 1
To study and prepare the NOT, OR, AND gate using BJT transistor
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective:
To study and prepare the NOT, OR, AND gate using BJT transistor.
Theory
NOT:
The NOT gate or inverter is a digital logic gate that implements logical negation. It
behaves according to the given truth table. A HIGH output (1) results if the inputs is
LOW (0). If the input is HIGH (1), a LOW output (0) results
OR
The OR gate is a digital logic gate that implements logical disjunction - it behaves
according to the given truth table. A HIGH output (1) results if one or both the inputs to
the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results.
AND
The AND gate is a digital logic gate that implements logical conjunction - it behaves
according to the given truth table. A HIGH output (1) results only if both the inputs to the
AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW
output results.
INPUT OUTPUT
A
NOT A
OUTPUT
INPUT OUTPUT
A B A OR B
A B A AND B
0
0
0
0 0
0
0
1
0
1
1
0 1
0
1
0
1
0
1
1 0
0
1
1
1
1 1
1
Symbols
NOT
AND
OR
Circuit
Vcc
5V
+V
Vcc2
5V
+V
Vcc1
5V
+V
R2
1k
B
R1
100
Q1
NPN
A
R4
100
C
Q2
NPN
Q3
NPN
R7
100
R3
100
D
R6
100
E
R5
1k
Q4
NPN
F
Q5
NPN
G
H
R8
1k
NOT
Fig 01
OR
Fig 02
AND
Fig 03
Equipment Required
•
•
•
•
•
Two BJT BC 108 (NPN)
Resistor 1K and 100 Ω
5 volts fixed supply
Multi-meter
Two Switch
Procedure
•
•
•
•
•
•
•
•
•
•
•
•
•
Connect the circuit as per Fig 01
Apply logic ‘0’ at terminal A and determine the logic level at terminal B , record
the reading in Table 1.
Apply logic ‘1’ at terminal A and determine the logic level at terminal B , record
the reading in Table 1.
Now Connect the circuit as per Fig 02
Apply logic ‘0’ at terminal C and D and determine the logic level at terminal E ,
record the reading in Table 2.
Apply logic ‘1’ at terminal C and D and determine the logic level at terminal E ,
record the reading in Table 2.
Apply logic ‘0’ at terminal C and ‘1’ at D and determine the logic level at
terminal E , record the reading in Table 2.
Apply logic ‘1’ at terminal C and ‘0’ at D and determine the logic level at
terminal E , record the reading in Table 2.
Now Connect the circuit as per Fig 03
Apply logic ‘0’ at terminal F and G and determine the logic level at terminal H ,
record the reading in Table 3.
Apply logic ‘1’ at terminal F and G and determine the logic level at terminal H ,
record the reading in Table 3.
Apply logic ‘0’ at terminal F and ‘1’ at G and determine the logic level at
terminal H , record the reading in Table 3.
Apply logic ‘1’ at terminal F and ‘0’ at G and determine the logic level at
terminal H , record the reading in Table 3.
Observation
Table 1
S.No A
Table 2
S.No C
B
D
E
Table 3
S.No F
G
H
Conclusion
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
EXPERIMENT # 2
To design transistorized NOR and NAND gate circuit using BJT
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To design transistorized NOR and NAND gate circuit using BJT
Theory
NOR
The NOR gate is a digital logic gate that implements logical NOR - it behaves according
to the given truth table. A HIGH output (1) results if both the inputs to the gate are LOW
(0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the
negation of the OR operator.
NAND
The NAND gate is a digital logic gate that behaves according to the given truth table. A
LOW output results only if both the inputs to the gate are HIGH. If one or both inputs are
LOW, a HIGH output results.
INPUT OUTPUT
A B A NOR B
0
0
1
0
1
0
1
0
0
1
1
0
INPUT OUTPUT
A B A NAND B
0
0
1
0
1
1
1
0
1
1
1
0
Symbols
NAND
NOR
Circuit
NOR
Fig 01
NAND
Fig 02
Equipment Required
•
•
•
•
•
Two BJT 2N 2222 (NPN)
Resistor 1K and 150 Ω
5 volts fixed supply
Multi-meter
Two DPDT Switch
Procedure
•
•
•
•
•
•
•
•
•
•
Connect the circuit as per Fig 01
Apply logic ‘0’ at terminal A and B and determine the logic level
record the reading in Table 1.
Apply logic ‘1’ at terminal A and B and determine the logic level
record the reading in Table 1.
Apply logic ‘0’ at terminal A and ‘1’ at B and determine the
terminal C , record the reading in Table 1.
Apply logic ‘1’ at terminal A and ‘0’ at B and determine the
terminal C , record the reading in Table 1.
Now Connect the circuit as per Fig 02
Apply logic ‘0’ at terminal D and E and determine the logic level
record the reading in Table 2.
Apply logic ‘1’ at terminal D and E and determine the logic level
record the reading in Table 2.
Apply logic ‘0’ at terminal D and ‘1’ at E and determine the
terminal F , record the reading in Table 2.
Apply logic ‘1’ at terminal D and ‘0’ at E and determine the
terminal F , record the reading in Table 2.
at terminal C ,
at terminal C ,
logic level at
logic level at
at terminal F ,
at terminal F ,
logic level at
logic level at
Observation
Table 1
S.No A
B
C
Table 2
S.No D
E
F
Conclusion
_____________________________________________________________________
_____________________________________________________________________
____________________________________________________________________
EXPERIMENT # 3
To Determine the Fan-out of digital IC
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To Determine the Fan-out of digital IC
Theory
Fan-out is a measure of the ability of a logic gate output, implemented electronically, to
drive a number of inputs of other logic gates of the same type. In most designs, logic
gates are connected together to form more complex circuits, and it is common for one
logic gate output to be connected to several logic gate inputs. The technology used to
implement logic gates usually allows gate inputs to be wired directly together with no
additional interfacing circuitry required.
Fanout=Iout (max) /I (due to one device)
Circuit Diagram
Equipment Required
• 74LS04 TTL not gate
• (8) Resistor 150 Ω each
• 5 volts fixed supply
• Multi-meter
Procedure
• Connect pin 14 to Vcc=5V and pin 7 to ground of 74ls04.
• Apply logic ‘0’ at pin 1 and connect ammeter at the output pin 2 of 74ls04.
• Now attached 150 Ω and record you reading in table 1
• Repeat step 3 until you get maximum current drawn from 74LS04 and record
your reading in table1
Observation
Table 1
150 Ω
Current (amps)
Difference of
current
1
2
3
4
5
6
7
8
9
Fan-Out =_______________________
Conclusion
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
EXPERIMENT # 4
To determine I and V parameter of Digital IC
Name: ________________________________________________
Registration No: ________________________________________
Program: ______________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To determine I and V parameter of Digital IC
Theory
Current and Voltage Parameter
1 VIH(min)—High Level Input Voltage. The minimum voltage level required for a
logic 1 at an input. Any voltage below this level will not be accepted as HIGH by
logic circuit.
2 VIL(max)—Low Level Input Voltage. The maximum voltage level required for a
logic 0 at an input. Any voltage above this level will not be accepted as LOW by
logic circuit.
3 VOH(min)—High Level Output Voltage. The minimum voltage level required for
a logic 1 at an output, under defined load condition.
4 VOL(max)—Low Level Output Voltage. The maximum voltage level required for
a logic 0 at an input. under defined load condition.
5 IIH-- High Level Input Current. The current that flows into an output when a
specified HIGH level voltage applied to that input.
6 IIL-- Low Level Input Current. The current that flows into an output when a
specified LOW level voltage applied to that input.
7 IOH-- High Level Output Current. The current that flows from an output in the
logic 1 state underspecified load condition.
8 IOL-- Low Level Output Current. The current that flows from an output in the
logic 0 state underspecified load condition.
Circuit Diagram
Fig -01
Fig 02
Equipment Required
•
•
•
•
•
74LS04 TTL not gate
Variable Resistor 2K
LED
5 volts fixed supply
Multi-meter
Procedure
•
•
•
•
•
Connect pin 14 to Vcc=5V and pin 7 to ground of 74ls04.
Connect the circuit according to Fig-01
Vary the value of variable resistor until LED just about to ONN. At this point
measure the value of VIL and VOH and IIL and IOH according to fig-02
Vary the value of variable resistor until LED just about to OFF. At this point
measure the value of VIH and VOL and IIH and IOL according to fig-02
Record your reading in Table 1
Observation
Table 1
S.No.
1
2
3
4
5
6
7
8
Parameter
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
Range
Conclusion
_____________________________________________________________________
_____________________________________________________________________
____________________________________________________________________
EXPERIMENT # 5
To design NOT OR and AND gate using N-Channel MOSFET
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To design NOT OR and AND gate using N-Channel MOSFET
Theory
NOT:
The NOT gate or inverter is a digital logic gate that implements logical negation. It
behaves according to the given truth table. A HIGH output (1) results if the inputs is
LOW (0). If the input is HIGH (1), a LOW output (0) results
OR
The OR gate is a digital logic gate that implements logical disjunction - it behaves
according to the given truth table. A HIGH output (1) results if one or both the inputs to
the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results.
AND
The AND gate is a digital logic gate that implements logical conjunction - it behaves
according to the given truth table. A HIGH output (1) results only if both the inputs to
the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a
LOW output results.
INPUT OUTPUT
A
NOT A
INPUT OUTPUT
A B A OR B
OUTPUT
A B A AND B
0
0
0
0 0
0
0
1
0
1
1
0 1
0
1
0
1
0
1
1 0
0
1
1
1
1 1
1
Symbols
NOT
AND
OR
IRF-630
Circuit Diagram
Fig-01
Equipment Required
•
•
•
•
•
N-MOS IRF-630
Resistor 330Ω
DPDT Switch
5 volts fixed supply
Multi-meter
Procedure
• Connect the circuit as shown in fig-01
• Apply logic 0 at terminal A and measure the output at terminal B, record this
reading in Table 1
• Apply logic 1 at terminal A and measure the output at terminal B, record this
reading in Table 1
• Apply logic 0 at terminal C and D and measure the output at terminal E, record
this reading in Table 2
• Apply logic 1 at terminal C and D and measure the output at terminal E, record
this reading in Table 2
• Apply logic 0 at terminal C and logic 1 at D and then measure the output at
terminal E, record this reading in Table 2
•
•
•
•
•
Apply logic 1 at terminal C and logic 0 at D and then measure the output at
terminal E, record this reading in Table 2
Apply logic 0 at terminal F and G and measure the output at terminal H, record
this reading in Table 3
Apply logic 1 at terminal F and G and measure the output at terminal H, record
this reading in Table 3
Apply logic 0 at terminal F and logic 1 at G and then measure the output at
terminal H, record this reading in Table 3
Apply logic 1 at terminal F and logic 0 at G and then measure the output at
terminal H, record this reading in Table 3
Observation
Table 1
S.No
A
B
Table 2
S.No
C
D
E
Table 3
S.No
F
G
H
Conclusion
_____________________________________________________________________
_____________________________________________________________________
____________________________________________________________________
EXPERIMENT # 6
To design NAND and NOR gate using N-Channel MOSFET
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To design NAND and NOR gate using N-Channel MOSFET
Theory
NOR
The NOR gate is a digital logic gate that implements logical NOR - it behaves according
to the given truth table . A HIGH output (1) results if both the inputs to the gate are
LOW(0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of
the negation of the OR operator.
NAND
The NAND gate is a digital logic gate that behaves according to the given truth table. A
LOW output results only if both the inputs to the gate are HIGH. If one or both inputs are
LOW, a HIGH output results.
INPUT OUTPUT
A B A NOR B
0
0
1
0
1
0
1
0
0
1
1
0
INPUT OUTPUT
A B A NAND B
0
0
1
0
1
1
1
0
1
1
1
0
Symbols
NAND
NOR
IRF-630
Circuit Diagram
NOR
NAND
Fig 01
Equipment Required
•
•
•
•
•
N-MOS IRF-630
Resistor 330Ω
DPDT Switch
5 volts fixed supply
Multi-meter
Procedure
•
•
•
•
•
•
•
•
•
Connect the circuit as shown in fig-01
Apply logic 0 at terminal A and B and measure the output at terminal C, record
this reading in Table 1
Apply logic 1 at terminal A and B and measure the output at terminal C, record
this reading in Table 1
Apply logic 0 at terminal A and logic 1 at B and then measure the output at
terminal C, record this reading in Table 1
Apply logic 1 at terminal A and logic 0 at B and then measure the output at
terminal C, record this reading in Table 1
Apply logic 0 at terminal D and E and measure the output at terminal F, record
this reading in Table 2
Apply logic 1 at terminal D and E and measure the output at terminal F, record
this reading in Table 2
Apply logic 0 at terminal D and logic 1 at E and then measure the output at
terminal F, record this reading in Table 2
Apply logic 1 at terminal D and logic 0 at E and then measure the output at
terminal F, record this reading in Table 2
Observation
Table 1
S.No A
B
C
S.No D
E
F
Table 2
Conclusion
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
EXPERIMENT # 7
To design and implement Tri-State logic device
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To design and implement tri-state logic device
Theory
In digital electronics three-state, tri-state, or 3-state logic allows output ports to have a
value of 0, 1, or Z. A Z output stands for the output port being disconnected from the rest
of the circuit, putting the output in a high impedance state. The intent of this state is to
allow multiple circuits to share the same output line or bus without affecting each other.
Tri-state is a registered trademark of National Semiconductor but is often used to
describe devices made by any manufacturer.
Three-state outputs are implemented in various families of digital integrated circuits such
as the 7400 series of TTL gates, and often in the data and address bus lines of
microprocessors. Three-state outputs may be found on individual logic gates, or in
multiples in one integrated circuit package as a buffer for connection to a bus.
Three-state buffers can be used to implement efficient multiplexers, especially those with
large numbers of inputs. Three-state logic devices are used to accommodate multiple bus
drivers. If the outputs of several tri-state logic are electrically connected together, only
one three-state logic device may be active. The other three-state logic devices may be in
the high impedance mode and thus will not affect the output of the active three-state logic
device. Three-state logic can reduce the number of wires needed to drive a set of LEDs
(tristate multiplexing).
74LS125 TTL Tri-state Buffer with active low enable
Circuit Diagram
Fig 01
Equipment Required
•
•
•
•
•
•
74LS04 TTL NOT Gate
Resistor 220Ω
DPDT Switch
74LS125 Tri-state buffer
5 volts fixed supply
Multi-meter
Procedure
•
•
•
•
•
•
•
•
•
•
•
Connect the circuit as shown in fig-01
Set V2 to 0V
Now set logic 0 at V1 and 0 at V2 , record this reading in Table 1
Now set logic 0 at V1 and 1 at V2 , record this reading in Table 1
Now set logic 1 at V1 and 0 at V2 , record this reading in Table 1
Now set logic 1 at V1 and 1 at V2 , record this reading in Table 1
Set V2 to 1V
Now set logic 0 at V1 and 0 at V2 , record this reading in Table 1
Now set logic 0 at V1 and 1 at V2 , record this reading in Table 1
Now set logic 1 at V1 and 0 at V2 , record this reading in Table 1
Now set logic 1 at V1 and 1 at V2 , record this reading in Table 1
Observation
S.No
1
2
3
4
5
6
7
8
V3
0
0
0
0
1
1
1
1
V1
0
0
1
0
0
1
1
1
V2
0
1
0
0
1
0
1
1
Table 1
LED1 LED2 LED3 LED4 Remarks
Conclusion
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
EXPERIMENT # 8
To implement digital to analog conversion using DAC 0808
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To implement digital to analog conversion using DAC 0808
Theory
DAC 0808 and LM-741 (sample and hold circuit), are readily obtainable commercial
product. DAC 0808 is an 8 bit DAC , it is connected to provide a full scale output of Vo
= +10 Vdc when all 8 digital inputs are 1s (high), where else if all the digital input are 0s
(low)the output voltage will be Vo=0 Vdc. Two dc power supply voltages are required
for the DAC0808 Vcc=5Vdc and VEE =-15Vdc.the 0.1-µF capacitor is to prevent
unwanted circuit oscillation, and to isolate any variation in VEE .Pin 2 is grounded (GND)
and pin 15is also reference to ground through a resistor.
Circuit Diagram
3
Fig 01
Equipment Required
•
•
•
•
•
•
•
DAC 0808
LM 741
DPDT Switches
0.1µF
5 k resistor
Power Supplies +15V, -15V, 5V, 10V
Multi-meter
Procedure
•
•
Connect the circuit as shown in fig-01
Recorded the following reading corresponding to the given input.
Observation
S.No
1
2
3
4
5
6
7
8
D0(MSB)
1
0
0
0
1
1
1
1
D1
0
0
0
0
1
0
1
0
D2
0
0
0
0
1
0
1
0
D3
0
0
0
0
1
1
0
0
D4
0
0
1
0
1
0
0
0
Table 1
D5 D6
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
D7(LSB) OUTPUT REMARKS
0
1
0
0
1
0
0
1
Conclusion
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
EXPERIMENT # 9
To implement analog to digital conversion using ADC 0804
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
To implement analog to digital conversion using ADC 0804
Theory
The ADC 0804 is an inexpensive and very popular ADC. ADC0804 is an 8 bit CMOS
microprocessor compatible successive approximation ADC that is supplied in a 12 PIN
DIP. It is capable f digitizing an analog input voltage with a range of 0 to +5 volts DC ,
and it only required a single Dc supple voltage usually +5Vdc.The digital output as both
TTL and CMOS compatible. According to given figure 10 KΩ resistor along with the
150-pF capacitor establish the frequency of operation
F=1/(1.1 x R x C) =607kHz
Circuit Diagram
Fig 01
Equipment Required
•
•
•
•
•
ADC0804
Resistor 10KΩ (1)
DPDT Switch(9)
5 volts fixed supply
Multi-meter
Procedure
•
•
Connect the circuit as shown in fig-01
Record 10 digital values corresponding to the analog input
Observation
S.No D0
1
2
3
4
D1
D2
D3
Table 1
D4 D5
D6
D7
Analog
Input
Vcc
Vcc/2
Vcc/4
Vcc/8
Conclusion
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
EXPERIMENT # 10
Introduction to WinCupl
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
Introduction to WinCupl
Theory
Programmable Logic
Programmable logic, as the name implies, is a family of components that contains arrays
of logic elements (AND, OR, INVERT, LATCH, FLIP-FLOP) that may be configured
into any logical function that the user desires and the component supports. There are
several classes of programmable logic devices: ASICs, FPGAs, PLAs, PROMs, PALs,
GALs, and complex PLDs.
GALs
GALs are Generic Array Logic devices. They are designed to emulate many common
PALs thought the use of macrocells. If a user has a design that is implemented using
several common PALs, he may configure several of the same GALs to emulate each of
the other devices. This will reduce the number of different devices in stock and increase
the quantity purchased. Usually, a large quantity of the same device should lower the
individual device cost. Also these devices are electrically erasable, which makes them
very useful for design engineers.
Using Logical Operators
Four standard logical operators are available for use: NOT, AND, OR, and XOR. The
following table lists the operators and their order of precedence, from highest to lowest.
Arithmetic Operator
WinCUPL
WinCUPL is a Universal Compiler for Programmable Logic. WinCUPL is a versatile
and powerful logic compiler that can be used to create very sophisticated logic designs
for SPLD and CPLD.
The WinCUPL Tools
The WinCUPL package includes the following tools:
WinCUPL A powerful front end and user interface for all of the WinCUPL tools
including the compiler. For more details on the features of WinCUPL.
CUPL Compiler Logic descriptions written in the CUPL language are compiled, and can
be assigned to specific logic devices (PLDs). Upon compilation, the CUPL compiler
searches its libraries and creates a file which can be downloaded to a device programmer.
From this point, the PLD can be programmed.
Simulator Designs can be simulated with CSIM before they are put into production.
CSIM compares the expected values to actual values calculated during CUPL operation.
Both the simulation inputs and the results of the simulation can be graphically viewed
and modified with WinSim.
WinSim Simulation input and results are set and displayed by WinSim in waveform.
CUPL Data Flow
The following diagram illustrates the data flow for creating a design and implementing
the design using CUPL.
First, a logic description is created using the CUPL language manually using the
WinCUPL source editor.
Then, the design is compiled to create a fuse map file for downloading to a device
programmer. Optionally, a test specification file may be created to verify the design.
CSIM is executed to compare the expected values in the test file to the actual values in
the absolute file created by CUPL. When simulation is completed without any errors, the
verified test vectors can be appended to the download file generated by CUPL.
Data Flow Diagram
The Project Window
The project window displays all of the files associated with the open project or design file
in a tree control. Double clicking any file within the window will open that file in the
editor or CUPL tool that is used to create or edit the file.
You can close the project by closing the project window.
If you open a design file rather than opening it as a project, you can display the project
window at any time by choosing Project from the view menu.
The Messages Window
The messages window displays the output from the compiler consisting of both status
information and error messages generated by the compiler. If you click on an error
message, the Error Message dialog will be displayed providing more information about
the specific error.
EXPERIMENT # 11
Programming Logical NOT, OR, AND, XOR, NOR, NAND, XNOR for
GAL16v8 using WinCupl
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
Programming Logical NOT, OR, AND, XOR, NOR, NAND, XNOR for GAL16v8 using
Wincupl
Theory
Programmable logic, as the name implies, is a family of components that contains arrays
of logic elements (AND, OR, INVERT, LATCH, FLIP-FLOP) that may be configured
into any logical function that the user desires and the component supports. There are
several classes of programmable logic devices: ASICs, FPGAs, PLAs, PROMs, PALs,
GALs, and complex PLDs.
GALs
GALs are Generic Array Logic devices. They are designed to emulate many common
PALs thought the use of macrocells. If a user has a design that is implemented using
several common PALs, he may configure several of the same GALs to emulate each of
the other devices. This will reduce the number of different devices in stock and increase
the quantity purchased. Usually, a large quantity of the same device should lower the
individual device cost. Also these devices are electrically erasable, which makes them
very useful for design engineers.
Using Logical Operators
Four standard logical operators are available for use: NOT, AND, OR, and XOR. The
following table lists the operators and their order of precedence, from highest to lowest.
Arithmetic Operator
WinCUPL
WinCUPL is a Universal Compiler for Programmable Logic. WinCUPL is a versatile
and powerful logic compiler that can be used to create very sophisticated logic designs
for SPLD and CPLD. The WinCUPL Tools
The WinCUPL package includes the following tools:
WinCUPL A powerful front end and user interface for all of the WinCUPL tools
including the compiler. For more details on the features of WinCUPL.
CUPL Compiler Logic descriptions written in the CUPL language are compiled, and can
be assigned to specific logic devices (PLDs). Upon compilation, the CUPL compiler
searches its libraries and creates a file which can be downloaded to a device programmer.
From this point, the PLD can be programmed.
Simulator Designs can be simulated with CSIM before they are put into production.
CSIM compares the expected values to actual values calculated during CUPL operation.
Both the simulation inputs and the results of the simulation can be graphically viewed
and modified with WinSim.
WinSim Simulation input and results are set and displayed by WinSim in waveform.
CUPL Data Flow
The following diagram illustrates the data flow for creating a design and implementing
the design using CUPL.
First, a logic description is created using the CUPL language manually using the
WinCUPL source editor.
Then, the design is compiled to create a fusemap file for downloading to a device
programmer. Optionally, a test specification file may be created to verify the design.
CSIM is executed to compare the expected values in the test file to the actual values in
the absolute file created by CUPL. When simulation is completed without any errors, the
verified test vectors can be appended to the download file generated by CUPL.
Data Flow Diagram
The Project Window
The project window displays all of the files associated with the open project or design file
in a tree control. Double clicking any file within the window will open that file in the
editor or CUPL tool that is used to create or edit the file.
You can close the project by closing the project window.
If you open a design file rather than opening it as a project, you can display the project
window at any time by choosing Project from the view menu.
The Messages Window
The messages window displays the output from the compiler consisting of both status
information and error messages generated by the compiler. If you click on an error
message, the Error Message dialog will be displayed providing more information about
the specific error.
Code
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
All_basic_Gates;
gat110;
04;
5/2/08;
Engr. Syed Sajjad Hussain Rizvi;
IQRA UNIVERSITY;
MAIN;
None;
g16v8a;
/* Inputs Pins: define inputs and assigning the name to
the input pins*/
Pin 1 =
Pin 2 =
a;
b;
/*Outputs Pins: define outputs as active HI levels
assigning the name to o/p pin*/
and
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
12
13
14
15
16
17
18
19
=
=
=
=
=
=
=
=
inva;
invb;
and;
nand;
or;
nor;
xor;
xnor;
/*
* Logic:
*/
inva
invb
and
nand
or
nor
xor
xnor
=
=
=
=
=
=
=
=
!a;
!b;
a &
!(a
a #
!(a
a $
!(a
Implementing logic gates
/* inverters */
b;
& b);
b;
# b);
b;
$ b);
/*
/*
/*
/*
/*
/*
and gate */
nand gate */
or gate */
nor gate */
exclusive or gate */
exclusive nor gate */
Equipment Required
•
•
•
•
GAL16v8
wincupl
Topwin programmer
Computer
Procedure
•
•
•
•
•
Code the given program
Analyze the given code using wincupl tool
develop the .jed file
Burn the . jed file to gal16v8
Test the given GAL for the given input and record you result in Table 1
Observation
S.No Pin
1
1
0
2
0
3
1
4
1
Pin Pin
2
12
0
1
0
1
Table 1
PIN PIN PIN
12
14
15
PIN
16
PIN PIN
17
18
Conclusion
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
EXPERIMENT # 12
Programming Logical expression on GAL16v8 using Wincupl
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
Programming Logical expression on GAL16v8 using Wincupl
Theory
Programmable logic, as the name implies, is a family of components that contains arrays
of logic elements (AND, OR, INVERT, LATCH, FLIP-FLOP) that may be configured
into any logical function that the user desires and the component supports. There are
several classes of programmable logic devices: ASICs, FPGAs, PLAs, PROMs, PALs,
GALs, and complex PLDs.
GALs
GALs are Generic Array Logic devices. They are designed to emulate many common
PALs thought the use of macrocells. If a user has a design that is implemented using
several common PALs, he may configure several of the same GALs to emulate each of
the other devices. This will reduce the number of different devices in stock and increase
the quantity purchased. Usually, a large quantity of the same device should lower the
individual device cost. Also these devices are electrically erasable, which makes them
very useful for design engineers.
Using Logical Operators
Four standard logical operators are available for use: NOT, AND, OR, and XOR. The
following table lists the operators and their order of precedence, from highest to lowest.
Arithmetic Operator
Code
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
Logic Expression;
Exp;
04;
5/2/08;
Engr. Syed Sajjad Hussain Rizvi;
IQRA UNIVERSITY;
MAIN;
None;
g16v8a;
/* Inputs Pins: define inputs and assigning the name to
the input pins*/
Pin 1 =
Pin 2 =
Pin 3 =
a;
b;
c;
/*Outputs Pins: define outputs as active HI levels
assigning the name to o/p pin*/
Pin
Pin
Pin
Pin
Pin
12
13
14
15
16
=
=
=
=
=
exp1;
exp2;
exp3;
exp4;
exp5;
/*
* Logic: Implementing logic gates
*/
exp1 = !(!a & b # c);
exp2 = !b & !a & c;
exp3 = c!(a & b $ c);
exp4 = a!(a & !c)# a $!a;
exp5 = !c $ a # !b;
and
Equipment Required
•
•
•
•
GAL16v8
Wincupl
Topwin programmer
Computer
Procedure
•
•
•
•
•
Code the given program
Analyze the given code using wincupl tool
develop the .jed file
Burn the .jed file to gal16v8
Test the given GAL for the given input and record you result in Table 1
Observation
S.No Pin
1
1
0
2
0
3
0
4
0
1
1
2
1
3
1
4
1
Pin
2
0
0
1
1
0
0
1
1
Pin
3
0
1
0
1
0
1
0
1
Table 1
PIN PIN
12
14
PIN
15
PIN
16
Conclusion
_____________________________________________________________________
_____________________________________________________________________
____________________________________________________________________
EXPERIMENT # 13
Programming Logical expression on GAL16v8 using Wincupl
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
Programming 3 X 8 line decoder on GAL16v8 using Wincupl
Theory
Programmable logic, as the name implies, is a family of components that contains arrays
of logic elements (AND, OR, INVERT, LATCH, FLIP-FLOP) that may be configured
into any logical function that the user desires and the component supports. There are
several classes of programmable logic devices: ASICs, FPGAs, PLAs, PROMs, PALs,
GALs, and complex PLDs.
GALs
GALs are Generic Array Logic devices. They are designed to emulate many common
PALs thought the use of macrocells. If a user has a design that is implemented using
several common PALs, he may configure several of the same GALs to emulate each of
the other devices. This will reduce the number of different devices in stock and increase
the quantity purchased. Usually, a large quantity of the same device should lower the
individual device cost. Also these devices are electrically erasable, which makes them
very useful for design engineers.
Using Logical Operators
Four standard logical operators are available for use: NOT, AND, OR, and XOR. The
following table lists the operators and their order of precedence, from highest to lowest.
Arithmetic Operator
Code
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
3to8decoder;
decoder;
04;
5/2/08;
Engr. Syed Sajjad Hussain Rizvi;
IQRA UNIVERSITY;
MAIN;
None;
g16v8a;
/* Inputs Pins: define inputs and assigning the name to
the input pins*/
Pin 1 =
Pin 2 =
Pin 3 =
a;
b;
c;
/*Outputs Pins: define outputs as active HI levels
assigning the name to o/p pin*/
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
12
13
14
15
16
17
18
19
=
=
=
=
=
=
=
=
exp1;
exp2;
exp3;
exp4;
exp5;
exp6;
exp7;
exp8;
/*
* Logic: Implementing logic gates
*/
exp1 = !(!a & !b & !c);
exp2 = !(!a & !b & c);
exp3 = !(!a & b & !c);
exp4 = !(!a & b & c);
and
exp5
exp6
exp7
exp8
=
=
=
=
!(a
!(a
!(a
!(a
&
&
&
&
!b & !c);
!b & c);
b & !c);
b & c);
Equipment Required
•
•
•
•
GAL16v8
wincupl
Topwin programmer
Computer
Procedure
•
•
•
•
•
Code the given program
Analyze the given code using wincupl tool
develop the .jed file
Burn the . jed file to gal16v8
Test the given GAL for the given input and record you result in Table 1
Observation
S.No Pin
1
1
0
2
0
3
0
4
0
1
1
2
1
3
1
4
1
Pin
2
0
0
1
1
0
0
1
1
Pin
3
0
1
0
1
0
1
0
1
PIN
12
PIN
13
Table 1
PIN PIN
14
15
PIN
16
PIN
17
PIN
18
PIN
19
Conclusion
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________
EXPERIMENT # 14
Programming Binary Full Adder on GAL16v8 using Wincupl
Name: ________________________________________________
Registration No: ________________________________________
Program: _____________________________________________
Remarks:
_______________________________________________________
_______________________________________________________
_______________________________________________________
______________________
Lab Instructor Signature
Objective
Programming Binary Full Adder on GAL16v8 using Wincupl
Theory
Programmable logic, as the name implies, is a family of components that contains arrays
of logic elements (AND, OR, INVERT, LATCH, FLIP-FLOP) that may be configured
into any logical function that the user desires and the component supports. There are
several classes of programmable logic devices: ASICs, FPGAs, PLAs, PROMs, PALs,
GALs, and complex PLDs.
GALs
GALs are Generic Array Logic devices. They are designed to emulate many common
PALs thought the use of macrocells. If a user has a design that is implemented using
several common PALs, he may configure several of the same GALs to emulate each of
the other devices. This will reduce the number of different devices in stock and increase
the quantity purchased. Usually, a large quantity of the same device should lower the
individual device cost. Also these devices are electrically erasable, which makes them
very useful for design engineers.
Using Logical Operators
Four standard logical operators are available for use: NOT, AND, OR, and XOR. The
following table lists the operators and their order of precedence, from highest to lowest.
Arithmetic Operator
Code
Name
Partno
Revision
Date
Designer
Company
Location
Assembly
Device
fulladder;
FA;
04;
5/2/08;
Engr. Syed Sajjad Hussain Rizvi;
IQRA UNIVERSITY;
MAIN;
None;
g16v8a;
/* Inputs Pins: define inputs and assigning the name to
the input pins*/
Pin 1 =
Pin 2 =
Pin 3 =
a;
b;
c;
/*Outputs Pins: define outputs as active HI levels and
assigning the name to o/p pin*/
Pin 12 = sum;
Pin 13 = carry;
/*
* Logic: Implementing logic gates
*/
sum = (a $ b)$ c;
carry = a & b # ( a $ b) & c;
Equipment Required
•
•
•
•
GAL16v8
wincupl
Topwin programmer
Computer
Procedure
•
•
•
•
•
Code the given program
Analyze the given code using wincupl tool
develop the .jed file
Burn the . jed file to gal16v8
Test the given GAL for the given input and record you result in Table 1
Observation
S.No Pin
1
1
0
2
0
3
0
4
0
1
1
2
1
3
1
4
1
Table 1
Pin Pin
2
3
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
PIN
12
PIN
13
Conclusion
_____________________________________________________________________
_____________________________________________________________________
_____________________________________________________________________